2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/acpi.h>
27 #include <linux/clk.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
31 #include <asm/byteorder.h>
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
38 #define DW_UART_UCV 0xf8 /* UART Component Version */
40 /* Component Parameter Register bits */
41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42 #define DW_UART_CPR_AFCE_MODE (1 << 4)
43 #define DW_UART_CPR_THRE_MODE (1 << 5)
44 #define DW_UART_CPR_SIR_MODE (1 << 6)
45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48 #define DW_UART_CPR_FIFO_STAT (1 << 10)
49 #define DW_UART_CPR_SHADOW (1 << 11)
50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
52 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
53 /* Helper for fifo size calculation */
54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
65 struct reset_control *rst;
66 struct uart_8250_dma dma;
69 #define BYT_PRV_CLK 0x800
70 #define BYT_PRV_CLK_EN (1 << 0)
71 #define BYT_PRV_CLK_M_VAL_SHIFT 1
72 #define BYT_PRV_CLK_N_VAL_SHIFT 16
73 #define BYT_PRV_CLK_UPDATE (1 << 31)
75 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
77 struct dw8250_data *d = p->private_data;
79 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
80 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
81 value |= UART_MSR_CTS;
82 value &= ~UART_MSR_DCTS;
85 /* Override any modem control signals if needed */
86 if (offset == UART_MSR) {
87 value |= d->msr_mask_on;
88 value &= ~d->msr_mask_off;
94 static void dw8250_force_idle(struct uart_port *p)
96 struct uart_8250_port *up = up_to_u8250p(p);
98 serial8250_clear_and_reinit_fifos(up);
99 (void)p->serial_in(p, UART_RX);
102 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
104 struct dw8250_data *d = p->private_data;
106 if (offset == UART_MCR)
109 writeb(value, p->membase + (offset << p->regshift));
111 /* Make sure LCR write wasn't ignored */
112 if (offset == UART_LCR) {
115 unsigned int lcr = p->serial_in(p, UART_LCR);
116 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
118 dw8250_force_idle(p);
119 writeb(value, p->membase + (UART_LCR << p->regshift));
122 * FIXME: this deadlocks if port->lock is already held
123 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
128 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
130 unsigned int value = readb(p->membase + (offset << p->regshift));
132 return dw8250_modify_msr(p, offset, value);
136 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
140 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
142 return dw8250_modify_msr(p, offset, value);
145 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
147 struct dw8250_data *d = p->private_data;
149 if (offset == UART_MCR)
153 __raw_writeq(value, p->membase + (offset << p->regshift));
154 /* Read back to ensure register write ordering. */
155 __raw_readq(p->membase + (UART_LCR << p->regshift));
157 /* Make sure LCR write wasn't ignored */
158 if (offset == UART_LCR) {
161 unsigned int lcr = p->serial_in(p, UART_LCR);
162 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
164 dw8250_force_idle(p);
165 __raw_writeq(value & 0xff,
166 p->membase + (UART_LCR << p->regshift));
169 * FIXME: this deadlocks if port->lock is already held
170 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
174 #endif /* CONFIG_64BIT */
176 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
178 struct dw8250_data *d = p->private_data;
180 if (offset == UART_MCR)
183 writel(value, p->membase + (offset << p->regshift));
185 /* Make sure LCR write wasn't ignored */
186 if (offset == UART_LCR) {
189 unsigned int lcr = p->serial_in(p, UART_LCR);
190 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
192 dw8250_force_idle(p);
193 writel(value, p->membase + (UART_LCR << p->regshift));
196 * FIXME: this deadlocks if port->lock is already held
197 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
202 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
204 unsigned int value = readl(p->membase + (offset << p->regshift));
206 return dw8250_modify_msr(p, offset, value);
209 static int dw8250_handle_irq(struct uart_port *p)
211 struct dw8250_data *d = p->private_data;
212 unsigned int iir = p->serial_in(p, UART_IIR);
214 if (serial8250_handle_irq(p, iir)) {
216 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
218 (void)p->serial_in(p, d->usr_reg);
227 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
230 pm_runtime_get_sync(port->dev);
232 serial8250_do_pm(port, state, old);
235 pm_runtime_put_sync_suspend(port->dev);
238 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
239 struct ktermios *old)
241 unsigned int baud = tty_termios_baud_rate(termios);
242 struct dw8250_data *d = p->private_data;
246 if (IS_ERR(d->clk) || !old)
249 /* Not requesting clock rates below 1.8432Mhz */
253 clk_disable_unprepare(d->clk);
254 rate = clk_round_rate(d->clk, baud * 16);
255 ret = clk_set_rate(d->clk, rate);
256 clk_prepare_enable(d->clk);
261 serial8250_do_set_termios(p, termios, old);
264 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
269 static void dw8250_setup_port(struct uart_8250_port *up)
271 struct uart_port *p = &up->port;
272 u32 reg = readl(p->membase + DW_UART_UCV);
275 * If the Component Version Register returns zero, we know that
276 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
281 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
282 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
284 reg = readl(p->membase + DW_UART_CPR);
288 /* Select the type based on fifo */
289 if (reg & DW_UART_CPR_FIFO_MODE) {
290 p->type = PORT_16550A;
291 p->flags |= UPF_FIXED_TYPE;
292 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
293 up->tx_loadsz = p->fifosize;
294 up->capabilities = UART_CAP_FIFO;
297 if (reg & DW_UART_CPR_AFCE_MODE)
298 up->capabilities |= UART_CAP_AFE;
301 static int dw8250_probe_of(struct uart_port *p,
302 struct dw8250_data *data)
304 struct device_node *np = p->dev->of_node;
305 struct uart_8250_port *up = up_to_u8250p(p);
311 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
312 p->serial_in = dw8250_serial_inq;
313 p->serial_out = dw8250_serial_outq;
314 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
315 p->type = PORT_OCTEON;
316 data->usr_reg = 0x27;
320 if (!of_property_read_u32(np, "reg-io-width", &val)) {
325 p->iotype = UPIO_MEM32;
326 p->serial_in = dw8250_serial_in32;
327 p->serial_out = dw8250_serial_out32;
330 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
335 dw8250_setup_port(up);
337 /* if we have a valid fifosize, try hooking up DMA here */
339 up->dma = &data->dma;
341 up->dma->rxconf.src_maxburst = p->fifosize / 4;
342 up->dma->txconf.dst_maxburst = p->fifosize / 4;
345 if (!of_property_read_u32(np, "reg-shift", &val))
348 /* get index of serial line, if found in DT aliases */
349 id = of_alias_get_id(np, "serial");
353 if (of_property_read_bool(np, "dcd-override")) {
354 /* Always report DCD as active */
355 data->msr_mask_on |= UART_MSR_DCD;
356 data->msr_mask_off |= UART_MSR_DDCD;
359 if (of_property_read_bool(np, "dsr-override")) {
360 /* Always report DSR as active */
361 data->msr_mask_on |= UART_MSR_DSR;
362 data->msr_mask_off |= UART_MSR_DDSR;
365 if (of_property_read_bool(np, "cts-override")) {
366 /* Always report CTS as active */
367 data->msr_mask_on |= UART_MSR_CTS;
368 data->msr_mask_off |= UART_MSR_DCTS;
371 if (of_property_read_bool(np, "ri-override")) {
372 /* Always report Ring indicator as inactive */
373 data->msr_mask_off |= UART_MSR_RI;
374 data->msr_mask_off |= UART_MSR_TERI;
380 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
382 struct device *dev = param;
384 if (dev != chan->device->dev->parent)
390 static int dw8250_probe_acpi(struct uart_8250_port *up,
391 struct dw8250_data *data)
393 struct uart_port *p = &up->port;
395 dw8250_setup_port(up);
397 p->iotype = UPIO_MEM32;
398 p->serial_in = dw8250_serial_in32;
399 p->serial_out = dw8250_serial_out32;
402 /* Platforms with iDMA */
403 if (platform_get_resource_byname(to_platform_device(up->port.dev),
404 IORESOURCE_MEM, "lpss_priv")) {
405 data->dma.rx_param = up->port.dev->parent;
406 data->dma.tx_param = up->port.dev->parent;
407 data->dma.fn = dw8250_idma_filter;
410 up->dma = &data->dma;
411 up->dma->rxconf.src_maxburst = p->fifosize / 4;
412 up->dma->txconf.dst_maxburst = p->fifosize / 4;
414 up->port.set_termios = dw8250_set_termios;
419 static int dw8250_probe(struct platform_device *pdev)
421 struct uart_8250_port uart = {};
422 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 int irq = platform_get_irq(pdev, 0);
424 struct dw8250_data *data;
428 dev_err(&pdev->dev, "no registers defined\n");
433 if (irq != -EPROBE_DEFER)
434 dev_err(&pdev->dev, "cannot get irq\n");
438 spin_lock_init(&uart.port.lock);
439 uart.port.mapbase = regs->start;
441 uart.port.handle_irq = dw8250_handle_irq;
442 uart.port.pm = dw8250_do_pm;
443 uart.port.type = PORT_8250;
444 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
445 uart.port.dev = &pdev->dev;
447 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
448 resource_size(regs));
449 if (!uart.port.membase)
452 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
456 data->usr_reg = DW_UART_USR;
458 /* Always ask for fixed clock rate from a property. */
459 device_property_read_u32(&pdev->dev, "clock-frequency",
462 /* If there is separate baudclk, get the rate from it. */
463 data->clk = devm_clk_get(&pdev->dev, "baudclk");
464 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
465 data->clk = devm_clk_get(&pdev->dev, NULL);
466 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
467 return -EPROBE_DEFER;
468 if (!IS_ERR_OR_NULL(data->clk)) {
469 err = clk_prepare_enable(data->clk);
471 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
474 uart.port.uartclk = clk_get_rate(data->clk);
477 /* If no clock rate is defined, fail. */
478 if (!uart.port.uartclk) {
479 dev_err(&pdev->dev, "clock rate not defined\n");
483 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
484 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
488 if (!IS_ERR(data->pclk)) {
489 err = clk_prepare_enable(data->pclk);
491 dev_err(&pdev->dev, "could not enable apb_pclk\n");
496 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
497 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
501 if (!IS_ERR(data->rst))
502 reset_control_deassert(data->rst);
504 data->dma.rx_param = data;
505 data->dma.tx_param = data;
506 data->dma.fn = dw8250_dma_filter;
508 uart.port.iotype = UPIO_MEM;
509 uart.port.serial_in = dw8250_serial_in;
510 uart.port.serial_out = dw8250_serial_out;
511 uart.port.private_data = data;
513 if (pdev->dev.of_node) {
514 err = dw8250_probe_of(&uart.port, data);
517 } else if (ACPI_HANDLE(&pdev->dev)) {
518 err = dw8250_probe_acpi(&uart, data);
526 data->line = serial8250_register_8250_port(&uart);
527 if (data->line < 0) {
532 platform_set_drvdata(pdev, data);
534 pm_runtime_set_active(&pdev->dev);
535 pm_runtime_enable(&pdev->dev);
540 if (!IS_ERR(data->rst))
541 reset_control_assert(data->rst);
544 if (!IS_ERR(data->pclk))
545 clk_disable_unprepare(data->pclk);
548 if (!IS_ERR(data->clk))
549 clk_disable_unprepare(data->clk);
554 static int dw8250_remove(struct platform_device *pdev)
556 struct dw8250_data *data = platform_get_drvdata(pdev);
558 pm_runtime_get_sync(&pdev->dev);
560 serial8250_unregister_port(data->line);
562 if (!IS_ERR(data->rst))
563 reset_control_assert(data->rst);
565 if (!IS_ERR(data->pclk))
566 clk_disable_unprepare(data->pclk);
568 if (!IS_ERR(data->clk))
569 clk_disable_unprepare(data->clk);
571 pm_runtime_disable(&pdev->dev);
572 pm_runtime_put_noidle(&pdev->dev);
577 #ifdef CONFIG_PM_SLEEP
578 static int dw8250_suspend(struct device *dev)
580 struct dw8250_data *data = dev_get_drvdata(dev);
582 serial8250_suspend_port(data->line);
587 static int dw8250_resume(struct device *dev)
589 struct dw8250_data *data = dev_get_drvdata(dev);
591 serial8250_resume_port(data->line);
595 #endif /* CONFIG_PM_SLEEP */
598 static int dw8250_runtime_suspend(struct device *dev)
600 struct dw8250_data *data = dev_get_drvdata(dev);
602 if (!IS_ERR(data->clk))
603 clk_disable_unprepare(data->clk);
605 if (!IS_ERR(data->pclk))
606 clk_disable_unprepare(data->pclk);
611 static int dw8250_runtime_resume(struct device *dev)
613 struct dw8250_data *data = dev_get_drvdata(dev);
615 if (!IS_ERR(data->pclk))
616 clk_prepare_enable(data->pclk);
618 if (!IS_ERR(data->clk))
619 clk_prepare_enable(data->clk);
625 static const struct dev_pm_ops dw8250_pm_ops = {
626 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
627 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
630 static const struct of_device_id dw8250_of_match[] = {
631 { .compatible = "snps,dw-apb-uart" },
632 { .compatible = "cavium,octeon-3860-uart" },
635 MODULE_DEVICE_TABLE(of, dw8250_of_match);
637 static const struct acpi_device_id dw8250_acpi_match[] = {
648 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
650 static struct platform_driver dw8250_platform_driver = {
652 .name = "dw-apb-uart",
653 .pm = &dw8250_pm_ops,
654 .of_match_table = dw8250_of_match,
655 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
657 .probe = dw8250_probe,
658 .remove = dw8250_remove,
661 module_platform_driver(dw8250_platform_driver);
663 MODULE_AUTHOR("Jamie Iles");
664 MODULE_LICENSE("GPL");
665 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
666 MODULE_ALIAS("platform:dw-apb-uart");