drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/acpi.h>
  29 #include <linux/clk.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include <asm/byteorder.h>
  33
  34 #include "8250.h"
  35
  36 /* Offsets for the DesignWare specific registers */
  37 #define DW_UART_USR     0x1f /* UART Status Register */
  38 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  39 #define DW_UART_UCV     0xf8 /* UART Component Version */
  40
  41 /* Component Parameter Register bits */
  42 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  43 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  44 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  45 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  46 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  48 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  49 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  50 #define DW_UART_CPR_SHADOW              (1 << 11)
  51 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  52 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  53 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  54 /* Helper for fifo size calculation */
  55 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  56
  57
  58 struct dw8250_data {
  59         u8                      usr_reg;
  60         int                     last_mcr;
  61         int                     line;
  62         struct clk              *clk;
  63         struct uart_8250_dma    dma;
  64 };
  65
  66 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  67 {
  68         struct dw8250_data *d = p->private_data;
  69
  70         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
  71         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
  72                 value |= UART_MSR_CTS;
  73                 value &= ~UART_MSR_DCTS;
  74         }
  75
  76         return value;
  77 }
  78
  79 static void dw8250_force_idle(struct uart_port *p)
  80 {
  81         serial8250_clear_and_reinit_fifos(container_of
  82                                           (p, struct uart_8250_port, port));
  83         (void)p->serial_in(p, UART_RX);
  84 }
  85
  86 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
  87 {
  88         struct dw8250_data *d = p->private_data;
  89
  90         if (offset == UART_MCR)
  91                 d->last_mcr = value;
  92
  93         writeb(value, p->membase + (offset << p->regshift));
  94
  95         /* Make sure LCR write wasn't ignored */
  96         if (offset == UART_LCR) {
  97                 int tries = 1000;
  98                 while (tries--) {
  99                         if (value == p->serial_in(p, UART_LCR))
 100                                 return;
 101                         dw8250_force_idle(p);
 102                         writeb(value, p->membase + (UART_LCR << p->regshift));
 103                 }
 104                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 105         }
 106 }
 107
 108 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 109 {
 110         unsigned int value = readb(p->membase + (offset << p->regshift));
 111
 112         return dw8250_modify_msr(p, offset, value);
 113 }
 114
 115 /* Read Back (rb) version to ensure register access ording. */
 116 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
 117 {
 118         dw8250_serial_out(p, offset, value);
 119         dw8250_serial_in(p, UART_LCR);
 120 }
 121
 122 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 123 {
 124         struct dw8250_data *d = p->private_data;
 125
 126         if (offset == UART_MCR)
 127                 d->last_mcr = value;
 128
 129         writel(value, p->membase + (offset << p->regshift));
 130
 131         /* Make sure LCR write wasn't ignored */
 132         if (offset == UART_LCR) {
 133                 int tries = 1000;
 134                 while (tries--) {
 135                         if (value == p->serial_in(p, UART_LCR))
 136                                 return;
 137                         dw8250_force_idle(p);
 138                         writel(value, p->membase + (UART_LCR << p->regshift));
 139                 }
 140                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 141         }
 142 }
 143
 144 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 145 {
 146         unsigned int value = readl(p->membase + (offset << p->regshift));
 147
 148         return dw8250_modify_msr(p, offset, value);
 149 }
 150
 151 static int dw8250_handle_irq(struct uart_port *p)
 152 {
 153         struct dw8250_data *d = p->private_data;
 154         unsigned int iir = p->serial_in(p, UART_IIR);
 155
 156         if (serial8250_handle_irq(p, iir)) {
 157                 return 1;
 158         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 159                 /* Clear the USR */
 160                 (void)p->serial_in(p, d->usr_reg);
 161
 162                 return 1;
 163         }
 164
 165         return 0;
 166 }
 167
 168 static void
 169 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 170 {
 171         if (!state)
 172                 pm_runtime_get_sync(port->dev);
 173
 174         serial8250_do_pm(port, state, old);
 175
 176         if (state)
 177                 pm_runtime_put_sync_suspend(port->dev);
 178 }
 179
 180 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
 181 {
 182         struct dw8250_data *data = param;
 183
 184         return chan->chan_id == data->dma.tx_chan_id ||
 185                chan->chan_id == data->dma.rx_chan_id;
 186 }
 187
 188 static void dw8250_setup_port(struct uart_8250_port *up)
 189 {
 190         struct uart_port        *p = &up->port;
 191         u32                     reg = readl(p->membase + DW_UART_UCV);
 192
 193         /*
 194          * If the Component Version Register returns zero, we know that
 195          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 196          */
 197         if (!reg)
 198                 return;
 199
 200         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 201                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 202
 203         reg = readl(p->membase + DW_UART_CPR);
 204         if (!reg)
 205                 return;
 206
 207         /* Select the type based on fifo */
 208         if (reg & DW_UART_CPR_FIFO_MODE) {
 209                 p->type = PORT_16550A;
 210                 p->flags |= UPF_FIXED_TYPE;
 211                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 212                 up->tx_loadsz = p->fifosize;
 213                 up->capabilities = UART_CAP_FIFO;
 214         }
 215
 216         if (reg & DW_UART_CPR_AFCE_MODE)
 217                 up->capabilities |= UART_CAP_AFE;
 218 }
 219
 220 static int dw8250_probe_of(struct uart_port *p,
 221                            struct dw8250_data *data)
 222 {
 223         struct device_node      *np = p->dev->of_node;
 224         u32                     val;
 225         bool has_ucv = true;
 226
 227         if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
 228 #ifdef __BIG_ENDIAN
 229                 /*
 230                  * Low order bits of these 64-bit registers, when
 231                  * accessed as a byte, are 7 bytes further down in the
 232                  * address space in big endian mode.
 233                  */
 234                 p->membase += 7;
 235 #endif
 236                 p->serial_out = dw8250_serial_out_rb;
 237                 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 238                 p->type = PORT_OCTEON;
 239                 data->usr_reg = 0x27;
 240                 has_ucv = false;
 241         } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
 242                 switch (val) {
 243                 case 1:
 244                         break;
 245                 case 4:
 246                         p->iotype = UPIO_MEM32;
 247                         p->serial_in = dw8250_serial_in32;
 248                         p->serial_out = dw8250_serial_out32;
 249                         break;
 250                 default:
 251                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 252                         return -EINVAL;
 253                 }
 254         }
 255         if (has_ucv)
 256                 dw8250_setup_port(container_of(p, struct uart_8250_port, port));
 257
 258         if (!of_property_read_u32(np, "reg-shift", &val))
 259                 p->regshift = val;
 260
 261         /* clock got configured through clk api, all done */
 262         if (p->uartclk)
 263                 return 0;
 264
 265         /* try to find out clock frequency from DT as fallback */
 266         if (of_property_read_u32(np, "clock-frequency", &val)) {
 267                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 268                 return -EINVAL;
 269         }
 270         p->uartclk = val;
 271
 272         return 0;
 273 }
 274
 275 #ifdef CONFIG_ACPI
 276 static int dw8250_probe_acpi(struct uart_8250_port *up,
 277                              struct dw8250_data *data)
 278 {
 279         const struct acpi_device_id *id;
 280         struct uart_port *p = &up->port;
 281
 282         dw8250_setup_port(up);
 283
 284         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 285         if (!id)
 286                 return -ENODEV;
 287
 288         p->iotype = UPIO_MEM32;
 289         p->serial_in = dw8250_serial_in32;
 290         p->serial_out = dw8250_serial_out32;
 291         p->regshift = 2;
 292
 293         if (!p->uartclk)
 294                 p->uartclk = (unsigned int)id->driver_data;
 295
 296         up->dma = &data->dma;
 297
 298         up->dma->rxconf.src_maxburst = p->fifosize / 4;
 299         up->dma->txconf.dst_maxburst = p->fifosize / 4;
 300
 301         return 0;
 302 }
 303 #else
 304 static inline int dw8250_probe_acpi(struct uart_8250_port *up,
 305                                     struct dw8250_data *data)
 306 {
 307         return -ENODEV;
 308 }
 309 #endif /* CONFIG_ACPI */
 310
 311 static int dw8250_probe(struct platform_device *pdev)
 312 {
 313         struct uart_8250_port uart = {};
 314         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 315         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 316         struct dw8250_data *data;
 317         int err;
 318
 319         if (!regs || !irq) {
 320                 dev_err(&pdev->dev, "no registers/irq defined\n");
 321                 return -EINVAL;
 322         }
 323
 324         spin_lock_init(&uart.port.lock);
 325         uart.port.mapbase = regs->start;
 326         uart.port.irq = irq->start;
 327         uart.port.handle_irq = dw8250_handle_irq;
 328         uart.port.pm = dw8250_do_pm;
 329         uart.port.type = PORT_8250;
 330         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 331         uart.port.dev = &pdev->dev;
 332
 333         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 334                                          resource_size(regs));
 335         if (!uart.port.membase)
 336                 return -ENOMEM;
 337
 338         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 339         if (!data)
 340                 return -ENOMEM;
 341
 342         data->usr_reg = DW_UART_USR;
 343         data->clk = devm_clk_get(&pdev->dev, NULL);
 344         if (!IS_ERR(data->clk)) {
 345                 clk_prepare_enable(data->clk);
 346                 uart.port.uartclk = clk_get_rate(data->clk);
 347         }
 348
 349         data->dma.rx_chan_id = -1;
 350         data->dma.tx_chan_id = -1;
 351         data->dma.rx_param = data;
 352         data->dma.tx_param = data;
 353         data->dma.fn = dw8250_dma_filter;
 354
 355         uart.port.iotype = UPIO_MEM;
 356         uart.port.serial_in = dw8250_serial_in;
 357         uart.port.serial_out = dw8250_serial_out;
 358         uart.port.private_data = data;
 359
 360         if (pdev->dev.of_node) {
 361                 err = dw8250_probe_of(&uart.port, data);
 362                 if (err)
 363                         return err;
 364         } else if (ACPI_HANDLE(&pdev->dev)) {
 365                 err = dw8250_probe_acpi(&uart, data);
 366                 if (err)
 367                         return err;
 368         } else {
 369                 return -ENODEV;
 370         }
 371
 372         data->line = serial8250_register_8250_port(&uart);
 373         if (data->line < 0)
 374                 return data->line;
 375
 376         platform_set_drvdata(pdev, data);
 377
 378         pm_runtime_set_active(&pdev->dev);
 379         pm_runtime_enable(&pdev->dev);
 380
 381         return 0;
 382 }
 383
 384 static int dw8250_remove(struct platform_device *pdev)
 385 {
 386         struct dw8250_data *data = platform_get_drvdata(pdev);
 387
 388         pm_runtime_get_sync(&pdev->dev);
 389
 390         serial8250_unregister_port(data->line);
 391
 392         if (!IS_ERR(data->clk))
 393                 clk_disable_unprepare(data->clk);
 394
 395         pm_runtime_disable(&pdev->dev);
 396         pm_runtime_put_noidle(&pdev->dev);
 397
 398         return 0;
 399 }
 400
 401 #ifdef CONFIG_PM
 402 static int dw8250_suspend(struct device *dev)
 403 {
 404         struct dw8250_data *data = dev_get_drvdata(dev);
 405
 406         serial8250_suspend_port(data->line);
 407
 408         return 0;
 409 }
 410
 411 static int dw8250_resume(struct device *dev)
 412 {
 413         struct dw8250_data *data = dev_get_drvdata(dev);
 414
 415         serial8250_resume_port(data->line);
 416
 417         return 0;
 418 }
 419 #endif /* CONFIG_PM */
 420
 421 #ifdef CONFIG_PM_RUNTIME
 422 static int dw8250_runtime_suspend(struct device *dev)
 423 {
 424         struct dw8250_data *data = dev_get_drvdata(dev);
 425
 426         if (!IS_ERR(data->clk))
 427                 clk_disable_unprepare(data->clk);
 428
 429         return 0;
 430 }
 431
 432 static int dw8250_runtime_resume(struct device *dev)
 433 {
 434         struct dw8250_data *data = dev_get_drvdata(dev);
 435
 436         if (!IS_ERR(data->clk))
 437                 clk_prepare_enable(data->clk);
 438
 439         return 0;
 440 }
 441 #endif
 442
 443 static const struct dev_pm_ops dw8250_pm_ops = {
 444         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 445         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 446 };
 447
 448 static const struct of_device_id dw8250_of_match[] = {
 449         { .compatible = "snps,dw-apb-uart" },
 450         { .compatible = "cavium,octeon-3860-uart" },
 451         { /* Sentinel */ }
 452 };
 453 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 454
 455 static const struct acpi_device_id dw8250_acpi_match[] = {
 456         { "INT33C4", 0 },
 457         { "INT33C5", 0 },
 458         { "80860F0A", 0 },
 459         { },
 460 };
 461 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 462
 463 static struct platform_driver dw8250_platform_driver = {
 464         .driver = {
 465                 .name           = "dw-apb-uart",
 466                 .owner          = THIS_MODULE,
 467                 .pm             = &dw8250_pm_ops,
 468                 .of_match_table = dw8250_of_match,
 469                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 470         },
 471         .probe                  = dw8250_probe,
 472         .remove                 = dw8250_remove,
 473 };
 474
 475 module_platform_driver(dw8250_platform_driver);
 476
 477 MODULE_AUTHOR("Jamie Iles");
 478 MODULE_LICENSE("GPL");
 479 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");