drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24 #include <linux/rational.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_data/dma-dw.h>
  31
  32 #include "8250.h"
  33
  34 /*
  35  * init function returns:
  36  *  > 0 - number of ports
  37  *  = 0 - use board->num_ports
  38  *  < 0 - error
  39  */
  40 struct pci_serial_quirk {
  41         u32     vendor;
  42         u32     device;
  43         u32     subvendor;
  44         u32     subdevice;
  45         int     (*probe)(struct pci_dev *dev);
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *,
  48                          const struct pciserial_board *,
  49                          struct uart_8250_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static int pci_default_setup(struct serial_private*,
  64           const struct pciserial_board*, struct uart_8250_port *, int);
  65
  66 static void moan_device(const char *str, struct pci_dev *dev)
  67 {
  68         dev_err(&dev->dev,
  69                "%s: %s\n"
  70                "Please send the output of lspci -vv, this\n"
  71                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  72                "manufacturer and name of serial board or\n"
  73                "modem board to <linux-serial@vger.kernel.org>.\n",
  74                pci_name(dev), str, dev->vendor, dev->device,
  75                dev->subsystem_vendor, dev->subsystem_device);
  76 }
  77
  78 static int
  79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  80            int bar, int offset, int regshift)
  81 {
  82         struct pci_dev *dev = priv->dev;
  83
  84         if (bar >= PCI_NUM_BAR_RESOURCES)
  85                 return -EINVAL;
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->port.iotype = UPIO_MEM;
  94                 port->port.iobase = 0;
  95                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
  96                 port->port.membase = priv->remapped_bar[bar] + offset;
  97                 port->port.regshift = regshift;
  98         } else {
  99                 port->port.iotype = UPIO_PORT;
 100                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 101                 port->port.mapbase = 0;
 102                 port->port.membase = NULL;
 103                 port->port.regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 110  */
 111 static int addidata_apci7800_setup(struct serial_private *priv,
 112                                 const struct pciserial_board *board,
 113                                 struct uart_8250_port *port, int idx)
 114 {
 115         unsigned int bar = 0, offset = board->first_offset;
 116         bar = FL_GET_BASE(board->flags);
 117
 118         if (idx < 2) {
 119                 offset += idx * board->uart_offset;
 120         } else if ((idx >= 2) && (idx < 4)) {
 121                 bar += 1;
 122                 offset += ((idx - 2) * board->uart_offset);
 123         } else if ((idx >= 4) && (idx < 6)) {
 124                 bar += 2;
 125                 offset += ((idx - 4) * board->uart_offset);
 126         } else if (idx >= 6) {
 127                 bar += 3;
 128                 offset += ((idx - 6) * board->uart_offset);
 129         }
 130
 131         return setup_port(priv, port, bar, offset, board->reg_shift);
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 140               struct uart_8250_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(priv, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct serial_private *priv,
 194                 const struct pciserial_board *board,
 195                 struct uart_8250_port *port, int idx)
 196 {
 197         unsigned int offset = board->first_offset;
 198         unsigned int bar = FL_GET_BASE(board->flags);
 199
 200         switch (priv->dev->subsystem_device) {
 201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 202                 if (idx == 3)
 203                         idx++;
 204                 break;
 205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 206                 if (idx > 0)
 207                         idx++;
 208                 if (idx > 2)
 209                         idx++;
 210                 break;
 211         }
 212         if (idx > 2)
 213                 offset = 0x18;
 214
 215         offset += idx * board->uart_offset;
 216
 217         return setup_port(priv, port, bar, offset, board->reg_shift);
 218 }
 219
 220 /*
 221  * Added for EKF Intel i960 serial boards
 222  */
 223 static int pci_inteli960ni_init(struct pci_dev *dev)
 224 {
 225         u32 oldval;
 226
 227         if (!(dev->subsystem_device & 0x1000))
 228                 return -ENODEV;
 229
 230         /* is firmware started? */
 231         pci_read_config_dword(dev, 0x44, &oldval);
 232         if (oldval == 0x00001000L) { /* RESET value */
 233                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 234                 return -ENODEV;
 235         }
 236         return 0;
 237 }
 238
 239 /*
 240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 241  * that the card interrupt be explicitly enabled or disabled.  This
 242  * seems to be mainly needed on card using the PLX which also use I/O
 243  * mapped memory.
 244  */
 245 static int pci_plx9050_init(struct pci_dev *dev)
 246 {
 247         u8 irq_config;
 248         void __iomem *p;
 249
 250         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 251                 moan_device("no memory in bar 0", dev);
 252                 return 0;
 253         }
 254
 255         irq_config = 0x41;
 256         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 257             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 258                 irq_config = 0x43;
 259
 260         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 261             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 262                 /*
 263                  * As the megawolf cards have the int pins active
 264                  * high, and have 2 UART chips, both ints must be
 265                  * enabled on the 9050. Also, the UARTS are set in
 266                  * 16450 mode by default, so we have to enable the
 267                  * 16C950 'enhanced' mode so that we can use the
 268                  * deep FIFOs
 269                  */
 270                 irq_config = 0x5b;
 271         /*
 272          * enable/disable interrupts
 273          */
 274         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 275         if (p == NULL)
 276                 return -ENOMEM;
 277         writel(irq_config, p + 0x4c);
 278
 279         /*
 280          * Read the register back to ensure that it took effect.
 281          */
 282         readl(p + 0x4c);
 283         iounmap(p);
 284
 285         return 0;
 286 }
 287
 288 static void pci_plx9050_exit(struct pci_dev *dev)
 289 {
 290         u8 __iomem *p;
 291
 292         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 293                 return;
 294
 295         /*
 296          * disable interrupts
 297          */
 298         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 299         if (p != NULL) {
 300                 writel(0, p + 0x4c);
 301
 302                 /*
 303                  * Read the register back to ensure that it took effect.
 304                  */
 305                 readl(p + 0x4c);
 306                 iounmap(p);
 307         }
 308 }
 309
 310 #define NI8420_INT_ENABLE_REG   0x38
 311 #define NI8420_INT_ENABLE_BIT   0x2000
 312
 313 static void pci_ni8420_exit(struct pci_dev *dev)
 314 {
 315         void __iomem *p;
 316         unsigned int bar = 0;
 317
 318         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 319                 moan_device("no memory in bar", dev);
 320                 return;
 321         }
 322
 323         p = pci_ioremap_bar(dev, bar);
 324         if (p == NULL)
 325                 return;
 326
 327         /* Disable the CPU Interrupt */
 328         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 329                p + NI8420_INT_ENABLE_REG);
 330         iounmap(p);
 331 }
 332
 333
 334 /* MITE registers */
 335 #define MITE_IOWBSR1    0xc4
 336 #define MITE_IOWCR1     0xf4
 337 #define MITE_LCIMR1     0x08
 338 #define MITE_LCIMR2     0x10
 339
 340 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 341
 342 static void pci_ni8430_exit(struct pci_dev *dev)
 343 {
 344         void __iomem *p;
 345         unsigned int bar = 0;
 346
 347         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 348                 moan_device("no memory in bar", dev);
 349                 return;
 350         }
 351
 352         p = pci_ioremap_bar(dev, bar);
 353         if (p == NULL)
 354                 return;
 355
 356         /* Disable the CPU Interrupt */
 357         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 358         iounmap(p);
 359 }
 360
 361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 362 static int
 363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 364                 struct uart_8250_port *port, int idx)
 365 {
 366         unsigned int bar, offset = board->first_offset;
 367
 368         bar = 0;
 369
 370         if (idx < 4) {
 371                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 372                 offset += idx * board->uart_offset;
 373         } else if (idx < 8) {
 374                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 375                 offset += idx * board->uart_offset + 0xC00;
 376         } else /* we have only 8 ports on PMC-OCTALPRO */
 377                 return 1;
 378
 379         return setup_port(priv, port, bar, offset, board->reg_shift);
 380 }
 381
 382 /*
 383 * This does initialization for PMC OCTALPRO cards:
 384 * maps the device memory, resets the UARTs (needed, bc
 385 * if the module is removed and inserted again, the card
 386 * is in the sleep mode) and enables global interrupt.
 387 */
 388
 389 /* global control register offset for SBS PMC-OctalPro */
 390 #define OCT_REG_CR_OFF          0x500
 391
 392 static int sbs_init(struct pci_dev *dev)
 393 {
 394         u8 __iomem *p;
 395
 396         p = pci_ioremap_bar(dev, 0);
 397
 398         if (p == NULL)
 399                 return -ENOMEM;
 400         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 401         writeb(0x10, p + OCT_REG_CR_OFF);
 402         udelay(50);
 403         writeb(0x0, p + OCT_REG_CR_OFF);
 404
 405         /* Set bit-2 (INTENABLE) of Control Register */
 406         writeb(0x4, p + OCT_REG_CR_OFF);
 407         iounmap(p);
 408
 409         return 0;
 410 }
 411
 412 /*
 413  * Disables the global interrupt of PMC-OctalPro
 414  */
 415
 416 static void sbs_exit(struct pci_dev *dev)
 417 {
 418         u8 __iomem *p;
 419
 420         p = pci_ioremap_bar(dev, 0);
 421         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 422         if (p != NULL)
 423                 writeb(0, p + OCT_REG_CR_OFF);
 424         iounmap(p);
 425 }
 426
 427 /*
 428  * SIIG serial cards have an PCI interface chip which also controls
 429  * the UART clocking frequency. Each UART can be clocked independently
 430  * (except cards equipped with 4 UARTs) and initial clocking settings
 431  * are stored in the EEPROM chip. It can cause problems because this
 432  * version of serial driver doesn't support differently clocked UART's
 433  * on single PCI card. To prevent this, initialization functions set
 434  * high frequency clocking for all UART's on given card. It is safe (I
 435  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 436  * with other OSes (like M$ DOS).
 437  *
 438  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 439  *
 440  * There is two family of SIIG serial cards with different PCI
 441  * interface chip and different configuration methods:
 442  *     - 10x cards have control registers in IO and/or memory space;
 443  *     - 20x cards have control registers in standard PCI configuration space.
 444  *
 445  * Note: all 10x cards have PCI device ids 0x10..
 446  *       all 20x cards have PCI device ids 0x20..
 447  *
 448  * There are also Quartet Serial cards which use Oxford Semiconductor
 449  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 450  *
 451  * Note: some SIIG cards are probed by the parport_serial object.
 452  */
 453
 454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 456
 457 static int pci_siig10x_init(struct pci_dev *dev)
 458 {
 459         u16 data;
 460         void __iomem *p;
 461
 462         switch (dev->device & 0xfff8) {
 463         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 464                 data = 0xffdf;
 465                 break;
 466         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 467                 data = 0xf7ff;
 468                 break;
 469         default:                        /* 1S1P, 4S */
 470                 data = 0xfffb;
 471                 break;
 472         }
 473
 474         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 475         if (p == NULL)
 476                 return -ENOMEM;
 477
 478         writew(readw(p + 0x28) & data, p + 0x28);
 479         readw(p + 0x28);
 480         iounmap(p);
 481         return 0;
 482 }
 483
 484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 486
 487 static int pci_siig20x_init(struct pci_dev *dev)
 488 {
 489         u8 data;
 490
 491         /* Change clock frequency for the first UART. */
 492         pci_read_config_byte(dev, 0x6f, &data);
 493         pci_write_config_byte(dev, 0x6f, data & 0xef);
 494
 495         /* If this card has 2 UART, we have to do the same with second UART. */
 496         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 497             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 498                 pci_read_config_byte(dev, 0x73, &data);
 499                 pci_write_config_byte(dev, 0x73, data & 0xef);
 500         }
 501         return 0;
 502 }
 503
 504 static int pci_siig_init(struct pci_dev *dev)
 505 {
 506         unsigned int type = dev->device & 0xff00;
 507
 508         if (type == 0x1000)
 509                 return pci_siig10x_init(dev);
 510         else if (type == 0x2000)
 511                 return pci_siig20x_init(dev);
 512
 513         moan_device("Unknown SIIG card", dev);
 514         return -ENODEV;
 515 }
 516
 517 static int pci_siig_setup(struct serial_private *priv,
 518                           const struct pciserial_board *board,
 519                           struct uart_8250_port *port, int idx)
 520 {
 521         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 522
 523         if (idx > 3) {
 524                 bar = 4;
 525                 offset = (idx - 4) * 8;
 526         }
 527
 528         return setup_port(priv, port, bar, offset, 0);
 529 }
 530
 531 /*
 532  * Timedia has an explosion of boards, and to avoid the PCI table from
 533  * growing *huge*, we use this function to collapse some 70 entries
 534  * in the PCI table into one, for sanity's and compactness's sake.
 535  */
 536 static const unsigned short timedia_single_port[] = {
 537         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 538 };
 539
 540 static const unsigned short timedia_dual_port[] = {
 541         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 542         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 543         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 544         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 545         0xD079, 0
 546 };
 547
 548 static const unsigned short timedia_quad_port[] = {
 549         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 550         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 551         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 552         0xB157, 0
 553 };
 554
 555 static const unsigned short timedia_eight_port[] = {
 556         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 557         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 558 };
 559
 560 static const struct timedia_struct {
 561         int num;
 562         const unsigned short *ids;
 563 } timedia_data[] = {
 564         { 1, timedia_single_port },
 565         { 2, timedia_dual_port },
 566         { 4, timedia_quad_port },
 567         { 8, timedia_eight_port }
 568 };
 569
 570 /*
 571  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 572  * listing them individually, this driver merely grabs them all with
 573  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 574  * and should be left free to be claimed by parport_serial instead.
 575  */
 576 static int pci_timedia_probe(struct pci_dev *dev)
 577 {
 578         /*
 579          * Check the third digit of the subdevice ID
 580          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 581          */
 582         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 583                 dev_info(&dev->dev,
 584                         "ignoring Timedia subdevice %04x for parport_serial\n",
 585                         dev->subsystem_device);
 586                 return -ENODEV;
 587         }
 588
 589         return 0;
 590 }
 591
 592 static int pci_timedia_init(struct pci_dev *dev)
 593 {
 594         const unsigned short *ids;
 595         int i, j;
 596
 597         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 598                 ids = timedia_data[i].ids;
 599                 for (j = 0; ids[j]; j++)
 600                         if (dev->subsystem_device == ids[j])
 601                                 return timedia_data[i].num;
 602         }
 603         return 0;
 604 }
 605
 606 /*
 607  * Timedia/SUNIX uses a mixture of BARs and offsets
 608  * Ugh, this is ugly as all hell --- TYT
 609  */
 610 static int
 611 pci_timedia_setup(struct serial_private *priv,
 612                   const struct pciserial_board *board,
 613                   struct uart_8250_port *port, int idx)
 614 {
 615         unsigned int bar = 0, offset = board->first_offset;
 616
 617         switch (idx) {
 618         case 0:
 619                 bar = 0;
 620                 break;
 621         case 1:
 622                 offset = board->uart_offset;
 623                 bar = 0;
 624                 break;
 625         case 2:
 626                 bar = 1;
 627                 break;
 628         case 3:
 629                 offset = board->uart_offset;
 630                 /* FALLTHROUGH */
 631         case 4: /* BAR 2 */
 632         case 5: /* BAR 3 */
 633         case 6: /* BAR 4 */
 634         case 7: /* BAR 5 */
 635                 bar = idx - 2;
 636         }
 637
 638         return setup_port(priv, port, bar, offset, board->reg_shift);
 639 }
 640
 641 /*
 642  * Some Titan cards are also a little weird
 643  */
 644 static int
 645 titan_400l_800l_setup(struct serial_private *priv,
 646                       const struct pciserial_board *board,
 647                       struct uart_8250_port *port, int idx)
 648 {
 649         unsigned int bar, offset = board->first_offset;
 650
 651         switch (idx) {
 652         case 0:
 653                 bar = 1;
 654                 break;
 655         case 1:
 656                 bar = 2;
 657                 break;
 658         default:
 659                 bar = 4;
 660                 offset = (idx - 2) * board->uart_offset;
 661         }
 662
 663         return setup_port(priv, port, bar, offset, board->reg_shift);
 664 }
 665
 666 static int pci_xircom_init(struct pci_dev *dev)
 667 {
 668         msleep(100);
 669         return 0;
 670 }
 671
 672 static int pci_ni8420_init(struct pci_dev *dev)
 673 {
 674         void __iomem *p;
 675         unsigned int bar = 0;
 676
 677         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 678                 moan_device("no memory in bar", dev);
 679                 return 0;
 680         }
 681
 682         p = pci_ioremap_bar(dev, bar);
 683         if (p == NULL)
 684                 return -ENOMEM;
 685
 686         /* Enable CPU Interrupt */
 687         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 688                p + NI8420_INT_ENABLE_REG);
 689
 690         iounmap(p);
 691         return 0;
 692 }
 693
 694 #define MITE_IOWBSR1_WSIZE      0xa
 695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 696 #define MITE_IOWBSR1_WENAB      (1 << 7)
 697 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 698 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 700
 701 static int pci_ni8430_init(struct pci_dev *dev)
 702 {
 703         void __iomem *p;
 704         struct pci_bus_region region;
 705         u32 device_window;
 706         unsigned int bar = 0;
 707
 708         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 709                 moan_device("no memory in bar", dev);
 710                 return 0;
 711         }
 712
 713         p = pci_ioremap_bar(dev, bar);
 714         if (p == NULL)
 715                 return -ENOMEM;
 716
 717         /*
 718          * Set device window address and size in BAR0, while acknowledging that
 719          * the resource structure may contain a translated address that differs
 720          * from the address the device responds to.
 721          */
 722         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 723         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 724                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 725         writel(device_window, p + MITE_IOWBSR1);
 726
 727         /* Set window access to go to RAMSEL IO address space */
 728         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 729                p + MITE_IOWCR1);
 730
 731         /* Enable IO Bus Interrupt 0 */
 732         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 733
 734         /* Enable CPU Interrupt */
 735         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 736
 737         iounmap(p);
 738         return 0;
 739 }
 740
 741 /* UART Port Control Register */
 742 #define NI8430_PORTCON  0x0f
 743 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 744
 745 static int
 746 pci_ni8430_setup(struct serial_private *priv,
 747                  const struct pciserial_board *board,
 748                  struct uart_8250_port *port, int idx)
 749 {
 750         struct pci_dev *dev = priv->dev;
 751         void __iomem *p;
 752         unsigned int bar, offset = board->first_offset;
 753
 754         if (idx >= board->num_ports)
 755                 return 1;
 756
 757         bar = FL_GET_BASE(board->flags);
 758         offset += idx * board->uart_offset;
 759
 760         p = pci_ioremap_bar(dev, bar);
 761         if (!p)
 762                 return -ENOMEM;
 763
 764         /* enable the transceiver */
 765         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 766                p + offset + NI8430_PORTCON);
 767
 768         iounmap(p);
 769
 770         return setup_port(priv, port, bar, offset, board->reg_shift);
 771 }
 772
 773 static int pci_netmos_9900_setup(struct serial_private *priv,
 774                                 const struct pciserial_board *board,
 775                                 struct uart_8250_port *port, int idx)
 776 {
 777         unsigned int bar;
 778
 779         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 780             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 781                 /* netmos apparently orders BARs by datasheet layout, so serial
 782                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 783                  */
 784                 bar = 3 * idx;
 785
 786                 return setup_port(priv, port, bar, 0, board->reg_shift);
 787         } else {
 788                 return pci_default_setup(priv, board, port, idx);
 789         }
 790 }
 791
 792 /* the 99xx series comes with a range of device IDs and a variety
 793  * of capabilities:
 794  *
 795  * 9900 has varying capabilities and can cascade to sub-controllers
 796  *   (cascading should be purely internal)
 797  * 9904 is hardwired with 4 serial ports
 798  * 9912 and 9922 are hardwired with 2 serial ports
 799  */
 800 static int pci_netmos_9900_numports(struct pci_dev *dev)
 801 {
 802         unsigned int c = dev->class;
 803         unsigned int pi;
 804         unsigned short sub_serports;
 805
 806         pi = c & 0xff;
 807
 808         if (pi == 2)
 809                 return 1;
 810
 811         if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 812                 /* two possibilities: 0x30ps encodes number of parallel and
 813                  * serial ports, or 0x1000 indicates *something*. This is not
 814                  * immediately obvious, since the 2s1p+4s configuration seems
 815                  * to offer all functionality on functions 0..2, while still
 816                  * advertising the same function 3 as the 4s+2s1p config.
 817                  */
 818                 sub_serports = dev->subsystem_device & 0xf;
 819                 if (sub_serports > 0)
 820                         return sub_serports;
 821
 822                 dev_err(&dev->dev,
 823                         "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 824                 return 0;
 825         }
 826
 827         moan_device("unknown NetMos/Mostech program interface", dev);
 828         return 0;
 829 }
 830
 831 static int pci_netmos_init(struct pci_dev *dev)
 832 {
 833         /* subdevice 0x00PS means <P> parallel, <S> serial */
 834         unsigned int num_serial = dev->subsystem_device & 0xf;
 835
 836         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 837                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 838                 return 0;
 839
 840         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 841                         dev->subsystem_device == 0x0299)
 842                 return 0;
 843
 844         switch (dev->device) { /* FALLTHROUGH on all */
 845         case PCI_DEVICE_ID_NETMOS_9904:
 846         case PCI_DEVICE_ID_NETMOS_9912:
 847         case PCI_DEVICE_ID_NETMOS_9922:
 848         case PCI_DEVICE_ID_NETMOS_9900:
 849                 num_serial = pci_netmos_9900_numports(dev);
 850                 break;
 851
 852         default:
 853                 break;
 854         }
 855
 856         if (num_serial == 0) {
 857                 moan_device("unknown NetMos/Mostech device", dev);
 858                 return -ENODEV;
 859         }
 860
 861         return num_serial;
 862 }
 863
 864 /*
 865  * These chips are available with optionally one parallel port and up to
 866  * two serial ports. Unfortunately they all have the same product id.
 867  *
 868  * Basic configuration is done over a region of 32 I/O ports. The base
 869  * ioport is called INTA or INTC, depending on docs/other drivers.
 870  *
 871  * The region of the 32 I/O ports is configured in POSIO0R...
 872  */
 873
 874 /* registers */
 875 #define ITE_887x_MISCR          0x9c
 876 #define ITE_887x_INTCBAR        0x78
 877 #define ITE_887x_UARTBAR        0x7c
 878 #define ITE_887x_PS0BAR         0x10
 879 #define ITE_887x_POSIO0         0x60
 880
 881 /* I/O space size */
 882 #define ITE_887x_IOSIZE         32
 883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 884 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 886 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 888 #define ITE_887x_POSIO_SPEED            (3 << 29)
 889 /* enable IO_Space bit */
 890 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 891
 892 static int pci_ite887x_init(struct pci_dev *dev)
 893 {
 894         /* inta_addr are the configuration addresses of the ITE */
 895         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 896                                                         0x200, 0x280, 0 };
 897         int ret, i, type;
 898         struct resource *iobase = NULL;
 899         u32 miscr, uartbar, ioport;
 900
 901         /* search for the base-ioport */
 902         i = 0;
 903         while (inta_addr[i] && iobase == NULL) {
 904                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 905                                                                 "ite887x");
 906                 if (iobase != NULL) {
 907                         /* write POSIO0R - speed | size | ioport */
 908                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 909                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 910                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 911                         /* write INTCBAR - ioport */
 912                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 913                                                                 inta_addr[i]);
 914                         ret = inb(inta_addr[i]);
 915                         if (ret != 0xff) {
 916                                 /* ioport connected */
 917                                 break;
 918                         }
 919                         release_region(iobase->start, ITE_887x_IOSIZE);
 920                         iobase = NULL;
 921                 }
 922                 i++;
 923         }
 924
 925         if (!inta_addr[i]) {
 926                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 927                 return -ENODEV;
 928         }
 929
 930         /* start of undocumented type checking (see parport_pc.c) */
 931         type = inb(iobase->start + 0x18) & 0x0f;
 932
 933         switch (type) {
 934         case 0x2:       /* ITE8871 (1P) */
 935         case 0xa:       /* ITE8875 (1P) */
 936                 ret = 0;
 937                 break;
 938         case 0xe:       /* ITE8872 (2S1P) */
 939                 ret = 2;
 940                 break;
 941         case 0x6:       /* ITE8873 (1S) */
 942                 ret = 1;
 943                 break;
 944         case 0x8:       /* ITE8874 (2S) */
 945                 ret = 2;
 946                 break;
 947         default:
 948                 moan_device("Unknown ITE887x", dev);
 949                 ret = -ENODEV;
 950         }
 951
 952         /* configure all serial ports */
 953         for (i = 0; i < ret; i++) {
 954                 /* read the I/O port from the device */
 955                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 956                                                                 &ioport);
 957                 ioport &= 0x0000FF00;   /* the actual base address */
 958                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 959                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 960                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 961
 962                 /* write the ioport to the UARTBAR */
 963                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 964                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 965                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 966                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 967
 968                 /* get current config */
 969                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 970                 /* disable interrupts (UARTx_Routing[3:0]) */
 971                 miscr &= ~(0xf << (12 - 4 * i));
 972                 /* activate the UART (UARTx_En) */
 973                 miscr |= 1 << (23 - i);
 974                 /* write new config with activated UART */
 975                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 976         }
 977
 978         if (ret <= 0) {
 979                 /* the device has no UARTs if we get here */
 980                 release_region(iobase->start, ITE_887x_IOSIZE);
 981         }
 982
 983         return ret;
 984 }
 985
 986 static void pci_ite887x_exit(struct pci_dev *dev)
 987 {
 988         u32 ioport;
 989         /* the ioport is bit 0-15 in POSIO0R */
 990         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 991         ioport &= 0xffff;
 992         release_region(ioport, ITE_887x_IOSIZE);
 993 }
 994
 995 /*
 996  * EndRun Technologies.
 997  * Determine the number of ports available on the device.
 998  */
 999 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1001
1002 static int pci_endrun_init(struct pci_dev *dev)
1003 {
1004         u8 __iomem *p;
1005         unsigned long deviceID;
1006         unsigned int  number_uarts = 0;
1007
1008         /* EndRun device is all 0xexxx */
1009         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010                 (dev->device & 0xf000) != 0xe000)
1011                 return 0;
1012
1013         p = pci_iomap(dev, 0, 5);
1014         if (p == NULL)
1015                 return -ENOMEM;
1016
1017         deviceID = ioread32(p);
1018         /* EndRun device */
1019         if (deviceID == 0x07000200) {
1020                 number_uarts = ioread8(p + 4);
1021                 dev_dbg(&dev->dev,
1022                         "%d ports detected on EndRun PCI Express device\n",
1023                         number_uarts);
1024         }
1025         pci_iounmap(dev, p);
1026         return number_uarts;
1027 }
1028
1029 /*
1030  * Oxford Semiconductor Inc.
1031  * Check that device is part of the Tornado range of devices, then determine
1032  * the number of ports available on the device.
1033  */
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1035 {
1036         u8 __iomem *p;
1037         unsigned long deviceID;
1038         unsigned int  number_uarts = 0;
1039
1040         /* OxSemi Tornado devices are all 0xCxxx */
1041         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042             (dev->device & 0xF000) != 0xC000)
1043                 return 0;
1044
1045         p = pci_iomap(dev, 0, 5);
1046         if (p == NULL)
1047                 return -ENOMEM;
1048
1049         deviceID = ioread32(p);
1050         /* Tornado device */
1051         if (deviceID == 0x07000200) {
1052                 number_uarts = ioread8(p + 4);
1053                 dev_dbg(&dev->dev,
1054                         "%d ports detected on Oxford PCI Express device\n",
1055                         number_uarts);
1056         }
1057         pci_iounmap(dev, p);
1058         return number_uarts;
1059 }
1060
1061 static int pci_asix_setup(struct serial_private *priv,
1062                   const struct pciserial_board *board,
1063                   struct uart_8250_port *port, int idx)
1064 {
1065         port->bugs |= UART_BUG_PARITY;
1066         return pci_default_setup(priv, board, port, idx);
1067 }
1068
1069 /* Quatech devices have their own extra interface features */
1070
1071 struct quatech_feature {
1072         u16 devid;
1073         bool amcc;
1074 };
1075
1076 #define QPCR_TEST_FOR1          0x3F
1077 #define QPCR_TEST_GET1          0x00
1078 #define QPCR_TEST_FOR2          0x40
1079 #define QPCR_TEST_GET2          0x40
1080 #define QPCR_TEST_FOR3          0x80
1081 #define QPCR_TEST_GET3          0x40
1082 #define QPCR_TEST_FOR4          0xC0
1083 #define QPCR_TEST_GET4          0x80
1084
1085 #define QOPR_CLOCK_X1           0x0000
1086 #define QOPR_CLOCK_X2           0x0001
1087 #define QOPR_CLOCK_X4           0x0002
1088 #define QOPR_CLOCK_X8           0x0003
1089 #define QOPR_CLOCK_RATE_MASK    0x0003
1090
1091
1092 static struct quatech_feature quatech_cards[] = {
1093         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1094         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1096         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1098         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1100         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1101         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1103         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1112         { 0, }
1113 };
1114
1115 static int pci_quatech_amcc(u16 devid)
1116 {
1117         struct quatech_feature *qf = &quatech_cards[0];
1118         while (qf->devid) {
1119                 if (qf->devid == devid)
1120                         return qf->amcc;
1121                 qf++;
1122         }
1123         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1124         return 0;
1125 };
1126
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1128 {
1129         unsigned long base = port->port.iobase;
1130         u8 LCR, val;
1131
1132         LCR = inb(base + UART_LCR);
1133         outb(0xBF, base + UART_LCR);
1134         val = inb(base + UART_SCR);
1135         outb(LCR, base + UART_LCR);
1136         return val;
1137 }
1138
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1140 {
1141         unsigned long base = port->port.iobase;
1142         u8 LCR, val;
1143
1144         LCR = inb(base + UART_LCR);
1145         outb(0xBF, base + UART_LCR);
1146         val = inb(base + UART_SCR);
1147         outb(qopr, base + UART_SCR);
1148         outb(LCR, base + UART_LCR);
1149 }
1150
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1152 {
1153         unsigned long base = port->port.iobase;
1154         u8 LCR, val, qmcr;
1155
1156         LCR = inb(base + UART_LCR);
1157         outb(0xBF, base + UART_LCR);
1158         val = inb(base + UART_SCR);
1159         outb(val | 0x10, base + UART_SCR);
1160         qmcr = inb(base + UART_MCR);
1161         outb(val, base + UART_SCR);
1162         outb(LCR, base + UART_LCR);
1163
1164         return qmcr;
1165 }
1166
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1168 {
1169         unsigned long base = port->port.iobase;
1170         u8 LCR, val;
1171
1172         LCR = inb(base + UART_LCR);
1173         outb(0xBF, base + UART_LCR);
1174         val = inb(base + UART_SCR);
1175         outb(val | 0x10, base + UART_SCR);
1176         outb(qmcr, base + UART_MCR);
1177         outb(val, base + UART_SCR);
1178         outb(LCR, base + UART_LCR);
1179 }
1180
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1182 {
1183         unsigned long base = port->port.iobase;
1184         u8 LCR, val;
1185
1186         LCR = inb(base + UART_LCR);
1187         outb(0xBF, base + UART_LCR);
1188         val = inb(base + UART_SCR);
1189         if (val & 0x20) {
1190                 outb(0x80, UART_LCR);
1191                 if (!(inb(UART_SCR) & 0x20)) {
1192                         outb(LCR, base + UART_LCR);
1193                         return 1;
1194                 }
1195         }
1196         return 0;
1197 }
1198
1199 static int pci_quatech_test(struct uart_8250_port *port)
1200 {
1201         u8 reg, qopr;
1202
1203         qopr = pci_quatech_rqopr(port);
1204         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205         reg = pci_quatech_rqopr(port) & 0xC0;
1206         if (reg != QPCR_TEST_GET1)
1207                 return -EINVAL;
1208         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209         reg = pci_quatech_rqopr(port) & 0xC0;
1210         if (reg != QPCR_TEST_GET2)
1211                 return -EINVAL;
1212         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213         reg = pci_quatech_rqopr(port) & 0xC0;
1214         if (reg != QPCR_TEST_GET3)
1215                 return -EINVAL;
1216         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217         reg = pci_quatech_rqopr(port) & 0xC0;
1218         if (reg != QPCR_TEST_GET4)
1219                 return -EINVAL;
1220
1221         pci_quatech_wqopr(port, qopr);
1222         return 0;
1223 }
1224
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227         u8 qopr, reg, set;
1228         unsigned long clock;
1229
1230         if (pci_quatech_test(port) < 0)
1231                 return 1843200;
1232
1233         qopr = pci_quatech_rqopr(port);
1234
1235         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236         reg = pci_quatech_rqopr(port);
1237         if (reg & QOPR_CLOCK_X8) {
1238                 clock = 1843200;
1239                 goto out;
1240         }
1241         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (!(reg & QOPR_CLOCK_X8)) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         reg &= QOPR_CLOCK_X8;
1248         if (reg == QOPR_CLOCK_X2) {
1249                 clock =  3685400;
1250                 set = QOPR_CLOCK_X2;
1251         } else if (reg == QOPR_CLOCK_X4) {
1252                 clock = 7372800;
1253                 set = QOPR_CLOCK_X4;
1254         } else if (reg == QOPR_CLOCK_X8) {
1255                 clock = 14745600;
1256                 set = QOPR_CLOCK_X8;
1257         } else {
1258                 clock = 1843200;
1259                 set = QOPR_CLOCK_X1;
1260         }
1261         qopr &= ~QOPR_CLOCK_RATE_MASK;
1262         qopr |= set;
1263
1264 out:
1265         pci_quatech_wqopr(port, qopr);
1266         return clock;
1267 }
1268
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271         u8 qmcr;
1272         int rs422 = 0;
1273
1274         if (!pci_quatech_has_qmcr(port))
1275                 return 0;
1276         qmcr = pci_quatech_rqmcr(port);
1277         pci_quatech_wqmcr(port, 0xFF);
1278         if (pci_quatech_rqmcr(port))
1279                 rs422 = 1;
1280         pci_quatech_wqmcr(port, qmcr);
1281         return rs422;
1282 }
1283
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286         if (pci_quatech_amcc(dev->device)) {
1287                 unsigned long base = pci_resource_start(dev, 0);
1288                 if (base) {
1289                         u32 tmp;
1290
1291                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1292                         tmp = inl(base + 0x3c);
1293                         outl(tmp | 0x01000000, base + 0x3c);
1294                         outl(tmp &= ~0x01000000, base + 0x3c);
1295                 }
1296         }
1297         return 0;
1298 }
1299
1300 static int pci_quatech_setup(struct serial_private *priv,
1301                   const struct pciserial_board *board,
1302                   struct uart_8250_port *port, int idx)
1303 {
1304         /* Needed by pci_quatech calls below */
1305         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1306         /* Set up the clocking */
1307         port->port.uartclk = pci_quatech_clock(port);
1308         /* For now just warn about RS422 */
1309         if (pci_quatech_rs422(port))
1310                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1311         return pci_default_setup(priv, board, port, idx);
1312 }
1313
1314 static void pci_quatech_exit(struct pci_dev *dev)
1315 {
1316 }
1317
1318 static int pci_default_setup(struct serial_private *priv,
1319                   const struct pciserial_board *board,
1320                   struct uart_8250_port *port, int idx)
1321 {
1322         unsigned int bar, offset = board->first_offset, maxnr;
1323
1324         bar = FL_GET_BASE(board->flags);
1325         if (board->flags & FL_BASE_BARS)
1326                 bar += idx;
1327         else
1328                 offset += idx * board->uart_offset;
1329
1330         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1331                 (board->reg_shift + 3);
1332
1333         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1334                 return 1;
1335
1336         return setup_port(priv, port, bar, offset, board->reg_shift);
1337 }
1338
1339 static int
1340 ce4100_serial_setup(struct serial_private *priv,
1341                   const struct pciserial_board *board,
1342                   struct uart_8250_port *port, int idx)
1343 {
1344         int ret;
1345
1346         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1347         port->port.iotype = UPIO_MEM32;
1348         port->port.type = PORT_XSCALE;
1349         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1350         port->port.regshift = 2;
1351
1352         return ret;
1353 }
1354
1355 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1356 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1357
1358 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1359 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1360
1361 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1362 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1363
1364 #define BYT_PRV_CLK                     0x800
1365 #define BYT_PRV_CLK_EN                  (1 << 0)
1366 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1367 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1368 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1369
1370 #define BYT_TX_OVF_INT                  0x820
1371 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1372
1373 static void
1374 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1375                 struct ktermios *old)
1376 {
1377         unsigned int baud = tty_termios_baud_rate(termios);
1378         unsigned long fref = 100000000, fuart = baud * 16;
1379         unsigned long w = BIT(15) - 1;
1380         unsigned long m, n;
1381         u32 reg;
1382
1383         /* Get Fuart closer to Fref */
1384         fuart *= rounddown_pow_of_two(fref / fuart);
1385
1386         /*
1387          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1388          * dividers must be adjusted.
1389          *
1390          * uartclk = (m / n) * 100 MHz, where m <= n
1391          */
1392         rational_best_approximation(fuart, fref, w, w, &m, &n);
1393         p->uartclk = fuart;
1394
1395         /* Reset the clock */
1396         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1397         writel(reg, p->membase + BYT_PRV_CLK);
1398         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1399         writel(reg, p->membase + BYT_PRV_CLK);
1400
1401         p->status &= ~UPSTAT_AUTOCTS;
1402         if (termios->c_cflag & CRTSCTS)
1403                 p->status |= UPSTAT_AUTOCTS;
1404
1405         serial8250_do_set_termios(p, termios, old);
1406 }
1407
1408 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1409 {
1410         struct dw_dma_slave *dws = param;
1411
1412         if (dws->dma_dev != chan->device->dev)
1413                 return false;
1414
1415         chan->private = dws;
1416         return true;
1417 }
1418
1419 static int
1420 byt_serial_setup(struct serial_private *priv,
1421                  const struct pciserial_board *board,
1422                  struct uart_8250_port *port, int idx)
1423 {
1424         struct pci_dev *pdev = priv->dev;
1425         struct device *dev = port->port.dev;
1426         struct uart_8250_dma *dma;
1427         struct dw_dma_slave *tx_param, *rx_param;
1428         struct pci_dev *dma_dev;
1429         int ret;
1430
1431         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1432         if (!dma)
1433                 return -ENOMEM;
1434
1435         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1436         if (!tx_param)
1437                 return -ENOMEM;
1438
1439         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1440         if (!rx_param)
1441                 return -ENOMEM;
1442
1443         switch (pdev->device) {
1444         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1445         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1446         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1447                 rx_param->src_id = 3;
1448                 tx_param->dst_id = 2;
1449                 break;
1450         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1451         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1452         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1453                 rx_param->src_id = 5;
1454                 tx_param->dst_id = 4;
1455                 break;
1456         default:
1457                 return -EINVAL;
1458         }
1459
1460         rx_param->src_master = 1;
1461         rx_param->dst_master = 0;
1462
1463         dma->rxconf.src_maxburst = 16;
1464
1465         tx_param->src_master = 1;
1466         tx_param->dst_master = 0;
1467
1468         dma->txconf.dst_maxburst = 16;
1469
1470         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1471         rx_param->dma_dev = &dma_dev->dev;
1472         tx_param->dma_dev = &dma_dev->dev;
1473
1474         dma->fn = byt_dma_filter;
1475         dma->rx_param = rx_param;
1476         dma->tx_param = tx_param;
1477
1478         ret = pci_default_setup(priv, board, port, idx);
1479         port->port.iotype = UPIO_MEM;
1480         port->port.type = PORT_16550A;
1481         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1482         port->port.set_termios = byt_set_termios;
1483         port->port.fifosize = 64;
1484         port->tx_loadsz = 64;
1485         port->dma = dma;
1486         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1487
1488         /* Disable Tx counter interrupts */
1489         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1490
1491         return ret;
1492 }
1493
1494 static int
1495 pci_omegapci_setup(struct serial_private *priv,
1496                       const struct pciserial_board *board,
1497                       struct uart_8250_port *port, int idx)
1498 {
1499         return setup_port(priv, port, 2, idx * 8, 0);
1500 }
1501
1502 static int
1503 pci_brcm_trumanage_setup(struct serial_private *priv,
1504                          const struct pciserial_board *board,
1505                          struct uart_8250_port *port, int idx)
1506 {
1507         int ret = pci_default_setup(priv, board, port, idx);
1508
1509         port->port.type = PORT_BRCM_TRUMANAGE;
1510         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1511         return ret;
1512 }
1513
1514 /* RTS will control by MCR if this bit is 0 */
1515 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1516 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1517 #define FINTEK_RTS_INVERT               BIT(5)
1518
1519 /* We should do proper H/W transceiver setting before change to RS485 mode */
1520 static int pci_fintek_rs485_config(struct uart_port *port,
1521                                struct serial_rs485 *rs485)
1522 {
1523         struct pci_dev *pci_dev = to_pci_dev(port->dev);
1524         u8 setting;
1525         u8 *index = (u8 *) port->private_data;
1526
1527         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1528
1529         if (!rs485)
1530                 rs485 = &port->rs485;
1531         else if (rs485->flags & SER_RS485_ENABLED)
1532                 memset(rs485->padding, 0, sizeof(rs485->padding));
1533         else
1534                 memset(rs485, 0, sizeof(*rs485));
1535
1536         /* F81504/508/512 not support RTS delay before or after send */
1537         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1538
1539         if (rs485->flags & SER_RS485_ENABLED) {
1540                 /* Enable RTS H/W control mode */
1541                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1542
1543                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1544                         /* RTS driving high on TX */
1545                         setting &= ~FINTEK_RTS_INVERT;
1546                 } else {
1547                         /* RTS driving low on TX */
1548                         setting |= FINTEK_RTS_INVERT;
1549                 }
1550
1551                 rs485->delay_rts_after_send = 0;
1552                 rs485->delay_rts_before_send = 0;
1553         } else {
1554                 /* Disable RTS H/W control mode */
1555                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1556         }
1557
1558         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1559
1560         if (rs485 != &port->rs485)
1561                 port->rs485 = *rs485;
1562
1563         return 0;
1564 }
1565
1566 static int pci_fintek_setup(struct serial_private *priv,
1567                             const struct pciserial_board *board,
1568                             struct uart_8250_port *port, int idx)
1569 {
1570         struct pci_dev *pdev = priv->dev;
1571         u8 *data;
1572         u8 config_base;
1573         u16 iobase;
1574
1575         config_base = 0x40 + 0x08 * idx;
1576
1577         /* Get the io address from configuration space */
1578         pci_read_config_word(pdev, config_base + 4, &iobase);
1579
1580         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1581
1582         port->port.iotype = UPIO_PORT;
1583         port->port.iobase = iobase;
1584         port->port.rs485_config = pci_fintek_rs485_config;
1585
1586         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1587         if (!data)
1588                 return -ENOMEM;
1589
1590         /* preserve index in PCI configuration space */
1591         *data = idx;
1592         port->port.private_data = data;
1593
1594         return 0;
1595 }
1596
1597 static int pci_fintek_init(struct pci_dev *dev)
1598 {
1599         unsigned long iobase;
1600         u32 max_port, i;
1601         u32 bar_data[3];
1602         u8 config_base;
1603         struct serial_private *priv = pci_get_drvdata(dev);
1604         struct uart_8250_port *port;
1605
1606         switch (dev->device) {
1607         case 0x1104: /* 4 ports */
1608         case 0x1108: /* 8 ports */
1609                 max_port = dev->device & 0xff;
1610                 break;
1611         case 0x1112: /* 12 ports */
1612                 max_port = 12;
1613                 break;
1614         default:
1615                 return -EINVAL;
1616         }
1617
1618         /* Get the io address dispatch from the BIOS */
1619         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1620         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1621         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1622
1623         for (i = 0; i < max_port; ++i) {
1624                 /* UART0 configuration offset start from 0x40 */
1625                 config_base = 0x40 + 0x08 * i;
1626
1627                 /* Calculate Real IO Port */
1628                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1629
1630                 /* Enable UART I/O port */
1631                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1632
1633                 /* Select 128-byte FIFO and 8x FIFO threshold */
1634                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1635
1636                 /* LSB UART */
1637                 pci_write_config_byte(dev, config_base + 0x04,
1638                                 (u8)(iobase & 0xff));
1639
1640                 /* MSB UART */
1641                 pci_write_config_byte(dev, config_base + 0x05,
1642                                 (u8)((iobase & 0xff00) >> 8));
1643
1644                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1645
1646                 if (priv) {
1647                         /* re-apply RS232/485 mode when
1648                          * pciserial_resume_ports()
1649                          */
1650                         port = serial8250_get_port(priv->line[i]);
1651                         pci_fintek_rs485_config(&port->port, NULL);
1652                 } else {
1653                         /* First init without port data
1654                          * force init to RS232 Mode
1655                          */
1656                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1657                 }
1658         }
1659
1660         return max_port;
1661 }
1662
1663 static int skip_tx_en_setup(struct serial_private *priv,
1664                         const struct pciserial_board *board,
1665                         struct uart_8250_port *port, int idx)
1666 {
1667         port->port.flags |= UPF_NO_TXEN_TEST;
1668         dev_dbg(&priv->dev->dev,
1669                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1670                 priv->dev->vendor, priv->dev->device,
1671                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1672
1673         return pci_default_setup(priv, board, port, idx);
1674 }
1675
1676 static void kt_handle_break(struct uart_port *p)
1677 {
1678         struct uart_8250_port *up = up_to_u8250p(p);
1679         /*
1680          * On receipt of a BI, serial device in Intel ME (Intel
1681          * management engine) needs to have its fifos cleared for sane
1682          * SOL (Serial Over Lan) output.
1683          */
1684         serial8250_clear_and_reinit_fifos(up);
1685 }
1686
1687 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1688 {
1689         struct uart_8250_port *up = up_to_u8250p(p);
1690         unsigned int val;
1691
1692         /*
1693          * When the Intel ME (management engine) gets reset its serial
1694          * port registers could return 0 momentarily.  Functions like
1695          * serial8250_console_write, read and save the IER, perform
1696          * some operation and then restore it.  In order to avoid
1697          * setting IER register inadvertently to 0, if the value read
1698          * is 0, double check with ier value in uart_8250_port and use
1699          * that instead.  up->ier should be the same value as what is
1700          * currently configured.
1701          */
1702         val = inb(p->iobase + offset);
1703         if (offset == UART_IER) {
1704                 if (val == 0)
1705                         val = up->ier;
1706         }
1707         return val;
1708 }
1709
1710 static int kt_serial_setup(struct serial_private *priv,
1711                            const struct pciserial_board *board,
1712                            struct uart_8250_port *port, int idx)
1713 {
1714         port->port.flags |= UPF_BUG_THRE;
1715         port->port.serial_in = kt_serial_in;
1716         port->port.handle_break = kt_handle_break;
1717         return skip_tx_en_setup(priv, board, port, idx);
1718 }
1719
1720 static int pci_eg20t_init(struct pci_dev *dev)
1721 {
1722 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1723         return -ENODEV;
1724 #else
1725         return 0;
1726 #endif
1727 }
1728
1729 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1730 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1731
1732 static int
1733 pci_xr17c154_setup(struct serial_private *priv,
1734                   const struct pciserial_board *board,
1735                   struct uart_8250_port *port, int idx)
1736 {
1737         port->port.flags |= UPF_EXAR_EFR;
1738         return pci_default_setup(priv, board, port, idx);
1739 }
1740
1741 static inline int
1742 xr17v35x_has_slave(struct serial_private *priv)
1743 {
1744         const int dev_id = priv->dev->device;
1745
1746         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1747                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1748 }
1749
1750 static int
1751 pci_xr17v35x_setup(struct serial_private *priv,
1752                   const struct pciserial_board *board,
1753                   struct uart_8250_port *port, int idx)
1754 {
1755         u8 __iomem *p;
1756
1757         p = pci_ioremap_bar(priv->dev, 0);
1758         if (p == NULL)
1759                 return -ENOMEM;
1760
1761         port->port.flags |= UPF_EXAR_EFR;
1762
1763         /*
1764          * Setup the uart clock for the devices on expansion slot to
1765          * half the clock speed of the main chip (which is 125MHz)
1766          */
1767         if (xr17v35x_has_slave(priv) && idx >= 8)
1768                 port->port.uartclk = (7812500 * 16 / 2);
1769
1770         /*
1771          * Setup Multipurpose Input/Output pins.
1772          */
1773         if (idx == 0) {
1774                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1775                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1776                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1777                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1778                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1779                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1780                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1781                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1782                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1783                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1784                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1785                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1786         }
1787         writeb(0x00, p + UART_EXAR_8XMODE);
1788         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1789         writeb(128, p + UART_EXAR_TXTRG);
1790         writeb(128, p + UART_EXAR_RXTRG);
1791         iounmap(p);
1792
1793         return pci_default_setup(priv, board, port, idx);
1794 }
1795
1796 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1797 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1798 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1799 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1800
1801 static int
1802 pci_fastcom335_setup(struct serial_private *priv,
1803                   const struct pciserial_board *board,
1804                   struct uart_8250_port *port, int idx)
1805 {
1806         u8 __iomem *p;
1807
1808         p = pci_ioremap_bar(priv->dev, 0);
1809         if (p == NULL)
1810                 return -ENOMEM;
1811
1812         port->port.flags |= UPF_EXAR_EFR;
1813
1814         /*
1815          * Setup Multipurpose Input/Output pins.
1816          */
1817         if (idx == 0) {
1818                 switch (priv->dev->device) {
1819                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1820                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1821                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1822                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1823                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1824                         break;
1825                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1826                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1827                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1828                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1829                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1830                         break;
1831                 }
1832                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1833                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1834                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1835         }
1836         writeb(0x00, p + UART_EXAR_8XMODE);
1837         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1838         writeb(32, p + UART_EXAR_TXTRG);
1839         writeb(32, p + UART_EXAR_RXTRG);
1840         iounmap(p);
1841
1842         return pci_default_setup(priv, board, port, idx);
1843 }
1844
1845 static int
1846 pci_wch_ch353_setup(struct serial_private *priv,
1847                     const struct pciserial_board *board,
1848                     struct uart_8250_port *port, int idx)
1849 {
1850         port->port.flags |= UPF_FIXED_TYPE;
1851         port->port.type = PORT_16550A;
1852         return pci_default_setup(priv, board, port, idx);
1853 }
1854
1855 static int
1856 pci_wch_ch38x_setup(struct serial_private *priv,
1857                     const struct pciserial_board *board,
1858                     struct uart_8250_port *port, int idx)
1859 {
1860         port->port.flags |= UPF_FIXED_TYPE;
1861         port->port.type = PORT_16850;
1862         return pci_default_setup(priv, board, port, idx);
1863 }
1864
1865 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1866 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1867 #define PCI_DEVICE_ID_OCTPRO            0x0001
1868 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1869 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1870 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1871 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1872 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1873 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1874 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1875 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1876 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1877 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1878 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1879 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1880 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1881 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1882 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1883 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1884 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1885 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1886 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1887 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1888 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1889 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1890 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1891 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1892 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1893 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1894 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1895 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1896 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1897 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1898 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1899 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1900 #define PCI_VENDOR_ID_WCH               0x4348
1901 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1902 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1903 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1904 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1905 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1906 #define PCI_VENDOR_ID_AGESTAR           0x5372
1907 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1908 #define PCI_VENDOR_ID_ASIX              0x9710
1909 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1910 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1911 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1912 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1913 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1914 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1915
1916 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1917 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1918
1919 #define PCIE_VENDOR_ID_WCH              0x1c00
1920 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1921 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1922
1923 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1924 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1925 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1926 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1927 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1928
1929 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1930 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1931 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1932
1933 /*
1934  * Master list of serial port init/setup/exit quirks.
1935  * This does not describe the general nature of the port.
1936  * (ie, baud base, number and location of ports, etc)
1937  *
1938  * This list is ordered alphabetically by vendor then device.
1939  * Specific entries must come before more generic entries.
1940  */
1941 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1942         /*
1943         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1944         */
1945         {
1946                 .vendor         = PCI_VENDOR_ID_AMCC,
1947                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1948                 .subvendor      = PCI_ANY_ID,
1949                 .subdevice      = PCI_ANY_ID,
1950                 .setup          = addidata_apci7800_setup,
1951         },
1952         /*
1953          * AFAVLAB cards - these may be called via parport_serial
1954          *  It is not clear whether this applies to all products.
1955          */
1956         {
1957                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1958                 .device         = PCI_ANY_ID,
1959                 .subvendor      = PCI_ANY_ID,
1960                 .subdevice      = PCI_ANY_ID,
1961                 .setup          = afavlab_setup,
1962         },
1963         /*
1964          * HP Diva
1965          */
1966         {
1967                 .vendor         = PCI_VENDOR_ID_HP,
1968                 .device         = PCI_DEVICE_ID_HP_DIVA,
1969                 .subvendor      = PCI_ANY_ID,
1970                 .subdevice      = PCI_ANY_ID,
1971                 .init           = pci_hp_diva_init,
1972                 .setup          = pci_hp_diva_setup,
1973         },
1974         /*
1975          * Intel
1976          */
1977         {
1978                 .vendor         = PCI_VENDOR_ID_INTEL,
1979                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1980                 .subvendor      = 0xe4bf,
1981                 .subdevice      = PCI_ANY_ID,
1982                 .init           = pci_inteli960ni_init,
1983                 .setup          = pci_default_setup,
1984         },
1985         {
1986                 .vendor         = PCI_VENDOR_ID_INTEL,
1987                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1988                 .subvendor      = PCI_ANY_ID,
1989                 .subdevice      = PCI_ANY_ID,
1990                 .setup          = skip_tx_en_setup,
1991         },
1992         {
1993                 .vendor         = PCI_VENDOR_ID_INTEL,
1994                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1995                 .subvendor      = PCI_ANY_ID,
1996                 .subdevice      = PCI_ANY_ID,
1997                 .setup          = skip_tx_en_setup,
1998         },
1999         {
2000                 .vendor         = PCI_VENDOR_ID_INTEL,
2001                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2002                 .subvendor      = PCI_ANY_ID,
2003                 .subdevice      = PCI_ANY_ID,
2004                 .setup          = skip_tx_en_setup,
2005         },
2006         {
2007                 .vendor         = PCI_VENDOR_ID_INTEL,
2008                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2009                 .subvendor      = PCI_ANY_ID,
2010                 .subdevice      = PCI_ANY_ID,
2011                 .setup          = ce4100_serial_setup,
2012         },
2013         {
2014                 .vendor         = PCI_VENDOR_ID_INTEL,
2015                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2016                 .subvendor      = PCI_ANY_ID,
2017                 .subdevice      = PCI_ANY_ID,
2018                 .setup          = kt_serial_setup,
2019         },
2020         {
2021                 .vendor         = PCI_VENDOR_ID_INTEL,
2022                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2023                 .subvendor      = PCI_ANY_ID,
2024                 .subdevice      = PCI_ANY_ID,
2025                 .setup          = byt_serial_setup,
2026         },
2027         {
2028                 .vendor         = PCI_VENDOR_ID_INTEL,
2029                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2030                 .subvendor      = PCI_ANY_ID,
2031                 .subdevice      = PCI_ANY_ID,
2032                 .setup          = byt_serial_setup,
2033         },
2034         {
2035                 .vendor         = PCI_VENDOR_ID_INTEL,
2036                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2037                 .subvendor      = PCI_ANY_ID,
2038                 .subdevice      = PCI_ANY_ID,
2039                 .setup          = byt_serial_setup,
2040         },
2041         {
2042                 .vendor         = PCI_VENDOR_ID_INTEL,
2043                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2044                 .subvendor      = PCI_ANY_ID,
2045                 .subdevice      = PCI_ANY_ID,
2046                 .setup          = byt_serial_setup,
2047         },
2048         {
2049                 .vendor         = PCI_VENDOR_ID_INTEL,
2050                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2051                 .subvendor      = PCI_ANY_ID,
2052                 .subdevice      = PCI_ANY_ID,
2053                 .setup          = byt_serial_setup,
2054         },
2055         {
2056                 .vendor         = PCI_VENDOR_ID_INTEL,
2057                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2058                 .subvendor      = PCI_ANY_ID,
2059                 .subdevice      = PCI_ANY_ID,
2060                 .setup          = byt_serial_setup,
2061         },
2062         /*
2063          * ITE
2064          */
2065         {
2066                 .vendor         = PCI_VENDOR_ID_ITE,
2067                 .device         = PCI_DEVICE_ID_ITE_8872,
2068                 .subvendor      = PCI_ANY_ID,
2069                 .subdevice      = PCI_ANY_ID,
2070                 .init           = pci_ite887x_init,
2071                 .setup          = pci_default_setup,
2072                 .exit           = pci_ite887x_exit,
2073         },
2074         /*
2075          * National Instruments
2076          */
2077         {
2078                 .vendor         = PCI_VENDOR_ID_NI,
2079                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2080                 .subvendor      = PCI_ANY_ID,
2081                 .subdevice      = PCI_ANY_ID,
2082                 .init           = pci_ni8420_init,
2083                 .setup          = pci_default_setup,
2084                 .exit           = pci_ni8420_exit,
2085         },
2086         {
2087                 .vendor         = PCI_VENDOR_ID_NI,
2088                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2089                 .subvendor      = PCI_ANY_ID,
2090                 .subdevice      = PCI_ANY_ID,
2091                 .init           = pci_ni8420_init,
2092                 .setup          = pci_default_setup,
2093                 .exit           = pci_ni8420_exit,
2094         },
2095         {
2096                 .vendor         = PCI_VENDOR_ID_NI,
2097                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2098                 .subvendor      = PCI_ANY_ID,
2099                 .subdevice      = PCI_ANY_ID,
2100                 .init           = pci_ni8420_init,
2101                 .setup          = pci_default_setup,
2102                 .exit           = pci_ni8420_exit,
2103         },
2104         {
2105                 .vendor         = PCI_VENDOR_ID_NI,
2106                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2107                 .subvendor      = PCI_ANY_ID,
2108                 .subdevice      = PCI_ANY_ID,
2109                 .init           = pci_ni8420_init,
2110                 .setup          = pci_default_setup,
2111                 .exit           = pci_ni8420_exit,
2112         },
2113         {
2114                 .vendor         = PCI_VENDOR_ID_NI,
2115                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2116                 .subvendor      = PCI_ANY_ID,
2117                 .subdevice      = PCI_ANY_ID,
2118                 .init           = pci_ni8420_init,
2119                 .setup          = pci_default_setup,
2120                 .exit           = pci_ni8420_exit,
2121         },
2122         {
2123                 .vendor         = PCI_VENDOR_ID_NI,
2124                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2125                 .subvendor      = PCI_ANY_ID,
2126                 .subdevice      = PCI_ANY_ID,
2127                 .init           = pci_ni8420_init,
2128                 .setup          = pci_default_setup,
2129                 .exit           = pci_ni8420_exit,
2130         },
2131         {
2132                 .vendor         = PCI_VENDOR_ID_NI,
2133                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2134                 .subvendor      = PCI_ANY_ID,
2135                 .subdevice      = PCI_ANY_ID,
2136                 .init           = pci_ni8420_init,
2137                 .setup          = pci_default_setup,
2138                 .exit           = pci_ni8420_exit,
2139         },
2140         {
2141                 .vendor         = PCI_VENDOR_ID_NI,
2142                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2143                 .subvendor      = PCI_ANY_ID,
2144                 .subdevice      = PCI_ANY_ID,
2145                 .init           = pci_ni8420_init,
2146                 .setup          = pci_default_setup,
2147                 .exit           = pci_ni8420_exit,
2148         },
2149         {
2150                 .vendor         = PCI_VENDOR_ID_NI,
2151                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2152                 .subvendor      = PCI_ANY_ID,
2153                 .subdevice      = PCI_ANY_ID,
2154                 .init           = pci_ni8420_init,
2155                 .setup          = pci_default_setup,
2156                 .exit           = pci_ni8420_exit,
2157         },
2158         {
2159                 .vendor         = PCI_VENDOR_ID_NI,
2160                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2161                 .subvendor      = PCI_ANY_ID,
2162                 .subdevice      = PCI_ANY_ID,
2163                 .init           = pci_ni8420_init,
2164                 .setup          = pci_default_setup,
2165                 .exit           = pci_ni8420_exit,
2166         },
2167         {
2168                 .vendor         = PCI_VENDOR_ID_NI,
2169                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2170                 .subvendor      = PCI_ANY_ID,
2171                 .subdevice      = PCI_ANY_ID,
2172                 .init           = pci_ni8420_init,
2173                 .setup          = pci_default_setup,
2174                 .exit           = pci_ni8420_exit,
2175         },
2176         {
2177                 .vendor         = PCI_VENDOR_ID_NI,
2178                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2179                 .subvendor      = PCI_ANY_ID,
2180                 .subdevice      = PCI_ANY_ID,
2181                 .init           = pci_ni8420_init,
2182                 .setup          = pci_default_setup,
2183                 .exit           = pci_ni8420_exit,
2184         },
2185         {
2186                 .vendor         = PCI_VENDOR_ID_NI,
2187                 .device         = PCI_ANY_ID,
2188                 .subvendor      = PCI_ANY_ID,
2189                 .subdevice      = PCI_ANY_ID,
2190                 .init           = pci_ni8430_init,
2191                 .setup          = pci_ni8430_setup,
2192                 .exit           = pci_ni8430_exit,
2193         },
2194         /* Quatech */
2195         {
2196                 .vendor         = PCI_VENDOR_ID_QUATECH,
2197                 .device         = PCI_ANY_ID,
2198                 .subvendor      = PCI_ANY_ID,
2199                 .subdevice      = PCI_ANY_ID,
2200                 .init           = pci_quatech_init,
2201                 .setup          = pci_quatech_setup,
2202                 .exit           = pci_quatech_exit,
2203         },
2204         /*
2205          * Panacom
2206          */
2207         {
2208                 .vendor         = PCI_VENDOR_ID_PANACOM,
2209                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2210                 .subvendor      = PCI_ANY_ID,
2211                 .subdevice      = PCI_ANY_ID,
2212                 .init           = pci_plx9050_init,
2213                 .setup          = pci_default_setup,
2214                 .exit           = pci_plx9050_exit,
2215         },
2216         {
2217                 .vendor         = PCI_VENDOR_ID_PANACOM,
2218                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2219                 .subvendor      = PCI_ANY_ID,
2220                 .subdevice      = PCI_ANY_ID,
2221                 .init           = pci_plx9050_init,
2222                 .setup          = pci_default_setup,
2223                 .exit           = pci_plx9050_exit,
2224         },
2225         /*
2226          * PLX
2227          */
2228         {
2229                 .vendor         = PCI_VENDOR_ID_PLX,
2230                 .device         = PCI_DEVICE_ID_PLX_9050,
2231                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2232                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2233                 .init           = pci_plx9050_init,
2234                 .setup          = pci_default_setup,
2235                 .exit           = pci_plx9050_exit,
2236         },
2237         {
2238                 .vendor         = PCI_VENDOR_ID_PLX,
2239                 .device         = PCI_DEVICE_ID_PLX_9050,
2240                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2241                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2242                 .init           = pci_plx9050_init,
2243                 .setup          = pci_default_setup,
2244                 .exit           = pci_plx9050_exit,
2245         },
2246         {
2247                 .vendor         = PCI_VENDOR_ID_PLX,
2248                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2249                 .subvendor      = PCI_VENDOR_ID_PLX,
2250                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2251                 .init           = pci_plx9050_init,
2252                 .setup          = pci_default_setup,
2253                 .exit           = pci_plx9050_exit,
2254         },
2255         /*
2256          * SBS Technologies, Inc., PMC-OCTALPRO 232
2257          */
2258         {
2259                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2260                 .device         = PCI_DEVICE_ID_OCTPRO,
2261                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2262                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2263                 .init           = sbs_init,
2264                 .setup          = sbs_setup,
2265                 .exit           = sbs_exit,
2266         },
2267         /*
2268          * SBS Technologies, Inc., PMC-OCTALPRO 422
2269          */
2270         {
2271                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2272                 .device         = PCI_DEVICE_ID_OCTPRO,
2273                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2274                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2275                 .init           = sbs_init,
2276                 .setup          = sbs_setup,
2277                 .exit           = sbs_exit,
2278         },
2279         /*
2280          * SBS Technologies, Inc., P-Octal 232
2281          */
2282         {
2283                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2284                 .device         = PCI_DEVICE_ID_OCTPRO,
2285                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2286                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2287                 .init           = sbs_init,
2288                 .setup          = sbs_setup,
2289                 .exit           = sbs_exit,
2290         },
2291         /*
2292          * SBS Technologies, Inc., P-Octal 422
2293          */
2294         {
2295                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2296                 .device         = PCI_DEVICE_ID_OCTPRO,
2297                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2298                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2299                 .init           = sbs_init,
2300                 .setup          = sbs_setup,
2301                 .exit           = sbs_exit,
2302         },
2303         /*
2304          * SIIG cards - these may be called via parport_serial
2305          */
2306         {
2307                 .vendor         = PCI_VENDOR_ID_SIIG,
2308                 .device         = PCI_ANY_ID,
2309                 .subvendor      = PCI_ANY_ID,
2310                 .subdevice      = PCI_ANY_ID,
2311                 .init           = pci_siig_init,
2312                 .setup          = pci_siig_setup,
2313         },
2314         /*
2315          * Titan cards
2316          */
2317         {
2318                 .vendor         = PCI_VENDOR_ID_TITAN,
2319                 .device         = PCI_DEVICE_ID_TITAN_400L,
2320                 .subvendor      = PCI_ANY_ID,
2321                 .subdevice      = PCI_ANY_ID,
2322                 .setup          = titan_400l_800l_setup,
2323         },
2324         {
2325                 .vendor         = PCI_VENDOR_ID_TITAN,
2326                 .device         = PCI_DEVICE_ID_TITAN_800L,
2327                 .subvendor      = PCI_ANY_ID,
2328                 .subdevice      = PCI_ANY_ID,
2329                 .setup          = titan_400l_800l_setup,
2330         },
2331         /*
2332          * Timedia cards
2333          */
2334         {
2335                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2336                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2337                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2338                 .subdevice      = PCI_ANY_ID,
2339                 .probe          = pci_timedia_probe,
2340                 .init           = pci_timedia_init,
2341                 .setup          = pci_timedia_setup,
2342         },
2343         {
2344                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2345                 .device         = PCI_ANY_ID,
2346                 .subvendor      = PCI_ANY_ID,
2347                 .subdevice      = PCI_ANY_ID,
2348                 .setup          = pci_timedia_setup,
2349         },
2350         /*
2351          * SUNIX (Timedia) cards
2352          * Do not "probe" for these cards as there is at least one combination
2353          * card that should be handled by parport_pc that doesn't match the
2354          * rule in pci_timedia_probe.
2355          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2356          * There are some boards with part number SER5037AL that report
2357          * subdevice ID 0x0002.
2358          */
2359         {
2360                 .vendor         = PCI_VENDOR_ID_SUNIX,
2361                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2362                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2363                 .subdevice      = PCI_ANY_ID,
2364                 .init           = pci_timedia_init,
2365                 .setup          = pci_timedia_setup,
2366         },
2367         /*
2368          * Exar cards
2369          */
2370         {
2371                 .vendor = PCI_VENDOR_ID_EXAR,
2372                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2373                 .subvendor      = PCI_ANY_ID,
2374                 .subdevice      = PCI_ANY_ID,
2375                 .setup          = pci_xr17c154_setup,
2376         },
2377         {
2378                 .vendor = PCI_VENDOR_ID_EXAR,
2379                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2380                 .subvendor      = PCI_ANY_ID,
2381                 .subdevice      = PCI_ANY_ID,
2382                 .setup          = pci_xr17c154_setup,
2383         },
2384         {
2385                 .vendor = PCI_VENDOR_ID_EXAR,
2386                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2387                 .subvendor      = PCI_ANY_ID,
2388                 .subdevice      = PCI_ANY_ID,
2389                 .setup          = pci_xr17c154_setup,
2390         },
2391         {
2392                 .vendor = PCI_VENDOR_ID_EXAR,
2393                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2394                 .subvendor      = PCI_ANY_ID,
2395                 .subdevice      = PCI_ANY_ID,
2396                 .setup          = pci_xr17v35x_setup,
2397         },
2398         {
2399                 .vendor = PCI_VENDOR_ID_EXAR,
2400                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2401                 .subvendor      = PCI_ANY_ID,
2402                 .subdevice      = PCI_ANY_ID,
2403                 .setup          = pci_xr17v35x_setup,
2404         },
2405         {
2406                 .vendor = PCI_VENDOR_ID_EXAR,
2407                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2408                 .subvendor      = PCI_ANY_ID,
2409                 .subdevice      = PCI_ANY_ID,
2410                 .setup          = pci_xr17v35x_setup,
2411         },
2412         {
2413                 .vendor = PCI_VENDOR_ID_EXAR,
2414                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2415                 .subvendor      = PCI_ANY_ID,
2416                 .subdevice      = PCI_ANY_ID,
2417                 .setup          = pci_xr17v35x_setup,
2418         },
2419         {
2420                 .vendor = PCI_VENDOR_ID_EXAR,
2421                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2422                 .subvendor      = PCI_ANY_ID,
2423                 .subdevice      = PCI_ANY_ID,
2424                 .setup          = pci_xr17v35x_setup,
2425         },
2426         /*
2427          * Xircom cards
2428          */
2429         {
2430                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2431                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2432                 .subvendor      = PCI_ANY_ID,
2433                 .subdevice      = PCI_ANY_ID,
2434                 .init           = pci_xircom_init,
2435                 .setup          = pci_default_setup,
2436         },
2437         /*
2438          * Netmos cards - these may be called via parport_serial
2439          */
2440         {
2441                 .vendor         = PCI_VENDOR_ID_NETMOS,
2442                 .device         = PCI_ANY_ID,
2443                 .subvendor      = PCI_ANY_ID,
2444                 .subdevice      = PCI_ANY_ID,
2445                 .init           = pci_netmos_init,
2446                 .setup          = pci_netmos_9900_setup,
2447         },
2448         /*
2449          * EndRun Technologies
2450         */
2451         {
2452                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2453                 .device         = PCI_ANY_ID,
2454                 .subvendor      = PCI_ANY_ID,
2455                 .subdevice      = PCI_ANY_ID,
2456                 .init           = pci_endrun_init,
2457                 .setup          = pci_default_setup,
2458         },
2459         /*
2460          * For Oxford Semiconductor Tornado based devices
2461          */
2462         {
2463                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2464                 .device         = PCI_ANY_ID,
2465                 .subvendor      = PCI_ANY_ID,
2466                 .subdevice      = PCI_ANY_ID,
2467                 .init           = pci_oxsemi_tornado_init,
2468                 .setup          = pci_default_setup,
2469         },
2470         {
2471                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2472                 .device         = PCI_ANY_ID,
2473                 .subvendor      = PCI_ANY_ID,
2474                 .subdevice      = PCI_ANY_ID,
2475                 .init           = pci_oxsemi_tornado_init,
2476                 .setup          = pci_default_setup,
2477         },
2478         {
2479                 .vendor         = PCI_VENDOR_ID_DIGI,
2480                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2481                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2482                 .subdevice              = PCI_ANY_ID,
2483                 .init                   = pci_oxsemi_tornado_init,
2484                 .setup          = pci_default_setup,
2485         },
2486         {
2487                 .vendor         = PCI_VENDOR_ID_INTEL,
2488                 .device         = 0x8811,
2489                 .subvendor      = PCI_ANY_ID,
2490                 .subdevice      = PCI_ANY_ID,
2491                 .init           = pci_eg20t_init,
2492                 .setup          = pci_default_setup,
2493         },
2494         {
2495                 .vendor         = PCI_VENDOR_ID_INTEL,
2496                 .device         = 0x8812,
2497                 .subvendor      = PCI_ANY_ID,
2498                 .subdevice      = PCI_ANY_ID,
2499                 .init           = pci_eg20t_init,
2500                 .setup          = pci_default_setup,
2501         },
2502         {
2503                 .vendor         = PCI_VENDOR_ID_INTEL,
2504                 .device         = 0x8813,
2505                 .subvendor      = PCI_ANY_ID,
2506                 .subdevice      = PCI_ANY_ID,
2507                 .init           = pci_eg20t_init,
2508                 .setup          = pci_default_setup,
2509         },
2510         {
2511                 .vendor         = PCI_VENDOR_ID_INTEL,
2512                 .device         = 0x8814,
2513                 .subvendor      = PCI_ANY_ID,
2514                 .subdevice      = PCI_ANY_ID,
2515                 .init           = pci_eg20t_init,
2516                 .setup          = pci_default_setup,
2517         },
2518         {
2519                 .vendor         = 0x10DB,
2520                 .device         = 0x8027,
2521                 .subvendor      = PCI_ANY_ID,
2522                 .subdevice      = PCI_ANY_ID,
2523                 .init           = pci_eg20t_init,
2524                 .setup          = pci_default_setup,
2525         },
2526         {
2527                 .vendor         = 0x10DB,
2528                 .device         = 0x8028,
2529                 .subvendor      = PCI_ANY_ID,
2530                 .subdevice      = PCI_ANY_ID,
2531                 .init           = pci_eg20t_init,
2532                 .setup          = pci_default_setup,
2533         },
2534         {
2535                 .vendor         = 0x10DB,
2536                 .device         = 0x8029,
2537                 .subvendor      = PCI_ANY_ID,
2538                 .subdevice      = PCI_ANY_ID,
2539                 .init           = pci_eg20t_init,
2540                 .setup          = pci_default_setup,
2541         },
2542         {
2543                 .vendor         = 0x10DB,
2544                 .device         = 0x800C,
2545                 .subvendor      = PCI_ANY_ID,
2546                 .subdevice      = PCI_ANY_ID,
2547                 .init           = pci_eg20t_init,
2548                 .setup          = pci_default_setup,
2549         },
2550         {
2551                 .vendor         = 0x10DB,
2552                 .device         = 0x800D,
2553                 .subvendor      = PCI_ANY_ID,
2554                 .subdevice      = PCI_ANY_ID,
2555                 .init           = pci_eg20t_init,
2556                 .setup          = pci_default_setup,
2557         },
2558         /*
2559          * Cronyx Omega PCI (PLX-chip based)
2560          */
2561         {
2562                 .vendor         = PCI_VENDOR_ID_PLX,
2563                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2564                 .subvendor      = PCI_ANY_ID,
2565                 .subdevice      = PCI_ANY_ID,
2566                 .setup          = pci_omegapci_setup,
2567         },
2568         /* WCH CH353 1S1P card (16550 clone) */
2569         {
2570                 .vendor         = PCI_VENDOR_ID_WCH,
2571                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2572                 .subvendor      = PCI_ANY_ID,
2573                 .subdevice      = PCI_ANY_ID,
2574                 .setup          = pci_wch_ch353_setup,
2575         },
2576         /* WCH CH353 2S1P card (16550 clone) */
2577         {
2578                 .vendor         = PCI_VENDOR_ID_WCH,
2579                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2580                 .subvendor      = PCI_ANY_ID,
2581                 .subdevice      = PCI_ANY_ID,
2582                 .setup          = pci_wch_ch353_setup,
2583         },
2584         /* WCH CH353 4S card (16550 clone) */
2585         {
2586                 .vendor         = PCI_VENDOR_ID_WCH,
2587                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2588                 .subvendor      = PCI_ANY_ID,
2589                 .subdevice      = PCI_ANY_ID,
2590                 .setup          = pci_wch_ch353_setup,
2591         },
2592         /* WCH CH353 2S1PF card (16550 clone) */
2593         {
2594                 .vendor         = PCI_VENDOR_ID_WCH,
2595                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2596                 .subvendor      = PCI_ANY_ID,
2597                 .subdevice      = PCI_ANY_ID,
2598                 .setup          = pci_wch_ch353_setup,
2599         },
2600         /* WCH CH352 2S card (16550 clone) */
2601         {
2602                 .vendor         = PCI_VENDOR_ID_WCH,
2603                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2604                 .subvendor      = PCI_ANY_ID,
2605                 .subdevice      = PCI_ANY_ID,
2606                 .setup          = pci_wch_ch353_setup,
2607         },
2608         /* WCH CH382 2S1P card (16850 clone) */
2609         {
2610                 .vendor         = PCIE_VENDOR_ID_WCH,
2611                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2612                 .subvendor      = PCI_ANY_ID,
2613                 .subdevice      = PCI_ANY_ID,
2614                 .setup          = pci_wch_ch38x_setup,
2615         },
2616         /* WCH CH384 4S card (16850 clone) */
2617         {
2618                 .vendor         = PCIE_VENDOR_ID_WCH,
2619                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2620                 .subvendor      = PCI_ANY_ID,
2621                 .subdevice      = PCI_ANY_ID,
2622                 .setup          = pci_wch_ch38x_setup,
2623         },
2624         /*
2625          * ASIX devices with FIFO bug
2626          */
2627         {
2628                 .vendor         = PCI_VENDOR_ID_ASIX,
2629                 .device         = PCI_ANY_ID,
2630                 .subvendor      = PCI_ANY_ID,
2631                 .subdevice      = PCI_ANY_ID,
2632                 .setup          = pci_asix_setup,
2633         },
2634         /*
2635          * Commtech, Inc. Fastcom adapters
2636          *
2637          */
2638         {
2639                 .vendor = PCI_VENDOR_ID_COMMTECH,
2640                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2641                 .subvendor      = PCI_ANY_ID,
2642                 .subdevice      = PCI_ANY_ID,
2643                 .setup          = pci_fastcom335_setup,
2644         },
2645         {
2646                 .vendor = PCI_VENDOR_ID_COMMTECH,
2647                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2648                 .subvendor      = PCI_ANY_ID,
2649                 .subdevice      = PCI_ANY_ID,
2650                 .setup          = pci_fastcom335_setup,
2651         },
2652         {
2653                 .vendor = PCI_VENDOR_ID_COMMTECH,
2654                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2655                 .subvendor      = PCI_ANY_ID,
2656                 .subdevice      = PCI_ANY_ID,
2657                 .setup          = pci_fastcom335_setup,
2658         },
2659         {
2660                 .vendor = PCI_VENDOR_ID_COMMTECH,
2661                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2662                 .subvendor      = PCI_ANY_ID,
2663                 .subdevice      = PCI_ANY_ID,
2664                 .setup          = pci_fastcom335_setup,
2665         },
2666         {
2667                 .vendor = PCI_VENDOR_ID_COMMTECH,
2668                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2669                 .subvendor      = PCI_ANY_ID,
2670                 .subdevice      = PCI_ANY_ID,
2671                 .setup          = pci_xr17v35x_setup,
2672         },
2673         {
2674                 .vendor = PCI_VENDOR_ID_COMMTECH,
2675                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2676                 .subvendor      = PCI_ANY_ID,
2677                 .subdevice      = PCI_ANY_ID,
2678                 .setup          = pci_xr17v35x_setup,
2679         },
2680         {
2681                 .vendor = PCI_VENDOR_ID_COMMTECH,
2682                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2683                 .subvendor      = PCI_ANY_ID,
2684                 .subdevice      = PCI_ANY_ID,
2685                 .setup          = pci_xr17v35x_setup,
2686         },
2687         /*
2688          * Broadcom TruManage (NetXtreme)
2689          */
2690         {
2691                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2692                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2693                 .subvendor      = PCI_ANY_ID,
2694                 .subdevice      = PCI_ANY_ID,
2695                 .setup          = pci_brcm_trumanage_setup,
2696         },
2697         {
2698                 .vendor         = 0x1c29,
2699                 .device         = 0x1104,
2700                 .subvendor      = PCI_ANY_ID,
2701                 .subdevice      = PCI_ANY_ID,
2702                 .setup          = pci_fintek_setup,
2703                 .init           = pci_fintek_init,
2704         },
2705         {
2706                 .vendor         = 0x1c29,
2707                 .device         = 0x1108,
2708                 .subvendor      = PCI_ANY_ID,
2709                 .subdevice      = PCI_ANY_ID,
2710                 .setup          = pci_fintek_setup,
2711                 .init           = pci_fintek_init,
2712         },
2713         {
2714                 .vendor         = 0x1c29,
2715                 .device         = 0x1112,
2716                 .subvendor      = PCI_ANY_ID,
2717                 .subdevice      = PCI_ANY_ID,
2718                 .setup          = pci_fintek_setup,
2719                 .init           = pci_fintek_init,
2720         },
2721
2722         /*
2723          * Default "match everything" terminator entry
2724          */
2725         {
2726                 .vendor         = PCI_ANY_ID,
2727                 .device         = PCI_ANY_ID,
2728                 .subvendor      = PCI_ANY_ID,
2729                 .subdevice      = PCI_ANY_ID,
2730                 .setup          = pci_default_setup,
2731         }
2732 };
2733
2734 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2735 {
2736         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2737 }
2738
2739 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2740 {
2741         struct pci_serial_quirk *quirk;
2742
2743         for (quirk = pci_serial_quirks; ; quirk++)
2744                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2745                     quirk_id_matches(quirk->device, dev->device) &&
2746                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2747                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2748                         break;
2749         return quirk;
2750 }
2751
2752 static inline int get_pci_irq(struct pci_dev *dev,
2753                                 const struct pciserial_board *board)
2754 {
2755         if (board->flags & FL_NOIRQ)
2756                 return 0;
2757         else
2758                 return dev->irq;
2759 }
2760
2761 /*
2762  * This is the configuration table for all of the PCI serial boards
2763  * which we support.  It is directly indexed by the pci_board_num_t enum
2764  * value, which is encoded in the pci_device_id PCI probe table's
2765  * driver_data member.
2766  *
2767  * The makeup of these names are:
2768  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2769  *
2770  *  bn          = PCI BAR number
2771  *  bt          = Index using PCI BARs
2772  *  n           = number of serial ports
2773  *  baud        = baud rate
2774  *  offsetinhex = offset for each sequential port (in hex)
2775  *
2776  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2777  *
2778  * Please note: in theory if n = 1, _bt infix should make no difference.
2779  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2780  */
2781 enum pci_board_num_t {
2782         pbn_default = 0,
2783
2784         pbn_b0_1_115200,
2785         pbn_b0_2_115200,
2786         pbn_b0_4_115200,
2787         pbn_b0_5_115200,
2788         pbn_b0_8_115200,
2789
2790         pbn_b0_1_921600,
2791         pbn_b0_2_921600,
2792         pbn_b0_4_921600,
2793
2794         pbn_b0_2_1130000,
2795
2796         pbn_b0_4_1152000,
2797
2798         pbn_b0_2_1152000_200,
2799         pbn_b0_4_1152000_200,
2800         pbn_b0_8_1152000_200,
2801
2802         pbn_b0_2_1843200,
2803         pbn_b0_4_1843200,
2804
2805         pbn_b0_2_1843200_200,
2806         pbn_b0_4_1843200_200,
2807         pbn_b0_8_1843200_200,
2808
2809         pbn_b0_1_4000000,
2810
2811         pbn_b0_bt_1_115200,
2812         pbn_b0_bt_2_115200,
2813         pbn_b0_bt_4_115200,
2814         pbn_b0_bt_8_115200,
2815
2816         pbn_b0_bt_1_460800,
2817         pbn_b0_bt_2_460800,
2818         pbn_b0_bt_4_460800,
2819
2820         pbn_b0_bt_1_921600,
2821         pbn_b0_bt_2_921600,
2822         pbn_b0_bt_4_921600,
2823         pbn_b0_bt_8_921600,
2824
2825         pbn_b1_1_115200,
2826         pbn_b1_2_115200,
2827         pbn_b1_4_115200,
2828         pbn_b1_8_115200,
2829         pbn_b1_16_115200,
2830
2831         pbn_b1_1_921600,
2832         pbn_b1_2_921600,
2833         pbn_b1_4_921600,
2834         pbn_b1_8_921600,
2835
2836         pbn_b1_2_1250000,
2837
2838         pbn_b1_bt_1_115200,
2839         pbn_b1_bt_2_115200,
2840         pbn_b1_bt_4_115200,
2841
2842         pbn_b1_bt_2_921600,
2843
2844         pbn_b1_1_1382400,
2845         pbn_b1_2_1382400,
2846         pbn_b1_4_1382400,
2847         pbn_b1_8_1382400,
2848
2849         pbn_b2_1_115200,
2850         pbn_b2_2_115200,
2851         pbn_b2_4_115200,
2852         pbn_b2_8_115200,
2853
2854         pbn_b2_1_460800,
2855         pbn_b2_4_460800,
2856         pbn_b2_8_460800,
2857         pbn_b2_16_460800,
2858
2859         pbn_b2_1_921600,
2860         pbn_b2_4_921600,
2861         pbn_b2_8_921600,
2862
2863         pbn_b2_8_1152000,
2864
2865         pbn_b2_bt_1_115200,
2866         pbn_b2_bt_2_115200,
2867         pbn_b2_bt_4_115200,
2868
2869         pbn_b2_bt_2_921600,
2870         pbn_b2_bt_4_921600,
2871
2872         pbn_b3_2_115200,
2873         pbn_b3_4_115200,
2874         pbn_b3_8_115200,
2875
2876         pbn_b4_bt_2_921600,
2877         pbn_b4_bt_4_921600,
2878         pbn_b4_bt_8_921600,
2879
2880         /*
2881          * Board-specific versions.
2882          */
2883         pbn_panacom,
2884         pbn_panacom2,
2885         pbn_panacom4,
2886         pbn_plx_romulus,
2887         pbn_endrun_2_4000000,
2888         pbn_oxsemi,
2889         pbn_oxsemi_1_4000000,
2890         pbn_oxsemi_2_4000000,
2891         pbn_oxsemi_4_4000000,
2892         pbn_oxsemi_8_4000000,
2893         pbn_intel_i960,
2894         pbn_sgi_ioc3,
2895         pbn_computone_4,
2896         pbn_computone_6,
2897         pbn_computone_8,
2898         pbn_sbsxrsio,
2899         pbn_exar_XR17C152,
2900         pbn_exar_XR17C154,
2901         pbn_exar_XR17C158,
2902         pbn_exar_XR17V352,
2903         pbn_exar_XR17V354,
2904         pbn_exar_XR17V358,
2905         pbn_exar_XR17V4358,
2906         pbn_exar_XR17V8358,
2907         pbn_exar_ibm_saturn,
2908         pbn_pasemi_1682M,
2909         pbn_ni8430_2,
2910         pbn_ni8430_4,
2911         pbn_ni8430_8,
2912         pbn_ni8430_16,
2913         pbn_ADDIDATA_PCIe_1_3906250,
2914         pbn_ADDIDATA_PCIe_2_3906250,
2915         pbn_ADDIDATA_PCIe_4_3906250,
2916         pbn_ADDIDATA_PCIe_8_3906250,
2917         pbn_ce4100_1_115200,
2918         pbn_byt,
2919         pbn_qrk,
2920         pbn_omegapci,
2921         pbn_NETMOS9900_2s_115200,
2922         pbn_brcm_trumanage,
2923         pbn_fintek_4,
2924         pbn_fintek_8,
2925         pbn_fintek_12,
2926         pbn_wch384_4,
2927         pbn_pericom_PI7C9X7951,
2928         pbn_pericom_PI7C9X7952,
2929         pbn_pericom_PI7C9X7954,
2930         pbn_pericom_PI7C9X7958,
2931 };
2932
2933 /*
2934  * uart_offset - the space between channels
2935  * reg_shift   - describes how the UART registers are mapped
2936  *               to PCI memory by the card.
2937  * For example IER register on SBS, Inc. PMC-OctPro is located at
2938  * offset 0x10 from the UART base, while UART_IER is defined as 1
2939  * in include/linux/serial_reg.h,
2940  * see first lines of serial_in() and serial_out() in 8250.c
2941 */
2942
2943 static struct pciserial_board pci_boards[] = {
2944         [pbn_default] = {
2945                 .flags          = FL_BASE0,
2946                 .num_ports      = 1,
2947                 .base_baud      = 115200,
2948                 .uart_offset    = 8,
2949         },
2950         [pbn_b0_1_115200] = {
2951                 .flags          = FL_BASE0,
2952                 .num_ports      = 1,
2953                 .base_baud      = 115200,
2954                 .uart_offset    = 8,
2955         },
2956         [pbn_b0_2_115200] = {
2957                 .flags          = FL_BASE0,
2958                 .num_ports      = 2,
2959                 .base_baud      = 115200,
2960                 .uart_offset    = 8,
2961         },
2962         [pbn_b0_4_115200] = {
2963                 .flags          = FL_BASE0,
2964                 .num_ports      = 4,
2965                 .base_baud      = 115200,
2966                 .uart_offset    = 8,
2967         },
2968         [pbn_b0_5_115200] = {
2969                 .flags          = FL_BASE0,
2970                 .num_ports      = 5,
2971                 .base_baud      = 115200,
2972                 .uart_offset    = 8,
2973         },
2974         [pbn_b0_8_115200] = {
2975                 .flags          = FL_BASE0,
2976                 .num_ports      = 8,
2977                 .base_baud      = 115200,
2978                 .uart_offset    = 8,
2979         },
2980         [pbn_b0_1_921600] = {
2981                 .flags          = FL_BASE0,
2982                 .num_ports      = 1,
2983                 .base_baud      = 921600,
2984                 .uart_offset    = 8,
2985         },
2986         [pbn_b0_2_921600] = {
2987                 .flags          = FL_BASE0,
2988                 .num_ports      = 2,
2989                 .base_baud      = 921600,
2990                 .uart_offset    = 8,
2991         },
2992         [pbn_b0_4_921600] = {
2993                 .flags          = FL_BASE0,
2994                 .num_ports      = 4,
2995                 .base_baud      = 921600,
2996                 .uart_offset    = 8,
2997         },
2998
2999         [pbn_b0_2_1130000] = {
3000                 .flags          = FL_BASE0,
3001                 .num_ports      = 2,
3002                 .base_baud      = 1130000,
3003                 .uart_offset    = 8,
3004         },
3005
3006         [pbn_b0_4_1152000] = {
3007                 .flags          = FL_BASE0,
3008                 .num_ports      = 4,
3009                 .base_baud      = 1152000,
3010                 .uart_offset    = 8,
3011         },
3012
3013         [pbn_b0_2_1152000_200] = {
3014                 .flags          = FL_BASE0,
3015                 .num_ports      = 2,
3016                 .base_baud      = 1152000,
3017                 .uart_offset    = 0x200,
3018         },
3019
3020         [pbn_b0_4_1152000_200] = {
3021                 .flags          = FL_BASE0,
3022                 .num_ports      = 4,
3023                 .base_baud      = 1152000,
3024                 .uart_offset    = 0x200,
3025         },
3026
3027         [pbn_b0_8_1152000_200] = {
3028                 .flags          = FL_BASE0,
3029                 .num_ports      = 8,
3030                 .base_baud      = 1152000,
3031                 .uart_offset    = 0x200,
3032         },
3033
3034         [pbn_b0_2_1843200] = {
3035                 .flags          = FL_BASE0,
3036                 .num_ports      = 2,
3037                 .base_baud      = 1843200,
3038                 .uart_offset    = 8,
3039         },
3040         [pbn_b0_4_1843200] = {
3041                 .flags          = FL_BASE0,
3042                 .num_ports      = 4,
3043                 .base_baud      = 1843200,
3044                 .uart_offset    = 8,
3045         },
3046
3047         [pbn_b0_2_1843200_200] = {
3048                 .flags          = FL_BASE0,
3049                 .num_ports      = 2,
3050                 .base_baud      = 1843200,
3051                 .uart_offset    = 0x200,
3052         },
3053         [pbn_b0_4_1843200_200] = {
3054                 .flags          = FL_BASE0,
3055                 .num_ports      = 4,
3056                 .base_baud      = 1843200,
3057                 .uart_offset    = 0x200,
3058         },
3059         [pbn_b0_8_1843200_200] = {
3060                 .flags          = FL_BASE0,
3061                 .num_ports      = 8,
3062                 .base_baud      = 1843200,
3063                 .uart_offset    = 0x200,
3064         },
3065         [pbn_b0_1_4000000] = {
3066                 .flags          = FL_BASE0,
3067                 .num_ports      = 1,
3068                 .base_baud      = 4000000,
3069                 .uart_offset    = 8,
3070         },
3071
3072         [pbn_b0_bt_1_115200] = {
3073                 .flags          = FL_BASE0|FL_BASE_BARS,
3074                 .num_ports      = 1,
3075                 .base_baud      = 115200,
3076                 .uart_offset    = 8,
3077         },
3078         [pbn_b0_bt_2_115200] = {
3079                 .flags          = FL_BASE0|FL_BASE_BARS,
3080                 .num_ports      = 2,
3081                 .base_baud      = 115200,
3082                 .uart_offset    = 8,
3083         },
3084         [pbn_b0_bt_4_115200] = {
3085                 .flags          = FL_BASE0|FL_BASE_BARS,
3086                 .num_ports      = 4,
3087                 .base_baud      = 115200,
3088                 .uart_offset    = 8,
3089         },
3090         [pbn_b0_bt_8_115200] = {
3091                 .flags          = FL_BASE0|FL_BASE_BARS,
3092                 .num_ports      = 8,
3093                 .base_baud      = 115200,
3094                 .uart_offset    = 8,
3095         },
3096
3097         [pbn_b0_bt_1_460800] = {
3098                 .flags          = FL_BASE0|FL_BASE_BARS,
3099                 .num_ports      = 1,
3100                 .base_baud      = 460800,
3101                 .uart_offset    = 8,
3102         },
3103         [pbn_b0_bt_2_460800] = {
3104                 .flags          = FL_BASE0|FL_BASE_BARS,
3105                 .num_ports      = 2,
3106                 .base_baud      = 460800,
3107                 .uart_offset    = 8,
3108         },
3109         [pbn_b0_bt_4_460800] = {
3110                 .flags          = FL_BASE0|FL_BASE_BARS,
3111                 .num_ports      = 4,
3112                 .base_baud      = 460800,
3113                 .uart_offset    = 8,
3114         },
3115
3116         [pbn_b0_bt_1_921600] = {
3117                 .flags          = FL_BASE0|FL_BASE_BARS,
3118                 .num_ports      = 1,
3119                 .base_baud      = 921600,
3120                 .uart_offset    = 8,
3121         },
3122         [pbn_b0_bt_2_921600] = {
3123                 .flags          = FL_BASE0|FL_BASE_BARS,
3124                 .num_ports      = 2,
3125                 .base_baud      = 921600,
3126                 .uart_offset    = 8,
3127         },
3128         [pbn_b0_bt_4_921600] = {
3129                 .flags          = FL_BASE0|FL_BASE_BARS,
3130                 .num_ports      = 4,
3131                 .base_baud      = 921600,
3132                 .uart_offset    = 8,
3133         },
3134         [pbn_b0_bt_8_921600] = {
3135                 .flags          = FL_BASE0|FL_BASE_BARS,
3136                 .num_ports      = 8,
3137                 .base_baud      = 921600,
3138                 .uart_offset    = 8,
3139         },
3140
3141         [pbn_b1_1_115200] = {
3142                 .flags          = FL_BASE1,
3143                 .num_ports      = 1,
3144                 .base_baud      = 115200,
3145                 .uart_offset    = 8,
3146         },
3147         [pbn_b1_2_115200] = {
3148                 .flags          = FL_BASE1,
3149                 .num_ports      = 2,
3150                 .base_baud      = 115200,
3151                 .uart_offset    = 8,
3152         },
3153         [pbn_b1_4_115200] = {
3154                 .flags          = FL_BASE1,
3155                 .num_ports      = 4,
3156                 .base_baud      = 115200,
3157                 .uart_offset    = 8,
3158         },
3159         [pbn_b1_8_115200] = {
3160                 .flags          = FL_BASE1,
3161                 .num_ports      = 8,
3162                 .base_baud      = 115200,
3163                 .uart_offset    = 8,
3164         },
3165         [pbn_b1_16_115200] = {
3166                 .flags          = FL_BASE1,
3167                 .num_ports      = 16,
3168                 .base_baud      = 115200,
3169                 .uart_offset    = 8,
3170         },
3171
3172         [pbn_b1_1_921600] = {
3173                 .flags          = FL_BASE1,
3174                 .num_ports      = 1,
3175                 .base_baud      = 921600,
3176                 .uart_offset    = 8,
3177         },
3178         [pbn_b1_2_921600] = {
3179                 .flags          = FL_BASE1,
3180                 .num_ports      = 2,
3181                 .base_baud      = 921600,
3182                 .uart_offset    = 8,
3183         },
3184         [pbn_b1_4_921600] = {
3185                 .flags          = FL_BASE1,
3186                 .num_ports      = 4,
3187                 .base_baud      = 921600,
3188                 .uart_offset    = 8,
3189         },
3190         [pbn_b1_8_921600] = {
3191                 .flags          = FL_BASE1,
3192                 .num_ports      = 8,
3193                 .base_baud      = 921600,
3194                 .uart_offset    = 8,
3195         },
3196         [pbn_b1_2_1250000] = {
3197                 .flags          = FL_BASE1,
3198                 .num_ports      = 2,
3199                 .base_baud      = 1250000,
3200                 .uart_offset    = 8,
3201         },
3202
3203         [pbn_b1_bt_1_115200] = {
3204                 .flags          = FL_BASE1|FL_BASE_BARS,
3205                 .num_ports      = 1,
3206                 .base_baud      = 115200,
3207                 .uart_offset    = 8,
3208         },
3209         [pbn_b1_bt_2_115200] = {
3210                 .flags          = FL_BASE1|FL_BASE_BARS,
3211                 .num_ports      = 2,
3212                 .base_baud      = 115200,
3213                 .uart_offset    = 8,
3214         },
3215         [pbn_b1_bt_4_115200] = {
3216                 .flags          = FL_BASE1|FL_BASE_BARS,
3217                 .num_ports      = 4,
3218                 .base_baud      = 115200,
3219                 .uart_offset    = 8,
3220         },
3221
3222         [pbn_b1_bt_2_921600] = {
3223                 .flags          = FL_BASE1|FL_BASE_BARS,
3224                 .num_ports      = 2,
3225                 .base_baud      = 921600,
3226                 .uart_offset    = 8,
3227         },
3228
3229         [pbn_b1_1_1382400] = {
3230                 .flags          = FL_BASE1,
3231                 .num_ports      = 1,
3232                 .base_baud      = 1382400,
3233                 .uart_offset    = 8,
3234         },
3235         [pbn_b1_2_1382400] = {
3236                 .flags          = FL_BASE1,
3237                 .num_ports      = 2,
3238                 .base_baud      = 1382400,
3239                 .uart_offset    = 8,
3240         },
3241         [pbn_b1_4_1382400] = {
3242                 .flags          = FL_BASE1,
3243                 .num_ports      = 4,
3244                 .base_baud      = 1382400,
3245                 .uart_offset    = 8,
3246         },
3247         [pbn_b1_8_1382400] = {
3248                 .flags          = FL_BASE1,
3249                 .num_ports      = 8,
3250                 .base_baud      = 1382400,
3251                 .uart_offset    = 8,
3252         },
3253
3254         [pbn_b2_1_115200] = {
3255                 .flags          = FL_BASE2,
3256                 .num_ports      = 1,
3257                 .base_baud      = 115200,
3258                 .uart_offset    = 8,
3259         },
3260         [pbn_b2_2_115200] = {
3261                 .flags          = FL_BASE2,
3262                 .num_ports      = 2,
3263                 .base_baud      = 115200,
3264                 .uart_offset    = 8,
3265         },
3266         [pbn_b2_4_115200] = {
3267                 .flags          = FL_BASE2,
3268                 .num_ports      = 4,
3269                 .base_baud      = 115200,
3270                 .uart_offset    = 8,
3271         },
3272         [pbn_b2_8_115200] = {
3273                 .flags          = FL_BASE2,
3274                 .num_ports      = 8,
3275                 .base_baud      = 115200,
3276                 .uart_offset    = 8,
3277         },
3278
3279         [pbn_b2_1_460800] = {
3280                 .flags          = FL_BASE2,
3281                 .num_ports      = 1,
3282                 .base_baud      = 460800,
3283                 .uart_offset    = 8,
3284         },
3285         [pbn_b2_4_460800] = {
3286                 .flags          = FL_BASE2,
3287                 .num_ports      = 4,
3288                 .base_baud      = 460800,
3289                 .uart_offset    = 8,
3290         },
3291         [pbn_b2_8_460800] = {
3292                 .flags          = FL_BASE2,
3293                 .num_ports      = 8,
3294                 .base_baud      = 460800,
3295                 .uart_offset    = 8,
3296         },
3297         [pbn_b2_16_460800] = {
3298                 .flags          = FL_BASE2,
3299                 .num_ports      = 16,
3300                 .base_baud      = 460800,
3301                 .uart_offset    = 8,
3302          },
3303
3304         [pbn_b2_1_921600] = {
3305                 .flags          = FL_BASE2,
3306                 .num_ports      = 1,
3307                 .base_baud      = 921600,
3308                 .uart_offset    = 8,
3309         },
3310         [pbn_b2_4_921600] = {
3311                 .flags          = FL_BASE2,
3312                 .num_ports      = 4,
3313                 .base_baud      = 921600,
3314                 .uart_offset    = 8,
3315         },
3316         [pbn_b2_8_921600] = {
3317                 .flags          = FL_BASE2,
3318                 .num_ports      = 8,
3319                 .base_baud      = 921600,
3320                 .uart_offset    = 8,
3321         },
3322
3323         [pbn_b2_8_1152000] = {
3324                 .flags          = FL_BASE2,
3325                 .num_ports      = 8,
3326                 .base_baud      = 1152000,
3327                 .uart_offset    = 8,
3328         },
3329
3330         [pbn_b2_bt_1_115200] = {
3331                 .flags          = FL_BASE2|FL_BASE_BARS,
3332                 .num_ports      = 1,
3333                 .base_baud      = 115200,
3334                 .uart_offset    = 8,
3335         },
3336         [pbn_b2_bt_2_115200] = {
3337                 .flags          = FL_BASE2|FL_BASE_BARS,
3338                 .num_ports      = 2,
3339                 .base_baud      = 115200,
3340                 .uart_offset    = 8,
3341         },
3342         [pbn_b2_bt_4_115200] = {
3343                 .flags          = FL_BASE2|FL_BASE_BARS,
3344                 .num_ports      = 4,
3345                 .base_baud      = 115200,
3346                 .uart_offset    = 8,
3347         },
3348
3349         [pbn_b2_bt_2_921600] = {
3350                 .flags          = FL_BASE2|FL_BASE_BARS,
3351                 .num_ports      = 2,
3352                 .base_baud      = 921600,
3353                 .uart_offset    = 8,
3354         },
3355         [pbn_b2_bt_4_921600] = {
3356                 .flags          = FL_BASE2|FL_BASE_BARS,
3357                 .num_ports      = 4,
3358                 .base_baud      = 921600,
3359                 .uart_offset    = 8,
3360         },
3361
3362         [pbn_b3_2_115200] = {
3363                 .flags          = FL_BASE3,
3364                 .num_ports      = 2,
3365                 .base_baud      = 115200,
3366                 .uart_offset    = 8,
3367         },
3368         [pbn_b3_4_115200] = {
3369                 .flags          = FL_BASE3,
3370                 .num_ports      = 4,
3371                 .base_baud      = 115200,
3372                 .uart_offset    = 8,
3373         },
3374         [pbn_b3_8_115200] = {
3375                 .flags          = FL_BASE3,
3376                 .num_ports      = 8,
3377                 .base_baud      = 115200,
3378                 .uart_offset    = 8,
3379         },
3380
3381         [pbn_b4_bt_2_921600] = {
3382                 .flags          = FL_BASE4,
3383                 .num_ports      = 2,
3384                 .base_baud      = 921600,
3385                 .uart_offset    = 8,
3386         },
3387         [pbn_b4_bt_4_921600] = {
3388                 .flags          = FL_BASE4,
3389                 .num_ports      = 4,
3390                 .base_baud      = 921600,
3391                 .uart_offset    = 8,
3392         },
3393         [pbn_b4_bt_8_921600] = {
3394                 .flags          = FL_BASE4,
3395                 .num_ports      = 8,
3396                 .base_baud      = 921600,
3397                 .uart_offset    = 8,
3398         },
3399
3400         /*
3401          * Entries following this are board-specific.
3402          */
3403
3404         /*
3405          * Panacom - IOMEM
3406          */
3407         [pbn_panacom] = {
3408                 .flags          = FL_BASE2,
3409                 .num_ports      = 2,
3410                 .base_baud      = 921600,
3411                 .uart_offset    = 0x400,
3412                 .reg_shift      = 7,
3413         },
3414         [pbn_panacom2] = {
3415                 .flags          = FL_BASE2|FL_BASE_BARS,
3416                 .num_ports      = 2,
3417                 .base_baud      = 921600,
3418                 .uart_offset    = 0x400,
3419                 .reg_shift      = 7,
3420         },
3421         [pbn_panacom4] = {
3422                 .flags          = FL_BASE2|FL_BASE_BARS,
3423                 .num_ports      = 4,
3424                 .base_baud      = 921600,
3425                 .uart_offset    = 0x400,
3426                 .reg_shift      = 7,
3427         },
3428
3429         /* I think this entry is broken - the first_offset looks wrong --rmk */
3430         [pbn_plx_romulus] = {
3431                 .flags          = FL_BASE2,
3432                 .num_ports      = 4,
3433                 .base_baud      = 921600,
3434                 .uart_offset    = 8 << 2,
3435                 .reg_shift      = 2,
3436                 .first_offset   = 0x03,
3437         },
3438
3439         /*
3440          * EndRun Technologies
3441         * Uses the size of PCI Base region 0 to
3442         * signal now many ports are available
3443         * 2 port 952 Uart support
3444         */
3445         [pbn_endrun_2_4000000] = {
3446                 .flags          = FL_BASE0,
3447                 .num_ports      = 2,
3448                 .base_baud      = 4000000,
3449                 .uart_offset    = 0x200,
3450                 .first_offset   = 0x1000,
3451         },
3452
3453         /*
3454          * This board uses the size of PCI Base region 0 to
3455          * signal now many ports are available
3456          */
3457         [pbn_oxsemi] = {
3458                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3459                 .num_ports      = 32,
3460                 .base_baud      = 115200,
3461                 .uart_offset    = 8,
3462         },
3463         [pbn_oxsemi_1_4000000] = {
3464                 .flags          = FL_BASE0,
3465                 .num_ports      = 1,
3466                 .base_baud      = 4000000,
3467                 .uart_offset    = 0x200,
3468                 .first_offset   = 0x1000,
3469         },
3470         [pbn_oxsemi_2_4000000] = {
3471                 .flags          = FL_BASE0,
3472                 .num_ports      = 2,
3473                 .base_baud      = 4000000,
3474                 .uart_offset    = 0x200,
3475                 .first_offset   = 0x1000,
3476         },
3477         [pbn_oxsemi_4_4000000] = {
3478                 .flags          = FL_BASE0,
3479                 .num_ports      = 4,
3480                 .base_baud      = 4000000,
3481                 .uart_offset    = 0x200,
3482                 .first_offset   = 0x1000,
3483         },
3484         [pbn_oxsemi_8_4000000] = {
3485                 .flags          = FL_BASE0,
3486                 .num_ports      = 8,
3487                 .base_baud      = 4000000,
3488                 .uart_offset    = 0x200,
3489                 .first_offset   = 0x1000,
3490         },
3491
3492
3493         /*
3494          * EKF addition for i960 Boards form EKF with serial port.
3495          * Max 256 ports.
3496          */
3497         [pbn_intel_i960] = {
3498                 .flags          = FL_BASE0,
3499                 .num_ports      = 32,
3500                 .base_baud      = 921600,
3501                 .uart_offset    = 8 << 2,
3502                 .reg_shift      = 2,
3503                 .first_offset   = 0x10000,
3504         },
3505         [pbn_sgi_ioc3] = {
3506                 .flags          = FL_BASE0|FL_NOIRQ,
3507                 .num_ports      = 1,
3508                 .base_baud      = 458333,
3509                 .uart_offset    = 8,
3510                 .reg_shift      = 0,
3511                 .first_offset   = 0x20178,
3512         },
3513
3514         /*
3515          * Computone - uses IOMEM.
3516          */
3517         [pbn_computone_4] = {
3518                 .flags          = FL_BASE0,
3519                 .num_ports      = 4,
3520                 .base_baud      = 921600,
3521                 .uart_offset    = 0x40,
3522                 .reg_shift      = 2,
3523                 .first_offset   = 0x200,
3524         },
3525         [pbn_computone_6] = {
3526                 .flags          = FL_BASE0,
3527                 .num_ports      = 6,
3528                 .base_baud      = 921600,
3529                 .uart_offset    = 0x40,
3530                 .reg_shift      = 2,
3531                 .first_offset   = 0x200,
3532         },
3533         [pbn_computone_8] = {
3534                 .flags          = FL_BASE0,
3535                 .num_ports      = 8,
3536                 .base_baud      = 921600,
3537                 .uart_offset    = 0x40,
3538                 .reg_shift      = 2,
3539                 .first_offset   = 0x200,
3540         },
3541         [pbn_sbsxrsio] = {
3542                 .flags          = FL_BASE0,
3543                 .num_ports      = 8,
3544                 .base_baud      = 460800,
3545                 .uart_offset    = 256,
3546                 .reg_shift      = 4,
3547         },
3548         /*
3549          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3550          *  Only basic 16550A support.
3551          *  XR17C15[24] are not tested, but they should work.
3552          */
3553         [pbn_exar_XR17C152] = {
3554                 .flags          = FL_BASE0,
3555                 .num_ports      = 2,
3556                 .base_baud      = 921600,
3557                 .uart_offset    = 0x200,
3558         },
3559         [pbn_exar_XR17C154] = {
3560                 .flags          = FL_BASE0,
3561                 .num_ports      = 4,
3562                 .base_baud      = 921600,
3563                 .uart_offset    = 0x200,
3564         },
3565         [pbn_exar_XR17C158] = {
3566                 .flags          = FL_BASE0,
3567                 .num_ports      = 8,
3568                 .base_baud      = 921600,
3569                 .uart_offset    = 0x200,
3570         },
3571         [pbn_exar_XR17V352] = {
3572                 .flags          = FL_BASE0,
3573                 .num_ports      = 2,
3574                 .base_baud      = 7812500,
3575                 .uart_offset    = 0x400,
3576                 .reg_shift      = 0,
3577                 .first_offset   = 0,
3578         },
3579         [pbn_exar_XR17V354] = {
3580                 .flags          = FL_BASE0,
3581                 .num_ports      = 4,
3582                 .base_baud      = 7812500,
3583                 .uart_offset    = 0x400,
3584                 .reg_shift      = 0,
3585                 .first_offset   = 0,
3586         },
3587         [pbn_exar_XR17V358] = {
3588                 .flags          = FL_BASE0,
3589                 .num_ports      = 8,
3590                 .base_baud      = 7812500,
3591                 .uart_offset    = 0x400,
3592                 .reg_shift      = 0,
3593                 .first_offset   = 0,
3594         },
3595         [pbn_exar_XR17V4358] = {
3596                 .flags          = FL_BASE0,
3597                 .num_ports      = 12,
3598                 .base_baud      = 7812500,
3599                 .uart_offset    = 0x400,
3600                 .reg_shift      = 0,
3601                 .first_offset   = 0,
3602         },
3603         [pbn_exar_XR17V8358] = {
3604                 .flags          = FL_BASE0,
3605                 .num_ports      = 16,
3606                 .base_baud      = 7812500,
3607                 .uart_offset    = 0x400,
3608                 .reg_shift      = 0,
3609                 .first_offset   = 0,
3610         },
3611         [pbn_exar_ibm_saturn] = {
3612                 .flags          = FL_BASE0,
3613                 .num_ports      = 1,
3614                 .base_baud      = 921600,
3615                 .uart_offset    = 0x200,
3616         },
3617
3618         /*
3619          * PA Semi PWRficient PA6T-1682M on-chip UART
3620          */
3621         [pbn_pasemi_1682M] = {
3622                 .flags          = FL_BASE0,
3623                 .num_ports      = 1,
3624                 .base_baud      = 8333333,
3625         },
3626         /*
3627          * National Instruments 843x
3628          */
3629         [pbn_ni8430_16] = {
3630                 .flags          = FL_BASE0,
3631                 .num_ports      = 16,
3632                 .base_baud      = 3686400,
3633                 .uart_offset    = 0x10,
3634                 .first_offset   = 0x800,
3635         },
3636         [pbn_ni8430_8] = {
3637                 .flags          = FL_BASE0,
3638                 .num_ports      = 8,
3639                 .base_baud      = 3686400,
3640                 .uart_offset    = 0x10,
3641                 .first_offset   = 0x800,
3642         },
3643         [pbn_ni8430_4] = {
3644                 .flags          = FL_BASE0,
3645                 .num_ports      = 4,
3646                 .base_baud      = 3686400,
3647                 .uart_offset    = 0x10,
3648                 .first_offset   = 0x800,
3649         },
3650         [pbn_ni8430_2] = {
3651                 .flags          = FL_BASE0,
3652                 .num_ports      = 2,
3653                 .base_baud      = 3686400,
3654                 .uart_offset    = 0x10,
3655                 .first_offset   = 0x800,
3656         },
3657         /*
3658          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3659          */
3660         [pbn_ADDIDATA_PCIe_1_3906250] = {
3661                 .flags          = FL_BASE0,
3662                 .num_ports      = 1,
3663                 .base_baud      = 3906250,
3664                 .uart_offset    = 0x200,
3665                 .first_offset   = 0x1000,
3666         },
3667         [pbn_ADDIDATA_PCIe_2_3906250] = {
3668                 .flags          = FL_BASE0,
3669                 .num_ports      = 2,
3670                 .base_baud      = 3906250,
3671                 .uart_offset    = 0x200,
3672                 .first_offset   = 0x1000,
3673         },
3674         [pbn_ADDIDATA_PCIe_4_3906250] = {
3675                 .flags          = FL_BASE0,
3676                 .num_ports      = 4,
3677                 .base_baud      = 3906250,
3678                 .uart_offset    = 0x200,
3679                 .first_offset   = 0x1000,
3680         },
3681         [pbn_ADDIDATA_PCIe_8_3906250] = {
3682                 .flags          = FL_BASE0,
3683                 .num_ports      = 8,
3684                 .base_baud      = 3906250,
3685                 .uart_offset    = 0x200,
3686                 .first_offset   = 0x1000,
3687         },
3688         [pbn_ce4100_1_115200] = {
3689                 .flags          = FL_BASE_BARS,
3690                 .num_ports      = 2,
3691                 .base_baud      = 921600,
3692                 .reg_shift      = 2,
3693         },
3694         /*
3695          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3696          * but is overridden by byt_set_termios.
3697          */
3698         [pbn_byt] = {
3699                 .flags          = FL_BASE0,
3700                 .num_ports      = 1,
3701                 .base_baud      = 2764800,
3702                 .uart_offset    = 0x80,
3703                 .reg_shift      = 2,
3704         },
3705         [pbn_qrk] = {
3706                 .flags          = FL_BASE0,
3707                 .num_ports      = 1,
3708                 .base_baud      = 2764800,
3709                 .reg_shift      = 2,
3710         },
3711         [pbn_omegapci] = {
3712                 .flags          = FL_BASE0,
3713                 .num_ports      = 8,
3714                 .base_baud      = 115200,
3715                 .uart_offset    = 0x200,
3716         },
3717         [pbn_NETMOS9900_2s_115200] = {
3718                 .flags          = FL_BASE0,
3719                 .num_ports      = 2,
3720                 .base_baud      = 115200,
3721         },
3722         [pbn_brcm_trumanage] = {
3723                 .flags          = FL_BASE0,
3724                 .num_ports      = 1,
3725                 .reg_shift      = 2,
3726                 .base_baud      = 115200,
3727         },
3728         [pbn_fintek_4] = {
3729                 .num_ports      = 4,
3730                 .uart_offset    = 8,
3731                 .base_baud      = 115200,
3732                 .first_offset   = 0x40,
3733         },
3734         [pbn_fintek_8] = {
3735                 .num_ports      = 8,
3736                 .uart_offset    = 8,
3737                 .base_baud      = 115200,
3738                 .first_offset   = 0x40,
3739         },
3740         [pbn_fintek_12] = {
3741                 .num_ports      = 12,
3742                 .uart_offset    = 8,
3743                 .base_baud      = 115200,
3744                 .first_offset   = 0x40,
3745         },
3746         [pbn_wch384_4] = {
3747                 .flags          = FL_BASE0,
3748                 .num_ports      = 4,
3749                 .base_baud      = 115200,
3750                 .uart_offset    = 8,
3751                 .first_offset   = 0xC0,
3752         },
3753         /*
3754          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3755          */
3756         [pbn_pericom_PI7C9X7951] = {
3757                 .flags          = FL_BASE0,
3758                 .num_ports      = 1,
3759                 .base_baud      = 921600,
3760                 .uart_offset    = 0x8,
3761         },
3762         [pbn_pericom_PI7C9X7952] = {
3763                 .flags          = FL_BASE0,
3764                 .num_ports      = 2,
3765                 .base_baud      = 921600,
3766                 .uart_offset    = 0x8,
3767         },
3768         [pbn_pericom_PI7C9X7954] = {
3769                 .flags          = FL_BASE0,
3770                 .num_ports      = 4,
3771                 .base_baud      = 921600,
3772                 .uart_offset    = 0x8,
3773         },
3774         [pbn_pericom_PI7C9X7958] = {
3775                 .flags          = FL_BASE0,
3776                 .num_ports      = 8,
3777                 .base_baud      = 921600,
3778                 .uart_offset    = 0x8,
3779         },
3780 };
3781
3782 static const struct pci_device_id blacklist[] = {
3783         /* softmodems */
3784         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3785         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3786         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3787
3788         /* multi-io cards handled by parport_serial */
3789         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3790         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3791         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3792         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3793
3794         /* Intel platforms with MID UART */
3795         { PCI_VDEVICE(INTEL, 0x081b), },
3796         { PCI_VDEVICE(INTEL, 0x081c), },
3797         { PCI_VDEVICE(INTEL, 0x081d), },
3798         { PCI_VDEVICE(INTEL, 0x1191), },
3799         { PCI_VDEVICE(INTEL, 0x19d8), },
3800 };
3801
3802 /*
3803  * Given a complete unknown PCI device, try to use some heuristics to
3804  * guess what the configuration might be, based on the pitiful PCI
3805  * serial specs.  Returns 0 on success, 1 on failure.
3806  */
3807 static int
3808 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3809 {
3810         const struct pci_device_id *bldev;
3811         int num_iomem, num_port, first_port = -1, i;
3812
3813         /*
3814          * If it is not a communications device or the programming
3815          * interface is greater than 6, give up.
3816          *
3817          * (Should we try to make guesses for multiport serial devices
3818          * later?)
3819          */
3820         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3821              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3822             (dev->class & 0xff) > 6)
3823                 return -ENODEV;
3824
3825         /*
3826          * Do not access blacklisted devices that are known not to
3827          * feature serial ports or are handled by other modules.
3828          */
3829         for (bldev = blacklist;
3830              bldev < blacklist + ARRAY_SIZE(blacklist);
3831              bldev++) {
3832                 if (dev->vendor == bldev->vendor &&
3833                     dev->device == bldev->device)
3834                         return -ENODEV;
3835         }
3836
3837         num_iomem = num_port = 0;
3838         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3839                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3840                         num_port++;
3841                         if (first_port == -1)
3842                                 first_port = i;
3843                 }
3844                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3845                         num_iomem++;
3846         }
3847
3848         /*
3849          * If there is 1 or 0 iomem regions, and exactly one port,
3850          * use it.  We guess the number of ports based on the IO
3851          * region size.
3852          */
3853         if (num_iomem <= 1 && num_port == 1) {
3854                 board->flags = first_port;
3855                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3856                 return 0;
3857         }
3858
3859         /*
3860          * Now guess if we've got a board which indexes by BARs.
3861          * Each IO BAR should be 8 bytes, and they should follow
3862          * consecutively.
3863          */
3864         first_port = -1;
3865         num_port = 0;
3866         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3867                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3868                     pci_resource_len(dev, i) == 8 &&
3869                     (first_port == -1 || (first_port + num_port) == i)) {
3870                         num_port++;
3871                         if (first_port == -1)
3872                                 first_port = i;
3873                 }
3874         }
3875
3876         if (num_port > 1) {
3877                 board->flags = first_port | FL_BASE_BARS;
3878                 board->num_ports = num_port;
3879                 return 0;
3880         }
3881
3882         return -ENODEV;
3883 }
3884
3885 static inline int
3886 serial_pci_matches(const struct pciserial_board *board,
3887                    const struct pciserial_board *guessed)
3888 {
3889         return
3890             board->num_ports == guessed->num_ports &&
3891             board->base_baud == guessed->base_baud &&
3892             board->uart_offset == guessed->uart_offset &&
3893             board->reg_shift == guessed->reg_shift &&
3894             board->first_offset == guessed->first_offset;
3895 }
3896
3897 struct serial_private *
3898 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3899 {
3900         struct uart_8250_port uart;
3901         struct serial_private *priv;
3902         struct pci_serial_quirk *quirk;
3903         int rc, nr_ports, i;
3904
3905         nr_ports = board->num_ports;
3906
3907         /*
3908          * Find an init and setup quirks.
3909          */
3910         quirk = find_quirk(dev);
3911
3912         /*
3913          * Run the new-style initialization function.
3914          * The initialization function returns:
3915          *  <0  - error
3916          *   0  - use board->num_ports
3917          *  >0  - number of ports
3918          */
3919         if (quirk->init) {
3920                 rc = quirk->init(dev);
3921                 if (rc < 0) {
3922                         priv = ERR_PTR(rc);
3923                         goto err_out;
3924                 }
3925                 if (rc)
3926                         nr_ports = rc;
3927         }
3928
3929         priv = kzalloc(sizeof(struct serial_private) +
3930                        sizeof(unsigned int) * nr_ports,
3931                        GFP_KERNEL);
3932         if (!priv) {
3933                 priv = ERR_PTR(-ENOMEM);
3934                 goto err_deinit;
3935         }
3936
3937         priv->dev = dev;
3938         priv->quirk = quirk;
3939
3940         memset(&uart, 0, sizeof(uart));
3941         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3942         uart.port.uartclk = board->base_baud * 16;
3943         uart.port.irq = get_pci_irq(dev, board);
3944         uart.port.dev = &dev->dev;
3945
3946         for (i = 0; i < nr_ports; i++) {
3947                 if (quirk->setup(priv, board, &uart, i))
3948                         break;
3949
3950                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3951                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3952
3953                 priv->line[i] = serial8250_register_8250_port(&uart);
3954                 if (priv->line[i] < 0) {
3955                         dev_err(&dev->dev,
3956                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3957                                 uart.port.iobase, uart.port.irq,
3958                                 uart.port.iotype, priv->line[i]);
3959                         break;
3960                 }
3961         }
3962         priv->nr = i;
3963         return priv;
3964
3965 err_deinit:
3966         if (quirk->exit)
3967                 quirk->exit(dev);
3968 err_out:
3969         return priv;
3970 }
3971 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3972
3973 void pciserial_remove_ports(struct serial_private *priv)
3974 {
3975         struct pci_serial_quirk *quirk;
3976         int i;
3977
3978         for (i = 0; i < priv->nr; i++)
3979                 serial8250_unregister_port(priv->line[i]);
3980
3981         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3982                 if (priv->remapped_bar[i])
3983                         iounmap(priv->remapped_bar[i]);
3984                 priv->remapped_bar[i] = NULL;
3985         }
3986
3987         /*
3988          * Find the exit quirks.
3989          */
3990         quirk = find_quirk(priv->dev);
3991         if (quirk->exit)
3992                 quirk->exit(priv->dev);
3993
3994         kfree(priv);
3995 }
3996 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3997
3998 void pciserial_suspend_ports(struct serial_private *priv)
3999 {
4000         int i;
4001
4002         for (i = 0; i < priv->nr; i++)
4003                 if (priv->line[i] >= 0)
4004                         serial8250_suspend_port(priv->line[i]);
4005
4006         /*
4007          * Ensure that every init quirk is properly torn down
4008          */
4009         if (priv->quirk->exit)
4010                 priv->quirk->exit(priv->dev);
4011 }
4012 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4013
4014 void pciserial_resume_ports(struct serial_private *priv)
4015 {
4016         int i;
4017
4018         /*
4019          * Ensure that the board is correctly configured.
4020          */
4021         if (priv->quirk->init)
4022                 priv->quirk->init(priv->dev);
4023
4024         for (i = 0; i < priv->nr; i++)
4025                 if (priv->line[i] >= 0)
4026                         serial8250_resume_port(priv->line[i]);
4027 }
4028 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4029
4030 /*
4031  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4032  * to the arrangement of serial ports on a PCI card.
4033  */
4034 static int
4035 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4036 {
4037         struct pci_serial_quirk *quirk;
4038         struct serial_private *priv;
4039         const struct pciserial_board *board;
4040         struct pciserial_board tmp;
4041         int rc;
4042
4043         quirk = find_quirk(dev);
4044         if (quirk->probe) {
4045                 rc = quirk->probe(dev);
4046                 if (rc)
4047                         return rc;
4048         }
4049
4050         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4051                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4052                         ent->driver_data);
4053                 return -EINVAL;
4054         }
4055
4056         board = &pci_boards[ent->driver_data];
4057
4058         rc = pci_enable_device(dev);
4059         pci_save_state(dev);
4060         if (rc)
4061                 return rc;
4062
4063         if (ent->driver_data == pbn_default) {
4064                 /*
4065                  * Use a copy of the pci_board entry for this;
4066                  * avoid changing entries in the table.
4067                  */
4068                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4069                 board = &tmp;
4070
4071                 /*
4072                  * We matched one of our class entries.  Try to
4073                  * determine the parameters of this board.
4074                  */
4075                 rc = serial_pci_guess_board(dev, &tmp);
4076                 if (rc)
4077                         goto disable;
4078         } else {
4079                 /*
4080                  * We matched an explicit entry.  If we are able to
4081                  * detect this boards settings with our heuristic,
4082                  * then we no longer need this entry.
4083                  */
4084                 memcpy(&tmp, &pci_boards[pbn_default],
4085                        sizeof(struct pciserial_board));
4086                 rc = serial_pci_guess_board(dev, &tmp);
4087                 if (rc == 0 && serial_pci_matches(board, &tmp))
4088                         moan_device("Redundant entry in serial pci_table.",
4089                                     dev);
4090         }
4091
4092         priv = pciserial_init_ports(dev, board);
4093         if (!IS_ERR(priv)) {
4094                 pci_set_drvdata(dev, priv);
4095                 return 0;
4096         }
4097
4098         rc = PTR_ERR(priv);
4099
4100  disable:
4101         pci_disable_device(dev);
4102         return rc;
4103 }
4104
4105 static void pciserial_remove_one(struct pci_dev *dev)
4106 {
4107         struct serial_private *priv = pci_get_drvdata(dev);
4108
4109         pciserial_remove_ports(priv);
4110
4111         pci_disable_device(dev);
4112 }
4113
4114 #ifdef CONFIG_PM_SLEEP
4115 static int pciserial_suspend_one(struct device *dev)
4116 {
4117         struct pci_dev *pdev = to_pci_dev(dev);
4118         struct serial_private *priv = pci_get_drvdata(pdev);
4119
4120         if (priv)
4121                 pciserial_suspend_ports(priv);
4122
4123         return 0;
4124 }
4125
4126 static int pciserial_resume_one(struct device *dev)
4127 {
4128         struct pci_dev *pdev = to_pci_dev(dev);
4129         struct serial_private *priv = pci_get_drvdata(pdev);
4130         int err;
4131
4132         if (priv) {
4133                 /*
4134                  * The device may have been disabled.  Re-enable it.
4135                  */
4136                 err = pci_enable_device(pdev);
4137                 /* FIXME: We cannot simply error out here */
4138                 if (err)
4139                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4140                 pciserial_resume_ports(priv);
4141         }
4142         return 0;
4143 }
4144 #endif
4145
4146 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4147                          pciserial_resume_one);
4148
4149 static struct pci_device_id serial_pci_tbl[] = {
4150         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4151         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4152                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4153                 pbn_b2_8_921600 },
4154         /* Advantech also use 0x3618 and 0xf618 */
4155         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4156                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4157                 pbn_b0_4_921600 },
4158         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4159                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4160                 pbn_b0_4_921600 },
4161         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4162                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4163                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4164                 pbn_b1_8_1382400 },
4165         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4166                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4167                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4168                 pbn_b1_4_1382400 },
4169         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4170                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4171                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4172                 pbn_b1_2_1382400 },
4173         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4174                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4175                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4176                 pbn_b1_8_1382400 },
4177         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4178                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4179                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4180                 pbn_b1_4_1382400 },
4181         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4182                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4183                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4184                 pbn_b1_2_1382400 },
4185         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4186                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4187                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4188                 pbn_b1_8_921600 },
4189         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4190                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4191                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4192                 pbn_b1_8_921600 },
4193         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4194                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4195                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4196                 pbn_b1_4_921600 },
4197         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4198                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4199                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4200                 pbn_b1_4_921600 },
4201         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4202                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4203                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4204                 pbn_b1_2_921600 },
4205         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4206                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4207                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4208                 pbn_b1_8_921600 },
4209         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4210                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4211                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4212                 pbn_b1_8_921600 },
4213         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4214                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4215                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4216                 pbn_b1_4_921600 },
4217         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4218                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4219                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4220                 pbn_b1_2_1250000 },
4221         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4222                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4223                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4224                 pbn_b0_2_1843200 },
4225         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4226                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4227                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4228                 pbn_b0_4_1843200 },
4229         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4230                 PCI_VENDOR_ID_AFAVLAB,
4231                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4232                 pbn_b0_4_1152000 },
4233         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4234                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4235                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4236                 pbn_b0_2_1843200_200 },
4237         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4238                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4239                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4240                 pbn_b0_4_1843200_200 },
4241         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4242                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4243                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4244                 pbn_b0_8_1843200_200 },
4245         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4246                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4247                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4248                 pbn_b0_2_1843200_200 },
4249         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4250                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4251                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4252                 pbn_b0_4_1843200_200 },
4253         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4254                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4255                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4256                 pbn_b0_8_1843200_200 },
4257         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4258                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4259                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4260                 pbn_b0_2_1843200_200 },
4261         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4262                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4263                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4264                 pbn_b0_4_1843200_200 },
4265         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4266                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4267                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4268                 pbn_b0_8_1843200_200 },
4269         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4270                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4272                 pbn_b0_2_1843200_200 },
4273         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4274                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4276                 pbn_b0_4_1843200_200 },
4277         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4278                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4280                 pbn_b0_8_1843200_200 },
4281         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4282                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4283                 0, 0, pbn_exar_ibm_saturn },
4284
4285         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287                 pbn_b2_bt_1_115200 },
4288         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290                 pbn_b2_bt_2_115200 },
4291         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293                 pbn_b2_bt_4_115200 },
4294         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296                 pbn_b2_bt_2_115200 },
4297         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299                 pbn_b2_bt_4_115200 },
4300         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4302                 pbn_b2_8_115200 },
4303         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305                 pbn_b2_8_460800 },
4306         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4307                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308                 pbn_b2_8_115200 },
4309
4310         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312                 pbn_b2_bt_2_115200 },
4313         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315                 pbn_b2_bt_2_921600 },
4316         /*
4317          * VScom SPCOM800, from sl@s.pl
4318          */
4319         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321                 pbn_b2_8_921600 },
4322         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324                 pbn_b2_4_921600 },
4325         /* Unknown card - subdevice 0x1584 */
4326         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4327                 PCI_VENDOR_ID_PLX,
4328                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4329                 pbn_b2_4_115200 },
4330         /* Unknown card - subdevice 0x1588 */
4331         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4332                 PCI_VENDOR_ID_PLX,
4333                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4334                 pbn_b2_8_115200 },
4335         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4336                 PCI_SUBVENDOR_ID_KEYSPAN,
4337                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4338                 pbn_panacom },
4339         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4340                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341                 pbn_panacom4 },
4342         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344                 pbn_panacom2 },
4345         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4346                 PCI_VENDOR_ID_ESDGMBH,
4347                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4348                 pbn_b2_4_115200 },
4349         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4350                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4351                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4352                 pbn_b2_4_460800 },
4353         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4354                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4355                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4356                 pbn_b2_8_460800 },
4357         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4358                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4359                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4360                 pbn_b2_16_460800 },
4361         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4362                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4363                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4364                 pbn_b2_16_460800 },
4365         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4366                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4367                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4368                 pbn_b2_4_460800 },
4369         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4370                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4371                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4372                 pbn_b2_8_460800 },
4373         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4374                 PCI_SUBVENDOR_ID_EXSYS,
4375                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4376                 pbn_b2_4_115200 },
4377         /*
4378          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4379          * (Exoray@isys.ca)
4380          */
4381         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4382                 0x10b5, 0x106a, 0, 0,
4383                 pbn_plx_romulus },
4384         /*
4385         * EndRun Technologies. PCI express device range.
4386         *    EndRun PTP/1588 has 2 Native UARTs.
4387         */
4388         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390                 pbn_endrun_2_4000000 },
4391         /*
4392          * Quatech cards. These actually have configurable clocks but for
4393          * now we just use the default.
4394          *
4395          * 100 series are RS232, 200 series RS422,
4396          */
4397         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4398                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399                 pbn_b1_4_115200 },
4400         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4401                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402                 pbn_b1_2_115200 },
4403         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4404                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405                 pbn_b2_2_115200 },
4406         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4407                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408                 pbn_b1_2_115200 },
4409         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4410                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411                 pbn_b2_2_115200 },
4412         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4413                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414                 pbn_b1_4_115200 },
4415         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4416                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417                 pbn_b1_8_115200 },
4418         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420                 pbn_b1_8_115200 },
4421         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423                 pbn_b1_4_115200 },
4424         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426                 pbn_b1_2_115200 },
4427         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4428                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429                 pbn_b1_4_115200 },
4430         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4431                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432                 pbn_b1_2_115200 },
4433         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435                 pbn_b2_4_115200 },
4436         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438                 pbn_b2_2_115200 },
4439         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441                 pbn_b2_1_115200 },
4442         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4443                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444                 pbn_b2_4_115200 },
4445         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4446                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447                 pbn_b2_2_115200 },
4448         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4449                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450                 pbn_b2_1_115200 },
4451         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453                 pbn_b0_8_115200 },
4454
4455         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4456                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4457                 0, 0,
4458                 pbn_b0_4_921600 },
4459         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4460                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4461                 0, 0,
4462                 pbn_b0_4_1152000 },
4463         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465                 pbn_b0_bt_2_921600 },
4466
4467                 /*
4468                  * The below card is a little controversial since it is the
4469                  * subject of a PCI vendor/device ID clash.  (See
4470                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4471                  * For now just used the hex ID 0x950a.
4472                  */
4473         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4474                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4475                 0, 0, pbn_b0_2_115200 },
4476         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4477                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4478                 0, 0, pbn_b0_2_115200 },
4479         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481                 pbn_b0_2_1130000 },
4482         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4483                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4484                 pbn_b0_1_921600 },
4485         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487                 pbn_b0_4_115200 },
4488         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_b0_bt_2_921600 },
4491         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493                 pbn_b2_8_1152000 },
4494
4495         /*
4496          * Oxford Semiconductor Inc. Tornado PCI express device range.
4497          */
4498         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4499                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500                 pbn_b0_1_4000000 },
4501         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4502                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503                 pbn_b0_1_4000000 },
4504         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4505                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506                 pbn_oxsemi_1_4000000 },
4507         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4508                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509                 pbn_oxsemi_1_4000000 },
4510         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4511                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512                 pbn_b0_1_4000000 },
4513         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4514                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515                 pbn_b0_1_4000000 },
4516         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4517                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518                 pbn_oxsemi_1_4000000 },
4519         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4520                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521                 pbn_oxsemi_1_4000000 },
4522         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524                 pbn_b0_1_4000000 },
4525         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4526                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527                 pbn_b0_1_4000000 },
4528         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4529                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530                 pbn_b0_1_4000000 },
4531         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4532                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533                 pbn_b0_1_4000000 },
4534         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4535                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536                 pbn_oxsemi_2_4000000 },
4537         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4538                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539                 pbn_oxsemi_2_4000000 },
4540         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4541                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542                 pbn_oxsemi_4_4000000 },
4543         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4544                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545                 pbn_oxsemi_4_4000000 },
4546         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4547                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548                 pbn_oxsemi_8_4000000 },
4549         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4550                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551                 pbn_oxsemi_8_4000000 },
4552         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4553                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554                 pbn_oxsemi_1_4000000 },
4555         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4556                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557                 pbn_oxsemi_1_4000000 },
4558         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560                 pbn_oxsemi_1_4000000 },
4561         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563                 pbn_oxsemi_1_4000000 },
4564         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4565                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566                 pbn_oxsemi_1_4000000 },
4567         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569                 pbn_oxsemi_1_4000000 },
4570         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572                 pbn_oxsemi_1_4000000 },
4573         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4574                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575                 pbn_oxsemi_1_4000000 },
4576         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4577                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578                 pbn_oxsemi_1_4000000 },
4579         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4580                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581                 pbn_oxsemi_1_4000000 },
4582         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4583                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584                 pbn_oxsemi_1_4000000 },
4585         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4586                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587                 pbn_oxsemi_1_4000000 },
4588         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4589                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590                 pbn_oxsemi_1_4000000 },
4591         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4592                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593                 pbn_oxsemi_1_4000000 },
4594         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596                 pbn_oxsemi_1_4000000 },
4597         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599                 pbn_oxsemi_1_4000000 },
4600         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4601                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602                 pbn_oxsemi_1_4000000 },
4603         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4604                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605                 pbn_oxsemi_1_4000000 },
4606         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4607                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608                 pbn_oxsemi_1_4000000 },
4609         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4610                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611                 pbn_oxsemi_1_4000000 },
4612         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4613                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614                 pbn_oxsemi_1_4000000 },
4615         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4616                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617                 pbn_oxsemi_1_4000000 },
4618         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4619                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620                 pbn_oxsemi_1_4000000 },
4621         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4622                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623                 pbn_oxsemi_1_4000000 },
4624         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4625                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626                 pbn_oxsemi_1_4000000 },
4627         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4628                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629                 pbn_oxsemi_1_4000000 },
4630         /*
4631          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4632          */
4633         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4634                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4635                 pbn_oxsemi_1_4000000 },
4636         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4637                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4638                 pbn_oxsemi_2_4000000 },
4639         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4640                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4641                 pbn_oxsemi_4_4000000 },
4642         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4643                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4644                 pbn_oxsemi_8_4000000 },
4645
4646         /*
4647          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4648          */
4649         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4650                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4651                 pbn_oxsemi_2_4000000 },
4652
4653         /*
4654          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4655          * from skokodyn@yahoo.com
4656          */
4657         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4658                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4659                 pbn_sbsxrsio },
4660         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4661                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4662                 pbn_sbsxrsio },
4663         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4664                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4665                 pbn_sbsxrsio },
4666         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4667                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4668                 pbn_sbsxrsio },
4669
4670         /*
4671          * Digitan DS560-558, from jimd@esoft.com
4672          */
4673         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4674                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675                 pbn_b1_1_115200 },
4676
4677         /*
4678          * Titan Electronic cards
4679          *  The 400L and 800L have a custom setup quirk.
4680          */
4681         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4682                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683                 pbn_b0_1_921600 },
4684         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4685                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686                 pbn_b0_2_921600 },
4687         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689                 pbn_b0_4_921600 },
4690         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4691                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692                 pbn_b0_4_921600 },
4693         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695                 pbn_b1_1_921600 },
4696         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698                 pbn_b1_bt_2_921600 },
4699         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701                 pbn_b0_bt_4_921600 },
4702         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704                 pbn_b0_bt_8_921600 },
4705         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707                 pbn_b4_bt_2_921600 },
4708         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710                 pbn_b4_bt_4_921600 },
4711         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4712                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713                 pbn_b4_bt_8_921600 },
4714         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4715                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716                 pbn_b0_4_921600 },
4717         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4718                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719                 pbn_b0_4_921600 },
4720         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4721                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722                 pbn_b0_4_921600 },
4723         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4724                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725                 pbn_oxsemi_1_4000000 },
4726         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4727                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728                 pbn_oxsemi_2_4000000 },
4729         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4730                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731                 pbn_oxsemi_4_4000000 },
4732         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4733                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734                 pbn_oxsemi_8_4000000 },
4735         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4736                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737                 pbn_oxsemi_2_4000000 },
4738         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4739                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740                 pbn_oxsemi_2_4000000 },
4741         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4742                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743                 pbn_b0_bt_2_921600 },
4744         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4745                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746                 pbn_b0_4_921600 },
4747         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749                 pbn_b0_4_921600 },
4750         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4751                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752                 pbn_b0_4_921600 },
4753         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755                 pbn_b0_4_921600 },
4756
4757         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759                 pbn_b2_1_460800 },
4760         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762                 pbn_b2_1_460800 },
4763         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765                 pbn_b2_1_460800 },
4766         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768                 pbn_b2_bt_2_921600 },
4769         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771                 pbn_b2_bt_2_921600 },
4772         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774                 pbn_b2_bt_2_921600 },
4775         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777                 pbn_b2_bt_4_921600 },
4778         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780                 pbn_b2_bt_4_921600 },
4781         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783                 pbn_b2_bt_4_921600 },
4784         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4785                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786                 pbn_b0_1_921600 },
4787         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4788                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789                 pbn_b0_1_921600 },
4790         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4791                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792                 pbn_b0_1_921600 },
4793         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795                 pbn_b0_bt_2_921600 },
4796         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798                 pbn_b0_bt_2_921600 },
4799         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801                 pbn_b0_bt_2_921600 },
4802         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804                 pbn_b0_bt_4_921600 },
4805         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4806                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807                 pbn_b0_bt_4_921600 },
4808         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810                 pbn_b0_bt_4_921600 },
4811         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4812                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813                 pbn_b0_bt_8_921600 },
4814         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4815                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816                 pbn_b0_bt_8_921600 },
4817         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4818                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819                 pbn_b0_bt_8_921600 },
4820
4821         /*
4822          * Computone devices submitted by Doug McNash dmcnash@computone.com
4823          */
4824         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4825                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4826                 0, 0, pbn_computone_4 },
4827         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4828                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4829                 0, 0, pbn_computone_8 },
4830         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4831                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4832                 0, 0, pbn_computone_6 },
4833
4834         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836                 pbn_oxsemi },
4837         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4838                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4839                 pbn_b0_bt_1_921600 },
4840
4841         /*
4842          * SUNIX (TIMEDIA)
4843          */
4844         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4845                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4846                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4847                 pbn_b0_bt_1_921600 },
4848
4849         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4850                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4851                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4852                 pbn_b0_bt_1_921600 },
4853
4854         /*
4855          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4856          */
4857         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4858                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859                 pbn_b0_bt_8_115200 },
4860         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4861                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862                 pbn_b0_bt_8_115200 },
4863
4864         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4865                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866                 pbn_b0_bt_2_115200 },
4867         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869                 pbn_b0_bt_2_115200 },
4870         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4871                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872                 pbn_b0_bt_2_115200 },
4873         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4874                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875                 pbn_b0_bt_2_115200 },
4876         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4877                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878                 pbn_b0_bt_2_115200 },
4879         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4880                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881                 pbn_b0_bt_4_460800 },
4882         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884                 pbn_b0_bt_4_460800 },
4885         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4886                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887                 pbn_b0_bt_2_460800 },
4888         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4889                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890                 pbn_b0_bt_2_460800 },
4891         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4892                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893                 pbn_b0_bt_2_460800 },
4894         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4895                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896                 pbn_b0_bt_1_115200 },
4897         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4898                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899                 pbn_b0_bt_1_460800 },
4900
4901         /*
4902          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4903          * Cards are identified by their subsystem vendor IDs, which
4904          * (in hex) match the model number.
4905          *
4906          * Note that JC140x are RS422/485 cards which require ox950
4907          * ACR = 0x10, and as such are not currently fully supported.
4908          */
4909         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4910                 0x1204, 0x0004, 0, 0,
4911                 pbn_b0_4_921600 },
4912         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4913                 0x1208, 0x0004, 0, 0,
4914                 pbn_b0_4_921600 },
4915 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4916                 0x1402, 0x0002, 0, 0,
4917                 pbn_b0_2_921600 }, */
4918 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4919                 0x1404, 0x0004, 0, 0,
4920                 pbn_b0_4_921600 }, */
4921         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4922                 0x1208, 0x0004, 0, 0,
4923                 pbn_b0_4_921600 },
4924
4925         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4926                 0x1204, 0x0004, 0, 0,
4927                 pbn_b0_4_921600 },
4928         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4929                 0x1208, 0x0004, 0, 0,
4930                 pbn_b0_4_921600 },
4931         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4932                 0x1208, 0x0004, 0, 0,
4933                 pbn_b0_4_921600 },
4934         /*
4935          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4936          */
4937         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939                 pbn_b1_1_1382400 },
4940
4941         /*
4942          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4943          */
4944         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4945                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946                 pbn_b1_1_1382400 },
4947
4948         /*
4949          * RAStel 2 port modem, gerg@moreton.com.au
4950          */
4951         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953                 pbn_b2_bt_2_115200 },
4954
4955         /*
4956          * EKF addition for i960 Boards form EKF with serial port
4957          */
4958         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4959                 0xE4BF, PCI_ANY_ID, 0, 0,
4960                 pbn_intel_i960 },
4961
4962         /*
4963          * Xircom Cardbus/Ethernet combos
4964          */
4965         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967                 pbn_b0_1_115200 },
4968         /*
4969          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4970          */
4971         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973                 pbn_b0_1_115200 },
4974
4975         /*
4976          * Untested PCI modems, sent in from various folks...
4977          */
4978
4979         /*
4980          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4981          */
4982         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4983                 0x1048, 0x1500, 0, 0,
4984                 pbn_b1_1_115200 },
4985
4986         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4987                 0xFF00, 0, 0, 0,
4988                 pbn_sgi_ioc3 },
4989
4990         /*
4991          * HP Diva card
4992          */
4993         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4994                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4995                 pbn_b1_1_115200 },
4996         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998                 pbn_b0_5_115200 },
4999         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001                 pbn_b2_1_115200 },
5002
5003         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005                 pbn_b3_2_115200 },
5006         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008                 pbn_b3_4_115200 },
5009         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011                 pbn_b3_8_115200 },
5012
5013         /*
5014          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5015          */
5016         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5017                 PCI_ANY_ID, PCI_ANY_ID,
5018                 0,
5019                 0, pbn_exar_XR17C152 },
5020         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5021                 PCI_ANY_ID, PCI_ANY_ID,
5022                 0,
5023                 0, pbn_exar_XR17C154 },
5024         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5025                 PCI_ANY_ID, PCI_ANY_ID,
5026                 0,
5027                 0, pbn_exar_XR17C158 },
5028         /*
5029          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5030          */
5031         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5032                 PCI_ANY_ID, PCI_ANY_ID,
5033                 0,
5034                 0, pbn_exar_XR17V352 },
5035         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5036                 PCI_ANY_ID, PCI_ANY_ID,
5037                 0,
5038                 0, pbn_exar_XR17V354 },
5039         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5040                 PCI_ANY_ID, PCI_ANY_ID,
5041                 0,
5042                 0, pbn_exar_XR17V358 },
5043         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5044                 PCI_ANY_ID, PCI_ANY_ID,
5045                 0,
5046                 0, pbn_exar_XR17V4358 },
5047         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5048                 PCI_ANY_ID, PCI_ANY_ID,
5049                 0,
5050                 0, pbn_exar_XR17V8358 },
5051         /*
5052          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5053          */
5054         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5055                 PCI_ANY_ID, PCI_ANY_ID,
5056                 0,
5057                 0, pbn_pericom_PI7C9X7951 },
5058         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5059                 PCI_ANY_ID, PCI_ANY_ID,
5060                 0,
5061                 0, pbn_pericom_PI7C9X7952 },
5062         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5063                 PCI_ANY_ID, PCI_ANY_ID,
5064                 0,
5065                 0, pbn_pericom_PI7C9X7954 },
5066         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5067                 PCI_ANY_ID, PCI_ANY_ID,
5068                 0,
5069                 0, pbn_pericom_PI7C9X7958 },
5070         /*
5071          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5072          */
5073         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075                 pbn_b0_1_115200 },
5076         /*
5077          * ITE
5078          */
5079         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5080                 PCI_ANY_ID, PCI_ANY_ID,
5081                 0, 0,
5082                 pbn_b1_bt_1_115200 },
5083
5084         /*
5085          * IntaShield IS-200
5086          */
5087         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5089                 pbn_b2_2_115200 },
5090         /*
5091          * IntaShield IS-400
5092          */
5093         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5095                 pbn_b2_4_115200 },
5096         /*
5097          * Perle PCI-RAS cards
5098          */
5099         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5100                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5101                 0, 0, pbn_b2_4_921600 },
5102         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5103                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5104                 0, 0, pbn_b2_8_921600 },
5105
5106         /*
5107          * Mainpine series cards: Fairly standard layout but fools
5108          * parts of the autodetect in some cases and uses otherwise
5109          * unmatched communications subclasses in the PCI Express case
5110          */
5111
5112         {       /* RockForceDUO */
5113                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5114                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5115                 0, 0, pbn_b0_2_115200 },
5116         {       /* RockForceQUATRO */
5117                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5118                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5119                 0, 0, pbn_b0_4_115200 },
5120         {       /* RockForceDUO+ */
5121                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5122                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5123                 0, 0, pbn_b0_2_115200 },
5124         {       /* RockForceQUATRO+ */
5125                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5126                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5127                 0, 0, pbn_b0_4_115200 },
5128         {       /* RockForce+ */
5129                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5130                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5131                 0, 0, pbn_b0_2_115200 },
5132         {       /* RockForce+ */
5133                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5134                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5135                 0, 0, pbn_b0_4_115200 },
5136         {       /* RockForceOCTO+ */
5137                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5138                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5139                 0, 0, pbn_b0_8_115200 },
5140         {       /* RockForceDUO+ */
5141                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5142                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5143                 0, 0, pbn_b0_2_115200 },
5144         {       /* RockForceQUARTRO+ */
5145                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5146                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5147                 0, 0, pbn_b0_4_115200 },
5148         {       /* RockForceOCTO+ */
5149                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5150                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5151                 0, 0, pbn_b0_8_115200 },
5152         {       /* RockForceD1 */
5153                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5154                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5155                 0, 0, pbn_b0_1_115200 },
5156         {       /* RockForceF1 */
5157                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5158                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5159                 0, 0, pbn_b0_1_115200 },
5160         {       /* RockForceD2 */
5161                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5162                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5163                 0, 0, pbn_b0_2_115200 },
5164         {       /* RockForceF2 */
5165                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5166                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5167                 0, 0, pbn_b0_2_115200 },
5168         {       /* RockForceD4 */
5169                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5170                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5171                 0, 0, pbn_b0_4_115200 },
5172         {       /* RockForceF4 */
5173                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5174                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5175                 0, 0, pbn_b0_4_115200 },
5176         {       /* RockForceD8 */
5177                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5178                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5179                 0, 0, pbn_b0_8_115200 },
5180         {       /* RockForceF8 */
5181                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5182                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5183                 0, 0, pbn_b0_8_115200 },
5184         {       /* IQ Express D1 */
5185                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5186                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5187                 0, 0, pbn_b0_1_115200 },
5188         {       /* IQ Express F1 */
5189                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5190                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5191                 0, 0, pbn_b0_1_115200 },
5192         {       /* IQ Express D2 */
5193                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5194                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5195                 0, 0, pbn_b0_2_115200 },
5196         {       /* IQ Express F2 */
5197                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5198                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5199                 0, 0, pbn_b0_2_115200 },
5200         {       /* IQ Express D4 */
5201                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5202                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5203                 0, 0, pbn_b0_4_115200 },
5204         {       /* IQ Express F4 */
5205                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5206                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5207                 0, 0, pbn_b0_4_115200 },
5208         {       /* IQ Express D8 */
5209                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5210                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5211                 0, 0, pbn_b0_8_115200 },
5212         {       /* IQ Express F8 */
5213                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5214                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5215                 0, 0, pbn_b0_8_115200 },
5216
5217
5218         /*
5219          * PA Semi PA6T-1682M on-chip UART
5220          */
5221         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5223                 pbn_pasemi_1682M },
5224
5225         /*
5226          * National Instruments
5227          */
5228         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5230                 pbn_b1_16_115200 },
5231         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5233                 pbn_b1_8_115200 },
5234         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5236                 pbn_b1_bt_4_115200 },
5237         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5239                 pbn_b1_bt_2_115200 },
5240         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5242                 pbn_b1_bt_4_115200 },
5243         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5245                 pbn_b1_bt_2_115200 },
5246         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5248                 pbn_b1_16_115200 },
5249         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5251                 pbn_b1_8_115200 },
5252         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5254                 pbn_b1_bt_4_115200 },
5255         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5257                 pbn_b1_bt_2_115200 },
5258         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5260                 pbn_b1_bt_4_115200 },
5261         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5263                 pbn_b1_bt_2_115200 },
5264         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5266                 pbn_ni8430_2 },
5267         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5269                 pbn_ni8430_2 },
5270         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5272                 pbn_ni8430_4 },
5273         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5275                 pbn_ni8430_4 },
5276         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5278                 pbn_ni8430_8 },
5279         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5281                 pbn_ni8430_8 },
5282         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284                 pbn_ni8430_16 },
5285         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5287                 pbn_ni8430_16 },
5288         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5290                 pbn_ni8430_2 },
5291         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293                 pbn_ni8430_2 },
5294         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5296                 pbn_ni8430_4 },
5297         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299                 pbn_ni8430_4 },
5300
5301         /*
5302         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5303         */
5304         {       PCI_VENDOR_ID_ADDIDATA,
5305                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5306                 PCI_ANY_ID,
5307                 PCI_ANY_ID,
5308                 0,
5309                 0,
5310                 pbn_b0_4_115200 },
5311
5312         {       PCI_VENDOR_ID_ADDIDATA,
5313                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5314                 PCI_ANY_ID,
5315                 PCI_ANY_ID,
5316                 0,
5317                 0,
5318                 pbn_b0_2_115200 },
5319
5320         {       PCI_VENDOR_ID_ADDIDATA,
5321                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5322                 PCI_ANY_ID,
5323                 PCI_ANY_ID,
5324                 0,
5325                 0,
5326                 pbn_b0_1_115200 },
5327
5328         {       PCI_VENDOR_ID_AMCC,
5329                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5330                 PCI_ANY_ID,
5331                 PCI_ANY_ID,
5332                 0,
5333                 0,
5334                 pbn_b1_8_115200 },
5335
5336         {       PCI_VENDOR_ID_ADDIDATA,
5337                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5338                 PCI_ANY_ID,
5339                 PCI_ANY_ID,
5340                 0,
5341                 0,
5342                 pbn_b0_4_115200 },
5343
5344         {       PCI_VENDOR_ID_ADDIDATA,
5345                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5346                 PCI_ANY_ID,
5347                 PCI_ANY_ID,
5348                 0,
5349                 0,
5350                 pbn_b0_2_115200 },
5351
5352         {       PCI_VENDOR_ID_ADDIDATA,
5353                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5354                 PCI_ANY_ID,
5355                 PCI_ANY_ID,
5356                 0,
5357                 0,
5358                 pbn_b0_1_115200 },
5359
5360         {       PCI_VENDOR_ID_ADDIDATA,
5361                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5362                 PCI_ANY_ID,
5363                 PCI_ANY_ID,
5364                 0,
5365                 0,
5366                 pbn_b0_4_115200 },
5367
5368         {       PCI_VENDOR_ID_ADDIDATA,
5369                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5370                 PCI_ANY_ID,
5371                 PCI_ANY_ID,
5372                 0,
5373                 0,
5374                 pbn_b0_2_115200 },
5375
5376         {       PCI_VENDOR_ID_ADDIDATA,
5377                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5378                 PCI_ANY_ID,
5379                 PCI_ANY_ID,
5380                 0,
5381                 0,
5382                 pbn_b0_1_115200 },
5383
5384         {       PCI_VENDOR_ID_ADDIDATA,
5385                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5386                 PCI_ANY_ID,
5387                 PCI_ANY_ID,
5388                 0,
5389                 0,
5390                 pbn_b0_8_115200 },
5391
5392         {       PCI_VENDOR_ID_ADDIDATA,
5393                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5394                 PCI_ANY_ID,
5395                 PCI_ANY_ID,
5396                 0,
5397                 0,
5398                 pbn_ADDIDATA_PCIe_4_3906250 },
5399
5400         {       PCI_VENDOR_ID_ADDIDATA,
5401                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5402                 PCI_ANY_ID,
5403                 PCI_ANY_ID,
5404                 0,
5405                 0,
5406                 pbn_ADDIDATA_PCIe_2_3906250 },
5407
5408         {       PCI_VENDOR_ID_ADDIDATA,
5409                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5410                 PCI_ANY_ID,
5411                 PCI_ANY_ID,
5412                 0,
5413                 0,
5414                 pbn_ADDIDATA_PCIe_1_3906250 },
5415
5416         {       PCI_VENDOR_ID_ADDIDATA,
5417                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5418                 PCI_ANY_ID,
5419                 PCI_ANY_ID,
5420                 0,
5421                 0,
5422                 pbn_ADDIDATA_PCIe_8_3906250 },
5423
5424         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5425                 PCI_VENDOR_ID_IBM, 0x0299,
5426                 0, 0, pbn_b0_bt_2_115200 },
5427
5428         /*
5429          * other NetMos 9835 devices are most likely handled by the
5430          * parport_serial driver, check drivers/parport/parport_serial.c
5431          * before adding them here.
5432          */
5433
5434         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5435                 0xA000, 0x1000,
5436                 0, 0, pbn_b0_1_115200 },
5437
5438         /* the 9901 is a rebranded 9912 */
5439         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5440                 0xA000, 0x1000,
5441                 0, 0, pbn_b0_1_115200 },
5442
5443         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5444                 0xA000, 0x1000,
5445                 0, 0, pbn_b0_1_115200 },
5446
5447         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5448                 0xA000, 0x1000,
5449                 0, 0, pbn_b0_1_115200 },
5450
5451         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5452                 0xA000, 0x1000,
5453                 0, 0, pbn_b0_1_115200 },
5454
5455         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5456                 0xA000, 0x3002,
5457                 0, 0, pbn_NETMOS9900_2s_115200 },
5458
5459         /*
5460          * Best Connectivity and Rosewill PCI Multi I/O cards
5461          */
5462
5463         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5464                 0xA000, 0x1000,
5465                 0, 0, pbn_b0_1_115200 },
5466
5467         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5468                 0xA000, 0x3002,
5469                 0, 0, pbn_b0_bt_2_115200 },
5470
5471         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5472                 0xA000, 0x3004,
5473                 0, 0, pbn_b0_bt_4_115200 },
5474         /* Intel CE4100 */
5475         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5476                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5477                 pbn_ce4100_1_115200 },
5478         /* Intel BayTrail */
5479         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5480                 PCI_ANY_ID,  PCI_ANY_ID,
5481                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5482                 pbn_byt },
5483         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5484                 PCI_ANY_ID,  PCI_ANY_ID,
5485                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5486                 pbn_byt },
5487         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5488                 PCI_ANY_ID,  PCI_ANY_ID,
5489                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5490                 pbn_byt },
5491         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5492                 PCI_ANY_ID,  PCI_ANY_ID,
5493                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5494                 pbn_byt },
5495
5496         /* Intel Broadwell */
5497         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5498                 PCI_ANY_ID,  PCI_ANY_ID,
5499                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5500                 pbn_byt },
5501         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5502                 PCI_ANY_ID,  PCI_ANY_ID,
5503                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5504                 pbn_byt },
5505
5506         /*
5507          * Intel Quark x1000
5508          */
5509         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5511                 pbn_qrk },
5512         /*
5513          * Cronyx Omega PCI
5514          */
5515         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5517                 pbn_omegapci },
5518
5519         /*
5520          * Broadcom TruManage
5521          */
5522         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5524                 pbn_brcm_trumanage },
5525
5526         /*
5527          * AgeStar as-prs2-009
5528          */
5529         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5530                 PCI_ANY_ID, PCI_ANY_ID,
5531                 0, 0, pbn_b0_bt_2_115200 },
5532
5533         /*
5534          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5535          * so not listed here.
5536          */
5537         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5538                 PCI_ANY_ID, PCI_ANY_ID,
5539                 0, 0, pbn_b0_bt_4_115200 },
5540
5541         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5542                 PCI_ANY_ID, PCI_ANY_ID,
5543                 0, 0, pbn_b0_bt_2_115200 },
5544
5545         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5546                 PCI_ANY_ID, PCI_ANY_ID,
5547                 0, 0, pbn_wch384_4 },
5548
5549         /*
5550          * Commtech, Inc. Fastcom adapters
5551          */
5552         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5553                 PCI_ANY_ID, PCI_ANY_ID,
5554                 0,
5555                 0, pbn_b0_2_1152000_200 },
5556         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5557                 PCI_ANY_ID, PCI_ANY_ID,
5558                 0,
5559                 0, pbn_b0_4_1152000_200 },
5560         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5561                 PCI_ANY_ID, PCI_ANY_ID,
5562                 0,
5563                 0, pbn_b0_4_1152000_200 },
5564         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5565                 PCI_ANY_ID, PCI_ANY_ID,
5566                 0,
5567                 0, pbn_b0_8_1152000_200 },
5568         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5569                 PCI_ANY_ID, PCI_ANY_ID,
5570                 0,
5571                 0, pbn_exar_XR17V352 },
5572         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5573                 PCI_ANY_ID, PCI_ANY_ID,
5574                 0,
5575                 0, pbn_exar_XR17V354 },
5576         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5577                 PCI_ANY_ID, PCI_ANY_ID,
5578                 0,
5579                 0, pbn_exar_XR17V358 },
5580
5581         /* Fintek PCI serial cards */
5582         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5583         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5584         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5585
5586         /*
5587          * These entries match devices with class COMMUNICATION_SERIAL,
5588          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5589          */
5590         {       PCI_ANY_ID, PCI_ANY_ID,
5591                 PCI_ANY_ID, PCI_ANY_ID,
5592                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5593                 0xffff00, pbn_default },
5594         {       PCI_ANY_ID, PCI_ANY_ID,
5595                 PCI_ANY_ID, PCI_ANY_ID,
5596                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5597                 0xffff00, pbn_default },
5598         {       PCI_ANY_ID, PCI_ANY_ID,
5599                 PCI_ANY_ID, PCI_ANY_ID,
5600                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5601                 0xffff00, pbn_default },
5602         { 0, }
5603 };
5604
5605 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5606                                                 pci_channel_state_t state)
5607 {
5608         struct serial_private *priv = pci_get_drvdata(dev);
5609
5610         if (state == pci_channel_io_perm_failure)
5611                 return PCI_ERS_RESULT_DISCONNECT;
5612
5613         if (priv)
5614                 pciserial_suspend_ports(priv);
5615
5616         pci_disable_device(dev);
5617
5618         return PCI_ERS_RESULT_NEED_RESET;
5619 }
5620
5621 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5622 {
5623         int rc;
5624
5625         rc = pci_enable_device(dev);
5626
5627         if (rc)
5628                 return PCI_ERS_RESULT_DISCONNECT;
5629
5630         pci_restore_state(dev);
5631         pci_save_state(dev);
5632
5633         return PCI_ERS_RESULT_RECOVERED;
5634 }
5635
5636 static void serial8250_io_resume(struct pci_dev *dev)
5637 {
5638         struct serial_private *priv = pci_get_drvdata(dev);
5639
5640         if (priv)
5641                 pciserial_resume_ports(priv);
5642 }
5643
5644 static const struct pci_error_handlers serial8250_err_handler = {
5645         .error_detected = serial8250_io_error_detected,
5646         .slot_reset = serial8250_io_slot_reset,
5647         .resume = serial8250_io_resume,
5648 };
5649
5650 static struct pci_driver serial_pci_driver = {
5651         .name           = "serial",
5652         .probe          = pciserial_init_one,
5653         .remove         = pciserial_remove_one,
5654         .driver         = {
5655                 .pm     = &pciserial_pm_ops,
5656         },
5657         .id_table       = serial_pci_tbl,
5658         .err_handler    = &serial8250_err_handler,
5659 };
5660
5661 module_pci_driver(serial_pci_driver);
5662
5663 MODULE_LICENSE("GPL");
5664 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5665 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);