drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24 #include <linux/rational.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_data/dma-dw.h>
  31 #include <linux/platform_data/dma-hsu.h>
  32
  33 #include "8250.h"
  34
  35 /*
  36  * init function returns:
  37  *  > 0 - number of ports
  38  *  = 0 - use board->num_ports
  39  *  < 0 - error
  40  */
  41 struct pci_serial_quirk {
  42         u32     vendor;
  43         u32     device;
  44         u32     subvendor;
  45         u32     subdevice;
  46         int     (*probe)(struct pci_dev *dev);
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *,
  49                          const struct pciserial_board *,
  50                          struct uart_8250_port *, int);
  51         void    (*exit)(struct pci_dev *dev);
  52 };
  53
  54 #define PCI_NUM_BAR_RESOURCES   6
  55
  56 struct serial_private {
  57         struct pci_dev          *dev;
  58         unsigned int            nr;
  59         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  60         struct pci_serial_quirk *quirk;
  61         int                     line[0];
  62 };
  63
  64 static int pci_default_setup(struct serial_private*,
  65           const struct pciserial_board*, struct uart_8250_port *, int);
  66
  67 static void moan_device(const char *str, struct pci_dev *dev)
  68 {
  69         dev_err(&dev->dev,
  70                "%s: %s\n"
  71                "Please send the output of lspci -vv, this\n"
  72                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  73                "manufacturer and name of serial board or\n"
  74                "modem board to <linux-serial@vger.kernel.org>.\n",
  75                pci_name(dev), str, dev->vendor, dev->device,
  76                dev->subsystem_vendor, dev->subsystem_device);
  77 }
  78
  79 static int
  80 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  81            int bar, int offset, int regshift)
  82 {
  83         struct pci_dev *dev = priv->dev;
  84
  85         if (bar >= PCI_NUM_BAR_RESOURCES)
  86                 return -EINVAL;
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->port.iotype = UPIO_MEM;
  95                 port->port.iobase = 0;
  96                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
  97                 port->port.membase = priv->remapped_bar[bar] + offset;
  98                 port->port.regshift = regshift;
  99         } else {
 100                 port->port.iotype = UPIO_PORT;
 101                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 102                 port->port.mapbase = 0;
 103                 port->port.membase = NULL;
 104                 port->port.regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 111  */
 112 static int addidata_apci7800_setup(struct serial_private *priv,
 113                                 const struct pciserial_board *board,
 114                                 struct uart_8250_port *port, int idx)
 115 {
 116         unsigned int bar = 0, offset = board->first_offset;
 117         bar = FL_GET_BASE(board->flags);
 118
 119         if (idx < 2) {
 120                 offset += idx * board->uart_offset;
 121         } else if ((idx >= 2) && (idx < 4)) {
 122                 bar += 1;
 123                 offset += ((idx - 2) * board->uart_offset);
 124         } else if ((idx >= 4) && (idx < 6)) {
 125                 bar += 2;
 126                 offset += ((idx - 4) * board->uart_offset);
 127         } else if (idx >= 6) {
 128                 bar += 3;
 129                 offset += ((idx - 6) * board->uart_offset);
 130         }
 131
 132         return setup_port(priv, port, bar, offset, board->reg_shift);
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 141               struct uart_8250_port *port, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(priv, port, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct serial_private *priv,
 195                 const struct pciserial_board *board,
 196                 struct uart_8250_port *port, int idx)
 197 {
 198         unsigned int offset = board->first_offset;
 199         unsigned int bar = FL_GET_BASE(board->flags);
 200
 201         switch (priv->dev->subsystem_device) {
 202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 203                 if (idx == 3)
 204                         idx++;
 205                 break;
 206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 207                 if (idx > 0)
 208                         idx++;
 209                 if (idx > 2)
 210                         idx++;
 211                 break;
 212         }
 213         if (idx > 2)
 214                 offset = 0x18;
 215
 216         offset += idx * board->uart_offset;
 217
 218         return setup_port(priv, port, bar, offset, board->reg_shift);
 219 }
 220
 221 /*
 222  * Added for EKF Intel i960 serial boards
 223  */
 224 static int pci_inteli960ni_init(struct pci_dev *dev)
 225 {
 226         u32 oldval;
 227
 228         if (!(dev->subsystem_device & 0x1000))
 229                 return -ENODEV;
 230
 231         /* is firmware started? */
 232         pci_read_config_dword(dev, 0x44, &oldval);
 233         if (oldval == 0x00001000L) { /* RESET value */
 234                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 235                 return -ENODEV;
 236         }
 237         return 0;
 238 }
 239
 240 /*
 241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 242  * that the card interrupt be explicitly enabled or disabled.  This
 243  * seems to be mainly needed on card using the PLX which also use I/O
 244  * mapped memory.
 245  */
 246 static int pci_plx9050_init(struct pci_dev *dev)
 247 {
 248         u8 irq_config;
 249         void __iomem *p;
 250
 251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 252                 moan_device("no memory in bar 0", dev);
 253                 return 0;
 254         }
 255
 256         irq_config = 0x41;
 257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 259                 irq_config = 0x43;
 260
 261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 263                 /*
 264                  * As the megawolf cards have the int pins active
 265                  * high, and have 2 UART chips, both ints must be
 266                  * enabled on the 9050. Also, the UARTS are set in
 267                  * 16450 mode by default, so we have to enable the
 268                  * 16C950 'enhanced' mode so that we can use the
 269                  * deep FIFOs
 270                  */
 271                 irq_config = 0x5b;
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 #define NI8420_INT_ENABLE_REG   0x38
 312 #define NI8420_INT_ENABLE_BIT   0x2000
 313
 314 static void pci_ni8420_exit(struct pci_dev *dev)
 315 {
 316         void __iomem *p;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         p = pci_ioremap_bar(dev, bar);
 325         if (p == NULL)
 326                 return;
 327
 328         /* Disable the CPU Interrupt */
 329         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 330                p + NI8420_INT_ENABLE_REG);
 331         iounmap(p);
 332 }
 333
 334
 335 /* MITE registers */
 336 #define MITE_IOWBSR1    0xc4
 337 #define MITE_IOWCR1     0xf4
 338 #define MITE_LCIMR1     0x08
 339 #define MITE_LCIMR2     0x10
 340
 341 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 342
 343 static void pci_ni8430_exit(struct pci_dev *dev)
 344 {
 345         void __iomem *p;
 346         unsigned int bar = 0;
 347
 348         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 349                 moan_device("no memory in bar", dev);
 350                 return;
 351         }
 352
 353         p = pci_ioremap_bar(dev, bar);
 354         if (p == NULL)
 355                 return;
 356
 357         /* Disable the CPU Interrupt */
 358         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 359         iounmap(p);
 360 }
 361
 362 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 363 static int
 364 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 365                 struct uart_8250_port *port, int idx)
 366 {
 367         unsigned int bar, offset = board->first_offset;
 368
 369         bar = 0;
 370
 371         if (idx < 4) {
 372                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 373                 offset += idx * board->uart_offset;
 374         } else if (idx < 8) {
 375                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 376                 offset += idx * board->uart_offset + 0xC00;
 377         } else /* we have only 8 ports on PMC-OCTALPRO */
 378                 return 1;
 379
 380         return setup_port(priv, port, bar, offset, board->reg_shift);
 381 }
 382
 383 /*
 384 * This does initialization for PMC OCTALPRO cards:
 385 * maps the device memory, resets the UARTs (needed, bc
 386 * if the module is removed and inserted again, the card
 387 * is in the sleep mode) and enables global interrupt.
 388 */
 389
 390 /* global control register offset for SBS PMC-OctalPro */
 391 #define OCT_REG_CR_OFF          0x500
 392
 393 static int sbs_init(struct pci_dev *dev)
 394 {
 395         u8 __iomem *p;
 396
 397         p = pci_ioremap_bar(dev, 0);
 398
 399         if (p == NULL)
 400                 return -ENOMEM;
 401         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 402         writeb(0x10, p + OCT_REG_CR_OFF);
 403         udelay(50);
 404         writeb(0x0, p + OCT_REG_CR_OFF);
 405
 406         /* Set bit-2 (INTENABLE) of Control Register */
 407         writeb(0x4, p + OCT_REG_CR_OFF);
 408         iounmap(p);
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * Disables the global interrupt of PMC-OctalPro
 415  */
 416
 417 static void sbs_exit(struct pci_dev *dev)
 418 {
 419         u8 __iomem *p;
 420
 421         p = pci_ioremap_bar(dev, 0);
 422         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 423         if (p != NULL)
 424                 writeb(0, p + OCT_REG_CR_OFF);
 425         iounmap(p);
 426 }
 427
 428 /*
 429  * SIIG serial cards have an PCI interface chip which also controls
 430  * the UART clocking frequency. Each UART can be clocked independently
 431  * (except cards equipped with 4 UARTs) and initial clocking settings
 432  * are stored in the EEPROM chip. It can cause problems because this
 433  * version of serial driver doesn't support differently clocked UART's
 434  * on single PCI card. To prevent this, initialization functions set
 435  * high frequency clocking for all UART's on given card. It is safe (I
 436  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 437  * with other OSes (like M$ DOS).
 438  *
 439  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 440  *
 441  * There is two family of SIIG serial cards with different PCI
 442  * interface chip and different configuration methods:
 443  *     - 10x cards have control registers in IO and/or memory space;
 444  *     - 20x cards have control registers in standard PCI configuration space.
 445  *
 446  * Note: all 10x cards have PCI device ids 0x10..
 447  *       all 20x cards have PCI device ids 0x20..
 448  *
 449  * There are also Quartet Serial cards which use Oxford Semiconductor
 450  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 451  *
 452  * Note: some SIIG cards are probed by the parport_serial object.
 453  */
 454
 455 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 456 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 457
 458 static int pci_siig10x_init(struct pci_dev *dev)
 459 {
 460         u16 data;
 461         void __iomem *p;
 462
 463         switch (dev->device & 0xfff8) {
 464         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 465                 data = 0xffdf;
 466                 break;
 467         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 468                 data = 0xf7ff;
 469                 break;
 470         default:                        /* 1S1P, 4S */
 471                 data = 0xfffb;
 472                 break;
 473         }
 474
 475         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 476         if (p == NULL)
 477                 return -ENOMEM;
 478
 479         writew(readw(p + 0x28) & data, p + 0x28);
 480         readw(p + 0x28);
 481         iounmap(p);
 482         return 0;
 483 }
 484
 485 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 486 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 487
 488 static int pci_siig20x_init(struct pci_dev *dev)
 489 {
 490         u8 data;
 491
 492         /* Change clock frequency for the first UART. */
 493         pci_read_config_byte(dev, 0x6f, &data);
 494         pci_write_config_byte(dev, 0x6f, data & 0xef);
 495
 496         /* If this card has 2 UART, we have to do the same with second UART. */
 497         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 498             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 499                 pci_read_config_byte(dev, 0x73, &data);
 500                 pci_write_config_byte(dev, 0x73, data & 0xef);
 501         }
 502         return 0;
 503 }
 504
 505 static int pci_siig_init(struct pci_dev *dev)
 506 {
 507         unsigned int type = dev->device & 0xff00;
 508
 509         if (type == 0x1000)
 510                 return pci_siig10x_init(dev);
 511         else if (type == 0x2000)
 512                 return pci_siig20x_init(dev);
 513
 514         moan_device("Unknown SIIG card", dev);
 515         return -ENODEV;
 516 }
 517
 518 static int pci_siig_setup(struct serial_private *priv,
 519                           const struct pciserial_board *board,
 520                           struct uart_8250_port *port, int idx)
 521 {
 522         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 523
 524         if (idx > 3) {
 525                 bar = 4;
 526                 offset = (idx - 4) * 8;
 527         }
 528
 529         return setup_port(priv, port, bar, offset, 0);
 530 }
 531
 532 /*
 533  * Timedia has an explosion of boards, and to avoid the PCI table from
 534  * growing *huge*, we use this function to collapse some 70 entries
 535  * in the PCI table into one, for sanity's and compactness's sake.
 536  */
 537 static const unsigned short timedia_single_port[] = {
 538         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 539 };
 540
 541 static const unsigned short timedia_dual_port[] = {
 542         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 543         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 544         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 545         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 546         0xD079, 0
 547 };
 548
 549 static const unsigned short timedia_quad_port[] = {
 550         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 551         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 552         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 553         0xB157, 0
 554 };
 555
 556 static const unsigned short timedia_eight_port[] = {
 557         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 558         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 559 };
 560
 561 static const struct timedia_struct {
 562         int num;
 563         const unsigned short *ids;
 564 } timedia_data[] = {
 565         { 1, timedia_single_port },
 566         { 2, timedia_dual_port },
 567         { 4, timedia_quad_port },
 568         { 8, timedia_eight_port }
 569 };
 570
 571 /*
 572  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 573  * listing them individually, this driver merely grabs them all with
 574  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 575  * and should be left free to be claimed by parport_serial instead.
 576  */
 577 static int pci_timedia_probe(struct pci_dev *dev)
 578 {
 579         /*
 580          * Check the third digit of the subdevice ID
 581          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 582          */
 583         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 584                 dev_info(&dev->dev,
 585                         "ignoring Timedia subdevice %04x for parport_serial\n",
 586                         dev->subsystem_device);
 587                 return -ENODEV;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int pci_timedia_init(struct pci_dev *dev)
 594 {
 595         const unsigned short *ids;
 596         int i, j;
 597
 598         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 599                 ids = timedia_data[i].ids;
 600                 for (j = 0; ids[j]; j++)
 601                         if (dev->subsystem_device == ids[j])
 602                                 return timedia_data[i].num;
 603         }
 604         return 0;
 605 }
 606
 607 /*
 608  * Timedia/SUNIX uses a mixture of BARs and offsets
 609  * Ugh, this is ugly as all hell --- TYT
 610  */
 611 static int
 612 pci_timedia_setup(struct serial_private *priv,
 613                   const struct pciserial_board *board,
 614                   struct uart_8250_port *port, int idx)
 615 {
 616         unsigned int bar = 0, offset = board->first_offset;
 617
 618         switch (idx) {
 619         case 0:
 620                 bar = 0;
 621                 break;
 622         case 1:
 623                 offset = board->uart_offset;
 624                 bar = 0;
 625                 break;
 626         case 2:
 627                 bar = 1;
 628                 break;
 629         case 3:
 630                 offset = board->uart_offset;
 631                 /* FALLTHROUGH */
 632         case 4: /* BAR 2 */
 633         case 5: /* BAR 3 */
 634         case 6: /* BAR 4 */
 635         case 7: /* BAR 5 */
 636                 bar = idx - 2;
 637         }
 638
 639         return setup_port(priv, port, bar, offset, board->reg_shift);
 640 }
 641
 642 /*
 643  * Some Titan cards are also a little weird
 644  */
 645 static int
 646 titan_400l_800l_setup(struct serial_private *priv,
 647                       const struct pciserial_board *board,
 648                       struct uart_8250_port *port, int idx)
 649 {
 650         unsigned int bar, offset = board->first_offset;
 651
 652         switch (idx) {
 653         case 0:
 654                 bar = 1;
 655                 break;
 656         case 1:
 657                 bar = 2;
 658                 break;
 659         default:
 660                 bar = 4;
 661                 offset = (idx - 2) * board->uart_offset;
 662         }
 663
 664         return setup_port(priv, port, bar, offset, board->reg_shift);
 665 }
 666
 667 static int pci_xircom_init(struct pci_dev *dev)
 668 {
 669         msleep(100);
 670         return 0;
 671 }
 672
 673 static int pci_ni8420_init(struct pci_dev *dev)
 674 {
 675         void __iomem *p;
 676         unsigned int bar = 0;
 677
 678         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 679                 moan_device("no memory in bar", dev);
 680                 return 0;
 681         }
 682
 683         p = pci_ioremap_bar(dev, bar);
 684         if (p == NULL)
 685                 return -ENOMEM;
 686
 687         /* Enable CPU Interrupt */
 688         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 689                p + NI8420_INT_ENABLE_REG);
 690
 691         iounmap(p);
 692         return 0;
 693 }
 694
 695 #define MITE_IOWBSR1_WSIZE      0xa
 696 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 697 #define MITE_IOWBSR1_WENAB      (1 << 7)
 698 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 699 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 700 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 701
 702 static int pci_ni8430_init(struct pci_dev *dev)
 703 {
 704         void __iomem *p;
 705         struct pci_bus_region region;
 706         u32 device_window;
 707         unsigned int bar = 0;
 708
 709         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 710                 moan_device("no memory in bar", dev);
 711                 return 0;
 712         }
 713
 714         p = pci_ioremap_bar(dev, bar);
 715         if (p == NULL)
 716                 return -ENOMEM;
 717
 718         /*
 719          * Set device window address and size in BAR0, while acknowledging that
 720          * the resource structure may contain a translated address that differs
 721          * from the address the device responds to.
 722          */
 723         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 724         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 725                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 726         writel(device_window, p + MITE_IOWBSR1);
 727
 728         /* Set window access to go to RAMSEL IO address space */
 729         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 730                p + MITE_IOWCR1);
 731
 732         /* Enable IO Bus Interrupt 0 */
 733         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 734
 735         /* Enable CPU Interrupt */
 736         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 737
 738         iounmap(p);
 739         return 0;
 740 }
 741
 742 /* UART Port Control Register */
 743 #define NI8430_PORTCON  0x0f
 744 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 745
 746 static int
 747 pci_ni8430_setup(struct serial_private *priv,
 748                  const struct pciserial_board *board,
 749                  struct uart_8250_port *port, int idx)
 750 {
 751         struct pci_dev *dev = priv->dev;
 752         void __iomem *p;
 753         unsigned int bar, offset = board->first_offset;
 754
 755         if (idx >= board->num_ports)
 756                 return 1;
 757
 758         bar = FL_GET_BASE(board->flags);
 759         offset += idx * board->uart_offset;
 760
 761         p = pci_ioremap_bar(dev, bar);
 762         if (!p)
 763                 return -ENOMEM;
 764
 765         /* enable the transceiver */
 766         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 767                p + offset + NI8430_PORTCON);
 768
 769         iounmap(p);
 770
 771         return setup_port(priv, port, bar, offset, board->reg_shift);
 772 }
 773
 774 static int pci_netmos_9900_setup(struct serial_private *priv,
 775                                 const struct pciserial_board *board,
 776                                 struct uart_8250_port *port, int idx)
 777 {
 778         unsigned int bar;
 779
 780         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 781             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 782                 /* netmos apparently orders BARs by datasheet layout, so serial
 783                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 784                  */
 785                 bar = 3 * idx;
 786
 787                 return setup_port(priv, port, bar, 0, board->reg_shift);
 788         } else {
 789                 return pci_default_setup(priv, board, port, idx);
 790         }
 791 }
 792
 793 /* the 99xx series comes with a range of device IDs and a variety
 794  * of capabilities:
 795  *
 796  * 9900 has varying capabilities and can cascade to sub-controllers
 797  *   (cascading should be purely internal)
 798  * 9904 is hardwired with 4 serial ports
 799  * 9912 and 9922 are hardwired with 2 serial ports
 800  */
 801 static int pci_netmos_9900_numports(struct pci_dev *dev)
 802 {
 803         unsigned int c = dev->class;
 804         unsigned int pi;
 805         unsigned short sub_serports;
 806
 807         pi = (c & 0xff);
 808
 809         if (pi == 2) {
 810                 return 1;
 811         } else if ((pi == 0) &&
 812                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 813                 /* two possibilities: 0x30ps encodes number of parallel and
 814                  * serial ports, or 0x1000 indicates *something*. This is not
 815                  * immediately obvious, since the 2s1p+4s configuration seems
 816                  * to offer all functionality on functions 0..2, while still
 817                  * advertising the same function 3 as the 4s+2s1p config.
 818                  */
 819                 sub_serports = dev->subsystem_device & 0xf;
 820                 if (sub_serports > 0) {
 821                         return sub_serports;
 822                 } else {
 823                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 824                         return 0;
 825                 }
 826         }
 827
 828         moan_device("unknown NetMos/Mostech program interface", dev);
 829         return 0;
 830 }
 831
 832 static int pci_netmos_init(struct pci_dev *dev)
 833 {
 834         /* subdevice 0x00PS means <P> parallel, <S> serial */
 835         unsigned int num_serial = dev->subsystem_device & 0xf;
 836
 837         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 838                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 839                 return 0;
 840
 841         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 842                         dev->subsystem_device == 0x0299)
 843                 return 0;
 844
 845         switch (dev->device) { /* FALLTHROUGH on all */
 846                 case PCI_DEVICE_ID_NETMOS_9904:
 847                 case PCI_DEVICE_ID_NETMOS_9912:
 848                 case PCI_DEVICE_ID_NETMOS_9922:
 849                 case PCI_DEVICE_ID_NETMOS_9900:
 850                         num_serial = pci_netmos_9900_numports(dev);
 851                         break;
 852
 853                 default:
 854                         if (num_serial == 0 ) {
 855                                 moan_device("unknown NetMos/Mostech device", dev);
 856                         }
 857         }
 858
 859         if (num_serial == 0)
 860                 return -ENODEV;
 861
 862         return num_serial;
 863 }
 864
 865 /*
 866  * These chips are available with optionally one parallel port and up to
 867  * two serial ports. Unfortunately they all have the same product id.
 868  *
 869  * Basic configuration is done over a region of 32 I/O ports. The base
 870  * ioport is called INTA or INTC, depending on docs/other drivers.
 871  *
 872  * The region of the 32 I/O ports is configured in POSIO0R...
 873  */
 874
 875 /* registers */
 876 #define ITE_887x_MISCR          0x9c
 877 #define ITE_887x_INTCBAR        0x78
 878 #define ITE_887x_UARTBAR        0x7c
 879 #define ITE_887x_PS0BAR         0x10
 880 #define ITE_887x_POSIO0         0x60
 881
 882 /* I/O space size */
 883 #define ITE_887x_IOSIZE         32
 884 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 885 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 886 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 887 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 888 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 889 #define ITE_887x_POSIO_SPEED            (3 << 29)
 890 /* enable IO_Space bit */
 891 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 892
 893 static int pci_ite887x_init(struct pci_dev *dev)
 894 {
 895         /* inta_addr are the configuration addresses of the ITE */
 896         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 897                                                         0x200, 0x280, 0 };
 898         int ret, i, type;
 899         struct resource *iobase = NULL;
 900         u32 miscr, uartbar, ioport;
 901
 902         /* search for the base-ioport */
 903         i = 0;
 904         while (inta_addr[i] && iobase == NULL) {
 905                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 906                                                                 "ite887x");
 907                 if (iobase != NULL) {
 908                         /* write POSIO0R - speed | size | ioport */
 909                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 910                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 911                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 912                         /* write INTCBAR - ioport */
 913                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 914                                                                 inta_addr[i]);
 915                         ret = inb(inta_addr[i]);
 916                         if (ret != 0xff) {
 917                                 /* ioport connected */
 918                                 break;
 919                         }
 920                         release_region(iobase->start, ITE_887x_IOSIZE);
 921                         iobase = NULL;
 922                 }
 923                 i++;
 924         }
 925
 926         if (!inta_addr[i]) {
 927                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 928                 return -ENODEV;
 929         }
 930
 931         /* start of undocumented type checking (see parport_pc.c) */
 932         type = inb(iobase->start + 0x18) & 0x0f;
 933
 934         switch (type) {
 935         case 0x2:       /* ITE8871 (1P) */
 936         case 0xa:       /* ITE8875 (1P) */
 937                 ret = 0;
 938                 break;
 939         case 0xe:       /* ITE8872 (2S1P) */
 940                 ret = 2;
 941                 break;
 942         case 0x6:       /* ITE8873 (1S) */
 943                 ret = 1;
 944                 break;
 945         case 0x8:       /* ITE8874 (2S) */
 946                 ret = 2;
 947                 break;
 948         default:
 949                 moan_device("Unknown ITE887x", dev);
 950                 ret = -ENODEV;
 951         }
 952
 953         /* configure all serial ports */
 954         for (i = 0; i < ret; i++) {
 955                 /* read the I/O port from the device */
 956                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 957                                                                 &ioport);
 958                 ioport &= 0x0000FF00;   /* the actual base address */
 959                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 960                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 961                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 962
 963                 /* write the ioport to the UARTBAR */
 964                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 965                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 966                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 967                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 968
 969                 /* get current config */
 970                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 971                 /* disable interrupts (UARTx_Routing[3:0]) */
 972                 miscr &= ~(0xf << (12 - 4 * i));
 973                 /* activate the UART (UARTx_En) */
 974                 miscr |= 1 << (23 - i);
 975                 /* write new config with activated UART */
 976                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 977         }
 978
 979         if (ret <= 0) {
 980                 /* the device has no UARTs if we get here */
 981                 release_region(iobase->start, ITE_887x_IOSIZE);
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void pci_ite887x_exit(struct pci_dev *dev)
 988 {
 989         u32 ioport;
 990         /* the ioport is bit 0-15 in POSIO0R */
 991         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 992         ioport &= 0xffff;
 993         release_region(ioport, ITE_887x_IOSIZE);
 994 }
 995
 996 /*
 997  * EndRun Technologies.
 998  * Determine the number of ports available on the device.
 999  */
1000 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1002
1003 static int pci_endrun_init(struct pci_dev *dev)
1004 {
1005         u8 __iomem *p;
1006         unsigned long deviceID;
1007         unsigned int  number_uarts = 0;
1008
1009         /* EndRun device is all 0xexxx */
1010         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011                 (dev->device & 0xf000) != 0xe000)
1012                 return 0;
1013
1014         p = pci_iomap(dev, 0, 5);
1015         if (p == NULL)
1016                 return -ENOMEM;
1017
1018         deviceID = ioread32(p);
1019         /* EndRun device */
1020         if (deviceID == 0x07000200) {
1021                 number_uarts = ioread8(p + 4);
1022                 dev_dbg(&dev->dev,
1023                         "%d ports detected on EndRun PCI Express device\n",
1024                         number_uarts);
1025         }
1026         pci_iounmap(dev, p);
1027         return number_uarts;
1028 }
1029
1030 /*
1031  * Oxford Semiconductor Inc.
1032  * Check that device is part of the Tornado range of devices, then determine
1033  * the number of ports available on the device.
1034  */
1035 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 {
1037         u8 __iomem *p;
1038         unsigned long deviceID;
1039         unsigned int  number_uarts = 0;
1040
1041         /* OxSemi Tornado devices are all 0xCxxx */
1042         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043             (dev->device & 0xF000) != 0xC000)
1044                 return 0;
1045
1046         p = pci_iomap(dev, 0, 5);
1047         if (p == NULL)
1048                 return -ENOMEM;
1049
1050         deviceID = ioread32(p);
1051         /* Tornado device */
1052         if (deviceID == 0x07000200) {
1053                 number_uarts = ioread8(p + 4);
1054                 dev_dbg(&dev->dev,
1055                         "%d ports detected on Oxford PCI Express device\n",
1056                         number_uarts);
1057         }
1058         pci_iounmap(dev, p);
1059         return number_uarts;
1060 }
1061
1062 static int pci_asix_setup(struct serial_private *priv,
1063                   const struct pciserial_board *board,
1064                   struct uart_8250_port *port, int idx)
1065 {
1066         port->bugs |= UART_BUG_PARITY;
1067         return pci_default_setup(priv, board, port, idx);
1068 }
1069
1070 /* Quatech devices have their own extra interface features */
1071
1072 struct quatech_feature {
1073         u16 devid;
1074         bool amcc;
1075 };
1076
1077 #define QPCR_TEST_FOR1          0x3F
1078 #define QPCR_TEST_GET1          0x00
1079 #define QPCR_TEST_FOR2          0x40
1080 #define QPCR_TEST_GET2          0x40
1081 #define QPCR_TEST_FOR3          0x80
1082 #define QPCR_TEST_GET3          0x40
1083 #define QPCR_TEST_FOR4          0xC0
1084 #define QPCR_TEST_GET4          0x80
1085
1086 #define QOPR_CLOCK_X1           0x0000
1087 #define QOPR_CLOCK_X2           0x0001
1088 #define QOPR_CLOCK_X4           0x0002
1089 #define QOPR_CLOCK_X8           0x0003
1090 #define QOPR_CLOCK_RATE_MASK    0x0003
1091
1092
1093 static struct quatech_feature quatech_cards[] = {
1094         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1096         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1098         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1100         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1101         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1103         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1105         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113         { 0, }
1114 };
1115
1116 static int pci_quatech_amcc(u16 devid)
1117 {
1118         struct quatech_feature *qf = &quatech_cards[0];
1119         while (qf->devid) {
1120                 if (qf->devid == devid)
1121                         return qf->amcc;
1122                 qf++;
1123         }
1124         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125         return 0;
1126 };
1127
1128 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 {
1130         unsigned long base = port->port.iobase;
1131         u8 LCR, val;
1132
1133         LCR = inb(base + UART_LCR);
1134         outb(0xBF, base + UART_LCR);
1135         val = inb(base + UART_SCR);
1136         outb(LCR, base + UART_LCR);
1137         return val;
1138 }
1139
1140 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(qopr, base + UART_SCR);
1149         outb(LCR, base + UART_LCR);
1150 }
1151
1152 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 {
1154         unsigned long base = port->port.iobase;
1155         u8 LCR, val, qmcr;
1156
1157         LCR = inb(base + UART_LCR);
1158         outb(0xBF, base + UART_LCR);
1159         val = inb(base + UART_SCR);
1160         outb(val | 0x10, base + UART_SCR);
1161         qmcr = inb(base + UART_MCR);
1162         outb(val, base + UART_SCR);
1163         outb(LCR, base + UART_LCR);
1164
1165         return qmcr;
1166 }
1167
1168 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 {
1170         unsigned long base = port->port.iobase;
1171         u8 LCR, val;
1172
1173         LCR = inb(base + UART_LCR);
1174         outb(0xBF, base + UART_LCR);
1175         val = inb(base + UART_SCR);
1176         outb(val | 0x10, base + UART_SCR);
1177         outb(qmcr, base + UART_MCR);
1178         outb(val, base + UART_SCR);
1179         outb(LCR, base + UART_LCR);
1180 }
1181
1182 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 {
1184         unsigned long base = port->port.iobase;
1185         u8 LCR, val;
1186
1187         LCR = inb(base + UART_LCR);
1188         outb(0xBF, base + UART_LCR);
1189         val = inb(base + UART_SCR);
1190         if (val & 0x20) {
1191                 outb(0x80, UART_LCR);
1192                 if (!(inb(UART_SCR) & 0x20)) {
1193                         outb(LCR, base + UART_LCR);
1194                         return 1;
1195                 }
1196         }
1197         return 0;
1198 }
1199
1200 static int pci_quatech_test(struct uart_8250_port *port)
1201 {
1202         u8 reg;
1203         u8 qopr = pci_quatech_rqopr(port);
1204         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205         reg = pci_quatech_rqopr(port) & 0xC0;
1206         if (reg != QPCR_TEST_GET1)
1207                 return -EINVAL;
1208         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209         reg = pci_quatech_rqopr(port) & 0xC0;
1210         if (reg != QPCR_TEST_GET2)
1211                 return -EINVAL;
1212         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213         reg = pci_quatech_rqopr(port) & 0xC0;
1214         if (reg != QPCR_TEST_GET3)
1215                 return -EINVAL;
1216         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217         reg = pci_quatech_rqopr(port) & 0xC0;
1218         if (reg != QPCR_TEST_GET4)
1219                 return -EINVAL;
1220
1221         pci_quatech_wqopr(port, qopr);
1222         return 0;
1223 }
1224
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227         u8 qopr, reg, set;
1228         unsigned long clock;
1229
1230         if (pci_quatech_test(port) < 0)
1231                 return 1843200;
1232
1233         qopr = pci_quatech_rqopr(port);
1234
1235         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236         reg = pci_quatech_rqopr(port);
1237         if (reg & QOPR_CLOCK_X8) {
1238                 clock = 1843200;
1239                 goto out;
1240         }
1241         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (!(reg & QOPR_CLOCK_X8)) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         reg &= QOPR_CLOCK_X8;
1248         if (reg == QOPR_CLOCK_X2) {
1249                 clock =  3685400;
1250                 set = QOPR_CLOCK_X2;
1251         } else if (reg == QOPR_CLOCK_X4) {
1252                 clock = 7372800;
1253                 set = QOPR_CLOCK_X4;
1254         } else if (reg == QOPR_CLOCK_X8) {
1255                 clock = 14745600;
1256                 set = QOPR_CLOCK_X8;
1257         } else {
1258                 clock = 1843200;
1259                 set = QOPR_CLOCK_X1;
1260         }
1261         qopr &= ~QOPR_CLOCK_RATE_MASK;
1262         qopr |= set;
1263
1264 out:
1265         pci_quatech_wqopr(port, qopr);
1266         return clock;
1267 }
1268
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271         u8 qmcr;
1272         int rs422 = 0;
1273
1274         if (!pci_quatech_has_qmcr(port))
1275                 return 0;
1276         qmcr = pci_quatech_rqmcr(port);
1277         pci_quatech_wqmcr(port, 0xFF);
1278         if (pci_quatech_rqmcr(port))
1279                 rs422 = 1;
1280         pci_quatech_wqmcr(port, qmcr);
1281         return rs422;
1282 }
1283
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286         if (pci_quatech_amcc(dev->device)) {
1287                 unsigned long base = pci_resource_start(dev, 0);
1288                 if (base) {
1289                         u32 tmp;
1290                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1291                         tmp = inl(base + 0x3c);
1292                         outl(tmp | 0x01000000, base + 0x3c);
1293                         outl(tmp &= ~0x01000000, base + 0x3c);
1294                 }
1295         }
1296         return 0;
1297 }
1298
1299 static int pci_quatech_setup(struct serial_private *priv,
1300                   const struct pciserial_board *board,
1301                   struct uart_8250_port *port, int idx)
1302 {
1303         /* Needed by pci_quatech calls below */
1304         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305         /* Set up the clocking */
1306         port->port.uartclk = pci_quatech_clock(port);
1307         /* For now just warn about RS422 */
1308         if (pci_quatech_rs422(port))
1309                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310         return pci_default_setup(priv, board, port, idx);
1311 }
1312
1313 static void pci_quatech_exit(struct pci_dev *dev)
1314 {
1315 }
1316
1317 static int pci_default_setup(struct serial_private *priv,
1318                   const struct pciserial_board *board,
1319                   struct uart_8250_port *port, int idx)
1320 {
1321         unsigned int bar, offset = board->first_offset, maxnr;
1322
1323         bar = FL_GET_BASE(board->flags);
1324         if (board->flags & FL_BASE_BARS)
1325                 bar += idx;
1326         else
1327                 offset += idx * board->uart_offset;
1328
1329         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330                 (board->reg_shift + 3);
1331
1332         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333                 return 1;
1334
1335         return setup_port(priv, port, bar, offset, board->reg_shift);
1336 }
1337
1338 static int pci_pericom_setup(struct serial_private *priv,
1339                   const struct pciserial_board *board,
1340                   struct uart_8250_port *port, int idx)
1341 {
1342         unsigned int bar, offset = board->first_offset, maxnr;
1343
1344         bar = FL_GET_BASE(board->flags);
1345         if (board->flags & FL_BASE_BARS)
1346                 bar += idx;
1347         else
1348                 offset += idx * board->uart_offset;
1349
1350         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351                 (board->reg_shift + 3);
1352
1353         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354                 return 1;
1355
1356         port->port.uartclk = 14745600;
1357
1358         return setup_port(priv, port, bar, offset, board->reg_shift);
1359 }
1360
1361 static int
1362 ce4100_serial_setup(struct serial_private *priv,
1363                   const struct pciserial_board *board,
1364                   struct uart_8250_port *port, int idx)
1365 {
1366         int ret;
1367
1368         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1369         port->port.iotype = UPIO_MEM32;
1370         port->port.type = PORT_XSCALE;
1371         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372         port->port.regshift = 2;
1373
1374         return ret;
1375 }
1376
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1378 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1379
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1381 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1382
1383 #define BYT_PRV_CLK                     0x800
1384 #define BYT_PRV_CLK_EN                  (1 << 0)
1385 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1386 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1387 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1388
1389 #define BYT_TX_OVF_INT                  0x820
1390 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1391
1392 static void
1393 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394                 struct ktermios *old)
1395 {
1396         unsigned int baud = tty_termios_baud_rate(termios);
1397         unsigned long fref = 100000000, fuart = baud * 16;
1398         unsigned long w = BIT(15) - 1;
1399         unsigned long m, n;
1400         u32 reg;
1401
1402         /* Get Fuart closer to Fref */
1403         fuart *= rounddown_pow_of_two(fref / fuart);
1404
1405         /*
1406          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407          * dividers must be adjusted.
1408          *
1409          * uartclk = (m / n) * 100 MHz, where m <= n
1410          */
1411         rational_best_approximation(fuart, fref, w, w, &m, &n);
1412         p->uartclk = fuart;
1413
1414         /* Reset the clock */
1415         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416         writel(reg, p->membase + BYT_PRV_CLK);
1417         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418         writel(reg, p->membase + BYT_PRV_CLK);
1419
1420         p->status &= ~UPSTAT_AUTOCTS;
1421         if (termios->c_cflag & CRTSCTS)
1422                 p->status |= UPSTAT_AUTOCTS;
1423
1424         serial8250_do_set_termios(p, termios, old);
1425 }
1426
1427 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1428 {
1429         struct dw_dma_slave *dws = param;
1430
1431         if (dws->dma_dev != chan->device->dev)
1432                 return false;
1433
1434         chan->private = dws;
1435         return true;
1436 }
1437
1438 static int
1439 byt_serial_setup(struct serial_private *priv,
1440                  const struct pciserial_board *board,
1441                  struct uart_8250_port *port, int idx)
1442 {
1443         struct pci_dev *pdev = priv->dev;
1444         struct device *dev = port->port.dev;
1445         struct uart_8250_dma *dma;
1446         struct dw_dma_slave *tx_param, *rx_param;
1447         struct pci_dev *dma_dev;
1448         int ret;
1449
1450         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1451         if (!dma)
1452                 return -ENOMEM;
1453
1454         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1455         if (!tx_param)
1456                 return -ENOMEM;
1457
1458         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1459         if (!rx_param)
1460                 return -ENOMEM;
1461
1462         switch (pdev->device) {
1463         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1464         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1465                 rx_param->src_id = 3;
1466                 tx_param->dst_id = 2;
1467                 break;
1468         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1469         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1470                 rx_param->src_id = 5;
1471                 tx_param->dst_id = 4;
1472                 break;
1473         default:
1474                 return -EINVAL;
1475         }
1476
1477         rx_param->src_master = 1;
1478         rx_param->dst_master = 0;
1479
1480         dma->rxconf.src_maxburst = 16;
1481
1482         tx_param->src_master = 1;
1483         tx_param->dst_master = 0;
1484
1485         dma->txconf.dst_maxburst = 16;
1486
1487         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1488         rx_param->dma_dev = &dma_dev->dev;
1489         tx_param->dma_dev = &dma_dev->dev;
1490
1491         dma->fn = byt_dma_filter;
1492         dma->rx_param = rx_param;
1493         dma->tx_param = tx_param;
1494
1495         ret = pci_default_setup(priv, board, port, idx);
1496         port->port.iotype = UPIO_MEM;
1497         port->port.type = PORT_16550A;
1498         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1499         port->port.set_termios = byt_set_termios;
1500         port->port.fifosize = 64;
1501         port->tx_loadsz = 64;
1502         port->dma = dma;
1503         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1504
1505         /* Disable Tx counter interrupts */
1506         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1507
1508         return ret;
1509 }
1510
1511 #define INTEL_MID_UART_PS               0x30
1512 #define INTEL_MID_UART_MUL              0x34
1513 #define INTEL_MID_UART_DIV              0x38
1514
1515 static void intel_mid_set_termios(struct uart_port *p,
1516                                   struct ktermios *termios,
1517                                   struct ktermios *old,
1518                                   unsigned long fref)
1519 {
1520         unsigned int baud = tty_termios_baud_rate(termios);
1521         unsigned short ps = 16;
1522         unsigned long fuart = baud * ps;
1523         unsigned long w = BIT(24) - 1;
1524         unsigned long mul, div;
1525
1526         if (fref < fuart) {
1527                 /* Find prescaler value that satisfies Fuart < Fref */
1528                 if (fref > baud)
1529                         ps = fref / baud;       /* baud rate too high */
1530                 else
1531                         ps = 1;                 /* PLL case */
1532                 fuart = baud * ps;
1533         } else {
1534                 /* Get Fuart closer to Fref */
1535                 fuart *= rounddown_pow_of_two(fref / fuart);
1536         }
1537
1538         rational_best_approximation(fuart, fref, w, w, &mul, &div);
1539         p->uartclk = fuart * 16 / ps;           /* core uses ps = 16 always */
1540
1541         writel(ps, p->membase + INTEL_MID_UART_PS);             /* set PS */
1542         writel(mul, p->membase + INTEL_MID_UART_MUL);           /* set MUL */
1543         writel(div, p->membase + INTEL_MID_UART_DIV);
1544
1545         serial8250_do_set_termios(p, termios, old);
1546 }
1547
1548 static void intel_mid_set_termios_38_4M(struct uart_port *p,
1549                                         struct ktermios *termios,
1550                                         struct ktermios *old)
1551 {
1552         intel_mid_set_termios(p, termios, old, 38400000);
1553 }
1554
1555 static void intel_mid_set_termios_50M(struct uart_port *p,
1556                                       struct ktermios *termios,
1557                                       struct ktermios *old)
1558 {
1559         /*
1560          * The uart clk is 50Mhz, and the baud rate come from:
1561          *      baud = 50M * MUL / (DIV * PS * DLAB)
1562          */
1563         intel_mid_set_termios(p, termios, old, 50000000);
1564 }
1565
1566 static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1567 {
1568         struct hsu_dma_slave *s = param;
1569
1570         if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1571                 return false;
1572
1573         chan->private = s;
1574         return true;
1575 }
1576
1577 static int intel_mid_serial_setup(struct serial_private *priv,
1578                                   const struct pciserial_board *board,
1579                                   struct uart_8250_port *port, int idx,
1580                                   int index, struct pci_dev *dma_dev)
1581 {
1582         struct device *dev = port->port.dev;
1583         struct uart_8250_dma *dma;
1584         struct hsu_dma_slave *tx_param, *rx_param;
1585
1586         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1587         if (!dma)
1588                 return -ENOMEM;
1589
1590         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1591         if (!tx_param)
1592                 return -ENOMEM;
1593
1594         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1595         if (!rx_param)
1596                 return -ENOMEM;
1597
1598         rx_param->chan_id = index * 2 + 1;
1599         tx_param->chan_id = index * 2;
1600
1601         dma->rxconf.src_maxburst = 64;
1602         dma->txconf.dst_maxburst = 64;
1603
1604         rx_param->dma_dev = &dma_dev->dev;
1605         tx_param->dma_dev = &dma_dev->dev;
1606
1607         dma->fn = intel_mid_dma_filter;
1608         dma->rx_param = rx_param;
1609         dma->tx_param = tx_param;
1610
1611         port->port.type = PORT_16750;
1612         port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1613         port->dma = dma;
1614
1615         return pci_default_setup(priv, board, port, idx);
1616 }
1617
1618 #define PCI_DEVICE_ID_INTEL_PNW_UART1   0x081b
1619 #define PCI_DEVICE_ID_INTEL_PNW_UART2   0x081c
1620 #define PCI_DEVICE_ID_INTEL_PNW_UART3   0x081d
1621
1622 static int pnw_serial_setup(struct serial_private *priv,
1623                             const struct pciserial_board *board,
1624                             struct uart_8250_port *port, int idx)
1625 {
1626         struct pci_dev *pdev = priv->dev;
1627         struct pci_dev *dma_dev;
1628         int index;
1629
1630         switch (pdev->device) {
1631         case PCI_DEVICE_ID_INTEL_PNW_UART1:
1632                 index = 0;
1633                 break;
1634         case PCI_DEVICE_ID_INTEL_PNW_UART2:
1635                 index = 1;
1636                 break;
1637         case PCI_DEVICE_ID_INTEL_PNW_UART3:
1638                 index = 2;
1639                 break;
1640         default:
1641                 return -EINVAL;
1642         }
1643
1644         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1645
1646         port->port.set_termios = intel_mid_set_termios_50M;
1647
1648         return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1649 }
1650
1651 #define PCI_DEVICE_ID_INTEL_TNG_UART    0x1191
1652
1653 static int tng_serial_setup(struct serial_private *priv,
1654                             const struct pciserial_board *board,
1655                             struct uart_8250_port *port, int idx)
1656 {
1657         struct pci_dev *pdev = priv->dev;
1658         struct pci_dev *dma_dev;
1659         int index = PCI_FUNC(pdev->devfn);
1660
1661         /* Currently no support for HSU port0 */
1662         if (index-- == 0)
1663                 return -ENODEV;
1664
1665         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1666
1667         port->port.set_termios = intel_mid_set_termios_38_4M;
1668
1669         return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1670 }
1671
1672 static int
1673 pci_omegapci_setup(struct serial_private *priv,
1674                       const struct pciserial_board *board,
1675                       struct uart_8250_port *port, int idx)
1676 {
1677         return setup_port(priv, port, 2, idx * 8, 0);
1678 }
1679
1680 static int
1681 pci_brcm_trumanage_setup(struct serial_private *priv,
1682                          const struct pciserial_board *board,
1683                          struct uart_8250_port *port, int idx)
1684 {
1685         int ret = pci_default_setup(priv, board, port, idx);
1686
1687         port->port.type = PORT_BRCM_TRUMANAGE;
1688         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1689         return ret;
1690 }
1691
1692 /* RTS will control by MCR if this bit is 0 */
1693 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1694 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1695 #define FINTEK_RTS_INVERT               BIT(5)
1696
1697 /* We should do proper H/W transceiver setting before change to RS485 mode */
1698 static int pci_fintek_rs485_config(struct uart_port *port,
1699                                struct serial_rs485 *rs485)
1700 {
1701         u8 setting;
1702         u8 *index = (u8 *) port->private_data;
1703         struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1704                                                 dev);
1705
1706         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1707
1708         if (!rs485)
1709                 rs485 = &port->rs485;
1710         else if (rs485->flags & SER_RS485_ENABLED)
1711                 memset(rs485->padding, 0, sizeof(rs485->padding));
1712         else
1713                 memset(rs485, 0, sizeof(*rs485));
1714
1715         /* F81504/508/512 not support RTS delay before or after send */
1716         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1717
1718         if (rs485->flags & SER_RS485_ENABLED) {
1719                 /* Enable RTS H/W control mode */
1720                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1721
1722                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1723                         /* RTS driving high on TX */
1724                         setting &= ~FINTEK_RTS_INVERT;
1725                 } else {
1726                         /* RTS driving low on TX */
1727                         setting |= FINTEK_RTS_INVERT;
1728                 }
1729
1730                 rs485->delay_rts_after_send = 0;
1731                 rs485->delay_rts_before_send = 0;
1732         } else {
1733                 /* Disable RTS H/W control mode */
1734                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1735         }
1736
1737         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1738
1739         if (rs485 != &port->rs485)
1740                 port->rs485 = *rs485;
1741
1742         return 0;
1743 }
1744
1745 static int pci_fintek_setup(struct serial_private *priv,
1746                             const struct pciserial_board *board,
1747                             struct uart_8250_port *port, int idx)
1748 {
1749         struct pci_dev *pdev = priv->dev;
1750         u8 *data;
1751         u8 config_base;
1752         u16 iobase;
1753
1754         config_base = 0x40 + 0x08 * idx;
1755
1756         /* Get the io address from configuration space */
1757         pci_read_config_word(pdev, config_base + 4, &iobase);
1758
1759         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1760
1761         port->port.iotype = UPIO_PORT;
1762         port->port.iobase = iobase;
1763         port->port.rs485_config = pci_fintek_rs485_config;
1764
1765         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1766         if (!data)
1767                 return -ENOMEM;
1768
1769         /* preserve index in PCI configuration space */
1770         *data = idx;
1771         port->port.private_data = data;
1772
1773         return 0;
1774 }
1775
1776 static int pci_fintek_init(struct pci_dev *dev)
1777 {
1778         unsigned long iobase;
1779         u32 max_port, i;
1780         u32 bar_data[3];
1781         u8 config_base;
1782         struct serial_private *priv = pci_get_drvdata(dev);
1783         struct uart_8250_port *port;
1784
1785         switch (dev->device) {
1786         case 0x1104: /* 4 ports */
1787         case 0x1108: /* 8 ports */
1788                 max_port = dev->device & 0xff;
1789                 break;
1790         case 0x1112: /* 12 ports */
1791                 max_port = 12;
1792                 break;
1793         default:
1794                 return -EINVAL;
1795         }
1796
1797         /* Get the io address dispatch from the BIOS */
1798         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1799         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1800         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1801
1802         for (i = 0; i < max_port; ++i) {
1803                 /* UART0 configuration offset start from 0x40 */
1804                 config_base = 0x40 + 0x08 * i;
1805
1806                 /* Calculate Real IO Port */
1807                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1808
1809                 /* Enable UART I/O port */
1810                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1811
1812                 /* Select 128-byte FIFO and 8x FIFO threshold */
1813                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1814
1815                 /* LSB UART */
1816                 pci_write_config_byte(dev, config_base + 0x04,
1817                                 (u8)(iobase & 0xff));
1818
1819                 /* MSB UART */
1820                 pci_write_config_byte(dev, config_base + 0x05,
1821                                 (u8)((iobase & 0xff00) >> 8));
1822
1823                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1824
1825                 if (priv) {
1826                         /* re-apply RS232/485 mode when
1827                          * pciserial_resume_ports()
1828                          */
1829                         port = serial8250_get_port(priv->line[i]);
1830                         pci_fintek_rs485_config(&port->port, NULL);
1831                 } else {
1832                         /* First init without port data
1833                          * force init to RS232 Mode
1834                          */
1835                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1836                 }
1837         }
1838
1839         return max_port;
1840 }
1841
1842 static int skip_tx_en_setup(struct serial_private *priv,
1843                         const struct pciserial_board *board,
1844                         struct uart_8250_port *port, int idx)
1845 {
1846         port->port.flags |= UPF_NO_TXEN_TEST;
1847         dev_dbg(&priv->dev->dev,
1848                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1849                 priv->dev->vendor, priv->dev->device,
1850                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1851
1852         return pci_default_setup(priv, board, port, idx);
1853 }
1854
1855 static void kt_handle_break(struct uart_port *p)
1856 {
1857         struct uart_8250_port *up = up_to_u8250p(p);
1858         /*
1859          * On receipt of a BI, serial device in Intel ME (Intel
1860          * management engine) needs to have its fifos cleared for sane
1861          * SOL (Serial Over Lan) output.
1862          */
1863         serial8250_clear_and_reinit_fifos(up);
1864 }
1865
1866 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1867 {
1868         struct uart_8250_port *up = up_to_u8250p(p);
1869         unsigned int val;
1870
1871         /*
1872          * When the Intel ME (management engine) gets reset its serial
1873          * port registers could return 0 momentarily.  Functions like
1874          * serial8250_console_write, read and save the IER, perform
1875          * some operation and then restore it.  In order to avoid
1876          * setting IER register inadvertently to 0, if the value read
1877          * is 0, double check with ier value in uart_8250_port and use
1878          * that instead.  up->ier should be the same value as what is
1879          * currently configured.
1880          */
1881         val = inb(p->iobase + offset);
1882         if (offset == UART_IER) {
1883                 if (val == 0)
1884                         val = up->ier;
1885         }
1886         return val;
1887 }
1888
1889 static int kt_serial_setup(struct serial_private *priv,
1890                            const struct pciserial_board *board,
1891                            struct uart_8250_port *port, int idx)
1892 {
1893         port->port.flags |= UPF_BUG_THRE;
1894         port->port.serial_in = kt_serial_in;
1895         port->port.handle_break = kt_handle_break;
1896         return skip_tx_en_setup(priv, board, port, idx);
1897 }
1898
1899 static int pci_eg20t_init(struct pci_dev *dev)
1900 {
1901 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1902         return -ENODEV;
1903 #else
1904         return 0;
1905 #endif
1906 }
1907
1908 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1909 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1910
1911 static int
1912 pci_xr17c154_setup(struct serial_private *priv,
1913                   const struct pciserial_board *board,
1914                   struct uart_8250_port *port, int idx)
1915 {
1916         port->port.flags |= UPF_EXAR_EFR;
1917         return pci_default_setup(priv, board, port, idx);
1918 }
1919
1920 static inline int
1921 xr17v35x_has_slave(struct serial_private *priv)
1922 {
1923         const int dev_id = priv->dev->device;
1924
1925         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1926                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1927 }
1928
1929 static int
1930 pci_xr17v35x_setup(struct serial_private *priv,
1931                   const struct pciserial_board *board,
1932                   struct uart_8250_port *port, int idx)
1933 {
1934         u8 __iomem *p;
1935
1936         p = pci_ioremap_bar(priv->dev, 0);
1937         if (p == NULL)
1938                 return -ENOMEM;
1939
1940         port->port.flags |= UPF_EXAR_EFR;
1941
1942         /*
1943          * Setup the uart clock for the devices on expansion slot to
1944          * half the clock speed of the main chip (which is 125MHz)
1945          */
1946         if (xr17v35x_has_slave(priv) && idx >= 8)
1947                 port->port.uartclk = (7812500 * 16 / 2);
1948
1949         /*
1950          * Setup Multipurpose Input/Output pins.
1951          */
1952         if (idx == 0) {
1953                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1954                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1955                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1956                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1957                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1958                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1959                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1960                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1961                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1962                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1963                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1964                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1965         }
1966         writeb(0x00, p + UART_EXAR_8XMODE);
1967         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1968         writeb(128, p + UART_EXAR_TXTRG);
1969         writeb(128, p + UART_EXAR_RXTRG);
1970         iounmap(p);
1971
1972         return pci_default_setup(priv, board, port, idx);
1973 }
1974
1975 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1976 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1977 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1978 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1979
1980 static int
1981 pci_fastcom335_setup(struct serial_private *priv,
1982                   const struct pciserial_board *board,
1983                   struct uart_8250_port *port, int idx)
1984 {
1985         u8 __iomem *p;
1986
1987         p = pci_ioremap_bar(priv->dev, 0);
1988         if (p == NULL)
1989                 return -ENOMEM;
1990
1991         port->port.flags |= UPF_EXAR_EFR;
1992
1993         /*
1994          * Setup Multipurpose Input/Output pins.
1995          */
1996         if (idx == 0) {
1997                 switch (priv->dev->device) {
1998                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1999                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
2000                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
2001                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
2002                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
2003                         break;
2004                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
2005                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
2006                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
2007                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
2008                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
2009                         break;
2010                 }
2011                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
2012                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
2013                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
2014         }
2015         writeb(0x00, p + UART_EXAR_8XMODE);
2016         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
2017         writeb(32, p + UART_EXAR_TXTRG);
2018         writeb(32, p + UART_EXAR_RXTRG);
2019         iounmap(p);
2020
2021         return pci_default_setup(priv, board, port, idx);
2022 }
2023
2024 static int
2025 pci_wch_ch353_setup(struct serial_private *priv,
2026                     const struct pciserial_board *board,
2027                     struct uart_8250_port *port, int idx)
2028 {
2029         port->port.flags |= UPF_FIXED_TYPE;
2030         port->port.type = PORT_16550A;
2031         return pci_default_setup(priv, board, port, idx);
2032 }
2033
2034 static int
2035 pci_wch_ch38x_setup(struct serial_private *priv,
2036                     const struct pciserial_board *board,
2037                     struct uart_8250_port *port, int idx)
2038 {
2039         port->port.flags |= UPF_FIXED_TYPE;
2040         port->port.type = PORT_16850;
2041         return pci_default_setup(priv, board, port, idx);
2042 }
2043
2044 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
2045 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
2046 #define PCI_DEVICE_ID_OCTPRO            0x0001
2047 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
2048 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
2049 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
2050 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
2051 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
2052 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
2053 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
2054 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
2055 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
2056 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
2057 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
2058 #define PCI_DEVICE_ID_TITAN_200I        0x8028
2059 #define PCI_DEVICE_ID_TITAN_400I        0x8048
2060 #define PCI_DEVICE_ID_TITAN_800I        0x8088
2061 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
2062 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
2063 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
2064 #define PCI_DEVICE_ID_TITAN_100E        0xA010
2065 #define PCI_DEVICE_ID_TITAN_200E        0xA012
2066 #define PCI_DEVICE_ID_TITAN_400E        0xA013
2067 #define PCI_DEVICE_ID_TITAN_800E        0xA014
2068 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
2069 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
2070 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
2071 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
2072 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
2073 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
2074 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
2075 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
2076 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
2077 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
2078 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
2079 #define PCI_VENDOR_ID_WCH               0x4348
2080 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
2081 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
2082 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
2083 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
2084 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
2085 #define PCI_VENDOR_ID_AGESTAR           0x5372
2086 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
2087 #define PCI_VENDOR_ID_ASIX              0x9710
2088 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
2089 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
2090 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
2091 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
2092 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
2093 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
2094
2095 #define PCI_VENDOR_ID_SUNIX             0x1fd4
2096 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
2097
2098 #define PCIE_VENDOR_ID_WCH              0x1c00
2099 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
2100 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
2101
2102 #define PCI_VENDOR_ID_PERICOM                   0x12D8
2103 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
2104 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
2105 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
2106 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
2107
2108 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2109 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
2110 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
2111
2112 /*
2113  * Master list of serial port init/setup/exit quirks.
2114  * This does not describe the general nature of the port.
2115  * (ie, baud base, number and location of ports, etc)
2116  *
2117  * This list is ordered alphabetically by vendor then device.
2118  * Specific entries must come before more generic entries.
2119  */
2120 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2121         /*
2122         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2123         */
2124         {
2125                 .vendor         = PCI_VENDOR_ID_AMCC,
2126                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2127                 .subvendor      = PCI_ANY_ID,
2128                 .subdevice      = PCI_ANY_ID,
2129                 .setup          = addidata_apci7800_setup,
2130         },
2131         /*
2132          * AFAVLAB cards - these may be called via parport_serial
2133          *  It is not clear whether this applies to all products.
2134          */
2135         {
2136                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
2137                 .device         = PCI_ANY_ID,
2138                 .subvendor      = PCI_ANY_ID,
2139                 .subdevice      = PCI_ANY_ID,
2140                 .setup          = afavlab_setup,
2141         },
2142         /*
2143          * HP Diva
2144          */
2145         {
2146                 .vendor         = PCI_VENDOR_ID_HP,
2147                 .device         = PCI_DEVICE_ID_HP_DIVA,
2148                 .subvendor      = PCI_ANY_ID,
2149                 .subdevice      = PCI_ANY_ID,
2150                 .init           = pci_hp_diva_init,
2151                 .setup          = pci_hp_diva_setup,
2152         },
2153         /*
2154          * Intel
2155          */
2156         {
2157                 .vendor         = PCI_VENDOR_ID_INTEL,
2158                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2159                 .subvendor      = 0xe4bf,
2160                 .subdevice      = PCI_ANY_ID,
2161                 .init           = pci_inteli960ni_init,
2162                 .setup          = pci_default_setup,
2163         },
2164         {
2165                 .vendor         = PCI_VENDOR_ID_INTEL,
2166                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2167                 .subvendor      = PCI_ANY_ID,
2168                 .subdevice      = PCI_ANY_ID,
2169                 .setup          = skip_tx_en_setup,
2170         },
2171         {
2172                 .vendor         = PCI_VENDOR_ID_INTEL,
2173                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2174                 .subvendor      = PCI_ANY_ID,
2175                 .subdevice      = PCI_ANY_ID,
2176                 .setup          = skip_tx_en_setup,
2177         },
2178         {
2179                 .vendor         = PCI_VENDOR_ID_INTEL,
2180                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2181                 .subvendor      = PCI_ANY_ID,
2182                 .subdevice      = PCI_ANY_ID,
2183                 .setup          = skip_tx_en_setup,
2184         },
2185         {
2186                 .vendor         = PCI_VENDOR_ID_INTEL,
2187                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2188                 .subvendor      = PCI_ANY_ID,
2189                 .subdevice      = PCI_ANY_ID,
2190                 .setup          = ce4100_serial_setup,
2191         },
2192         {
2193                 .vendor         = PCI_VENDOR_ID_INTEL,
2194                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2195                 .subvendor      = PCI_ANY_ID,
2196                 .subdevice      = PCI_ANY_ID,
2197                 .setup          = kt_serial_setup,
2198         },
2199         {
2200                 .vendor         = PCI_VENDOR_ID_INTEL,
2201                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2202                 .subvendor      = PCI_ANY_ID,
2203                 .subdevice      = PCI_ANY_ID,
2204                 .setup          = byt_serial_setup,
2205         },
2206         {
2207                 .vendor         = PCI_VENDOR_ID_INTEL,
2208                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2209                 .subvendor      = PCI_ANY_ID,
2210                 .subdevice      = PCI_ANY_ID,
2211                 .setup          = byt_serial_setup,
2212         },
2213         {
2214                 .vendor         = PCI_VENDOR_ID_INTEL,
2215                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART1,
2216                 .subvendor      = PCI_ANY_ID,
2217                 .subdevice      = PCI_ANY_ID,
2218                 .setup          = pnw_serial_setup,
2219         },
2220         {
2221                 .vendor         = PCI_VENDOR_ID_INTEL,
2222                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART2,
2223                 .subvendor      = PCI_ANY_ID,
2224                 .subdevice      = PCI_ANY_ID,
2225                 .setup          = pnw_serial_setup,
2226         },
2227         {
2228                 .vendor         = PCI_VENDOR_ID_INTEL,
2229                 .device         = PCI_DEVICE_ID_INTEL_PNW_UART3,
2230                 .subvendor      = PCI_ANY_ID,
2231                 .subdevice      = PCI_ANY_ID,
2232                 .setup          = pnw_serial_setup,
2233         },
2234         {
2235                 .vendor         = PCI_VENDOR_ID_INTEL,
2236                 .device         = PCI_DEVICE_ID_INTEL_TNG_UART,
2237                 .subvendor      = PCI_ANY_ID,
2238                 .subdevice      = PCI_ANY_ID,
2239                 .setup          = tng_serial_setup,
2240         },
2241         {
2242                 .vendor         = PCI_VENDOR_ID_INTEL,
2243                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2244                 .subvendor      = PCI_ANY_ID,
2245                 .subdevice      = PCI_ANY_ID,
2246                 .setup          = byt_serial_setup,
2247         },
2248         {
2249                 .vendor         = PCI_VENDOR_ID_INTEL,
2250                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2251                 .subvendor      = PCI_ANY_ID,
2252                 .subdevice      = PCI_ANY_ID,
2253                 .setup          = byt_serial_setup,
2254         },
2255         /*
2256          * ITE
2257          */
2258         {
2259                 .vendor         = PCI_VENDOR_ID_ITE,
2260                 .device         = PCI_DEVICE_ID_ITE_8872,
2261                 .subvendor      = PCI_ANY_ID,
2262                 .subdevice      = PCI_ANY_ID,
2263                 .init           = pci_ite887x_init,
2264                 .setup          = pci_default_setup,
2265                 .exit           = pci_ite887x_exit,
2266         },
2267         /*
2268          * National Instruments
2269          */
2270         {
2271                 .vendor         = PCI_VENDOR_ID_NI,
2272                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2273                 .subvendor      = PCI_ANY_ID,
2274                 .subdevice      = PCI_ANY_ID,
2275                 .init           = pci_ni8420_init,
2276                 .setup          = pci_default_setup,
2277                 .exit           = pci_ni8420_exit,
2278         },
2279         {
2280                 .vendor         = PCI_VENDOR_ID_NI,
2281                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2282                 .subvendor      = PCI_ANY_ID,
2283                 .subdevice      = PCI_ANY_ID,
2284                 .init           = pci_ni8420_init,
2285                 .setup          = pci_default_setup,
2286                 .exit           = pci_ni8420_exit,
2287         },
2288         {
2289                 .vendor         = PCI_VENDOR_ID_NI,
2290                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2291                 .subvendor      = PCI_ANY_ID,
2292                 .subdevice      = PCI_ANY_ID,
2293                 .init           = pci_ni8420_init,
2294                 .setup          = pci_default_setup,
2295                 .exit           = pci_ni8420_exit,
2296         },
2297         {
2298                 .vendor         = PCI_VENDOR_ID_NI,
2299                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2300                 .subvendor      = PCI_ANY_ID,
2301                 .subdevice      = PCI_ANY_ID,
2302                 .init           = pci_ni8420_init,
2303                 .setup          = pci_default_setup,
2304                 .exit           = pci_ni8420_exit,
2305         },
2306         {
2307                 .vendor         = PCI_VENDOR_ID_NI,
2308                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2309                 .subvendor      = PCI_ANY_ID,
2310                 .subdevice      = PCI_ANY_ID,
2311                 .init           = pci_ni8420_init,
2312                 .setup          = pci_default_setup,
2313                 .exit           = pci_ni8420_exit,
2314         },
2315         {
2316                 .vendor         = PCI_VENDOR_ID_NI,
2317                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2318                 .subvendor      = PCI_ANY_ID,
2319                 .subdevice      = PCI_ANY_ID,
2320                 .init           = pci_ni8420_init,
2321                 .setup          = pci_default_setup,
2322                 .exit           = pci_ni8420_exit,
2323         },
2324         {
2325                 .vendor         = PCI_VENDOR_ID_NI,
2326                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2327                 .subvendor      = PCI_ANY_ID,
2328                 .subdevice      = PCI_ANY_ID,
2329                 .init           = pci_ni8420_init,
2330                 .setup          = pci_default_setup,
2331                 .exit           = pci_ni8420_exit,
2332         },
2333         {
2334                 .vendor         = PCI_VENDOR_ID_NI,
2335                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2336                 .subvendor      = PCI_ANY_ID,
2337                 .subdevice      = PCI_ANY_ID,
2338                 .init           = pci_ni8420_init,
2339                 .setup          = pci_default_setup,
2340                 .exit           = pci_ni8420_exit,
2341         },
2342         {
2343                 .vendor         = PCI_VENDOR_ID_NI,
2344                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2345                 .subvendor      = PCI_ANY_ID,
2346                 .subdevice      = PCI_ANY_ID,
2347                 .init           = pci_ni8420_init,
2348                 .setup          = pci_default_setup,
2349                 .exit           = pci_ni8420_exit,
2350         },
2351         {
2352                 .vendor         = PCI_VENDOR_ID_NI,
2353                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2354                 .subvendor      = PCI_ANY_ID,
2355                 .subdevice      = PCI_ANY_ID,
2356                 .init           = pci_ni8420_init,
2357                 .setup          = pci_default_setup,
2358                 .exit           = pci_ni8420_exit,
2359         },
2360         {
2361                 .vendor         = PCI_VENDOR_ID_NI,
2362                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2363                 .subvendor      = PCI_ANY_ID,
2364                 .subdevice      = PCI_ANY_ID,
2365                 .init           = pci_ni8420_init,
2366                 .setup          = pci_default_setup,
2367                 .exit           = pci_ni8420_exit,
2368         },
2369         {
2370                 .vendor         = PCI_VENDOR_ID_NI,
2371                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2372                 .subvendor      = PCI_ANY_ID,
2373                 .subdevice      = PCI_ANY_ID,
2374                 .init           = pci_ni8420_init,
2375                 .setup          = pci_default_setup,
2376                 .exit           = pci_ni8420_exit,
2377         },
2378         {
2379                 .vendor         = PCI_VENDOR_ID_NI,
2380                 .device         = PCI_ANY_ID,
2381                 .subvendor      = PCI_ANY_ID,
2382                 .subdevice      = PCI_ANY_ID,
2383                 .init           = pci_ni8430_init,
2384                 .setup          = pci_ni8430_setup,
2385                 .exit           = pci_ni8430_exit,
2386         },
2387         /* Quatech */
2388         {
2389                 .vendor         = PCI_VENDOR_ID_QUATECH,
2390                 .device         = PCI_ANY_ID,
2391                 .subvendor      = PCI_ANY_ID,
2392                 .subdevice      = PCI_ANY_ID,
2393                 .init           = pci_quatech_init,
2394                 .setup          = pci_quatech_setup,
2395                 .exit           = pci_quatech_exit,
2396         },
2397         /*
2398          * Panacom
2399          */
2400         {
2401                 .vendor         = PCI_VENDOR_ID_PANACOM,
2402                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2403                 .subvendor      = PCI_ANY_ID,
2404                 .subdevice      = PCI_ANY_ID,
2405                 .init           = pci_plx9050_init,
2406                 .setup          = pci_default_setup,
2407                 .exit           = pci_plx9050_exit,
2408         },
2409         {
2410                 .vendor         = PCI_VENDOR_ID_PANACOM,
2411                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2412                 .subvendor      = PCI_ANY_ID,
2413                 .subdevice      = PCI_ANY_ID,
2414                 .init           = pci_plx9050_init,
2415                 .setup          = pci_default_setup,
2416                 .exit           = pci_plx9050_exit,
2417         },
2418         /*
2419          * Pericom
2420          */
2421         {
2422                 .vendor         = PCI_VENDOR_ID_PERICOM,
2423                 .device         = PCI_ANY_ID,
2424                 .subvendor      = PCI_ANY_ID,
2425                 .subdevice      = PCI_ANY_ID,
2426                 .setup          = pci_pericom_setup,
2427         },
2428         /*
2429          * PLX
2430          */
2431         {
2432                 .vendor         = PCI_VENDOR_ID_PLX,
2433                 .device         = PCI_DEVICE_ID_PLX_9050,
2434                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2435                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2436                 .init           = pci_plx9050_init,
2437                 .setup          = pci_default_setup,
2438                 .exit           = pci_plx9050_exit,
2439         },
2440         {
2441                 .vendor         = PCI_VENDOR_ID_PLX,
2442                 .device         = PCI_DEVICE_ID_PLX_9050,
2443                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2444                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2445                 .init           = pci_plx9050_init,
2446                 .setup          = pci_default_setup,
2447                 .exit           = pci_plx9050_exit,
2448         },
2449         {
2450                 .vendor         = PCI_VENDOR_ID_PLX,
2451                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2452                 .subvendor      = PCI_VENDOR_ID_PLX,
2453                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2454                 .init           = pci_plx9050_init,
2455                 .setup          = pci_default_setup,
2456                 .exit           = pci_plx9050_exit,
2457         },
2458         /*
2459          * SBS Technologies, Inc., PMC-OCTALPRO 232
2460          */
2461         {
2462                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2463                 .device         = PCI_DEVICE_ID_OCTPRO,
2464                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2465                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2466                 .init           = sbs_init,
2467                 .setup          = sbs_setup,
2468                 .exit           = sbs_exit,
2469         },
2470         /*
2471          * SBS Technologies, Inc., PMC-OCTALPRO 422
2472          */
2473         {
2474                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2475                 .device         = PCI_DEVICE_ID_OCTPRO,
2476                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2477                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2478                 .init           = sbs_init,
2479                 .setup          = sbs_setup,
2480                 .exit           = sbs_exit,
2481         },
2482         /*
2483          * SBS Technologies, Inc., P-Octal 232
2484          */
2485         {
2486                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2487                 .device         = PCI_DEVICE_ID_OCTPRO,
2488                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2489                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2490                 .init           = sbs_init,
2491                 .setup          = sbs_setup,
2492                 .exit           = sbs_exit,
2493         },
2494         /*
2495          * SBS Technologies, Inc., P-Octal 422
2496          */
2497         {
2498                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2499                 .device         = PCI_DEVICE_ID_OCTPRO,
2500                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2501                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2502                 .init           = sbs_init,
2503                 .setup          = sbs_setup,
2504                 .exit           = sbs_exit,
2505         },
2506         /*
2507          * SIIG cards - these may be called via parport_serial
2508          */
2509         {
2510                 .vendor         = PCI_VENDOR_ID_SIIG,
2511                 .device         = PCI_ANY_ID,
2512                 .subvendor      = PCI_ANY_ID,
2513                 .subdevice      = PCI_ANY_ID,
2514                 .init           = pci_siig_init,
2515                 .setup          = pci_siig_setup,
2516         },
2517         /*
2518          * Titan cards
2519          */
2520         {
2521                 .vendor         = PCI_VENDOR_ID_TITAN,
2522                 .device         = PCI_DEVICE_ID_TITAN_400L,
2523                 .subvendor      = PCI_ANY_ID,
2524                 .subdevice      = PCI_ANY_ID,
2525                 .setup          = titan_400l_800l_setup,
2526         },
2527         {
2528                 .vendor         = PCI_VENDOR_ID_TITAN,
2529                 .device         = PCI_DEVICE_ID_TITAN_800L,
2530                 .subvendor      = PCI_ANY_ID,
2531                 .subdevice      = PCI_ANY_ID,
2532                 .setup          = titan_400l_800l_setup,
2533         },
2534         /*
2535          * Timedia cards
2536          */
2537         {
2538                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2539                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2540                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2541                 .subdevice      = PCI_ANY_ID,
2542                 .probe          = pci_timedia_probe,
2543                 .init           = pci_timedia_init,
2544                 .setup          = pci_timedia_setup,
2545         },
2546         {
2547                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2548                 .device         = PCI_ANY_ID,
2549                 .subvendor      = PCI_ANY_ID,
2550                 .subdevice      = PCI_ANY_ID,
2551                 .setup          = pci_timedia_setup,
2552         },
2553         /*
2554          * SUNIX (Timedia) cards
2555          * Do not "probe" for these cards as there is at least one combination
2556          * card that should be handled by parport_pc that doesn't match the
2557          * rule in pci_timedia_probe.
2558          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2559          * There are some boards with part number SER5037AL that report
2560          * subdevice ID 0x0002.
2561          */
2562         {
2563                 .vendor         = PCI_VENDOR_ID_SUNIX,
2564                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2565                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2566                 .subdevice      = PCI_ANY_ID,
2567                 .init           = pci_timedia_init,
2568                 .setup          = pci_timedia_setup,
2569         },
2570         /*
2571          * Exar cards
2572          */
2573         {
2574                 .vendor = PCI_VENDOR_ID_EXAR,
2575                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2576                 .subvendor      = PCI_ANY_ID,
2577                 .subdevice      = PCI_ANY_ID,
2578                 .setup          = pci_xr17c154_setup,
2579         },
2580         {
2581                 .vendor = PCI_VENDOR_ID_EXAR,
2582                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2583                 .subvendor      = PCI_ANY_ID,
2584                 .subdevice      = PCI_ANY_ID,
2585                 .setup          = pci_xr17c154_setup,
2586         },
2587         {
2588                 .vendor = PCI_VENDOR_ID_EXAR,
2589                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2590                 .subvendor      = PCI_ANY_ID,
2591                 .subdevice      = PCI_ANY_ID,
2592                 .setup          = pci_xr17c154_setup,
2593         },
2594         {
2595                 .vendor = PCI_VENDOR_ID_EXAR,
2596                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2597                 .subvendor      = PCI_ANY_ID,
2598                 .subdevice      = PCI_ANY_ID,
2599                 .setup          = pci_xr17v35x_setup,
2600         },
2601         {
2602                 .vendor = PCI_VENDOR_ID_EXAR,
2603                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2604                 .subvendor      = PCI_ANY_ID,
2605                 .subdevice      = PCI_ANY_ID,
2606                 .setup          = pci_xr17v35x_setup,
2607         },
2608         {
2609                 .vendor = PCI_VENDOR_ID_EXAR,
2610                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2611                 .subvendor      = PCI_ANY_ID,
2612                 .subdevice      = PCI_ANY_ID,
2613                 .setup          = pci_xr17v35x_setup,
2614         },
2615         {
2616                 .vendor = PCI_VENDOR_ID_EXAR,
2617                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2618                 .subvendor      = PCI_ANY_ID,
2619                 .subdevice      = PCI_ANY_ID,
2620                 .setup          = pci_xr17v35x_setup,
2621         },
2622         {
2623                 .vendor = PCI_VENDOR_ID_EXAR,
2624                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2625                 .subvendor      = PCI_ANY_ID,
2626                 .subdevice      = PCI_ANY_ID,
2627                 .setup          = pci_xr17v35x_setup,
2628         },
2629         /*
2630          * Xircom cards
2631          */
2632         {
2633                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2634                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2635                 .subvendor      = PCI_ANY_ID,
2636                 .subdevice      = PCI_ANY_ID,
2637                 .init           = pci_xircom_init,
2638                 .setup          = pci_default_setup,
2639         },
2640         /*
2641          * Netmos cards - these may be called via parport_serial
2642          */
2643         {
2644                 .vendor         = PCI_VENDOR_ID_NETMOS,
2645                 .device         = PCI_ANY_ID,
2646                 .subvendor      = PCI_ANY_ID,
2647                 .subdevice      = PCI_ANY_ID,
2648                 .init           = pci_netmos_init,
2649                 .setup          = pci_netmos_9900_setup,
2650         },
2651         /*
2652          * EndRun Technologies
2653         */
2654         {
2655                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2656                 .device         = PCI_ANY_ID,
2657                 .subvendor      = PCI_ANY_ID,
2658                 .subdevice      = PCI_ANY_ID,
2659                 .init           = pci_endrun_init,
2660                 .setup          = pci_default_setup,
2661         },
2662         /*
2663          * For Oxford Semiconductor Tornado based devices
2664          */
2665         {
2666                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2667                 .device         = PCI_ANY_ID,
2668                 .subvendor      = PCI_ANY_ID,
2669                 .subdevice      = PCI_ANY_ID,
2670                 .init           = pci_oxsemi_tornado_init,
2671                 .setup          = pci_default_setup,
2672         },
2673         {
2674                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2675                 .device         = PCI_ANY_ID,
2676                 .subvendor      = PCI_ANY_ID,
2677                 .subdevice      = PCI_ANY_ID,
2678                 .init           = pci_oxsemi_tornado_init,
2679                 .setup          = pci_default_setup,
2680         },
2681         {
2682                 .vendor         = PCI_VENDOR_ID_DIGI,
2683                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2684                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2685                 .subdevice              = PCI_ANY_ID,
2686                 .init                   = pci_oxsemi_tornado_init,
2687                 .setup          = pci_default_setup,
2688         },
2689         {
2690                 .vendor         = PCI_VENDOR_ID_INTEL,
2691                 .device         = 0x8811,
2692                 .subvendor      = PCI_ANY_ID,
2693                 .subdevice      = PCI_ANY_ID,
2694                 .init           = pci_eg20t_init,
2695                 .setup          = pci_default_setup,
2696         },
2697         {
2698                 .vendor         = PCI_VENDOR_ID_INTEL,
2699                 .device         = 0x8812,
2700                 .subvendor      = PCI_ANY_ID,
2701                 .subdevice      = PCI_ANY_ID,
2702                 .init           = pci_eg20t_init,
2703                 .setup          = pci_default_setup,
2704         },
2705         {
2706                 .vendor         = PCI_VENDOR_ID_INTEL,
2707                 .device         = 0x8813,
2708                 .subvendor      = PCI_ANY_ID,
2709                 .subdevice      = PCI_ANY_ID,
2710                 .init           = pci_eg20t_init,
2711                 .setup          = pci_default_setup,
2712         },
2713         {
2714                 .vendor         = PCI_VENDOR_ID_INTEL,
2715                 .device         = 0x8814,
2716                 .subvendor      = PCI_ANY_ID,
2717                 .subdevice      = PCI_ANY_ID,
2718                 .init           = pci_eg20t_init,
2719                 .setup          = pci_default_setup,
2720         },
2721         {
2722                 .vendor         = 0x10DB,
2723                 .device         = 0x8027,
2724                 .subvendor      = PCI_ANY_ID,
2725                 .subdevice      = PCI_ANY_ID,
2726                 .init           = pci_eg20t_init,
2727                 .setup          = pci_default_setup,
2728         },
2729         {
2730                 .vendor         = 0x10DB,
2731                 .device         = 0x8028,
2732                 .subvendor      = PCI_ANY_ID,
2733                 .subdevice      = PCI_ANY_ID,
2734                 .init           = pci_eg20t_init,
2735                 .setup          = pci_default_setup,
2736         },
2737         {
2738                 .vendor         = 0x10DB,
2739                 .device         = 0x8029,
2740                 .subvendor      = PCI_ANY_ID,
2741                 .subdevice      = PCI_ANY_ID,
2742                 .init           = pci_eg20t_init,
2743                 .setup          = pci_default_setup,
2744         },
2745         {
2746                 .vendor         = 0x10DB,
2747                 .device         = 0x800C,
2748                 .subvendor      = PCI_ANY_ID,
2749                 .subdevice      = PCI_ANY_ID,
2750                 .init           = pci_eg20t_init,
2751                 .setup          = pci_default_setup,
2752         },
2753         {
2754                 .vendor         = 0x10DB,
2755                 .device         = 0x800D,
2756                 .subvendor      = PCI_ANY_ID,
2757                 .subdevice      = PCI_ANY_ID,
2758                 .init           = pci_eg20t_init,
2759                 .setup          = pci_default_setup,
2760         },
2761         /*
2762          * Cronyx Omega PCI (PLX-chip based)
2763          */
2764         {
2765                 .vendor         = PCI_VENDOR_ID_PLX,
2766                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2767                 .subvendor      = PCI_ANY_ID,
2768                 .subdevice      = PCI_ANY_ID,
2769                 .setup          = pci_omegapci_setup,
2770         },
2771         /* WCH CH353 1S1P card (16550 clone) */
2772         {
2773                 .vendor         = PCI_VENDOR_ID_WCH,
2774                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2775                 .subvendor      = PCI_ANY_ID,
2776                 .subdevice      = PCI_ANY_ID,
2777                 .setup          = pci_wch_ch353_setup,
2778         },
2779         /* WCH CH353 2S1P card (16550 clone) */
2780         {
2781                 .vendor         = PCI_VENDOR_ID_WCH,
2782                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2783                 .subvendor      = PCI_ANY_ID,
2784                 .subdevice      = PCI_ANY_ID,
2785                 .setup          = pci_wch_ch353_setup,
2786         },
2787         /* WCH CH353 4S card (16550 clone) */
2788         {
2789                 .vendor         = PCI_VENDOR_ID_WCH,
2790                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2791                 .subvendor      = PCI_ANY_ID,
2792                 .subdevice      = PCI_ANY_ID,
2793                 .setup          = pci_wch_ch353_setup,
2794         },
2795         /* WCH CH353 2S1PF card (16550 clone) */
2796         {
2797                 .vendor         = PCI_VENDOR_ID_WCH,
2798                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2799                 .subvendor      = PCI_ANY_ID,
2800                 .subdevice      = PCI_ANY_ID,
2801                 .setup          = pci_wch_ch353_setup,
2802         },
2803         /* WCH CH352 2S card (16550 clone) */
2804         {
2805                 .vendor         = PCI_VENDOR_ID_WCH,
2806                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2807                 .subvendor      = PCI_ANY_ID,
2808                 .subdevice      = PCI_ANY_ID,
2809                 .setup          = pci_wch_ch353_setup,
2810         },
2811         /* WCH CH382 2S1P card (16850 clone) */
2812         {
2813                 .vendor         = PCIE_VENDOR_ID_WCH,
2814                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2815                 .subvendor      = PCI_ANY_ID,
2816                 .subdevice      = PCI_ANY_ID,
2817                 .setup          = pci_wch_ch38x_setup,
2818         },
2819         /* WCH CH384 4S card (16850 clone) */
2820         {
2821                 .vendor         = PCIE_VENDOR_ID_WCH,
2822                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2823                 .subvendor      = PCI_ANY_ID,
2824                 .subdevice      = PCI_ANY_ID,
2825                 .setup          = pci_wch_ch38x_setup,
2826         },
2827         /*
2828          * ASIX devices with FIFO bug
2829          */
2830         {
2831                 .vendor         = PCI_VENDOR_ID_ASIX,
2832                 .device         = PCI_ANY_ID,
2833                 .subvendor      = PCI_ANY_ID,
2834                 .subdevice      = PCI_ANY_ID,
2835                 .setup          = pci_asix_setup,
2836         },
2837         /*
2838          * Commtech, Inc. Fastcom adapters
2839          *
2840          */
2841         {
2842                 .vendor = PCI_VENDOR_ID_COMMTECH,
2843                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2844                 .subvendor      = PCI_ANY_ID,
2845                 .subdevice      = PCI_ANY_ID,
2846                 .setup          = pci_fastcom335_setup,
2847         },
2848         {
2849                 .vendor = PCI_VENDOR_ID_COMMTECH,
2850                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2851                 .subvendor      = PCI_ANY_ID,
2852                 .subdevice      = PCI_ANY_ID,
2853                 .setup          = pci_fastcom335_setup,
2854         },
2855         {
2856                 .vendor = PCI_VENDOR_ID_COMMTECH,
2857                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2858                 .subvendor      = PCI_ANY_ID,
2859                 .subdevice      = PCI_ANY_ID,
2860                 .setup          = pci_fastcom335_setup,
2861         },
2862         {
2863                 .vendor = PCI_VENDOR_ID_COMMTECH,
2864                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2865                 .subvendor      = PCI_ANY_ID,
2866                 .subdevice      = PCI_ANY_ID,
2867                 .setup          = pci_fastcom335_setup,
2868         },
2869         {
2870                 .vendor = PCI_VENDOR_ID_COMMTECH,
2871                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2872                 .subvendor      = PCI_ANY_ID,
2873                 .subdevice      = PCI_ANY_ID,
2874                 .setup          = pci_xr17v35x_setup,
2875         },
2876         {
2877                 .vendor = PCI_VENDOR_ID_COMMTECH,
2878                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2879                 .subvendor      = PCI_ANY_ID,
2880                 .subdevice      = PCI_ANY_ID,
2881                 .setup          = pci_xr17v35x_setup,
2882         },
2883         {
2884                 .vendor = PCI_VENDOR_ID_COMMTECH,
2885                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2886                 .subvendor      = PCI_ANY_ID,
2887                 .subdevice      = PCI_ANY_ID,
2888                 .setup          = pci_xr17v35x_setup,
2889         },
2890         /*
2891          * Broadcom TruManage (NetXtreme)
2892          */
2893         {
2894                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2895                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2896                 .subvendor      = PCI_ANY_ID,
2897                 .subdevice      = PCI_ANY_ID,
2898                 .setup          = pci_brcm_trumanage_setup,
2899         },
2900         {
2901                 .vendor         = 0x1c29,
2902                 .device         = 0x1104,
2903                 .subvendor      = PCI_ANY_ID,
2904                 .subdevice      = PCI_ANY_ID,
2905                 .setup          = pci_fintek_setup,
2906                 .init           = pci_fintek_init,
2907         },
2908         {
2909                 .vendor         = 0x1c29,
2910                 .device         = 0x1108,
2911                 .subvendor      = PCI_ANY_ID,
2912                 .subdevice      = PCI_ANY_ID,
2913                 .setup          = pci_fintek_setup,
2914                 .init           = pci_fintek_init,
2915         },
2916         {
2917                 .vendor         = 0x1c29,
2918                 .device         = 0x1112,
2919                 .subvendor      = PCI_ANY_ID,
2920                 .subdevice      = PCI_ANY_ID,
2921                 .setup          = pci_fintek_setup,
2922                 .init           = pci_fintek_init,
2923         },
2924
2925         /*
2926          * Default "match everything" terminator entry
2927          */
2928         {
2929                 .vendor         = PCI_ANY_ID,
2930                 .device         = PCI_ANY_ID,
2931                 .subvendor      = PCI_ANY_ID,
2932                 .subdevice      = PCI_ANY_ID,
2933                 .setup          = pci_default_setup,
2934         }
2935 };
2936
2937 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2938 {
2939         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2940 }
2941
2942 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2943 {
2944         struct pci_serial_quirk *quirk;
2945
2946         for (quirk = pci_serial_quirks; ; quirk++)
2947                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2948                     quirk_id_matches(quirk->device, dev->device) &&
2949                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2950                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2951                         break;
2952         return quirk;
2953 }
2954
2955 static inline int get_pci_irq(struct pci_dev *dev,
2956                                 const struct pciserial_board *board)
2957 {
2958         if (board->flags & FL_NOIRQ)
2959                 return 0;
2960         else
2961                 return dev->irq;
2962 }
2963
2964 /*
2965  * This is the configuration table for all of the PCI serial boards
2966  * which we support.  It is directly indexed by the pci_board_num_t enum
2967  * value, which is encoded in the pci_device_id PCI probe table's
2968  * driver_data member.
2969  *
2970  * The makeup of these names are:
2971  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2972  *
2973  *  bn          = PCI BAR number
2974  *  bt          = Index using PCI BARs
2975  *  n           = number of serial ports
2976  *  baud        = baud rate
2977  *  offsetinhex = offset for each sequential port (in hex)
2978  *
2979  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2980  *
2981  * Please note: in theory if n = 1, _bt infix should make no difference.
2982  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2983  */
2984 enum pci_board_num_t {
2985         pbn_default = 0,
2986
2987         pbn_b0_1_115200,
2988         pbn_b0_2_115200,
2989         pbn_b0_4_115200,
2990         pbn_b0_5_115200,
2991         pbn_b0_8_115200,
2992
2993         pbn_b0_1_921600,
2994         pbn_b0_2_921600,
2995         pbn_b0_4_921600,
2996
2997         pbn_b0_2_1130000,
2998
2999         pbn_b0_4_1152000,
3000
3001         pbn_b0_2_1152000_200,
3002         pbn_b0_4_1152000_200,
3003         pbn_b0_8_1152000_200,
3004
3005         pbn_b0_2_1843200,
3006         pbn_b0_4_1843200,
3007
3008         pbn_b0_2_1843200_200,
3009         pbn_b0_4_1843200_200,
3010         pbn_b0_8_1843200_200,
3011
3012         pbn_b0_1_4000000,
3013
3014         pbn_b0_bt_1_115200,
3015         pbn_b0_bt_2_115200,
3016         pbn_b0_bt_4_115200,
3017         pbn_b0_bt_8_115200,
3018
3019         pbn_b0_bt_1_460800,
3020         pbn_b0_bt_2_460800,
3021         pbn_b0_bt_4_460800,
3022
3023         pbn_b0_bt_1_921600,
3024         pbn_b0_bt_2_921600,
3025         pbn_b0_bt_4_921600,
3026         pbn_b0_bt_8_921600,
3027
3028         pbn_b1_1_115200,
3029         pbn_b1_2_115200,
3030         pbn_b1_4_115200,
3031         pbn_b1_8_115200,
3032         pbn_b1_16_115200,
3033
3034         pbn_b1_1_921600,
3035         pbn_b1_2_921600,
3036         pbn_b1_4_921600,
3037         pbn_b1_8_921600,
3038
3039         pbn_b1_2_1250000,
3040
3041         pbn_b1_bt_1_115200,
3042         pbn_b1_bt_2_115200,
3043         pbn_b1_bt_4_115200,
3044
3045         pbn_b1_bt_2_921600,
3046
3047         pbn_b1_1_1382400,
3048         pbn_b1_2_1382400,
3049         pbn_b1_4_1382400,
3050         pbn_b1_8_1382400,
3051
3052         pbn_b2_1_115200,
3053         pbn_b2_2_115200,
3054         pbn_b2_4_115200,
3055         pbn_b2_8_115200,
3056
3057         pbn_b2_1_460800,
3058         pbn_b2_4_460800,
3059         pbn_b2_8_460800,
3060         pbn_b2_16_460800,
3061
3062         pbn_b2_1_921600,
3063         pbn_b2_4_921600,
3064         pbn_b2_8_921600,
3065
3066         pbn_b2_8_1152000,
3067
3068         pbn_b2_bt_1_115200,
3069         pbn_b2_bt_2_115200,
3070         pbn_b2_bt_4_115200,
3071
3072         pbn_b2_bt_2_921600,
3073         pbn_b2_bt_4_921600,
3074
3075         pbn_b3_2_115200,
3076         pbn_b3_4_115200,
3077         pbn_b3_8_115200,
3078
3079         pbn_b4_bt_2_921600,
3080         pbn_b4_bt_4_921600,
3081         pbn_b4_bt_8_921600,
3082
3083         /*
3084          * Board-specific versions.
3085          */
3086         pbn_panacom,
3087         pbn_panacom2,
3088         pbn_panacom4,
3089         pbn_plx_romulus,
3090         pbn_endrun_2_4000000,
3091         pbn_oxsemi,
3092         pbn_oxsemi_1_4000000,
3093         pbn_oxsemi_2_4000000,
3094         pbn_oxsemi_4_4000000,
3095         pbn_oxsemi_8_4000000,
3096         pbn_intel_i960,
3097         pbn_sgi_ioc3,
3098         pbn_computone_4,
3099         pbn_computone_6,
3100         pbn_computone_8,
3101         pbn_sbsxrsio,
3102         pbn_exar_XR17C152,
3103         pbn_exar_XR17C154,
3104         pbn_exar_XR17C158,
3105         pbn_exar_XR17V352,
3106         pbn_exar_XR17V354,
3107         pbn_exar_XR17V358,
3108         pbn_exar_XR17V4358,
3109         pbn_exar_XR17V8358,
3110         pbn_exar_ibm_saturn,
3111         pbn_pasemi_1682M,
3112         pbn_ni8430_2,
3113         pbn_ni8430_4,
3114         pbn_ni8430_8,
3115         pbn_ni8430_16,
3116         pbn_ADDIDATA_PCIe_1_3906250,
3117         pbn_ADDIDATA_PCIe_2_3906250,
3118         pbn_ADDIDATA_PCIe_4_3906250,
3119         pbn_ADDIDATA_PCIe_8_3906250,
3120         pbn_ce4100_1_115200,
3121         pbn_byt,
3122         pbn_pnw,
3123         pbn_tng,
3124         pbn_qrk,
3125         pbn_omegapci,
3126         pbn_NETMOS9900_2s_115200,
3127         pbn_brcm_trumanage,
3128         pbn_fintek_4,
3129         pbn_fintek_8,
3130         pbn_fintek_12,
3131         pbn_wch384_4,
3132         pbn_pericom_PI7C9X7951,
3133         pbn_pericom_PI7C9X7952,
3134         pbn_pericom_PI7C9X7954,
3135         pbn_pericom_PI7C9X7958,
3136 };
3137
3138 /*
3139  * uart_offset - the space between channels
3140  * reg_shift   - describes how the UART registers are mapped
3141  *               to PCI memory by the card.
3142  * For example IER register on SBS, Inc. PMC-OctPro is located at
3143  * offset 0x10 from the UART base, while UART_IER is defined as 1
3144  * in include/linux/serial_reg.h,
3145  * see first lines of serial_in() and serial_out() in 8250.c
3146 */
3147
3148 static struct pciserial_board pci_boards[] = {
3149         [pbn_default] = {
3150                 .flags          = FL_BASE0,
3151                 .num_ports      = 1,
3152                 .base_baud      = 115200,
3153                 .uart_offset    = 8,
3154         },
3155         [pbn_b0_1_115200] = {
3156                 .flags          = FL_BASE0,
3157                 .num_ports      = 1,
3158                 .base_baud      = 115200,
3159                 .uart_offset    = 8,
3160         },
3161         [pbn_b0_2_115200] = {
3162                 .flags          = FL_BASE0,
3163                 .num_ports      = 2,
3164                 .base_baud      = 115200,
3165                 .uart_offset    = 8,
3166         },
3167         [pbn_b0_4_115200] = {
3168                 .flags          = FL_BASE0,
3169                 .num_ports      = 4,
3170                 .base_baud      = 115200,
3171                 .uart_offset    = 8,
3172         },
3173         [pbn_b0_5_115200] = {
3174                 .flags          = FL_BASE0,
3175                 .num_ports      = 5,
3176                 .base_baud      = 115200,
3177                 .uart_offset    = 8,
3178         },
3179         [pbn_b0_8_115200] = {
3180                 .flags          = FL_BASE0,
3181                 .num_ports      = 8,
3182                 .base_baud      = 115200,
3183                 .uart_offset    = 8,
3184         },
3185         [pbn_b0_1_921600] = {
3186                 .flags          = FL_BASE0,
3187                 .num_ports      = 1,
3188                 .base_baud      = 921600,
3189                 .uart_offset    = 8,
3190         },
3191         [pbn_b0_2_921600] = {
3192                 .flags          = FL_BASE0,
3193                 .num_ports      = 2,
3194                 .base_baud      = 921600,
3195                 .uart_offset    = 8,
3196         },
3197         [pbn_b0_4_921600] = {
3198                 .flags          = FL_BASE0,
3199                 .num_ports      = 4,
3200                 .base_baud      = 921600,
3201                 .uart_offset    = 8,
3202         },
3203
3204         [pbn_b0_2_1130000] = {
3205                 .flags          = FL_BASE0,
3206                 .num_ports      = 2,
3207                 .base_baud      = 1130000,
3208                 .uart_offset    = 8,
3209         },
3210
3211         [pbn_b0_4_1152000] = {
3212                 .flags          = FL_BASE0,
3213                 .num_ports      = 4,
3214                 .base_baud      = 1152000,
3215                 .uart_offset    = 8,
3216         },
3217
3218         [pbn_b0_2_1152000_200] = {
3219                 .flags          = FL_BASE0,
3220                 .num_ports      = 2,
3221                 .base_baud      = 1152000,
3222                 .uart_offset    = 0x200,
3223         },
3224
3225         [pbn_b0_4_1152000_200] = {
3226                 .flags          = FL_BASE0,
3227                 .num_ports      = 4,
3228                 .base_baud      = 1152000,
3229                 .uart_offset    = 0x200,
3230         },
3231
3232         [pbn_b0_8_1152000_200] = {
3233                 .flags          = FL_BASE0,
3234                 .num_ports      = 8,
3235                 .base_baud      = 1152000,
3236                 .uart_offset    = 0x200,
3237         },
3238
3239         [pbn_b0_2_1843200] = {
3240                 .flags          = FL_BASE0,
3241                 .num_ports      = 2,
3242                 .base_baud      = 1843200,
3243                 .uart_offset    = 8,
3244         },
3245         [pbn_b0_4_1843200] = {
3246                 .flags          = FL_BASE0,
3247                 .num_ports      = 4,
3248                 .base_baud      = 1843200,
3249                 .uart_offset    = 8,
3250         },
3251
3252         [pbn_b0_2_1843200_200] = {
3253                 .flags          = FL_BASE0,
3254                 .num_ports      = 2,
3255                 .base_baud      = 1843200,
3256                 .uart_offset    = 0x200,
3257         },
3258         [pbn_b0_4_1843200_200] = {
3259                 .flags          = FL_BASE0,
3260                 .num_ports      = 4,
3261                 .base_baud      = 1843200,
3262                 .uart_offset    = 0x200,
3263         },
3264         [pbn_b0_8_1843200_200] = {
3265                 .flags          = FL_BASE0,
3266                 .num_ports      = 8,
3267                 .base_baud      = 1843200,
3268                 .uart_offset    = 0x200,
3269         },
3270         [pbn_b0_1_4000000] = {
3271                 .flags          = FL_BASE0,
3272                 .num_ports      = 1,
3273                 .base_baud      = 4000000,
3274                 .uart_offset    = 8,
3275         },
3276
3277         [pbn_b0_bt_1_115200] = {
3278                 .flags          = FL_BASE0|FL_BASE_BARS,
3279                 .num_ports      = 1,
3280                 .base_baud      = 115200,
3281                 .uart_offset    = 8,
3282         },
3283         [pbn_b0_bt_2_115200] = {
3284                 .flags          = FL_BASE0|FL_BASE_BARS,
3285                 .num_ports      = 2,
3286                 .base_baud      = 115200,
3287                 .uart_offset    = 8,
3288         },
3289         [pbn_b0_bt_4_115200] = {
3290                 .flags          = FL_BASE0|FL_BASE_BARS,
3291                 .num_ports      = 4,
3292                 .base_baud      = 115200,
3293                 .uart_offset    = 8,
3294         },
3295         [pbn_b0_bt_8_115200] = {
3296                 .flags          = FL_BASE0|FL_BASE_BARS,
3297                 .num_ports      = 8,
3298                 .base_baud      = 115200,
3299                 .uart_offset    = 8,
3300         },
3301
3302         [pbn_b0_bt_1_460800] = {
3303                 .flags          = FL_BASE0|FL_BASE_BARS,
3304                 .num_ports      = 1,
3305                 .base_baud      = 460800,
3306                 .uart_offset    = 8,
3307         },
3308         [pbn_b0_bt_2_460800] = {
3309                 .flags          = FL_BASE0|FL_BASE_BARS,
3310                 .num_ports      = 2,
3311                 .base_baud      = 460800,
3312                 .uart_offset    = 8,
3313         },
3314         [pbn_b0_bt_4_460800] = {
3315                 .flags          = FL_BASE0|FL_BASE_BARS,
3316                 .num_ports      = 4,
3317                 .base_baud      = 460800,
3318                 .uart_offset    = 8,
3319         },
3320
3321         [pbn_b0_bt_1_921600] = {
3322                 .flags          = FL_BASE0|FL_BASE_BARS,
3323                 .num_ports      = 1,
3324                 .base_baud      = 921600,
3325                 .uart_offset    = 8,
3326         },
3327         [pbn_b0_bt_2_921600] = {
3328                 .flags          = FL_BASE0|FL_BASE_BARS,
3329                 .num_ports      = 2,
3330                 .base_baud      = 921600,
3331                 .uart_offset    = 8,
3332         },
3333         [pbn_b0_bt_4_921600] = {
3334                 .flags          = FL_BASE0|FL_BASE_BARS,
3335                 .num_ports      = 4,
3336                 .base_baud      = 921600,
3337                 .uart_offset    = 8,
3338         },
3339         [pbn_b0_bt_8_921600] = {
3340                 .flags          = FL_BASE0|FL_BASE_BARS,
3341                 .num_ports      = 8,
3342                 .base_baud      = 921600,
3343                 .uart_offset    = 8,
3344         },
3345
3346         [pbn_b1_1_115200] = {
3347                 .flags          = FL_BASE1,
3348                 .num_ports      = 1,
3349                 .base_baud      = 115200,
3350                 .uart_offset    = 8,
3351         },
3352         [pbn_b1_2_115200] = {
3353                 .flags          = FL_BASE1,
3354                 .num_ports      = 2,
3355                 .base_baud      = 115200,
3356                 .uart_offset    = 8,
3357         },
3358         [pbn_b1_4_115200] = {
3359                 .flags          = FL_BASE1,
3360                 .num_ports      = 4,
3361                 .base_baud      = 115200,
3362                 .uart_offset    = 8,
3363         },
3364         [pbn_b1_8_115200] = {
3365                 .flags          = FL_BASE1,
3366                 .num_ports      = 8,
3367                 .base_baud      = 115200,
3368                 .uart_offset    = 8,
3369         },
3370         [pbn_b1_16_115200] = {
3371                 .flags          = FL_BASE1,
3372                 .num_ports      = 16,
3373                 .base_baud      = 115200,
3374                 .uart_offset    = 8,
3375         },
3376
3377         [pbn_b1_1_921600] = {
3378                 .flags          = FL_BASE1,
3379                 .num_ports      = 1,
3380                 .base_baud      = 921600,
3381                 .uart_offset    = 8,
3382         },
3383         [pbn_b1_2_921600] = {
3384                 .flags          = FL_BASE1,
3385                 .num_ports      = 2,
3386                 .base_baud      = 921600,
3387                 .uart_offset    = 8,
3388         },
3389         [pbn_b1_4_921600] = {
3390                 .flags          = FL_BASE1,
3391                 .num_ports      = 4,
3392                 .base_baud      = 921600,
3393                 .uart_offset    = 8,
3394         },
3395         [pbn_b1_8_921600] = {
3396                 .flags          = FL_BASE1,
3397                 .num_ports      = 8,
3398                 .base_baud      = 921600,
3399                 .uart_offset    = 8,
3400         },
3401         [pbn_b1_2_1250000] = {
3402                 .flags          = FL_BASE1,
3403                 .num_ports      = 2,
3404                 .base_baud      = 1250000,
3405                 .uart_offset    = 8,
3406         },
3407
3408         [pbn_b1_bt_1_115200] = {
3409                 .flags          = FL_BASE1|FL_BASE_BARS,
3410                 .num_ports      = 1,
3411                 .base_baud      = 115200,
3412                 .uart_offset    = 8,
3413         },
3414         [pbn_b1_bt_2_115200] = {
3415                 .flags          = FL_BASE1|FL_BASE_BARS,
3416                 .num_ports      = 2,
3417                 .base_baud      = 115200,
3418                 .uart_offset    = 8,
3419         },
3420         [pbn_b1_bt_4_115200] = {
3421                 .flags          = FL_BASE1|FL_BASE_BARS,
3422                 .num_ports      = 4,
3423                 .base_baud      = 115200,
3424                 .uart_offset    = 8,
3425         },
3426
3427         [pbn_b1_bt_2_921600] = {
3428                 .flags          = FL_BASE1|FL_BASE_BARS,
3429                 .num_ports      = 2,
3430                 .base_baud      = 921600,
3431                 .uart_offset    = 8,
3432         },
3433
3434         [pbn_b1_1_1382400] = {
3435                 .flags          = FL_BASE1,
3436                 .num_ports      = 1,
3437                 .base_baud      = 1382400,
3438                 .uart_offset    = 8,
3439         },
3440         [pbn_b1_2_1382400] = {
3441                 .flags          = FL_BASE1,
3442                 .num_ports      = 2,
3443                 .base_baud      = 1382400,
3444                 .uart_offset    = 8,
3445         },
3446         [pbn_b1_4_1382400] = {
3447                 .flags          = FL_BASE1,
3448                 .num_ports      = 4,
3449                 .base_baud      = 1382400,
3450                 .uart_offset    = 8,
3451         },
3452         [pbn_b1_8_1382400] = {
3453                 .flags          = FL_BASE1,
3454                 .num_ports      = 8,
3455                 .base_baud      = 1382400,
3456                 .uart_offset    = 8,
3457         },
3458
3459         [pbn_b2_1_115200] = {
3460                 .flags          = FL_BASE2,
3461                 .num_ports      = 1,
3462                 .base_baud      = 115200,
3463                 .uart_offset    = 8,
3464         },
3465         [pbn_b2_2_115200] = {
3466                 .flags          = FL_BASE2,
3467                 .num_ports      = 2,
3468                 .base_baud      = 115200,
3469                 .uart_offset    = 8,
3470         },
3471         [pbn_b2_4_115200] = {
3472                 .flags          = FL_BASE2,
3473                 .num_ports      = 4,
3474                 .base_baud      = 115200,
3475                 .uart_offset    = 8,
3476         },
3477         [pbn_b2_8_115200] = {
3478                 .flags          = FL_BASE2,
3479                 .num_ports      = 8,
3480                 .base_baud      = 115200,
3481                 .uart_offset    = 8,
3482         },
3483
3484         [pbn_b2_1_460800] = {
3485                 .flags          = FL_BASE2,
3486                 .num_ports      = 1,
3487                 .base_baud      = 460800,
3488                 .uart_offset    = 8,
3489         },
3490         [pbn_b2_4_460800] = {
3491                 .flags          = FL_BASE2,
3492                 .num_ports      = 4,
3493                 .base_baud      = 460800,
3494                 .uart_offset    = 8,
3495         },
3496         [pbn_b2_8_460800] = {
3497                 .flags          = FL_BASE2,
3498                 .num_ports      = 8,
3499                 .base_baud      = 460800,
3500                 .uart_offset    = 8,
3501         },
3502         [pbn_b2_16_460800] = {
3503                 .flags          = FL_BASE2,
3504                 .num_ports      = 16,
3505                 .base_baud      = 460800,
3506                 .uart_offset    = 8,
3507          },
3508
3509         [pbn_b2_1_921600] = {
3510                 .flags          = FL_BASE2,
3511                 .num_ports      = 1,
3512                 .base_baud      = 921600,
3513                 .uart_offset    = 8,
3514         },
3515         [pbn_b2_4_921600] = {
3516                 .flags          = FL_BASE2,
3517                 .num_ports      = 4,
3518                 .base_baud      = 921600,
3519                 .uart_offset    = 8,
3520         },
3521         [pbn_b2_8_921600] = {
3522                 .flags          = FL_BASE2,
3523                 .num_ports      = 8,
3524                 .base_baud      = 921600,
3525                 .uart_offset    = 8,
3526         },
3527
3528         [pbn_b2_8_1152000] = {
3529                 .flags          = FL_BASE2,
3530                 .num_ports      = 8,
3531                 .base_baud      = 1152000,
3532                 .uart_offset    = 8,
3533         },
3534
3535         [pbn_b2_bt_1_115200] = {
3536                 .flags          = FL_BASE2|FL_BASE_BARS,
3537                 .num_ports      = 1,
3538                 .base_baud      = 115200,
3539                 .uart_offset    = 8,
3540         },
3541         [pbn_b2_bt_2_115200] = {
3542                 .flags          = FL_BASE2|FL_BASE_BARS,
3543                 .num_ports      = 2,
3544                 .base_baud      = 115200,
3545                 .uart_offset    = 8,
3546         },
3547         [pbn_b2_bt_4_115200] = {
3548                 .flags          = FL_BASE2|FL_BASE_BARS,
3549                 .num_ports      = 4,
3550                 .base_baud      = 115200,
3551                 .uart_offset    = 8,
3552         },
3553
3554         [pbn_b2_bt_2_921600] = {
3555                 .flags          = FL_BASE2|FL_BASE_BARS,
3556                 .num_ports      = 2,
3557                 .base_baud      = 921600,
3558                 .uart_offset    = 8,
3559         },
3560         [pbn_b2_bt_4_921600] = {
3561                 .flags          = FL_BASE2|FL_BASE_BARS,
3562                 .num_ports      = 4,
3563                 .base_baud      = 921600,
3564                 .uart_offset    = 8,
3565         },
3566
3567         [pbn_b3_2_115200] = {
3568                 .flags          = FL_BASE3,
3569                 .num_ports      = 2,
3570                 .base_baud      = 115200,
3571                 .uart_offset    = 8,
3572         },
3573         [pbn_b3_4_115200] = {
3574                 .flags          = FL_BASE3,
3575                 .num_ports      = 4,
3576                 .base_baud      = 115200,
3577                 .uart_offset    = 8,
3578         },
3579         [pbn_b3_8_115200] = {
3580                 .flags          = FL_BASE3,
3581                 .num_ports      = 8,
3582                 .base_baud      = 115200,
3583                 .uart_offset    = 8,
3584         },
3585
3586         [pbn_b4_bt_2_921600] = {
3587                 .flags          = FL_BASE4,
3588                 .num_ports      = 2,
3589                 .base_baud      = 921600,
3590                 .uart_offset    = 8,
3591         },
3592         [pbn_b4_bt_4_921600] = {
3593                 .flags          = FL_BASE4,
3594                 .num_ports      = 4,
3595                 .base_baud      = 921600,
3596                 .uart_offset    = 8,
3597         },
3598         [pbn_b4_bt_8_921600] = {
3599                 .flags          = FL_BASE4,
3600                 .num_ports      = 8,
3601                 .base_baud      = 921600,
3602                 .uart_offset    = 8,
3603         },
3604
3605         /*
3606          * Entries following this are board-specific.
3607          */
3608
3609         /*
3610          * Panacom - IOMEM
3611          */
3612         [pbn_panacom] = {
3613                 .flags          = FL_BASE2,
3614                 .num_ports      = 2,
3615                 .base_baud      = 921600,
3616                 .uart_offset    = 0x400,
3617                 .reg_shift      = 7,
3618         },
3619         [pbn_panacom2] = {
3620                 .flags          = FL_BASE2|FL_BASE_BARS,
3621                 .num_ports      = 2,
3622                 .base_baud      = 921600,
3623                 .uart_offset    = 0x400,
3624                 .reg_shift      = 7,
3625         },
3626         [pbn_panacom4] = {
3627                 .flags          = FL_BASE2|FL_BASE_BARS,
3628                 .num_ports      = 4,
3629                 .base_baud      = 921600,
3630                 .uart_offset    = 0x400,
3631                 .reg_shift      = 7,
3632         },
3633
3634         /* I think this entry is broken - the first_offset looks wrong --rmk */
3635         [pbn_plx_romulus] = {
3636                 .flags          = FL_BASE2,
3637                 .num_ports      = 4,
3638                 .base_baud      = 921600,
3639                 .uart_offset    = 8 << 2,
3640                 .reg_shift      = 2,
3641                 .first_offset   = 0x03,
3642         },
3643
3644         /*
3645          * EndRun Technologies
3646         * Uses the size of PCI Base region 0 to
3647         * signal now many ports are available
3648         * 2 port 952 Uart support
3649         */
3650         [pbn_endrun_2_4000000] = {
3651                 .flags          = FL_BASE0,
3652                 .num_ports      = 2,
3653                 .base_baud      = 4000000,
3654                 .uart_offset    = 0x200,
3655                 .first_offset   = 0x1000,
3656         },
3657
3658         /*
3659          * This board uses the size of PCI Base region 0 to
3660          * signal now many ports are available
3661          */
3662         [pbn_oxsemi] = {
3663                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3664                 .num_ports      = 32,
3665                 .base_baud      = 115200,
3666                 .uart_offset    = 8,
3667         },
3668         [pbn_oxsemi_1_4000000] = {
3669                 .flags          = FL_BASE0,
3670                 .num_ports      = 1,
3671                 .base_baud      = 4000000,
3672                 .uart_offset    = 0x200,
3673                 .first_offset   = 0x1000,
3674         },
3675         [pbn_oxsemi_2_4000000] = {
3676                 .flags          = FL_BASE0,
3677                 .num_ports      = 2,
3678                 .base_baud      = 4000000,
3679                 .uart_offset    = 0x200,
3680                 .first_offset   = 0x1000,
3681         },
3682         [pbn_oxsemi_4_4000000] = {
3683                 .flags          = FL_BASE0,
3684                 .num_ports      = 4,
3685                 .base_baud      = 4000000,
3686                 .uart_offset    = 0x200,
3687                 .first_offset   = 0x1000,
3688         },
3689         [pbn_oxsemi_8_4000000] = {
3690                 .flags          = FL_BASE0,
3691                 .num_ports      = 8,
3692                 .base_baud      = 4000000,
3693                 .uart_offset    = 0x200,
3694                 .first_offset   = 0x1000,
3695         },
3696
3697
3698         /*
3699          * EKF addition for i960 Boards form EKF with serial port.
3700          * Max 256 ports.
3701          */
3702         [pbn_intel_i960] = {
3703                 .flags          = FL_BASE0,
3704                 .num_ports      = 32,
3705                 .base_baud      = 921600,
3706                 .uart_offset    = 8 << 2,
3707                 .reg_shift      = 2,
3708                 .first_offset   = 0x10000,
3709         },
3710         [pbn_sgi_ioc3] = {
3711                 .flags          = FL_BASE0|FL_NOIRQ,
3712                 .num_ports      = 1,
3713                 .base_baud      = 458333,
3714                 .uart_offset    = 8,
3715                 .reg_shift      = 0,
3716                 .first_offset   = 0x20178,
3717         },
3718
3719         /*
3720          * Computone - uses IOMEM.
3721          */
3722         [pbn_computone_4] = {
3723                 .flags          = FL_BASE0,
3724                 .num_ports      = 4,
3725                 .base_baud      = 921600,
3726                 .uart_offset    = 0x40,
3727                 .reg_shift      = 2,
3728                 .first_offset   = 0x200,
3729         },
3730         [pbn_computone_6] = {
3731                 .flags          = FL_BASE0,
3732                 .num_ports      = 6,
3733                 .base_baud      = 921600,
3734                 .uart_offset    = 0x40,
3735                 .reg_shift      = 2,
3736                 .first_offset   = 0x200,
3737         },
3738         [pbn_computone_8] = {
3739                 .flags          = FL_BASE0,
3740                 .num_ports      = 8,
3741                 .base_baud      = 921600,
3742                 .uart_offset    = 0x40,
3743                 .reg_shift      = 2,
3744                 .first_offset   = 0x200,
3745         },
3746         [pbn_sbsxrsio] = {
3747                 .flags          = FL_BASE0,
3748                 .num_ports      = 8,
3749                 .base_baud      = 460800,
3750                 .uart_offset    = 256,
3751                 .reg_shift      = 4,
3752         },
3753         /*
3754          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3755          *  Only basic 16550A support.
3756          *  XR17C15[24] are not tested, but they should work.
3757          */
3758         [pbn_exar_XR17C152] = {
3759                 .flags          = FL_BASE0,
3760                 .num_ports      = 2,
3761                 .base_baud      = 921600,
3762                 .uart_offset    = 0x200,
3763         },
3764         [pbn_exar_XR17C154] = {
3765                 .flags          = FL_BASE0,
3766                 .num_ports      = 4,
3767                 .base_baud      = 921600,
3768                 .uart_offset    = 0x200,
3769         },
3770         [pbn_exar_XR17C158] = {
3771                 .flags          = FL_BASE0,
3772                 .num_ports      = 8,
3773                 .base_baud      = 921600,
3774                 .uart_offset    = 0x200,
3775         },
3776         [pbn_exar_XR17V352] = {
3777                 .flags          = FL_BASE0,
3778                 .num_ports      = 2,
3779                 .base_baud      = 7812500,
3780                 .uart_offset    = 0x400,
3781                 .reg_shift      = 0,
3782                 .first_offset   = 0,
3783         },
3784         [pbn_exar_XR17V354] = {
3785                 .flags          = FL_BASE0,
3786                 .num_ports      = 4,
3787                 .base_baud      = 7812500,
3788                 .uart_offset    = 0x400,
3789                 .reg_shift      = 0,
3790                 .first_offset   = 0,
3791         },
3792         [pbn_exar_XR17V358] = {
3793                 .flags          = FL_BASE0,
3794                 .num_ports      = 8,
3795                 .base_baud      = 7812500,
3796                 .uart_offset    = 0x400,
3797                 .reg_shift      = 0,
3798                 .first_offset   = 0,
3799         },
3800         [pbn_exar_XR17V4358] = {
3801                 .flags          = FL_BASE0,
3802                 .num_ports      = 12,
3803                 .base_baud      = 7812500,
3804                 .uart_offset    = 0x400,
3805                 .reg_shift      = 0,
3806                 .first_offset   = 0,
3807         },
3808         [pbn_exar_XR17V8358] = {
3809                 .flags          = FL_BASE0,
3810                 .num_ports      = 16,
3811                 .base_baud      = 7812500,
3812                 .uart_offset    = 0x400,
3813                 .reg_shift      = 0,
3814                 .first_offset   = 0,
3815         },
3816         [pbn_exar_ibm_saturn] = {
3817                 .flags          = FL_BASE0,
3818                 .num_ports      = 1,
3819                 .base_baud      = 921600,
3820                 .uart_offset    = 0x200,
3821         },
3822
3823         /*
3824          * PA Semi PWRficient PA6T-1682M on-chip UART
3825          */
3826         [pbn_pasemi_1682M] = {
3827                 .flags          = FL_BASE0,
3828                 .num_ports      = 1,
3829                 .base_baud      = 8333333,
3830         },
3831         /*
3832          * National Instruments 843x
3833          */
3834         [pbn_ni8430_16] = {
3835                 .flags          = FL_BASE0,
3836                 .num_ports      = 16,
3837                 .base_baud      = 3686400,
3838                 .uart_offset    = 0x10,
3839                 .first_offset   = 0x800,
3840         },
3841         [pbn_ni8430_8] = {
3842                 .flags          = FL_BASE0,
3843                 .num_ports      = 8,
3844                 .base_baud      = 3686400,
3845                 .uart_offset    = 0x10,
3846                 .first_offset   = 0x800,
3847         },
3848         [pbn_ni8430_4] = {
3849                 .flags          = FL_BASE0,
3850                 .num_ports      = 4,
3851                 .base_baud      = 3686400,
3852                 .uart_offset    = 0x10,
3853                 .first_offset   = 0x800,
3854         },
3855         [pbn_ni8430_2] = {
3856                 .flags          = FL_BASE0,
3857                 .num_ports      = 2,
3858                 .base_baud      = 3686400,
3859                 .uart_offset    = 0x10,
3860                 .first_offset   = 0x800,
3861         },
3862         /*
3863          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3864          */
3865         [pbn_ADDIDATA_PCIe_1_3906250] = {
3866                 .flags          = FL_BASE0,
3867                 .num_ports      = 1,
3868                 .base_baud      = 3906250,
3869                 .uart_offset    = 0x200,
3870                 .first_offset   = 0x1000,
3871         },
3872         [pbn_ADDIDATA_PCIe_2_3906250] = {
3873                 .flags          = FL_BASE0,
3874                 .num_ports      = 2,
3875                 .base_baud      = 3906250,
3876                 .uart_offset    = 0x200,
3877                 .first_offset   = 0x1000,
3878         },
3879         [pbn_ADDIDATA_PCIe_4_3906250] = {
3880                 .flags          = FL_BASE0,
3881                 .num_ports      = 4,
3882                 .base_baud      = 3906250,
3883                 .uart_offset    = 0x200,
3884                 .first_offset   = 0x1000,
3885         },
3886         [pbn_ADDIDATA_PCIe_8_3906250] = {
3887                 .flags          = FL_BASE0,
3888                 .num_ports      = 8,
3889                 .base_baud      = 3906250,
3890                 .uart_offset    = 0x200,
3891                 .first_offset   = 0x1000,
3892         },
3893         [pbn_ce4100_1_115200] = {
3894                 .flags          = FL_BASE_BARS,
3895                 .num_ports      = 2,
3896                 .base_baud      = 921600,
3897                 .reg_shift      = 2,
3898         },
3899         /*
3900          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3901          * but is overridden by byt_set_termios.
3902          */
3903         [pbn_byt] = {
3904                 .flags          = FL_BASE0,
3905                 .num_ports      = 1,
3906                 .base_baud      = 2764800,
3907                 .uart_offset    = 0x80,
3908                 .reg_shift      = 2,
3909         },
3910         [pbn_pnw] = {
3911                 .flags          = FL_BASE0,
3912                 .num_ports      = 1,
3913                 .base_baud      = 115200,
3914         },
3915         [pbn_tng] = {
3916                 .flags          = FL_BASE0,
3917                 .num_ports      = 1,
3918                 .base_baud      = 1843200,
3919         },
3920         [pbn_qrk] = {
3921                 .flags          = FL_BASE0,
3922                 .num_ports      = 1,
3923                 .base_baud      = 2764800,
3924                 .reg_shift      = 2,
3925         },
3926         [pbn_omegapci] = {
3927                 .flags          = FL_BASE0,
3928                 .num_ports      = 8,
3929                 .base_baud      = 115200,
3930                 .uart_offset    = 0x200,
3931         },
3932         [pbn_NETMOS9900_2s_115200] = {
3933                 .flags          = FL_BASE0,
3934                 .num_ports      = 2,
3935                 .base_baud      = 115200,
3936         },
3937         [pbn_brcm_trumanage] = {
3938                 .flags          = FL_BASE0,
3939                 .num_ports      = 1,
3940                 .reg_shift      = 2,
3941                 .base_baud      = 115200,
3942         },
3943         [pbn_fintek_4] = {
3944                 .num_ports      = 4,
3945                 .uart_offset    = 8,
3946                 .base_baud      = 115200,
3947                 .first_offset   = 0x40,
3948         },
3949         [pbn_fintek_8] = {
3950                 .num_ports      = 8,
3951                 .uart_offset    = 8,
3952                 .base_baud      = 115200,
3953                 .first_offset   = 0x40,
3954         },
3955         [pbn_fintek_12] = {
3956                 .num_ports      = 12,
3957                 .uart_offset    = 8,
3958                 .base_baud      = 115200,
3959                 .first_offset   = 0x40,
3960         },
3961         [pbn_wch384_4] = {
3962                 .flags          = FL_BASE0,
3963                 .num_ports      = 4,
3964                 .base_baud      = 115200,
3965                 .uart_offset    = 8,
3966                 .first_offset   = 0xC0,
3967         },
3968         /*
3969          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3970          */
3971         [pbn_pericom_PI7C9X7951] = {
3972                 .flags          = FL_BASE0,
3973                 .num_ports      = 1,
3974                 .base_baud      = 921600,
3975                 .uart_offset    = 0x8,
3976         },
3977         [pbn_pericom_PI7C9X7952] = {
3978                 .flags          = FL_BASE0,
3979                 .num_ports      = 2,
3980                 .base_baud      = 921600,
3981                 .uart_offset    = 0x8,
3982         },
3983         [pbn_pericom_PI7C9X7954] = {
3984                 .flags          = FL_BASE0,
3985                 .num_ports      = 4,
3986                 .base_baud      = 921600,
3987                 .uart_offset    = 0x8,
3988         },
3989         [pbn_pericom_PI7C9X7958] = {
3990                 .flags          = FL_BASE0,
3991                 .num_ports      = 8,
3992                 .base_baud      = 921600,
3993                 .uart_offset    = 0x8,
3994         },
3995 };
3996
3997 static const struct pci_device_id blacklist[] = {
3998         /* softmodems */
3999         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
4000         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
4001         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
4002
4003         /* multi-io cards handled by parport_serial */
4004         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
4005         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
4006         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
4007         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
4008 };
4009
4010 /*
4011  * Given a complete unknown PCI device, try to use some heuristics to
4012  * guess what the configuration might be, based on the pitiful PCI
4013  * serial specs.  Returns 0 on success, 1 on failure.
4014  */
4015 static int
4016 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4017 {
4018         const struct pci_device_id *bldev;
4019         int num_iomem, num_port, first_port = -1, i;
4020
4021         /*
4022          * If it is not a communications device or the programming
4023          * interface is greater than 6, give up.
4024          *
4025          * (Should we try to make guesses for multiport serial devices
4026          * later?)
4027          */
4028         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4029              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4030             (dev->class & 0xff) > 6)
4031                 return -ENODEV;
4032
4033         /*
4034          * Do not access blacklisted devices that are known not to
4035          * feature serial ports or are handled by other modules.
4036          */
4037         for (bldev = blacklist;
4038              bldev < blacklist + ARRAY_SIZE(blacklist);
4039              bldev++) {
4040                 if (dev->vendor == bldev->vendor &&
4041                     dev->device == bldev->device)
4042                         return -ENODEV;
4043         }
4044
4045         num_iomem = num_port = 0;
4046         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4047                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4048                         num_port++;
4049                         if (first_port == -1)
4050                                 first_port = i;
4051                 }
4052                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4053                         num_iomem++;
4054         }
4055
4056         /*
4057          * If there is 1 or 0 iomem regions, and exactly one port,
4058          * use it.  We guess the number of ports based on the IO
4059          * region size.
4060          */
4061         if (num_iomem <= 1 && num_port == 1) {
4062                 board->flags = first_port;
4063                 board->num_ports = pci_resource_len(dev, first_port) / 8;
4064                 return 0;
4065         }
4066
4067         /*
4068          * Now guess if we've got a board which indexes by BARs.
4069          * Each IO BAR should be 8 bytes, and they should follow
4070          * consecutively.
4071          */
4072         first_port = -1;
4073         num_port = 0;
4074         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4075                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4076                     pci_resource_len(dev, i) == 8 &&
4077                     (first_port == -1 || (first_port + num_port) == i)) {
4078                         num_port++;
4079                         if (first_port == -1)
4080                                 first_port = i;
4081                 }
4082         }
4083
4084         if (num_port > 1) {
4085                 board->flags = first_port | FL_BASE_BARS;
4086                 board->num_ports = num_port;
4087                 return 0;
4088         }
4089
4090         return -ENODEV;
4091 }
4092
4093 static inline int
4094 serial_pci_matches(const struct pciserial_board *board,
4095                    const struct pciserial_board *guessed)
4096 {
4097         return
4098             board->num_ports == guessed->num_ports &&
4099             board->base_baud == guessed->base_baud &&
4100             board->uart_offset == guessed->uart_offset &&
4101             board->reg_shift == guessed->reg_shift &&
4102             board->first_offset == guessed->first_offset;
4103 }
4104
4105 struct serial_private *
4106 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4107 {
4108         struct uart_8250_port uart;
4109         struct serial_private *priv;
4110         struct pci_serial_quirk *quirk;
4111         int rc, nr_ports, i;
4112
4113         nr_ports = board->num_ports;
4114
4115         /*
4116          * Find an init and setup quirks.
4117          */
4118         quirk = find_quirk(dev);
4119
4120         /*
4121          * Run the new-style initialization function.
4122          * The initialization function returns:
4123          *  <0  - error
4124          *   0  - use board->num_ports
4125          *  >0  - number of ports
4126          */
4127         if (quirk->init) {
4128                 rc = quirk->init(dev);
4129                 if (rc < 0) {
4130                         priv = ERR_PTR(rc);
4131                         goto err_out;
4132                 }
4133                 if (rc)
4134                         nr_ports = rc;
4135         }
4136
4137         priv = kzalloc(sizeof(struct serial_private) +
4138                        sizeof(unsigned int) * nr_ports,
4139                        GFP_KERNEL);
4140         if (!priv) {
4141                 priv = ERR_PTR(-ENOMEM);
4142                 goto err_deinit;
4143         }
4144
4145         priv->dev = dev;
4146         priv->quirk = quirk;
4147
4148         memset(&uart, 0, sizeof(uart));
4149         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4150         uart.port.uartclk = board->base_baud * 16;
4151         uart.port.irq = get_pci_irq(dev, board);
4152         uart.port.dev = &dev->dev;
4153
4154         for (i = 0; i < nr_ports; i++) {
4155                 if (quirk->setup(priv, board, &uart, i))
4156                         break;
4157
4158                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4159                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4160
4161                 priv->line[i] = serial8250_register_8250_port(&uart);
4162                 if (priv->line[i] < 0) {
4163                         dev_err(&dev->dev,
4164                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4165                                 uart.port.iobase, uart.port.irq,
4166                                 uart.port.iotype, priv->line[i]);
4167                         break;
4168                 }
4169         }
4170         priv->nr = i;
4171         return priv;
4172
4173 err_deinit:
4174         if (quirk->exit)
4175                 quirk->exit(dev);
4176 err_out:
4177         return priv;
4178 }
4179 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4180
4181 void pciserial_remove_ports(struct serial_private *priv)
4182 {
4183         struct pci_serial_quirk *quirk;
4184         int i;
4185
4186         for (i = 0; i < priv->nr; i++)
4187                 serial8250_unregister_port(priv->line[i]);
4188
4189         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4190                 if (priv->remapped_bar[i])
4191                         iounmap(priv->remapped_bar[i]);
4192                 priv->remapped_bar[i] = NULL;
4193         }
4194
4195         /*
4196          * Find the exit quirks.
4197          */
4198         quirk = find_quirk(priv->dev);
4199         if (quirk->exit)
4200                 quirk->exit(priv->dev);
4201
4202         kfree(priv);
4203 }
4204 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4205
4206 void pciserial_suspend_ports(struct serial_private *priv)
4207 {
4208         int i;
4209
4210         for (i = 0; i < priv->nr; i++)
4211                 if (priv->line[i] >= 0)
4212                         serial8250_suspend_port(priv->line[i]);
4213
4214         /*
4215          * Ensure that every init quirk is properly torn down
4216          */
4217         if (priv->quirk->exit)
4218                 priv->quirk->exit(priv->dev);
4219 }
4220 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4221
4222 void pciserial_resume_ports(struct serial_private *priv)
4223 {
4224         int i;
4225
4226         /*
4227          * Ensure that the board is correctly configured.
4228          */
4229         if (priv->quirk->init)
4230                 priv->quirk->init(priv->dev);
4231
4232         for (i = 0; i < priv->nr; i++)
4233                 if (priv->line[i] >= 0)
4234                         serial8250_resume_port(priv->line[i]);
4235 }
4236 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4237
4238 /*
4239  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4240  * to the arrangement of serial ports on a PCI card.
4241  */
4242 static int
4243 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4244 {
4245         struct pci_serial_quirk *quirk;
4246         struct serial_private *priv;
4247         const struct pciserial_board *board;
4248         struct pciserial_board tmp;
4249         int rc;
4250
4251         quirk = find_quirk(dev);
4252         if (quirk->probe) {
4253                 rc = quirk->probe(dev);
4254                 if (rc)
4255                         return rc;
4256         }
4257
4258         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4259                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4260                         ent->driver_data);
4261                 return -EINVAL;
4262         }
4263
4264         board = &pci_boards[ent->driver_data];
4265
4266         rc = pci_enable_device(dev);
4267         pci_save_state(dev);
4268         if (rc)
4269                 return rc;
4270
4271         if (ent->driver_data == pbn_default) {
4272                 /*
4273                  * Use a copy of the pci_board entry for this;
4274                  * avoid changing entries in the table.
4275                  */
4276                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4277                 board = &tmp;
4278
4279                 /*
4280                  * We matched one of our class entries.  Try to
4281                  * determine the parameters of this board.
4282                  */
4283                 rc = serial_pci_guess_board(dev, &tmp);
4284                 if (rc)
4285                         goto disable;
4286         } else {
4287                 /*
4288                  * We matched an explicit entry.  If we are able to
4289                  * detect this boards settings with our heuristic,
4290                  * then we no longer need this entry.
4291                  */
4292                 memcpy(&tmp, &pci_boards[pbn_default],
4293                        sizeof(struct pciserial_board));
4294                 rc = serial_pci_guess_board(dev, &tmp);
4295                 if (rc == 0 && serial_pci_matches(board, &tmp))
4296                         moan_device("Redundant entry in serial pci_table.",
4297                                     dev);
4298         }
4299
4300         priv = pciserial_init_ports(dev, board);
4301         if (!IS_ERR(priv)) {
4302                 pci_set_drvdata(dev, priv);
4303                 return 0;
4304         }
4305
4306         rc = PTR_ERR(priv);
4307
4308  disable:
4309         pci_disable_device(dev);
4310         return rc;
4311 }
4312
4313 static void pciserial_remove_one(struct pci_dev *dev)
4314 {
4315         struct serial_private *priv = pci_get_drvdata(dev);
4316
4317         pciserial_remove_ports(priv);
4318
4319         pci_disable_device(dev);
4320 }
4321
4322 #ifdef CONFIG_PM_SLEEP
4323 static int pciserial_suspend_one(struct device *dev)
4324 {
4325         struct pci_dev *pdev = to_pci_dev(dev);
4326         struct serial_private *priv = pci_get_drvdata(pdev);
4327
4328         if (priv)
4329                 pciserial_suspend_ports(priv);
4330
4331         return 0;
4332 }
4333
4334 static int pciserial_resume_one(struct device *dev)
4335 {
4336         struct pci_dev *pdev = to_pci_dev(dev);
4337         struct serial_private *priv = pci_get_drvdata(pdev);
4338         int err;
4339
4340         if (priv) {
4341                 /*
4342                  * The device may have been disabled.  Re-enable it.
4343                  */
4344                 err = pci_enable_device(pdev);
4345                 /* FIXME: We cannot simply error out here */
4346                 if (err)
4347                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4348                 pciserial_resume_ports(priv);
4349         }
4350         return 0;
4351 }
4352 #endif
4353
4354 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4355                          pciserial_resume_one);
4356
4357 static struct pci_device_id serial_pci_tbl[] = {
4358         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4359         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4360                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4361                 pbn_b2_8_921600 },
4362         /* Advantech also use 0x3618 and 0xf618 */
4363         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4364                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4365                 pbn_b0_4_921600 },
4366         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4367                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4368                 pbn_b0_4_921600 },
4369         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4370                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4371                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4372                 pbn_b1_8_1382400 },
4373         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4374                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4375                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4376                 pbn_b1_4_1382400 },
4377         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4378                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4379                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4380                 pbn_b1_2_1382400 },
4381         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4382                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4383                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4384                 pbn_b1_8_1382400 },
4385         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4386                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4387                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4388                 pbn_b1_4_1382400 },
4389         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4390                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4391                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4392                 pbn_b1_2_1382400 },
4393         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4394                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4395                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4396                 pbn_b1_8_921600 },
4397         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4398                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4399                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4400                 pbn_b1_8_921600 },
4401         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4402                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4403                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4404                 pbn_b1_4_921600 },
4405         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4406                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4407                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4408                 pbn_b1_4_921600 },
4409         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4410                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4411                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4412                 pbn_b1_2_921600 },
4413         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4414                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4415                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4416                 pbn_b1_8_921600 },
4417         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4418                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4419                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4420                 pbn_b1_8_921600 },
4421         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4422                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4423                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4424                 pbn_b1_4_921600 },
4425         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4426                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4427                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4428                 pbn_b1_2_1250000 },
4429         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4430                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4431                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4432                 pbn_b0_2_1843200 },
4433         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4434                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4435                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4436                 pbn_b0_4_1843200 },
4437         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4438                 PCI_VENDOR_ID_AFAVLAB,
4439                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4440                 pbn_b0_4_1152000 },
4441         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4442                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4443                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4444                 pbn_b0_2_1843200_200 },
4445         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4446                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4447                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4448                 pbn_b0_4_1843200_200 },
4449         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4450                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4451                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4452                 pbn_b0_8_1843200_200 },
4453         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4454                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4455                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4456                 pbn_b0_2_1843200_200 },
4457         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4458                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4459                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4460                 pbn_b0_4_1843200_200 },
4461         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4462                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4463                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4464                 pbn_b0_8_1843200_200 },
4465         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4466                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4467                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4468                 pbn_b0_2_1843200_200 },
4469         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4470                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4471                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4472                 pbn_b0_4_1843200_200 },
4473         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4474                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4475                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4476                 pbn_b0_8_1843200_200 },
4477         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4478                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4479                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4480                 pbn_b0_2_1843200_200 },
4481         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4482                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4483                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4484                 pbn_b0_4_1843200_200 },
4485         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4486                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4487                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4488                 pbn_b0_8_1843200_200 },
4489         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4490                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4491                 0, 0, pbn_exar_ibm_saturn },
4492
4493         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495                 pbn_b2_bt_1_115200 },
4496         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498                 pbn_b2_bt_2_115200 },
4499         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501                 pbn_b2_bt_4_115200 },
4502         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504                 pbn_b2_bt_2_115200 },
4505         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507                 pbn_b2_bt_4_115200 },
4508         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510                 pbn_b2_8_115200 },
4511         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513                 pbn_b2_8_460800 },
4514         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516                 pbn_b2_8_115200 },
4517
4518         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520                 pbn_b2_bt_2_115200 },
4521         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4522                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523                 pbn_b2_bt_2_921600 },
4524         /*
4525          * VScom SPCOM800, from sl@s.pl
4526          */
4527         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529                 pbn_b2_8_921600 },
4530         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532                 pbn_b2_4_921600 },
4533         /* Unknown card - subdevice 0x1584 */
4534         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4535                 PCI_VENDOR_ID_PLX,
4536                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4537                 pbn_b2_4_115200 },
4538         /* Unknown card - subdevice 0x1588 */
4539         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4540                 PCI_VENDOR_ID_PLX,
4541                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4542                 pbn_b2_8_115200 },
4543         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4544                 PCI_SUBVENDOR_ID_KEYSPAN,
4545                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4546                 pbn_panacom },
4547         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549                 pbn_panacom4 },
4550         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552                 pbn_panacom2 },
4553         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4554                 PCI_VENDOR_ID_ESDGMBH,
4555                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4556                 pbn_b2_4_115200 },
4557         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4558                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4559                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4560                 pbn_b2_4_460800 },
4561         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4562                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4563                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4564                 pbn_b2_8_460800 },
4565         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4566                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4567                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4568                 pbn_b2_16_460800 },
4569         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4570                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4571                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4572                 pbn_b2_16_460800 },
4573         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4574                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4575                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4576                 pbn_b2_4_460800 },
4577         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4578                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4579                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4580                 pbn_b2_8_460800 },
4581         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4582                 PCI_SUBVENDOR_ID_EXSYS,
4583                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4584                 pbn_b2_4_115200 },
4585         /*
4586          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4587          * (Exoray@isys.ca)
4588          */
4589         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4590                 0x10b5, 0x106a, 0, 0,
4591                 pbn_plx_romulus },
4592         /*
4593         * EndRun Technologies. PCI express device range.
4594         *    EndRun PTP/1588 has 2 Native UARTs.
4595         */
4596         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598                 pbn_endrun_2_4000000 },
4599         /*
4600          * Quatech cards. These actually have configurable clocks but for
4601          * now we just use the default.
4602          *
4603          * 100 series are RS232, 200 series RS422,
4604          */
4605         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4606                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607                 pbn_b1_4_115200 },
4608         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610                 pbn_b1_2_115200 },
4611         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613                 pbn_b2_2_115200 },
4614         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616                 pbn_b1_2_115200 },
4617         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619                 pbn_b2_2_115200 },
4620         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622                 pbn_b1_4_115200 },
4623         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625                 pbn_b1_8_115200 },
4626         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4627                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628                 pbn_b1_8_115200 },
4629         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4630                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631                 pbn_b1_4_115200 },
4632         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4633                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634                 pbn_b1_2_115200 },
4635         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4636                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637                 pbn_b1_4_115200 },
4638         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4639                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640                 pbn_b1_2_115200 },
4641         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4642                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643                 pbn_b2_4_115200 },
4644         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646                 pbn_b2_2_115200 },
4647         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649                 pbn_b2_1_115200 },
4650         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652                 pbn_b2_4_115200 },
4653         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655                 pbn_b2_2_115200 },
4656         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658                 pbn_b2_1_115200 },
4659         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661                 pbn_b0_8_115200 },
4662
4663         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4664                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4665                 0, 0,
4666                 pbn_b0_4_921600 },
4667         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4668                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4669                 0, 0,
4670                 pbn_b0_4_1152000 },
4671         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4672                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673                 pbn_b0_bt_2_921600 },
4674
4675                 /*
4676                  * The below card is a little controversial since it is the
4677                  * subject of a PCI vendor/device ID clash.  (See
4678                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4679                  * For now just used the hex ID 0x950a.
4680                  */
4681         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4682                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4683                 0, 0, pbn_b0_2_115200 },
4684         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4685                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4686                 0, 0, pbn_b0_2_115200 },
4687         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689                 pbn_b0_2_1130000 },
4690         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4691                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4692                 pbn_b0_1_921600 },
4693         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695                 pbn_b0_4_115200 },
4696         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698                 pbn_b0_bt_2_921600 },
4699         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4700                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4701                 pbn_b2_8_1152000 },
4702
4703         /*
4704          * Oxford Semiconductor Inc. Tornado PCI express device range.
4705          */
4706         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708                 pbn_b0_1_4000000 },
4709         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711                 pbn_b0_1_4000000 },
4712         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4713                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714                 pbn_oxsemi_1_4000000 },
4715         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4716                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717                 pbn_oxsemi_1_4000000 },
4718         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4719                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720                 pbn_b0_1_4000000 },
4721         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4722                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723                 pbn_b0_1_4000000 },
4724         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726                 pbn_oxsemi_1_4000000 },
4727         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729                 pbn_oxsemi_1_4000000 },
4730         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732                 pbn_b0_1_4000000 },
4733         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735                 pbn_b0_1_4000000 },
4736         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738                 pbn_b0_1_4000000 },
4739         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741                 pbn_b0_1_4000000 },
4742         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4743                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744                 pbn_oxsemi_2_4000000 },
4745         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747                 pbn_oxsemi_2_4000000 },
4748         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750                 pbn_oxsemi_4_4000000 },
4751         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753                 pbn_oxsemi_4_4000000 },
4754         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756                 pbn_oxsemi_8_4000000 },
4757         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759                 pbn_oxsemi_8_4000000 },
4760         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762                 pbn_oxsemi_1_4000000 },
4763         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765                 pbn_oxsemi_1_4000000 },
4766         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768                 pbn_oxsemi_1_4000000 },
4769         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771                 pbn_oxsemi_1_4000000 },
4772         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774                 pbn_oxsemi_1_4000000 },
4775         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777                 pbn_oxsemi_1_4000000 },
4778         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780                 pbn_oxsemi_1_4000000 },
4781         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783                 pbn_oxsemi_1_4000000 },
4784         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4785                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786                 pbn_oxsemi_1_4000000 },
4787         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4788                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789                 pbn_oxsemi_1_4000000 },
4790         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4791                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792                 pbn_oxsemi_1_4000000 },
4793         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795                 pbn_oxsemi_1_4000000 },
4796         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798                 pbn_oxsemi_1_4000000 },
4799         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801                 pbn_oxsemi_1_4000000 },
4802         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804                 pbn_oxsemi_1_4000000 },
4805         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4806                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807                 pbn_oxsemi_1_4000000 },
4808         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810                 pbn_oxsemi_1_4000000 },
4811         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4812                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813                 pbn_oxsemi_1_4000000 },
4814         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4815                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816                 pbn_oxsemi_1_4000000 },
4817         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4818                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819                 pbn_oxsemi_1_4000000 },
4820         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4821                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822                 pbn_oxsemi_1_4000000 },
4823         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4824                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825                 pbn_oxsemi_1_4000000 },
4826         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4827                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828                 pbn_oxsemi_1_4000000 },
4829         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831                 pbn_oxsemi_1_4000000 },
4832         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4833                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834                 pbn_oxsemi_1_4000000 },
4835         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837                 pbn_oxsemi_1_4000000 },
4838         /*
4839          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4840          */
4841         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4842                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4843                 pbn_oxsemi_1_4000000 },
4844         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4845                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4846                 pbn_oxsemi_2_4000000 },
4847         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4848                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4849                 pbn_oxsemi_4_4000000 },
4850         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4851                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4852                 pbn_oxsemi_8_4000000 },
4853
4854         /*
4855          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4856          */
4857         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4858                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4859                 pbn_oxsemi_2_4000000 },
4860
4861         /*
4862          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4863          * from skokodyn@yahoo.com
4864          */
4865         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4866                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4867                 pbn_sbsxrsio },
4868         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4869                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4870                 pbn_sbsxrsio },
4871         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4872                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4873                 pbn_sbsxrsio },
4874         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4875                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4876                 pbn_sbsxrsio },
4877
4878         /*
4879          * Digitan DS560-558, from jimd@esoft.com
4880          */
4881         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4882                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883                 pbn_b1_1_115200 },
4884
4885         /*
4886          * Titan Electronic cards
4887          *  The 400L and 800L have a custom setup quirk.
4888          */
4889         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891                 pbn_b0_1_921600 },
4892         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894                 pbn_b0_2_921600 },
4895         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897                 pbn_b0_4_921600 },
4898         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900                 pbn_b0_4_921600 },
4901         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903                 pbn_b1_1_921600 },
4904         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906                 pbn_b1_bt_2_921600 },
4907         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909                 pbn_b0_bt_4_921600 },
4910         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912                 pbn_b0_bt_8_921600 },
4913         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915                 pbn_b4_bt_2_921600 },
4916         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918                 pbn_b4_bt_4_921600 },
4919         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921                 pbn_b4_bt_8_921600 },
4922         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924                 pbn_b0_4_921600 },
4925         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927                 pbn_b0_4_921600 },
4928         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930                 pbn_b0_4_921600 },
4931         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933                 pbn_oxsemi_1_4000000 },
4934         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936                 pbn_oxsemi_2_4000000 },
4937         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939                 pbn_oxsemi_4_4000000 },
4940         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942                 pbn_oxsemi_8_4000000 },
4943         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945                 pbn_oxsemi_2_4000000 },
4946         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948                 pbn_oxsemi_2_4000000 },
4949         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951                 pbn_b0_bt_2_921600 },
4952         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954                 pbn_b0_4_921600 },
4955         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957                 pbn_b0_4_921600 },
4958         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960                 pbn_b0_4_921600 },
4961         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963                 pbn_b0_4_921600 },
4964
4965         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967                 pbn_b2_1_460800 },
4968         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970                 pbn_b2_1_460800 },
4971         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973                 pbn_b2_1_460800 },
4974         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976                 pbn_b2_bt_2_921600 },
4977         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979                 pbn_b2_bt_2_921600 },
4980         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982                 pbn_b2_bt_2_921600 },
4983         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985                 pbn_b2_bt_4_921600 },
4986         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988                 pbn_b2_bt_4_921600 },
4989         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4991                 pbn_b2_bt_4_921600 },
4992         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4994                 pbn_b0_1_921600 },
4995         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4997                 pbn_b0_1_921600 },
4998         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000                 pbn_b0_1_921600 },
5001         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
5002                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003                 pbn_b0_bt_2_921600 },
5004         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
5005                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006                 pbn_b0_bt_2_921600 },
5007         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
5008                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5009                 pbn_b0_bt_2_921600 },
5010         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
5011                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012                 pbn_b0_bt_4_921600 },
5013         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
5014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015                 pbn_b0_bt_4_921600 },
5016         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018                 pbn_b0_bt_4_921600 },
5019         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021                 pbn_b0_bt_8_921600 },
5022         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5023                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5024                 pbn_b0_bt_8_921600 },
5025         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5026                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027                 pbn_b0_bt_8_921600 },
5028
5029         /*
5030          * Computone devices submitted by Doug McNash dmcnash@computone.com
5031          */
5032         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5033                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5034                 0, 0, pbn_computone_4 },
5035         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5036                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5037                 0, 0, pbn_computone_8 },
5038         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5039                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5040                 0, 0, pbn_computone_6 },
5041
5042         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5043                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044                 pbn_oxsemi },
5045         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5046                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5047                 pbn_b0_bt_1_921600 },
5048
5049         /*
5050          * SUNIX (TIMEDIA)
5051          */
5052         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5053                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5054                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
5055                 pbn_b0_bt_1_921600 },
5056
5057         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5058                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5059                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5060                 pbn_b0_bt_1_921600 },
5061
5062         /*
5063          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5064          */
5065         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5066                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5067                 pbn_b0_bt_8_115200 },
5068         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5069                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5070                 pbn_b0_bt_8_115200 },
5071
5072         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5074                 pbn_b0_bt_2_115200 },
5075         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077                 pbn_b0_bt_2_115200 },
5078         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080                 pbn_b0_bt_2_115200 },
5081         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
5082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083                 pbn_b0_bt_2_115200 },
5084         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
5085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5086                 pbn_b0_bt_2_115200 },
5087         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089                 pbn_b0_bt_4_460800 },
5090         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092                 pbn_b0_bt_4_460800 },
5093         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095                 pbn_b0_bt_2_460800 },
5096         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098                 pbn_b0_bt_2_460800 },
5099         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101                 pbn_b0_bt_2_460800 },
5102         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5104                 pbn_b0_bt_1_115200 },
5105         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5107                 pbn_b0_bt_1_460800 },
5108
5109         /*
5110          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5111          * Cards are identified by their subsystem vendor IDs, which
5112          * (in hex) match the model number.
5113          *
5114          * Note that JC140x are RS422/485 cards which require ox950
5115          * ACR = 0x10, and as such are not currently fully supported.
5116          */
5117         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5118                 0x1204, 0x0004, 0, 0,
5119                 pbn_b0_4_921600 },
5120         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5121                 0x1208, 0x0004, 0, 0,
5122                 pbn_b0_4_921600 },
5123 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5124                 0x1402, 0x0002, 0, 0,
5125                 pbn_b0_2_921600 }, */
5126 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5127                 0x1404, 0x0004, 0, 0,
5128                 pbn_b0_4_921600 }, */
5129         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5130                 0x1208, 0x0004, 0, 0,
5131                 pbn_b0_4_921600 },
5132
5133         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5134                 0x1204, 0x0004, 0, 0,
5135                 pbn_b0_4_921600 },
5136         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5137                 0x1208, 0x0004, 0, 0,
5138                 pbn_b0_4_921600 },
5139         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5140                 0x1208, 0x0004, 0, 0,
5141                 pbn_b0_4_921600 },
5142         /*
5143          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5144          */
5145         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5146                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5147                 pbn_b1_1_1382400 },
5148
5149         /*
5150          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5151          */
5152         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154                 pbn_b1_1_1382400 },
5155
5156         /*
5157          * RAStel 2 port modem, gerg@moreton.com.au
5158          */
5159         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5161                 pbn_b2_bt_2_115200 },
5162
5163         /*
5164          * EKF addition for i960 Boards form EKF with serial port
5165          */
5166         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5167                 0xE4BF, PCI_ANY_ID, 0, 0,
5168                 pbn_intel_i960 },
5169
5170         /*
5171          * Xircom Cardbus/Ethernet combos
5172          */
5173         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5175                 pbn_b0_1_115200 },
5176         /*
5177          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5178          */
5179         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181                 pbn_b0_1_115200 },
5182
5183         /*
5184          * Untested PCI modems, sent in from various folks...
5185          */
5186
5187         /*
5188          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5189          */
5190         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5191                 0x1048, 0x1500, 0, 0,
5192                 pbn_b1_1_115200 },
5193
5194         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5195                 0xFF00, 0, 0, 0,
5196                 pbn_sgi_ioc3 },
5197
5198         /*
5199          * HP Diva card
5200          */
5201         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5202                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5203                 pbn_b1_1_115200 },
5204         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206                 pbn_b0_5_115200 },
5207         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209                 pbn_b2_1_115200 },
5210
5211         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5213                 pbn_b3_2_115200 },
5214         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5216                 pbn_b3_4_115200 },
5217         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5219                 pbn_b3_8_115200 },
5220
5221         /*
5222          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5223          */
5224         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5225                 PCI_ANY_ID, PCI_ANY_ID,
5226                 0,
5227                 0, pbn_exar_XR17C152 },
5228         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5229                 PCI_ANY_ID, PCI_ANY_ID,
5230                 0,
5231                 0, pbn_exar_XR17C154 },
5232         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5233                 PCI_ANY_ID, PCI_ANY_ID,
5234                 0,
5235                 0, pbn_exar_XR17C158 },
5236         /*
5237          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5238          */
5239         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5240                 PCI_ANY_ID, PCI_ANY_ID,
5241                 0,
5242                 0, pbn_exar_XR17V352 },
5243         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5244                 PCI_ANY_ID, PCI_ANY_ID,
5245                 0,
5246                 0, pbn_exar_XR17V354 },
5247         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5248                 PCI_ANY_ID, PCI_ANY_ID,
5249                 0,
5250                 0, pbn_exar_XR17V358 },
5251         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5252                 PCI_ANY_ID, PCI_ANY_ID,
5253                 0,
5254                 0, pbn_exar_XR17V4358 },
5255         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5256                 PCI_ANY_ID, PCI_ANY_ID,
5257                 0,
5258                 0, pbn_exar_XR17V8358 },
5259         /*
5260          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5261          */
5262         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5263                 PCI_ANY_ID, PCI_ANY_ID,
5264                 0,
5265                 0, pbn_pericom_PI7C9X7951 },
5266         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5267                 PCI_ANY_ID, PCI_ANY_ID,
5268                 0,
5269                 0, pbn_pericom_PI7C9X7952 },
5270         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5271                 PCI_ANY_ID, PCI_ANY_ID,
5272                 0,
5273                 0, pbn_pericom_PI7C9X7954 },
5274         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5275                 PCI_ANY_ID, PCI_ANY_ID,
5276                 0,
5277                 0, pbn_pericom_PI7C9X7958 },
5278         /*
5279          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5280          */
5281         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5283                 pbn_b0_1_115200 },
5284         /*
5285          * ITE
5286          */
5287         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5288                 PCI_ANY_ID, PCI_ANY_ID,
5289                 0, 0,
5290                 pbn_b1_bt_1_115200 },
5291
5292         /*
5293          * IntaShield IS-200
5294          */
5295         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5297                 pbn_b2_2_115200 },
5298         /*
5299          * IntaShield IS-400
5300          */
5301         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5303                 pbn_b2_4_115200 },
5304         /*
5305          * Perle PCI-RAS cards
5306          */
5307         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5308                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5309                 0, 0, pbn_b2_4_921600 },
5310         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5311                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5312                 0, 0, pbn_b2_8_921600 },
5313
5314         /*
5315          * Mainpine series cards: Fairly standard layout but fools
5316          * parts of the autodetect in some cases and uses otherwise
5317          * unmatched communications subclasses in the PCI Express case
5318          */
5319
5320         {       /* RockForceDUO */
5321                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5322                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5323                 0, 0, pbn_b0_2_115200 },
5324         {       /* RockForceQUATRO */
5325                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5326                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5327                 0, 0, pbn_b0_4_115200 },
5328         {       /* RockForceDUO+ */
5329                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5330                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5331                 0, 0, pbn_b0_2_115200 },
5332         {       /* RockForceQUATRO+ */
5333                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5334                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5335                 0, 0, pbn_b0_4_115200 },
5336         {       /* RockForce+ */
5337                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5338                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5339                 0, 0, pbn_b0_2_115200 },
5340         {       /* RockForce+ */
5341                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5342                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5343                 0, 0, pbn_b0_4_115200 },
5344         {       /* RockForceOCTO+ */
5345                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5346                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5347                 0, 0, pbn_b0_8_115200 },
5348         {       /* RockForceDUO+ */
5349                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5350                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5351                 0, 0, pbn_b0_2_115200 },
5352         {       /* RockForceQUARTRO+ */
5353                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5354                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5355                 0, 0, pbn_b0_4_115200 },
5356         {       /* RockForceOCTO+ */
5357                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5358                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5359                 0, 0, pbn_b0_8_115200 },
5360         {       /* RockForceD1 */
5361                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5362                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5363                 0, 0, pbn_b0_1_115200 },
5364         {       /* RockForceF1 */
5365                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5366                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5367                 0, 0, pbn_b0_1_115200 },
5368         {       /* RockForceD2 */
5369                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5370                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5371                 0, 0, pbn_b0_2_115200 },
5372         {       /* RockForceF2 */
5373                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5374                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5375                 0, 0, pbn_b0_2_115200 },
5376         {       /* RockForceD4 */
5377                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5378                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5379                 0, 0, pbn_b0_4_115200 },
5380         {       /* RockForceF4 */
5381                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5382                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5383                 0, 0, pbn_b0_4_115200 },
5384         {       /* RockForceD8 */
5385                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5386                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5387                 0, 0, pbn_b0_8_115200 },
5388         {       /* RockForceF8 */
5389                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5390                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5391                 0, 0, pbn_b0_8_115200 },
5392         {       /* IQ Express D1 */
5393                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5394                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5395                 0, 0, pbn_b0_1_115200 },
5396         {       /* IQ Express F1 */
5397                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5398                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5399                 0, 0, pbn_b0_1_115200 },
5400         {       /* IQ Express D2 */
5401                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5402                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5403                 0, 0, pbn_b0_2_115200 },
5404         {       /* IQ Express F2 */
5405                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5406                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5407                 0, 0, pbn_b0_2_115200 },
5408         {       /* IQ Express D4 */
5409                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5410                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5411                 0, 0, pbn_b0_4_115200 },
5412         {       /* IQ Express F4 */
5413                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5414                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5415                 0, 0, pbn_b0_4_115200 },
5416         {       /* IQ Express D8 */
5417                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5418                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5419                 0, 0, pbn_b0_8_115200 },
5420         {       /* IQ Express F8 */
5421                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5422                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5423                 0, 0, pbn_b0_8_115200 },
5424
5425
5426         /*
5427          * PA Semi PA6T-1682M on-chip UART
5428          */
5429         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5430                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5431                 pbn_pasemi_1682M },
5432
5433         /*
5434          * National Instruments
5435          */
5436         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5438                 pbn_b1_16_115200 },
5439         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5441                 pbn_b1_8_115200 },
5442         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5443                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5444                 pbn_b1_bt_4_115200 },
5445         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5446                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5447                 pbn_b1_bt_2_115200 },
5448         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5449                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5450                 pbn_b1_bt_4_115200 },
5451         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5452                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5453                 pbn_b1_bt_2_115200 },
5454         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5455                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5456                 pbn_b1_16_115200 },
5457         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5458                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5459                 pbn_b1_8_115200 },
5460         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5461                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5462                 pbn_b1_bt_4_115200 },
5463         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5465                 pbn_b1_bt_2_115200 },
5466         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5467                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5468                 pbn_b1_bt_4_115200 },
5469         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5471                 pbn_b1_bt_2_115200 },
5472         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5474                 pbn_ni8430_2 },
5475         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5477                 pbn_ni8430_2 },
5478         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5480                 pbn_ni8430_4 },
5481         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5483                 pbn_ni8430_4 },
5484         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5486                 pbn_ni8430_8 },
5487         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5489                 pbn_ni8430_8 },
5490         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5492                 pbn_ni8430_16 },
5493         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5495                 pbn_ni8430_16 },
5496         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5498                 pbn_ni8430_2 },
5499         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5501                 pbn_ni8430_2 },
5502         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5504                 pbn_ni8430_4 },
5505         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5507                 pbn_ni8430_4 },
5508
5509         /*
5510         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5511         */
5512         {       PCI_VENDOR_ID_ADDIDATA,
5513                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5514                 PCI_ANY_ID,
5515                 PCI_ANY_ID,
5516                 0,
5517                 0,
5518                 pbn_b0_4_115200 },
5519
5520         {       PCI_VENDOR_ID_ADDIDATA,
5521                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5522                 PCI_ANY_ID,
5523                 PCI_ANY_ID,
5524                 0,
5525                 0,
5526                 pbn_b0_2_115200 },
5527
5528         {       PCI_VENDOR_ID_ADDIDATA,
5529                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5530                 PCI_ANY_ID,
5531                 PCI_ANY_ID,
5532                 0,
5533                 0,
5534                 pbn_b0_1_115200 },
5535
5536         {       PCI_VENDOR_ID_AMCC,
5537                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5538                 PCI_ANY_ID,
5539                 PCI_ANY_ID,
5540                 0,
5541                 0,
5542                 pbn_b1_8_115200 },
5543
5544         {       PCI_VENDOR_ID_ADDIDATA,
5545                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5546                 PCI_ANY_ID,
5547                 PCI_ANY_ID,
5548                 0,
5549                 0,
5550                 pbn_b0_4_115200 },
5551
5552         {       PCI_VENDOR_ID_ADDIDATA,
5553                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5554                 PCI_ANY_ID,
5555                 PCI_ANY_ID,
5556                 0,
5557                 0,
5558                 pbn_b0_2_115200 },
5559
5560         {       PCI_VENDOR_ID_ADDIDATA,
5561                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5562                 PCI_ANY_ID,
5563                 PCI_ANY_ID,
5564                 0,
5565                 0,
5566                 pbn_b0_1_115200 },
5567
5568         {       PCI_VENDOR_ID_ADDIDATA,
5569                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5570                 PCI_ANY_ID,
5571                 PCI_ANY_ID,
5572                 0,
5573                 0,
5574                 pbn_b0_4_115200 },
5575
5576         {       PCI_VENDOR_ID_ADDIDATA,
5577                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5578                 PCI_ANY_ID,
5579                 PCI_ANY_ID,
5580                 0,
5581                 0,
5582                 pbn_b0_2_115200 },
5583
5584         {       PCI_VENDOR_ID_ADDIDATA,
5585                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5586                 PCI_ANY_ID,
5587                 PCI_ANY_ID,
5588                 0,
5589                 0,
5590                 pbn_b0_1_115200 },
5591
5592         {       PCI_VENDOR_ID_ADDIDATA,
5593                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5594                 PCI_ANY_ID,
5595                 PCI_ANY_ID,
5596                 0,
5597                 0,
5598                 pbn_b0_8_115200 },
5599
5600         {       PCI_VENDOR_ID_ADDIDATA,
5601                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5602                 PCI_ANY_ID,
5603                 PCI_ANY_ID,
5604                 0,
5605                 0,
5606                 pbn_ADDIDATA_PCIe_4_3906250 },
5607
5608         {       PCI_VENDOR_ID_ADDIDATA,
5609                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5610                 PCI_ANY_ID,
5611                 PCI_ANY_ID,
5612                 0,
5613                 0,
5614                 pbn_ADDIDATA_PCIe_2_3906250 },
5615
5616         {       PCI_VENDOR_ID_ADDIDATA,
5617                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5618                 PCI_ANY_ID,
5619                 PCI_ANY_ID,
5620                 0,
5621                 0,
5622                 pbn_ADDIDATA_PCIe_1_3906250 },
5623
5624         {       PCI_VENDOR_ID_ADDIDATA,
5625                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5626                 PCI_ANY_ID,
5627                 PCI_ANY_ID,
5628                 0,
5629                 0,
5630                 pbn_ADDIDATA_PCIe_8_3906250 },
5631
5632         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5633                 PCI_VENDOR_ID_IBM, 0x0299,
5634                 0, 0, pbn_b0_bt_2_115200 },
5635
5636         /*
5637          * other NetMos 9835 devices are most likely handled by the
5638          * parport_serial driver, check drivers/parport/parport_serial.c
5639          * before adding them here.
5640          */
5641
5642         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5643                 0xA000, 0x1000,
5644                 0, 0, pbn_b0_1_115200 },
5645
5646         /* the 9901 is a rebranded 9912 */
5647         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5648                 0xA000, 0x1000,
5649                 0, 0, pbn_b0_1_115200 },
5650
5651         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5652                 0xA000, 0x1000,
5653                 0, 0, pbn_b0_1_115200 },
5654
5655         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5656                 0xA000, 0x1000,
5657                 0, 0, pbn_b0_1_115200 },
5658
5659         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5660                 0xA000, 0x1000,
5661                 0, 0, pbn_b0_1_115200 },
5662
5663         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5664                 0xA000, 0x3002,
5665                 0, 0, pbn_NETMOS9900_2s_115200 },
5666
5667         /*
5668          * Best Connectivity and Rosewill PCI Multi I/O cards
5669          */
5670
5671         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5672                 0xA000, 0x1000,
5673                 0, 0, pbn_b0_1_115200 },
5674
5675         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5676                 0xA000, 0x3002,
5677                 0, 0, pbn_b0_bt_2_115200 },
5678
5679         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5680                 0xA000, 0x3004,
5681                 0, 0, pbn_b0_bt_4_115200 },
5682         /* Intel CE4100 */
5683         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5684                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5685                 pbn_ce4100_1_115200 },
5686         /* Intel BayTrail */
5687         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5688                 PCI_ANY_ID,  PCI_ANY_ID,
5689                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5690                 pbn_byt },
5691         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5692                 PCI_ANY_ID,  PCI_ANY_ID,
5693                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5694                 pbn_byt },
5695         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5696                 PCI_ANY_ID,  PCI_ANY_ID,
5697                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5698                 pbn_byt },
5699         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5700                 PCI_ANY_ID,  PCI_ANY_ID,
5701                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5702                 pbn_byt },
5703
5704         /*
5705          * Intel Penwell
5706          */
5707         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5708                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5709                 pbn_pnw},
5710         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5711                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5712                 pbn_pnw},
5713         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5714                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5715                 pbn_pnw},
5716
5717         /*
5718          * Intel Tangier
5719          */
5720         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5721                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5722                 pbn_tng},
5723
5724         /*
5725          * Intel Quark x1000
5726          */
5727         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5729                 pbn_qrk },
5730         /*
5731          * Cronyx Omega PCI
5732          */
5733         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5735                 pbn_omegapci },
5736
5737         /*
5738          * Broadcom TruManage
5739          */
5740         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5741                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5742                 pbn_brcm_trumanage },
5743
5744         /*
5745          * AgeStar as-prs2-009
5746          */
5747         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5748                 PCI_ANY_ID, PCI_ANY_ID,
5749                 0, 0, pbn_b0_bt_2_115200 },
5750
5751         /*
5752          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5753          * so not listed here.
5754          */
5755         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5756                 PCI_ANY_ID, PCI_ANY_ID,
5757                 0, 0, pbn_b0_bt_4_115200 },
5758
5759         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5760                 PCI_ANY_ID, PCI_ANY_ID,
5761                 0, 0, pbn_b0_bt_2_115200 },
5762
5763         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5764                 PCI_ANY_ID, PCI_ANY_ID,
5765                 0, 0, pbn_wch384_4 },
5766
5767         /*
5768          * Commtech, Inc. Fastcom adapters
5769          */
5770         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5771                 PCI_ANY_ID, PCI_ANY_ID,
5772                 0,
5773                 0, pbn_b0_2_1152000_200 },
5774         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5775                 PCI_ANY_ID, PCI_ANY_ID,
5776                 0,
5777                 0, pbn_b0_4_1152000_200 },
5778         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5779                 PCI_ANY_ID, PCI_ANY_ID,
5780                 0,
5781                 0, pbn_b0_4_1152000_200 },
5782         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5783                 PCI_ANY_ID, PCI_ANY_ID,
5784                 0,
5785                 0, pbn_b0_8_1152000_200 },
5786         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5787                 PCI_ANY_ID, PCI_ANY_ID,
5788                 0,
5789                 0, pbn_exar_XR17V352 },
5790         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5791                 PCI_ANY_ID, PCI_ANY_ID,
5792                 0,
5793                 0, pbn_exar_XR17V354 },
5794         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5795                 PCI_ANY_ID, PCI_ANY_ID,
5796                 0,
5797                 0, pbn_exar_XR17V358 },
5798
5799         /* Fintek PCI serial cards */
5800         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5801         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5802         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5803
5804         /*
5805          * These entries match devices with class COMMUNICATION_SERIAL,
5806          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5807          */
5808         {       PCI_ANY_ID, PCI_ANY_ID,
5809                 PCI_ANY_ID, PCI_ANY_ID,
5810                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5811                 0xffff00, pbn_default },
5812         {       PCI_ANY_ID, PCI_ANY_ID,
5813                 PCI_ANY_ID, PCI_ANY_ID,
5814                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5815                 0xffff00, pbn_default },
5816         {       PCI_ANY_ID, PCI_ANY_ID,
5817                 PCI_ANY_ID, PCI_ANY_ID,
5818                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5819                 0xffff00, pbn_default },
5820         { 0, }
5821 };
5822
5823 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5824                                                 pci_channel_state_t state)
5825 {
5826         struct serial_private *priv = pci_get_drvdata(dev);
5827
5828         if (state == pci_channel_io_perm_failure)
5829                 return PCI_ERS_RESULT_DISCONNECT;
5830
5831         if (priv)
5832                 pciserial_suspend_ports(priv);
5833
5834         pci_disable_device(dev);
5835
5836         return PCI_ERS_RESULT_NEED_RESET;
5837 }
5838
5839 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5840 {
5841         int rc;
5842
5843         rc = pci_enable_device(dev);
5844
5845         if (rc)
5846                 return PCI_ERS_RESULT_DISCONNECT;
5847
5848         pci_restore_state(dev);
5849         pci_save_state(dev);
5850
5851         return PCI_ERS_RESULT_RECOVERED;
5852 }
5853
5854 static void serial8250_io_resume(struct pci_dev *dev)
5855 {
5856         struct serial_private *priv = pci_get_drvdata(dev);
5857
5858         if (priv)
5859                 pciserial_resume_ports(priv);
5860 }
5861
5862 static const struct pci_error_handlers serial8250_err_handler = {
5863         .error_detected = serial8250_io_error_detected,
5864         .slot_reset = serial8250_io_slot_reset,
5865         .resume = serial8250_io_resume,
5866 };
5867
5868 static struct pci_driver serial_pci_driver = {
5869         .name           = "serial",
5870         .probe          = pciserial_init_one,
5871         .remove         = pciserial_remove_one,
5872         .driver         = {
5873                 .pm     = &pciserial_pm_ops,
5874         },
5875         .id_table       = serial_pci_tbl,
5876         .err_handler    = &serial8250_err_handler,
5877 };
5878
5879 module_pci_driver(serial_pci_driver);
5880
5881 MODULE_LICENSE("GPL");
5882 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5883 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);