drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24 #include <linux/rational.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_data/dma-dw.h>
  31
  32 #include "8250.h"
  33
  34 /*
  35  * init function returns:
  36  *  > 0 - number of ports
  37  *  = 0 - use board->num_ports
  38  *  < 0 - error
  39  */
  40 struct pci_serial_quirk {
  41         u32     vendor;
  42         u32     device;
  43         u32     subvendor;
  44         u32     subdevice;
  45         int     (*probe)(struct pci_dev *dev);
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *,
  48                          const struct pciserial_board *,
  49                          struct uart_8250_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static int pci_default_setup(struct serial_private*,
  64           const struct pciserial_board*, struct uart_8250_port *, int);
  65
  66 static void moan_device(const char *str, struct pci_dev *dev)
  67 {
  68         dev_err(&dev->dev,
  69                "%s: %s\n"
  70                "Please send the output of lspci -vv, this\n"
  71                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  72                "manufacturer and name of serial board or\n"
  73                "modem board to <linux-serial@vger.kernel.org>.\n",
  74                pci_name(dev), str, dev->vendor, dev->device,
  75                dev->subsystem_vendor, dev->subsystem_device);
  76 }
  77
  78 static int
  79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  80            int bar, int offset, int regshift)
  81 {
  82         struct pci_dev *dev = priv->dev;
  83
  84         if (bar >= PCI_NUM_BAR_RESOURCES)
  85                 return -EINVAL;
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->port.iotype = UPIO_MEM;
  94                 port->port.iobase = 0;
  95                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
  96                 port->port.membase = priv->remapped_bar[bar] + offset;
  97                 port->port.regshift = regshift;
  98         } else {
  99                 port->port.iotype = UPIO_PORT;
 100                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 101                 port->port.mapbase = 0;
 102                 port->port.membase = NULL;
 103                 port->port.regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 110  */
 111 static int addidata_apci7800_setup(struct serial_private *priv,
 112                                 const struct pciserial_board *board,
 113                                 struct uart_8250_port *port, int idx)
 114 {
 115         unsigned int bar = 0, offset = board->first_offset;
 116         bar = FL_GET_BASE(board->flags);
 117
 118         if (idx < 2) {
 119                 offset += idx * board->uart_offset;
 120         } else if ((idx >= 2) && (idx < 4)) {
 121                 bar += 1;
 122                 offset += ((idx - 2) * board->uart_offset);
 123         } else if ((idx >= 4) && (idx < 6)) {
 124                 bar += 2;
 125                 offset += ((idx - 4) * board->uart_offset);
 126         } else if (idx >= 6) {
 127                 bar += 3;
 128                 offset += ((idx - 6) * board->uart_offset);
 129         }
 130
 131         return setup_port(priv, port, bar, offset, board->reg_shift);
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 140               struct uart_8250_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(priv, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct serial_private *priv,
 194                 const struct pciserial_board *board,
 195                 struct uart_8250_port *port, int idx)
 196 {
 197         unsigned int offset = board->first_offset;
 198         unsigned int bar = FL_GET_BASE(board->flags);
 199
 200         switch (priv->dev->subsystem_device) {
 201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 202                 if (idx == 3)
 203                         idx++;
 204                 break;
 205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 206                 if (idx > 0)
 207                         idx++;
 208                 if (idx > 2)
 209                         idx++;
 210                 break;
 211         }
 212         if (idx > 2)
 213                 offset = 0x18;
 214
 215         offset += idx * board->uart_offset;
 216
 217         return setup_port(priv, port, bar, offset, board->reg_shift);
 218 }
 219
 220 /*
 221  * Added for EKF Intel i960 serial boards
 222  */
 223 static int pci_inteli960ni_init(struct pci_dev *dev)
 224 {
 225         u32 oldval;
 226
 227         if (!(dev->subsystem_device & 0x1000))
 228                 return -ENODEV;
 229
 230         /* is firmware started? */
 231         pci_read_config_dword(dev, 0x44, &oldval);
 232         if (oldval == 0x00001000L) { /* RESET value */
 233                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 234                 return -ENODEV;
 235         }
 236         return 0;
 237 }
 238
 239 /*
 240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 241  * that the card interrupt be explicitly enabled or disabled.  This
 242  * seems to be mainly needed on card using the PLX which also use I/O
 243  * mapped memory.
 244  */
 245 static int pci_plx9050_init(struct pci_dev *dev)
 246 {
 247         u8 irq_config;
 248         void __iomem *p;
 249
 250         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 251                 moan_device("no memory in bar 0", dev);
 252                 return 0;
 253         }
 254
 255         irq_config = 0x41;
 256         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 257             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 258                 irq_config = 0x43;
 259
 260         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 261             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 262                 /*
 263                  * As the megawolf cards have the int pins active
 264                  * high, and have 2 UART chips, both ints must be
 265                  * enabled on the 9050. Also, the UARTS are set in
 266                  * 16450 mode by default, so we have to enable the
 267                  * 16C950 'enhanced' mode so that we can use the
 268                  * deep FIFOs
 269                  */
 270                 irq_config = 0x5b;
 271         /*
 272          * enable/disable interrupts
 273          */
 274         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 275         if (p == NULL)
 276                 return -ENOMEM;
 277         writel(irq_config, p + 0x4c);
 278
 279         /*
 280          * Read the register back to ensure that it took effect.
 281          */
 282         readl(p + 0x4c);
 283         iounmap(p);
 284
 285         return 0;
 286 }
 287
 288 static void pci_plx9050_exit(struct pci_dev *dev)
 289 {
 290         u8 __iomem *p;
 291
 292         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 293                 return;
 294
 295         /*
 296          * disable interrupts
 297          */
 298         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 299         if (p != NULL) {
 300                 writel(0, p + 0x4c);
 301
 302                 /*
 303                  * Read the register back to ensure that it took effect.
 304                  */
 305                 readl(p + 0x4c);
 306                 iounmap(p);
 307         }
 308 }
 309
 310 #define NI8420_INT_ENABLE_REG   0x38
 311 #define NI8420_INT_ENABLE_BIT   0x2000
 312
 313 static void pci_ni8420_exit(struct pci_dev *dev)
 314 {
 315         void __iomem *p;
 316         unsigned int bar = 0;
 317
 318         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 319                 moan_device("no memory in bar", dev);
 320                 return;
 321         }
 322
 323         p = pci_ioremap_bar(dev, bar);
 324         if (p == NULL)
 325                 return;
 326
 327         /* Disable the CPU Interrupt */
 328         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 329                p + NI8420_INT_ENABLE_REG);
 330         iounmap(p);
 331 }
 332
 333
 334 /* MITE registers */
 335 #define MITE_IOWBSR1    0xc4
 336 #define MITE_IOWCR1     0xf4
 337 #define MITE_LCIMR1     0x08
 338 #define MITE_LCIMR2     0x10
 339
 340 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 341
 342 static void pci_ni8430_exit(struct pci_dev *dev)
 343 {
 344         void __iomem *p;
 345         unsigned int bar = 0;
 346
 347         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 348                 moan_device("no memory in bar", dev);
 349                 return;
 350         }
 351
 352         p = pci_ioremap_bar(dev, bar);
 353         if (p == NULL)
 354                 return;
 355
 356         /* Disable the CPU Interrupt */
 357         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 358         iounmap(p);
 359 }
 360
 361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 362 static int
 363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 364                 struct uart_8250_port *port, int idx)
 365 {
 366         unsigned int bar, offset = board->first_offset;
 367
 368         bar = 0;
 369
 370         if (idx < 4) {
 371                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 372                 offset += idx * board->uart_offset;
 373         } else if (idx < 8) {
 374                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 375                 offset += idx * board->uart_offset + 0xC00;
 376         } else /* we have only 8 ports on PMC-OCTALPRO */
 377                 return 1;
 378
 379         return setup_port(priv, port, bar, offset, board->reg_shift);
 380 }
 381
 382 /*
 383 * This does initialization for PMC OCTALPRO cards:
 384 * maps the device memory, resets the UARTs (needed, bc
 385 * if the module is removed and inserted again, the card
 386 * is in the sleep mode) and enables global interrupt.
 387 */
 388
 389 /* global control register offset for SBS PMC-OctalPro */
 390 #define OCT_REG_CR_OFF          0x500
 391
 392 static int sbs_init(struct pci_dev *dev)
 393 {
 394         u8 __iomem *p;
 395
 396         p = pci_ioremap_bar(dev, 0);
 397
 398         if (p == NULL)
 399                 return -ENOMEM;
 400         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 401         writeb(0x10, p + OCT_REG_CR_OFF);
 402         udelay(50);
 403         writeb(0x0, p + OCT_REG_CR_OFF);
 404
 405         /* Set bit-2 (INTENABLE) of Control Register */
 406         writeb(0x4, p + OCT_REG_CR_OFF);
 407         iounmap(p);
 408
 409         return 0;
 410 }
 411
 412 /*
 413  * Disables the global interrupt of PMC-OctalPro
 414  */
 415
 416 static void sbs_exit(struct pci_dev *dev)
 417 {
 418         u8 __iomem *p;
 419
 420         p = pci_ioremap_bar(dev, 0);
 421         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 422         if (p != NULL)
 423                 writeb(0, p + OCT_REG_CR_OFF);
 424         iounmap(p);
 425 }
 426
 427 /*
 428  * SIIG serial cards have an PCI interface chip which also controls
 429  * the UART clocking frequency. Each UART can be clocked independently
 430  * (except cards equipped with 4 UARTs) and initial clocking settings
 431  * are stored in the EEPROM chip. It can cause problems because this
 432  * version of serial driver doesn't support differently clocked UART's
 433  * on single PCI card. To prevent this, initialization functions set
 434  * high frequency clocking for all UART's on given card. It is safe (I
 435  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 436  * with other OSes (like M$ DOS).
 437  *
 438  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 439  *
 440  * There is two family of SIIG serial cards with different PCI
 441  * interface chip and different configuration methods:
 442  *     - 10x cards have control registers in IO and/or memory space;
 443  *     - 20x cards have control registers in standard PCI configuration space.
 444  *
 445  * Note: all 10x cards have PCI device ids 0x10..
 446  *       all 20x cards have PCI device ids 0x20..
 447  *
 448  * There are also Quartet Serial cards which use Oxford Semiconductor
 449  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 450  *
 451  * Note: some SIIG cards are probed by the parport_serial object.
 452  */
 453
 454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 456
 457 static int pci_siig10x_init(struct pci_dev *dev)
 458 {
 459         u16 data;
 460         void __iomem *p;
 461
 462         switch (dev->device & 0xfff8) {
 463         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 464                 data = 0xffdf;
 465                 break;
 466         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 467                 data = 0xf7ff;
 468                 break;
 469         default:                        /* 1S1P, 4S */
 470                 data = 0xfffb;
 471                 break;
 472         }
 473
 474         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 475         if (p == NULL)
 476                 return -ENOMEM;
 477
 478         writew(readw(p + 0x28) & data, p + 0x28);
 479         readw(p + 0x28);
 480         iounmap(p);
 481         return 0;
 482 }
 483
 484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 486
 487 static int pci_siig20x_init(struct pci_dev *dev)
 488 {
 489         u8 data;
 490
 491         /* Change clock frequency for the first UART. */
 492         pci_read_config_byte(dev, 0x6f, &data);
 493         pci_write_config_byte(dev, 0x6f, data & 0xef);
 494
 495         /* If this card has 2 UART, we have to do the same with second UART. */
 496         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 497             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 498                 pci_read_config_byte(dev, 0x73, &data);
 499                 pci_write_config_byte(dev, 0x73, data & 0xef);
 500         }
 501         return 0;
 502 }
 503
 504 static int pci_siig_init(struct pci_dev *dev)
 505 {
 506         unsigned int type = dev->device & 0xff00;
 507
 508         if (type == 0x1000)
 509                 return pci_siig10x_init(dev);
 510         else if (type == 0x2000)
 511                 return pci_siig20x_init(dev);
 512
 513         moan_device("Unknown SIIG card", dev);
 514         return -ENODEV;
 515 }
 516
 517 static int pci_siig_setup(struct serial_private *priv,
 518                           const struct pciserial_board *board,
 519                           struct uart_8250_port *port, int idx)
 520 {
 521         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 522
 523         if (idx > 3) {
 524                 bar = 4;
 525                 offset = (idx - 4) * 8;
 526         }
 527
 528         return setup_port(priv, port, bar, offset, 0);
 529 }
 530
 531 /*
 532  * Timedia has an explosion of boards, and to avoid the PCI table from
 533  * growing *huge*, we use this function to collapse some 70 entries
 534  * in the PCI table into one, for sanity's and compactness's sake.
 535  */
 536 static const unsigned short timedia_single_port[] = {
 537         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 538 };
 539
 540 static const unsigned short timedia_dual_port[] = {
 541         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 542         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 543         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 544         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 545         0xD079, 0
 546 };
 547
 548 static const unsigned short timedia_quad_port[] = {
 549         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 550         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 551         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 552         0xB157, 0
 553 };
 554
 555 static const unsigned short timedia_eight_port[] = {
 556         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 557         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 558 };
 559
 560 static const struct timedia_struct {
 561         int num;
 562         const unsigned short *ids;
 563 } timedia_data[] = {
 564         { 1, timedia_single_port },
 565         { 2, timedia_dual_port },
 566         { 4, timedia_quad_port },
 567         { 8, timedia_eight_port }
 568 };
 569
 570 /*
 571  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 572  * listing them individually, this driver merely grabs them all with
 573  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 574  * and should be left free to be claimed by parport_serial instead.
 575  */
 576 static int pci_timedia_probe(struct pci_dev *dev)
 577 {
 578         /*
 579          * Check the third digit of the subdevice ID
 580          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 581          */
 582         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 583                 dev_info(&dev->dev,
 584                         "ignoring Timedia subdevice %04x for parport_serial\n",
 585                         dev->subsystem_device);
 586                 return -ENODEV;
 587         }
 588
 589         return 0;
 590 }
 591
 592 static int pci_timedia_init(struct pci_dev *dev)
 593 {
 594         const unsigned short *ids;
 595         int i, j;
 596
 597         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 598                 ids = timedia_data[i].ids;
 599                 for (j = 0; ids[j]; j++)
 600                         if (dev->subsystem_device == ids[j])
 601                                 return timedia_data[i].num;
 602         }
 603         return 0;
 604 }
 605
 606 /*
 607  * Timedia/SUNIX uses a mixture of BARs and offsets
 608  * Ugh, this is ugly as all hell --- TYT
 609  */
 610 static int
 611 pci_timedia_setup(struct serial_private *priv,
 612                   const struct pciserial_board *board,
 613                   struct uart_8250_port *port, int idx)
 614 {
 615         unsigned int bar = 0, offset = board->first_offset;
 616
 617         switch (idx) {
 618         case 0:
 619                 bar = 0;
 620                 break;
 621         case 1:
 622                 offset = board->uart_offset;
 623                 bar = 0;
 624                 break;
 625         case 2:
 626                 bar = 1;
 627                 break;
 628         case 3:
 629                 offset = board->uart_offset;
 630                 /* FALLTHROUGH */
 631         case 4: /* BAR 2 */
 632         case 5: /* BAR 3 */
 633         case 6: /* BAR 4 */
 634         case 7: /* BAR 5 */
 635                 bar = idx - 2;
 636         }
 637
 638         return setup_port(priv, port, bar, offset, board->reg_shift);
 639 }
 640
 641 /*
 642  * Some Titan cards are also a little weird
 643  */
 644 static int
 645 titan_400l_800l_setup(struct serial_private *priv,
 646                       const struct pciserial_board *board,
 647                       struct uart_8250_port *port, int idx)
 648 {
 649         unsigned int bar, offset = board->first_offset;
 650
 651         switch (idx) {
 652         case 0:
 653                 bar = 1;
 654                 break;
 655         case 1:
 656                 bar = 2;
 657                 break;
 658         default:
 659                 bar = 4;
 660                 offset = (idx - 2) * board->uart_offset;
 661         }
 662
 663         return setup_port(priv, port, bar, offset, board->reg_shift);
 664 }
 665
 666 static int pci_xircom_init(struct pci_dev *dev)
 667 {
 668         msleep(100);
 669         return 0;
 670 }
 671
 672 static int pci_ni8420_init(struct pci_dev *dev)
 673 {
 674         void __iomem *p;
 675         unsigned int bar = 0;
 676
 677         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 678                 moan_device("no memory in bar", dev);
 679                 return 0;
 680         }
 681
 682         p = pci_ioremap_bar(dev, bar);
 683         if (p == NULL)
 684                 return -ENOMEM;
 685
 686         /* Enable CPU Interrupt */
 687         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 688                p + NI8420_INT_ENABLE_REG);
 689
 690         iounmap(p);
 691         return 0;
 692 }
 693
 694 #define MITE_IOWBSR1_WSIZE      0xa
 695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 696 #define MITE_IOWBSR1_WENAB      (1 << 7)
 697 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 698 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 700
 701 static int pci_ni8430_init(struct pci_dev *dev)
 702 {
 703         void __iomem *p;
 704         struct pci_bus_region region;
 705         u32 device_window;
 706         unsigned int bar = 0;
 707
 708         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 709                 moan_device("no memory in bar", dev);
 710                 return 0;
 711         }
 712
 713         p = pci_ioremap_bar(dev, bar);
 714         if (p == NULL)
 715                 return -ENOMEM;
 716
 717         /*
 718          * Set device window address and size in BAR0, while acknowledging that
 719          * the resource structure may contain a translated address that differs
 720          * from the address the device responds to.
 721          */
 722         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 723         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 724                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 725         writel(device_window, p + MITE_IOWBSR1);
 726
 727         /* Set window access to go to RAMSEL IO address space */
 728         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 729                p + MITE_IOWCR1);
 730
 731         /* Enable IO Bus Interrupt 0 */
 732         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 733
 734         /* Enable CPU Interrupt */
 735         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 736
 737         iounmap(p);
 738         return 0;
 739 }
 740
 741 /* UART Port Control Register */
 742 #define NI8430_PORTCON  0x0f
 743 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 744
 745 static int
 746 pci_ni8430_setup(struct serial_private *priv,
 747                  const struct pciserial_board *board,
 748                  struct uart_8250_port *port, int idx)
 749 {
 750         struct pci_dev *dev = priv->dev;
 751         void __iomem *p;
 752         unsigned int bar, offset = board->first_offset;
 753
 754         if (idx >= board->num_ports)
 755                 return 1;
 756
 757         bar = FL_GET_BASE(board->flags);
 758         offset += idx * board->uart_offset;
 759
 760         p = pci_ioremap_bar(dev, bar);
 761         if (!p)
 762                 return -ENOMEM;
 763
 764         /* enable the transceiver */
 765         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 766                p + offset + NI8430_PORTCON);
 767
 768         iounmap(p);
 769
 770         return setup_port(priv, port, bar, offset, board->reg_shift);
 771 }
 772
 773 static int pci_netmos_9900_setup(struct serial_private *priv,
 774                                 const struct pciserial_board *board,
 775                                 struct uart_8250_port *port, int idx)
 776 {
 777         unsigned int bar;
 778
 779         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 780             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 781                 /* netmos apparently orders BARs by datasheet layout, so serial
 782                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 783                  */
 784                 bar = 3 * idx;
 785
 786                 return setup_port(priv, port, bar, 0, board->reg_shift);
 787         } else {
 788                 return pci_default_setup(priv, board, port, idx);
 789         }
 790 }
 791
 792 /* the 99xx series comes with a range of device IDs and a variety
 793  * of capabilities:
 794  *
 795  * 9900 has varying capabilities and can cascade to sub-controllers
 796  *   (cascading should be purely internal)
 797  * 9904 is hardwired with 4 serial ports
 798  * 9912 and 9922 are hardwired with 2 serial ports
 799  */
 800 static int pci_netmos_9900_numports(struct pci_dev *dev)
 801 {
 802         unsigned int c = dev->class;
 803         unsigned int pi;
 804         unsigned short sub_serports;
 805
 806         pi = (c & 0xff);
 807
 808         if (pi == 2) {
 809                 return 1;
 810         } else if ((pi == 0) &&
 811                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 812                 /* two possibilities: 0x30ps encodes number of parallel and
 813                  * serial ports, or 0x1000 indicates *something*. This is not
 814                  * immediately obvious, since the 2s1p+4s configuration seems
 815                  * to offer all functionality on functions 0..2, while still
 816                  * advertising the same function 3 as the 4s+2s1p config.
 817                  */
 818                 sub_serports = dev->subsystem_device & 0xf;
 819                 if (sub_serports > 0) {
 820                         return sub_serports;
 821                 } else {
 822                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 823                         return 0;
 824                 }
 825         }
 826
 827         moan_device("unknown NetMos/Mostech program interface", dev);
 828         return 0;
 829 }
 830
 831 static int pci_netmos_init(struct pci_dev *dev)
 832 {
 833         /* subdevice 0x00PS means <P> parallel, <S> serial */
 834         unsigned int num_serial = dev->subsystem_device & 0xf;
 835
 836         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 837                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 838                 return 0;
 839
 840         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 841                         dev->subsystem_device == 0x0299)
 842                 return 0;
 843
 844         switch (dev->device) { /* FALLTHROUGH on all */
 845                 case PCI_DEVICE_ID_NETMOS_9904:
 846                 case PCI_DEVICE_ID_NETMOS_9912:
 847                 case PCI_DEVICE_ID_NETMOS_9922:
 848                 case PCI_DEVICE_ID_NETMOS_9900:
 849                         num_serial = pci_netmos_9900_numports(dev);
 850                         break;
 851
 852                 default:
 853                         if (num_serial == 0 ) {
 854                                 moan_device("unknown NetMos/Mostech device", dev);
 855                         }
 856         }
 857
 858         if (num_serial == 0)
 859                 return -ENODEV;
 860
 861         return num_serial;
 862 }
 863
 864 /*
 865  * These chips are available with optionally one parallel port and up to
 866  * two serial ports. Unfortunately they all have the same product id.
 867  *
 868  * Basic configuration is done over a region of 32 I/O ports. The base
 869  * ioport is called INTA or INTC, depending on docs/other drivers.
 870  *
 871  * The region of the 32 I/O ports is configured in POSIO0R...
 872  */
 873
 874 /* registers */
 875 #define ITE_887x_MISCR          0x9c
 876 #define ITE_887x_INTCBAR        0x78
 877 #define ITE_887x_UARTBAR        0x7c
 878 #define ITE_887x_PS0BAR         0x10
 879 #define ITE_887x_POSIO0         0x60
 880
 881 /* I/O space size */
 882 #define ITE_887x_IOSIZE         32
 883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 884 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 886 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 888 #define ITE_887x_POSIO_SPEED            (3 << 29)
 889 /* enable IO_Space bit */
 890 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 891
 892 static int pci_ite887x_init(struct pci_dev *dev)
 893 {
 894         /* inta_addr are the configuration addresses of the ITE */
 895         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 896                                                         0x200, 0x280, 0 };
 897         int ret, i, type;
 898         struct resource *iobase = NULL;
 899         u32 miscr, uartbar, ioport;
 900
 901         /* search for the base-ioport */
 902         i = 0;
 903         while (inta_addr[i] && iobase == NULL) {
 904                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 905                                                                 "ite887x");
 906                 if (iobase != NULL) {
 907                         /* write POSIO0R - speed | size | ioport */
 908                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 909                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 910                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 911                         /* write INTCBAR - ioport */
 912                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 913                                                                 inta_addr[i]);
 914                         ret = inb(inta_addr[i]);
 915                         if (ret != 0xff) {
 916                                 /* ioport connected */
 917                                 break;
 918                         }
 919                         release_region(iobase->start, ITE_887x_IOSIZE);
 920                         iobase = NULL;
 921                 }
 922                 i++;
 923         }
 924
 925         if (!inta_addr[i]) {
 926                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 927                 return -ENODEV;
 928         }
 929
 930         /* start of undocumented type checking (see parport_pc.c) */
 931         type = inb(iobase->start + 0x18) & 0x0f;
 932
 933         switch (type) {
 934         case 0x2:       /* ITE8871 (1P) */
 935         case 0xa:       /* ITE8875 (1P) */
 936                 ret = 0;
 937                 break;
 938         case 0xe:       /* ITE8872 (2S1P) */
 939                 ret = 2;
 940                 break;
 941         case 0x6:       /* ITE8873 (1S) */
 942                 ret = 1;
 943                 break;
 944         case 0x8:       /* ITE8874 (2S) */
 945                 ret = 2;
 946                 break;
 947         default:
 948                 moan_device("Unknown ITE887x", dev);
 949                 ret = -ENODEV;
 950         }
 951
 952         /* configure all serial ports */
 953         for (i = 0; i < ret; i++) {
 954                 /* read the I/O port from the device */
 955                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 956                                                                 &ioport);
 957                 ioport &= 0x0000FF00;   /* the actual base address */
 958                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 959                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 960                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 961
 962                 /* write the ioport to the UARTBAR */
 963                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 964                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 965                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 966                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 967
 968                 /* get current config */
 969                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 970                 /* disable interrupts (UARTx_Routing[3:0]) */
 971                 miscr &= ~(0xf << (12 - 4 * i));
 972                 /* activate the UART (UARTx_En) */
 973                 miscr |= 1 << (23 - i);
 974                 /* write new config with activated UART */
 975                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 976         }
 977
 978         if (ret <= 0) {
 979                 /* the device has no UARTs if we get here */
 980                 release_region(iobase->start, ITE_887x_IOSIZE);
 981         }
 982
 983         return ret;
 984 }
 985
 986 static void pci_ite887x_exit(struct pci_dev *dev)
 987 {
 988         u32 ioport;
 989         /* the ioport is bit 0-15 in POSIO0R */
 990         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 991         ioport &= 0xffff;
 992         release_region(ioport, ITE_887x_IOSIZE);
 993 }
 994
 995 /*
 996  * EndRun Technologies.
 997  * Determine the number of ports available on the device.
 998  */
 999 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1001
1002 static int pci_endrun_init(struct pci_dev *dev)
1003 {
1004         u8 __iomem *p;
1005         unsigned long deviceID;
1006         unsigned int  number_uarts = 0;
1007
1008         /* EndRun device is all 0xexxx */
1009         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010                 (dev->device & 0xf000) != 0xe000)
1011                 return 0;
1012
1013         p = pci_iomap(dev, 0, 5);
1014         if (p == NULL)
1015                 return -ENOMEM;
1016
1017         deviceID = ioread32(p);
1018         /* EndRun device */
1019         if (deviceID == 0x07000200) {
1020                 number_uarts = ioread8(p + 4);
1021                 dev_dbg(&dev->dev,
1022                         "%d ports detected on EndRun PCI Express device\n",
1023                         number_uarts);
1024         }
1025         pci_iounmap(dev, p);
1026         return number_uarts;
1027 }
1028
1029 /*
1030  * Oxford Semiconductor Inc.
1031  * Check that device is part of the Tornado range of devices, then determine
1032  * the number of ports available on the device.
1033  */
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1035 {
1036         u8 __iomem *p;
1037         unsigned long deviceID;
1038         unsigned int  number_uarts = 0;
1039
1040         /* OxSemi Tornado devices are all 0xCxxx */
1041         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042             (dev->device & 0xF000) != 0xC000)
1043                 return 0;
1044
1045         p = pci_iomap(dev, 0, 5);
1046         if (p == NULL)
1047                 return -ENOMEM;
1048
1049         deviceID = ioread32(p);
1050         /* Tornado device */
1051         if (deviceID == 0x07000200) {
1052                 number_uarts = ioread8(p + 4);
1053                 dev_dbg(&dev->dev,
1054                         "%d ports detected on Oxford PCI Express device\n",
1055                         number_uarts);
1056         }
1057         pci_iounmap(dev, p);
1058         return number_uarts;
1059 }
1060
1061 static int pci_asix_setup(struct serial_private *priv,
1062                   const struct pciserial_board *board,
1063                   struct uart_8250_port *port, int idx)
1064 {
1065         port->bugs |= UART_BUG_PARITY;
1066         return pci_default_setup(priv, board, port, idx);
1067 }
1068
1069 /* Quatech devices have their own extra interface features */
1070
1071 struct quatech_feature {
1072         u16 devid;
1073         bool amcc;
1074 };
1075
1076 #define QPCR_TEST_FOR1          0x3F
1077 #define QPCR_TEST_GET1          0x00
1078 #define QPCR_TEST_FOR2          0x40
1079 #define QPCR_TEST_GET2          0x40
1080 #define QPCR_TEST_FOR3          0x80
1081 #define QPCR_TEST_GET3          0x40
1082 #define QPCR_TEST_FOR4          0xC0
1083 #define QPCR_TEST_GET4          0x80
1084
1085 #define QOPR_CLOCK_X1           0x0000
1086 #define QOPR_CLOCK_X2           0x0001
1087 #define QOPR_CLOCK_X4           0x0002
1088 #define QOPR_CLOCK_X8           0x0003
1089 #define QOPR_CLOCK_RATE_MASK    0x0003
1090
1091
1092 static struct quatech_feature quatech_cards[] = {
1093         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1094         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1096         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1098         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1100         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1101         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1103         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1112         { 0, }
1113 };
1114
1115 static int pci_quatech_amcc(u16 devid)
1116 {
1117         struct quatech_feature *qf = &quatech_cards[0];
1118         while (qf->devid) {
1119                 if (qf->devid == devid)
1120                         return qf->amcc;
1121                 qf++;
1122         }
1123         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1124         return 0;
1125 };
1126
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1128 {
1129         unsigned long base = port->port.iobase;
1130         u8 LCR, val;
1131
1132         LCR = inb(base + UART_LCR);
1133         outb(0xBF, base + UART_LCR);
1134         val = inb(base + UART_SCR);
1135         outb(LCR, base + UART_LCR);
1136         return val;
1137 }
1138
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1140 {
1141         unsigned long base = port->port.iobase;
1142         u8 LCR, val;
1143
1144         LCR = inb(base + UART_LCR);
1145         outb(0xBF, base + UART_LCR);
1146         val = inb(base + UART_SCR);
1147         outb(qopr, base + UART_SCR);
1148         outb(LCR, base + UART_LCR);
1149 }
1150
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1152 {
1153         unsigned long base = port->port.iobase;
1154         u8 LCR, val, qmcr;
1155
1156         LCR = inb(base + UART_LCR);
1157         outb(0xBF, base + UART_LCR);
1158         val = inb(base + UART_SCR);
1159         outb(val | 0x10, base + UART_SCR);
1160         qmcr = inb(base + UART_MCR);
1161         outb(val, base + UART_SCR);
1162         outb(LCR, base + UART_LCR);
1163
1164         return qmcr;
1165 }
1166
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1168 {
1169         unsigned long base = port->port.iobase;
1170         u8 LCR, val;
1171
1172         LCR = inb(base + UART_LCR);
1173         outb(0xBF, base + UART_LCR);
1174         val = inb(base + UART_SCR);
1175         outb(val | 0x10, base + UART_SCR);
1176         outb(qmcr, base + UART_MCR);
1177         outb(val, base + UART_SCR);
1178         outb(LCR, base + UART_LCR);
1179 }
1180
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1182 {
1183         unsigned long base = port->port.iobase;
1184         u8 LCR, val;
1185
1186         LCR = inb(base + UART_LCR);
1187         outb(0xBF, base + UART_LCR);
1188         val = inb(base + UART_SCR);
1189         if (val & 0x20) {
1190                 outb(0x80, UART_LCR);
1191                 if (!(inb(UART_SCR) & 0x20)) {
1192                         outb(LCR, base + UART_LCR);
1193                         return 1;
1194                 }
1195         }
1196         return 0;
1197 }
1198
1199 static int pci_quatech_test(struct uart_8250_port *port)
1200 {
1201         u8 reg;
1202         u8 qopr = pci_quatech_rqopr(port);
1203         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1204         reg = pci_quatech_rqopr(port) & 0xC0;
1205         if (reg != QPCR_TEST_GET1)
1206                 return -EINVAL;
1207         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1208         reg = pci_quatech_rqopr(port) & 0xC0;
1209         if (reg != QPCR_TEST_GET2)
1210                 return -EINVAL;
1211         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1212         reg = pci_quatech_rqopr(port) & 0xC0;
1213         if (reg != QPCR_TEST_GET3)
1214                 return -EINVAL;
1215         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1216         reg = pci_quatech_rqopr(port) & 0xC0;
1217         if (reg != QPCR_TEST_GET4)
1218                 return -EINVAL;
1219
1220         pci_quatech_wqopr(port, qopr);
1221         return 0;
1222 }
1223
1224 static int pci_quatech_clock(struct uart_8250_port *port)
1225 {
1226         u8 qopr, reg, set;
1227         unsigned long clock;
1228
1229         if (pci_quatech_test(port) < 0)
1230                 return 1843200;
1231
1232         qopr = pci_quatech_rqopr(port);
1233
1234         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1235         reg = pci_quatech_rqopr(port);
1236         if (reg & QOPR_CLOCK_X8) {
1237                 clock = 1843200;
1238                 goto out;
1239         }
1240         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1241         reg = pci_quatech_rqopr(port);
1242         if (!(reg & QOPR_CLOCK_X8)) {
1243                 clock = 1843200;
1244                 goto out;
1245         }
1246         reg &= QOPR_CLOCK_X8;
1247         if (reg == QOPR_CLOCK_X2) {
1248                 clock =  3685400;
1249                 set = QOPR_CLOCK_X2;
1250         } else if (reg == QOPR_CLOCK_X4) {
1251                 clock = 7372800;
1252                 set = QOPR_CLOCK_X4;
1253         } else if (reg == QOPR_CLOCK_X8) {
1254                 clock = 14745600;
1255                 set = QOPR_CLOCK_X8;
1256         } else {
1257                 clock = 1843200;
1258                 set = QOPR_CLOCK_X1;
1259         }
1260         qopr &= ~QOPR_CLOCK_RATE_MASK;
1261         qopr |= set;
1262
1263 out:
1264         pci_quatech_wqopr(port, qopr);
1265         return clock;
1266 }
1267
1268 static int pci_quatech_rs422(struct uart_8250_port *port)
1269 {
1270         u8 qmcr;
1271         int rs422 = 0;
1272
1273         if (!pci_quatech_has_qmcr(port))
1274                 return 0;
1275         qmcr = pci_quatech_rqmcr(port);
1276         pci_quatech_wqmcr(port, 0xFF);
1277         if (pci_quatech_rqmcr(port))
1278                 rs422 = 1;
1279         pci_quatech_wqmcr(port, qmcr);
1280         return rs422;
1281 }
1282
1283 static int pci_quatech_init(struct pci_dev *dev)
1284 {
1285         if (pci_quatech_amcc(dev->device)) {
1286                 unsigned long base = pci_resource_start(dev, 0);
1287                 if (base) {
1288                         u32 tmp;
1289                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1290                         tmp = inl(base + 0x3c);
1291                         outl(tmp | 0x01000000, base + 0x3c);
1292                         outl(tmp &= ~0x01000000, base + 0x3c);
1293                 }
1294         }
1295         return 0;
1296 }
1297
1298 static int pci_quatech_setup(struct serial_private *priv,
1299                   const struct pciserial_board *board,
1300                   struct uart_8250_port *port, int idx)
1301 {
1302         /* Needed by pci_quatech calls below */
1303         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1304         /* Set up the clocking */
1305         port->port.uartclk = pci_quatech_clock(port);
1306         /* For now just warn about RS422 */
1307         if (pci_quatech_rs422(port))
1308                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1309         return pci_default_setup(priv, board, port, idx);
1310 }
1311
1312 static void pci_quatech_exit(struct pci_dev *dev)
1313 {
1314 }
1315
1316 static int pci_default_setup(struct serial_private *priv,
1317                   const struct pciserial_board *board,
1318                   struct uart_8250_port *port, int idx)
1319 {
1320         unsigned int bar, offset = board->first_offset, maxnr;
1321
1322         bar = FL_GET_BASE(board->flags);
1323         if (board->flags & FL_BASE_BARS)
1324                 bar += idx;
1325         else
1326                 offset += idx * board->uart_offset;
1327
1328         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1329                 (board->reg_shift + 3);
1330
1331         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1332                 return 1;
1333
1334         return setup_port(priv, port, bar, offset, board->reg_shift);
1335 }
1336
1337 static int pci_pericom_setup(struct serial_private *priv,
1338                   const struct pciserial_board *board,
1339                   struct uart_8250_port *port, int idx)
1340 {
1341         unsigned int bar, offset = board->first_offset, maxnr;
1342
1343         bar = FL_GET_BASE(board->flags);
1344         if (board->flags & FL_BASE_BARS)
1345                 bar += idx;
1346         else
1347                 offset += idx * board->uart_offset;
1348
1349         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1350                 (board->reg_shift + 3);
1351
1352         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1353                 return 1;
1354
1355         port->port.uartclk = 14745600;
1356
1357         return setup_port(priv, port, bar, offset, board->reg_shift);
1358 }
1359
1360 static int
1361 ce4100_serial_setup(struct serial_private *priv,
1362                   const struct pciserial_board *board,
1363                   struct uart_8250_port *port, int idx)
1364 {
1365         int ret;
1366
1367         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1368         port->port.iotype = UPIO_MEM32;
1369         port->port.type = PORT_XSCALE;
1370         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1371         port->port.regshift = 2;
1372
1373         return ret;
1374 }
1375
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1378
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1381
1382 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1383 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1384
1385 #define BYT_PRV_CLK                     0x800
1386 #define BYT_PRV_CLK_EN                  (1 << 0)
1387 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1388 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1389 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1390
1391 #define BYT_TX_OVF_INT                  0x820
1392 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1393
1394 static void
1395 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1396                 struct ktermios *old)
1397 {
1398         unsigned int baud = tty_termios_baud_rate(termios);
1399         unsigned long fref = 100000000, fuart = baud * 16;
1400         unsigned long w = BIT(15) - 1;
1401         unsigned long m, n;
1402         u32 reg;
1403
1404         /* Get Fuart closer to Fref */
1405         fuart *= rounddown_pow_of_two(fref / fuart);
1406
1407         /*
1408          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1409          * dividers must be adjusted.
1410          *
1411          * uartclk = (m / n) * 100 MHz, where m <= n
1412          */
1413         rational_best_approximation(fuart, fref, w, w, &m, &n);
1414         p->uartclk = fuart;
1415
1416         /* Reset the clock */
1417         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1418         writel(reg, p->membase + BYT_PRV_CLK);
1419         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1420         writel(reg, p->membase + BYT_PRV_CLK);
1421
1422         p->status &= ~UPSTAT_AUTOCTS;
1423         if (termios->c_cflag & CRTSCTS)
1424                 p->status |= UPSTAT_AUTOCTS;
1425
1426         serial8250_do_set_termios(p, termios, old);
1427 }
1428
1429 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1430 {
1431         struct dw_dma_slave *dws = param;
1432
1433         if (dws->dma_dev != chan->device->dev)
1434                 return false;
1435
1436         chan->private = dws;
1437         return true;
1438 }
1439
1440 static int
1441 byt_serial_setup(struct serial_private *priv,
1442                  const struct pciserial_board *board,
1443                  struct uart_8250_port *port, int idx)
1444 {
1445         struct pci_dev *pdev = priv->dev;
1446         struct device *dev = port->port.dev;
1447         struct uart_8250_dma *dma;
1448         struct dw_dma_slave *tx_param, *rx_param;
1449         struct pci_dev *dma_dev;
1450         int ret;
1451
1452         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1453         if (!dma)
1454                 return -ENOMEM;
1455
1456         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1457         if (!tx_param)
1458                 return -ENOMEM;
1459
1460         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1461         if (!rx_param)
1462                 return -ENOMEM;
1463
1464         switch (pdev->device) {
1465         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1466         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1467         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1468                 rx_param->src_id = 3;
1469                 tx_param->dst_id = 2;
1470                 break;
1471         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1472         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1473         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1474                 rx_param->src_id = 5;
1475                 tx_param->dst_id = 4;
1476                 break;
1477         default:
1478                 return -EINVAL;
1479         }
1480
1481         rx_param->src_master = 1;
1482         rx_param->dst_master = 0;
1483
1484         dma->rxconf.src_maxburst = 16;
1485
1486         tx_param->src_master = 1;
1487         tx_param->dst_master = 0;
1488
1489         dma->txconf.dst_maxburst = 16;
1490
1491         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1492         rx_param->dma_dev = &dma_dev->dev;
1493         tx_param->dma_dev = &dma_dev->dev;
1494
1495         dma->fn = byt_dma_filter;
1496         dma->rx_param = rx_param;
1497         dma->tx_param = tx_param;
1498
1499         ret = pci_default_setup(priv, board, port, idx);
1500         port->port.iotype = UPIO_MEM;
1501         port->port.type = PORT_16550A;
1502         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1503         port->port.set_termios = byt_set_termios;
1504         port->port.fifosize = 64;
1505         port->tx_loadsz = 64;
1506         port->dma = dma;
1507         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1508
1509         /* Disable Tx counter interrupts */
1510         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1511
1512         return ret;
1513 }
1514
1515 static int
1516 pci_omegapci_setup(struct serial_private *priv,
1517                       const struct pciserial_board *board,
1518                       struct uart_8250_port *port, int idx)
1519 {
1520         return setup_port(priv, port, 2, idx * 8, 0);
1521 }
1522
1523 static int
1524 pci_brcm_trumanage_setup(struct serial_private *priv,
1525                          const struct pciserial_board *board,
1526                          struct uart_8250_port *port, int idx)
1527 {
1528         int ret = pci_default_setup(priv, board, port, idx);
1529
1530         port->port.type = PORT_BRCM_TRUMANAGE;
1531         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1532         return ret;
1533 }
1534
1535 /* RTS will control by MCR if this bit is 0 */
1536 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1537 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1538 #define FINTEK_RTS_INVERT               BIT(5)
1539
1540 /* We should do proper H/W transceiver setting before change to RS485 mode */
1541 static int pci_fintek_rs485_config(struct uart_port *port,
1542                                struct serial_rs485 *rs485)
1543 {
1544         u8 setting;
1545         u8 *index = (u8 *) port->private_data;
1546         struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1547                                                 dev);
1548
1549         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1550
1551         if (!rs485)
1552                 rs485 = &port->rs485;
1553         else if (rs485->flags & SER_RS485_ENABLED)
1554                 memset(rs485->padding, 0, sizeof(rs485->padding));
1555         else
1556                 memset(rs485, 0, sizeof(*rs485));
1557
1558         /* F81504/508/512 not support RTS delay before or after send */
1559         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1560
1561         if (rs485->flags & SER_RS485_ENABLED) {
1562                 /* Enable RTS H/W control mode */
1563                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1564
1565                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1566                         /* RTS driving high on TX */
1567                         setting &= ~FINTEK_RTS_INVERT;
1568                 } else {
1569                         /* RTS driving low on TX */
1570                         setting |= FINTEK_RTS_INVERT;
1571                 }
1572
1573                 rs485->delay_rts_after_send = 0;
1574                 rs485->delay_rts_before_send = 0;
1575         } else {
1576                 /* Disable RTS H/W control mode */
1577                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1578         }
1579
1580         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1581
1582         if (rs485 != &port->rs485)
1583                 port->rs485 = *rs485;
1584
1585         return 0;
1586 }
1587
1588 static int pci_fintek_setup(struct serial_private *priv,
1589                             const struct pciserial_board *board,
1590                             struct uart_8250_port *port, int idx)
1591 {
1592         struct pci_dev *pdev = priv->dev;
1593         u8 *data;
1594         u8 config_base;
1595         u16 iobase;
1596
1597         config_base = 0x40 + 0x08 * idx;
1598
1599         /* Get the io address from configuration space */
1600         pci_read_config_word(pdev, config_base + 4, &iobase);
1601
1602         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1603
1604         port->port.iotype = UPIO_PORT;
1605         port->port.iobase = iobase;
1606         port->port.rs485_config = pci_fintek_rs485_config;
1607
1608         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1609         if (!data)
1610                 return -ENOMEM;
1611
1612         /* preserve index in PCI configuration space */
1613         *data = idx;
1614         port->port.private_data = data;
1615
1616         return 0;
1617 }
1618
1619 static int pci_fintek_init(struct pci_dev *dev)
1620 {
1621         unsigned long iobase;
1622         u32 max_port, i;
1623         u32 bar_data[3];
1624         u8 config_base;
1625         struct serial_private *priv = pci_get_drvdata(dev);
1626         struct uart_8250_port *port;
1627
1628         switch (dev->device) {
1629         case 0x1104: /* 4 ports */
1630         case 0x1108: /* 8 ports */
1631                 max_port = dev->device & 0xff;
1632                 break;
1633         case 0x1112: /* 12 ports */
1634                 max_port = 12;
1635                 break;
1636         default:
1637                 return -EINVAL;
1638         }
1639
1640         /* Get the io address dispatch from the BIOS */
1641         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1642         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1643         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1644
1645         for (i = 0; i < max_port; ++i) {
1646                 /* UART0 configuration offset start from 0x40 */
1647                 config_base = 0x40 + 0x08 * i;
1648
1649                 /* Calculate Real IO Port */
1650                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1651
1652                 /* Enable UART I/O port */
1653                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1654
1655                 /* Select 128-byte FIFO and 8x FIFO threshold */
1656                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1657
1658                 /* LSB UART */
1659                 pci_write_config_byte(dev, config_base + 0x04,
1660                                 (u8)(iobase & 0xff));
1661
1662                 /* MSB UART */
1663                 pci_write_config_byte(dev, config_base + 0x05,
1664                                 (u8)((iobase & 0xff00) >> 8));
1665
1666                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1667
1668                 if (priv) {
1669                         /* re-apply RS232/485 mode when
1670                          * pciserial_resume_ports()
1671                          */
1672                         port = serial8250_get_port(priv->line[i]);
1673                         pci_fintek_rs485_config(&port->port, NULL);
1674                 } else {
1675                         /* First init without port data
1676                          * force init to RS232 Mode
1677                          */
1678                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1679                 }
1680         }
1681
1682         return max_port;
1683 }
1684
1685 static int skip_tx_en_setup(struct serial_private *priv,
1686                         const struct pciserial_board *board,
1687                         struct uart_8250_port *port, int idx)
1688 {
1689         port->port.flags |= UPF_NO_TXEN_TEST;
1690         dev_dbg(&priv->dev->dev,
1691                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1692                 priv->dev->vendor, priv->dev->device,
1693                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1694
1695         return pci_default_setup(priv, board, port, idx);
1696 }
1697
1698 static void kt_handle_break(struct uart_port *p)
1699 {
1700         struct uart_8250_port *up = up_to_u8250p(p);
1701         /*
1702          * On receipt of a BI, serial device in Intel ME (Intel
1703          * management engine) needs to have its fifos cleared for sane
1704          * SOL (Serial Over Lan) output.
1705          */
1706         serial8250_clear_and_reinit_fifos(up);
1707 }
1708
1709 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1710 {
1711         struct uart_8250_port *up = up_to_u8250p(p);
1712         unsigned int val;
1713
1714         /*
1715          * When the Intel ME (management engine) gets reset its serial
1716          * port registers could return 0 momentarily.  Functions like
1717          * serial8250_console_write, read and save the IER, perform
1718          * some operation and then restore it.  In order to avoid
1719          * setting IER register inadvertently to 0, if the value read
1720          * is 0, double check with ier value in uart_8250_port and use
1721          * that instead.  up->ier should be the same value as what is
1722          * currently configured.
1723          */
1724         val = inb(p->iobase + offset);
1725         if (offset == UART_IER) {
1726                 if (val == 0)
1727                         val = up->ier;
1728         }
1729         return val;
1730 }
1731
1732 static int kt_serial_setup(struct serial_private *priv,
1733                            const struct pciserial_board *board,
1734                            struct uart_8250_port *port, int idx)
1735 {
1736         port->port.flags |= UPF_BUG_THRE;
1737         port->port.serial_in = kt_serial_in;
1738         port->port.handle_break = kt_handle_break;
1739         return skip_tx_en_setup(priv, board, port, idx);
1740 }
1741
1742 static int pci_eg20t_init(struct pci_dev *dev)
1743 {
1744 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1745         return -ENODEV;
1746 #else
1747         return 0;
1748 #endif
1749 }
1750
1751 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1752 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1753
1754 static int
1755 pci_xr17c154_setup(struct serial_private *priv,
1756                   const struct pciserial_board *board,
1757                   struct uart_8250_port *port, int idx)
1758 {
1759         port->port.flags |= UPF_EXAR_EFR;
1760         return pci_default_setup(priv, board, port, idx);
1761 }
1762
1763 static inline int
1764 xr17v35x_has_slave(struct serial_private *priv)
1765 {
1766         const int dev_id = priv->dev->device;
1767
1768         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1769                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1770 }
1771
1772 static int
1773 pci_xr17v35x_setup(struct serial_private *priv,
1774                   const struct pciserial_board *board,
1775                   struct uart_8250_port *port, int idx)
1776 {
1777         u8 __iomem *p;
1778
1779         p = pci_ioremap_bar(priv->dev, 0);
1780         if (p == NULL)
1781                 return -ENOMEM;
1782
1783         port->port.flags |= UPF_EXAR_EFR;
1784
1785         /*
1786          * Setup the uart clock for the devices on expansion slot to
1787          * half the clock speed of the main chip (which is 125MHz)
1788          */
1789         if (xr17v35x_has_slave(priv) && idx >= 8)
1790                 port->port.uartclk = (7812500 * 16 / 2);
1791
1792         /*
1793          * Setup Multipurpose Input/Output pins.
1794          */
1795         if (idx == 0) {
1796                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1797                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1798                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1799                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1800                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1801                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1802                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1803                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1804                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1805                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1806                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1807                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1808         }
1809         writeb(0x00, p + UART_EXAR_8XMODE);
1810         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1811         writeb(128, p + UART_EXAR_TXTRG);
1812         writeb(128, p + UART_EXAR_RXTRG);
1813         iounmap(p);
1814
1815         return pci_default_setup(priv, board, port, idx);
1816 }
1817
1818 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1819 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1820 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1821 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1822
1823 static int
1824 pci_fastcom335_setup(struct serial_private *priv,
1825                   const struct pciserial_board *board,
1826                   struct uart_8250_port *port, int idx)
1827 {
1828         u8 __iomem *p;
1829
1830         p = pci_ioremap_bar(priv->dev, 0);
1831         if (p == NULL)
1832                 return -ENOMEM;
1833
1834         port->port.flags |= UPF_EXAR_EFR;
1835
1836         /*
1837          * Setup Multipurpose Input/Output pins.
1838          */
1839         if (idx == 0) {
1840                 switch (priv->dev->device) {
1841                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1842                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1843                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1844                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1845                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1846                         break;
1847                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1848                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1849                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1850                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1851                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1852                         break;
1853                 }
1854                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1855                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1856                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1857         }
1858         writeb(0x00, p + UART_EXAR_8XMODE);
1859         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1860         writeb(32, p + UART_EXAR_TXTRG);
1861         writeb(32, p + UART_EXAR_RXTRG);
1862         iounmap(p);
1863
1864         return pci_default_setup(priv, board, port, idx);
1865 }
1866
1867 static int
1868 pci_wch_ch353_setup(struct serial_private *priv,
1869                     const struct pciserial_board *board,
1870                     struct uart_8250_port *port, int idx)
1871 {
1872         port->port.flags |= UPF_FIXED_TYPE;
1873         port->port.type = PORT_16550A;
1874         return pci_default_setup(priv, board, port, idx);
1875 }
1876
1877 static int
1878 pci_wch_ch38x_setup(struct serial_private *priv,
1879                     const struct pciserial_board *board,
1880                     struct uart_8250_port *port, int idx)
1881 {
1882         port->port.flags |= UPF_FIXED_TYPE;
1883         port->port.type = PORT_16850;
1884         return pci_default_setup(priv, board, port, idx);
1885 }
1886
1887 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1888 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1889 #define PCI_DEVICE_ID_OCTPRO            0x0001
1890 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1891 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1892 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1893 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1894 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1895 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1896 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1897 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1898 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1899 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1900 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1901 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1902 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1903 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1904 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1905 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1906 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1907 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1908 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1909 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1910 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1911 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1912 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1913 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1914 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1915 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1916 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1917 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1918 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1919 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1920 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1921 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1922 #define PCI_VENDOR_ID_WCH               0x4348
1923 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1924 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1925 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1926 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1927 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1928 #define PCI_VENDOR_ID_AGESTAR           0x5372
1929 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1930 #define PCI_VENDOR_ID_ASIX              0x9710
1931 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1932 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1933 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1934 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1935 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1936 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1937
1938 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1939 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1940
1941 #define PCIE_VENDOR_ID_WCH              0x1c00
1942 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1943 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1944
1945 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1946 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1947 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1948 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1949 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1950
1951 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1952 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1953 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1954
1955 /*
1956  * Master list of serial port init/setup/exit quirks.
1957  * This does not describe the general nature of the port.
1958  * (ie, baud base, number and location of ports, etc)
1959  *
1960  * This list is ordered alphabetically by vendor then device.
1961  * Specific entries must come before more generic entries.
1962  */
1963 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1964         /*
1965         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1966         */
1967         {
1968                 .vendor         = PCI_VENDOR_ID_AMCC,
1969                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1970                 .subvendor      = PCI_ANY_ID,
1971                 .subdevice      = PCI_ANY_ID,
1972                 .setup          = addidata_apci7800_setup,
1973         },
1974         /*
1975          * AFAVLAB cards - these may be called via parport_serial
1976          *  It is not clear whether this applies to all products.
1977          */
1978         {
1979                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1980                 .device         = PCI_ANY_ID,
1981                 .subvendor      = PCI_ANY_ID,
1982                 .subdevice      = PCI_ANY_ID,
1983                 .setup          = afavlab_setup,
1984         },
1985         /*
1986          * HP Diva
1987          */
1988         {
1989                 .vendor         = PCI_VENDOR_ID_HP,
1990                 .device         = PCI_DEVICE_ID_HP_DIVA,
1991                 .subvendor      = PCI_ANY_ID,
1992                 .subdevice      = PCI_ANY_ID,
1993                 .init           = pci_hp_diva_init,
1994                 .setup          = pci_hp_diva_setup,
1995         },
1996         /*
1997          * Intel
1998          */
1999         {
2000                 .vendor         = PCI_VENDOR_ID_INTEL,
2001                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2002                 .subvendor      = 0xe4bf,
2003                 .subdevice      = PCI_ANY_ID,
2004                 .init           = pci_inteli960ni_init,
2005                 .setup          = pci_default_setup,
2006         },
2007         {
2008                 .vendor         = PCI_VENDOR_ID_INTEL,
2009                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2010                 .subvendor      = PCI_ANY_ID,
2011                 .subdevice      = PCI_ANY_ID,
2012                 .setup          = skip_tx_en_setup,
2013         },
2014         {
2015                 .vendor         = PCI_VENDOR_ID_INTEL,
2016                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2017                 .subvendor      = PCI_ANY_ID,
2018                 .subdevice      = PCI_ANY_ID,
2019                 .setup          = skip_tx_en_setup,
2020         },
2021         {
2022                 .vendor         = PCI_VENDOR_ID_INTEL,
2023                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2024                 .subvendor      = PCI_ANY_ID,
2025                 .subdevice      = PCI_ANY_ID,
2026                 .setup          = skip_tx_en_setup,
2027         },
2028         {
2029                 .vendor         = PCI_VENDOR_ID_INTEL,
2030                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2031                 .subvendor      = PCI_ANY_ID,
2032                 .subdevice      = PCI_ANY_ID,
2033                 .setup          = ce4100_serial_setup,
2034         },
2035         {
2036                 .vendor         = PCI_VENDOR_ID_INTEL,
2037                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2038                 .subvendor      = PCI_ANY_ID,
2039                 .subdevice      = PCI_ANY_ID,
2040                 .setup          = kt_serial_setup,
2041         },
2042         {
2043                 .vendor         = PCI_VENDOR_ID_INTEL,
2044                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2045                 .subvendor      = PCI_ANY_ID,
2046                 .subdevice      = PCI_ANY_ID,
2047                 .setup          = byt_serial_setup,
2048         },
2049         {
2050                 .vendor         = PCI_VENDOR_ID_INTEL,
2051                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2052                 .subvendor      = PCI_ANY_ID,
2053                 .subdevice      = PCI_ANY_ID,
2054                 .setup          = byt_serial_setup,
2055         },
2056         {
2057                 .vendor         = PCI_VENDOR_ID_INTEL,
2058                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2059                 .subvendor      = PCI_ANY_ID,
2060                 .subdevice      = PCI_ANY_ID,
2061                 .setup          = byt_serial_setup,
2062         },
2063         {
2064                 .vendor         = PCI_VENDOR_ID_INTEL,
2065                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2066                 .subvendor      = PCI_ANY_ID,
2067                 .subdevice      = PCI_ANY_ID,
2068                 .setup          = byt_serial_setup,
2069         },
2070         {
2071                 .vendor         = PCI_VENDOR_ID_INTEL,
2072                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2073                 .subvendor      = PCI_ANY_ID,
2074                 .subdevice      = PCI_ANY_ID,
2075                 .setup          = byt_serial_setup,
2076         },
2077         {
2078                 .vendor         = PCI_VENDOR_ID_INTEL,
2079                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2080                 .subvendor      = PCI_ANY_ID,
2081                 .subdevice      = PCI_ANY_ID,
2082                 .setup          = byt_serial_setup,
2083         },
2084         /*
2085          * ITE
2086          */
2087         {
2088                 .vendor         = PCI_VENDOR_ID_ITE,
2089                 .device         = PCI_DEVICE_ID_ITE_8872,
2090                 .subvendor      = PCI_ANY_ID,
2091                 .subdevice      = PCI_ANY_ID,
2092                 .init           = pci_ite887x_init,
2093                 .setup          = pci_default_setup,
2094                 .exit           = pci_ite887x_exit,
2095         },
2096         /*
2097          * National Instruments
2098          */
2099         {
2100                 .vendor         = PCI_VENDOR_ID_NI,
2101                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2102                 .subvendor      = PCI_ANY_ID,
2103                 .subdevice      = PCI_ANY_ID,
2104                 .init           = pci_ni8420_init,
2105                 .setup          = pci_default_setup,
2106                 .exit           = pci_ni8420_exit,
2107         },
2108         {
2109                 .vendor         = PCI_VENDOR_ID_NI,
2110                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2111                 .subvendor      = PCI_ANY_ID,
2112                 .subdevice      = PCI_ANY_ID,
2113                 .init           = pci_ni8420_init,
2114                 .setup          = pci_default_setup,
2115                 .exit           = pci_ni8420_exit,
2116         },
2117         {
2118                 .vendor         = PCI_VENDOR_ID_NI,
2119                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2120                 .subvendor      = PCI_ANY_ID,
2121                 .subdevice      = PCI_ANY_ID,
2122                 .init           = pci_ni8420_init,
2123                 .setup          = pci_default_setup,
2124                 .exit           = pci_ni8420_exit,
2125         },
2126         {
2127                 .vendor         = PCI_VENDOR_ID_NI,
2128                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2129                 .subvendor      = PCI_ANY_ID,
2130                 .subdevice      = PCI_ANY_ID,
2131                 .init           = pci_ni8420_init,
2132                 .setup          = pci_default_setup,
2133                 .exit           = pci_ni8420_exit,
2134         },
2135         {
2136                 .vendor         = PCI_VENDOR_ID_NI,
2137                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2138                 .subvendor      = PCI_ANY_ID,
2139                 .subdevice      = PCI_ANY_ID,
2140                 .init           = pci_ni8420_init,
2141                 .setup          = pci_default_setup,
2142                 .exit           = pci_ni8420_exit,
2143         },
2144         {
2145                 .vendor         = PCI_VENDOR_ID_NI,
2146                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2147                 .subvendor      = PCI_ANY_ID,
2148                 .subdevice      = PCI_ANY_ID,
2149                 .init           = pci_ni8420_init,
2150                 .setup          = pci_default_setup,
2151                 .exit           = pci_ni8420_exit,
2152         },
2153         {
2154                 .vendor         = PCI_VENDOR_ID_NI,
2155                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2156                 .subvendor      = PCI_ANY_ID,
2157                 .subdevice      = PCI_ANY_ID,
2158                 .init           = pci_ni8420_init,
2159                 .setup          = pci_default_setup,
2160                 .exit           = pci_ni8420_exit,
2161         },
2162         {
2163                 .vendor         = PCI_VENDOR_ID_NI,
2164                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2165                 .subvendor      = PCI_ANY_ID,
2166                 .subdevice      = PCI_ANY_ID,
2167                 .init           = pci_ni8420_init,
2168                 .setup          = pci_default_setup,
2169                 .exit           = pci_ni8420_exit,
2170         },
2171         {
2172                 .vendor         = PCI_VENDOR_ID_NI,
2173                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2174                 .subvendor      = PCI_ANY_ID,
2175                 .subdevice      = PCI_ANY_ID,
2176                 .init           = pci_ni8420_init,
2177                 .setup          = pci_default_setup,
2178                 .exit           = pci_ni8420_exit,
2179         },
2180         {
2181                 .vendor         = PCI_VENDOR_ID_NI,
2182                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2183                 .subvendor      = PCI_ANY_ID,
2184                 .subdevice      = PCI_ANY_ID,
2185                 .init           = pci_ni8420_init,
2186                 .setup          = pci_default_setup,
2187                 .exit           = pci_ni8420_exit,
2188         },
2189         {
2190                 .vendor         = PCI_VENDOR_ID_NI,
2191                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2192                 .subvendor      = PCI_ANY_ID,
2193                 .subdevice      = PCI_ANY_ID,
2194                 .init           = pci_ni8420_init,
2195                 .setup          = pci_default_setup,
2196                 .exit           = pci_ni8420_exit,
2197         },
2198         {
2199                 .vendor         = PCI_VENDOR_ID_NI,
2200                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2201                 .subvendor      = PCI_ANY_ID,
2202                 .subdevice      = PCI_ANY_ID,
2203                 .init           = pci_ni8420_init,
2204                 .setup          = pci_default_setup,
2205                 .exit           = pci_ni8420_exit,
2206         },
2207         {
2208                 .vendor         = PCI_VENDOR_ID_NI,
2209                 .device         = PCI_ANY_ID,
2210                 .subvendor      = PCI_ANY_ID,
2211                 .subdevice      = PCI_ANY_ID,
2212                 .init           = pci_ni8430_init,
2213                 .setup          = pci_ni8430_setup,
2214                 .exit           = pci_ni8430_exit,
2215         },
2216         /* Quatech */
2217         {
2218                 .vendor         = PCI_VENDOR_ID_QUATECH,
2219                 .device         = PCI_ANY_ID,
2220                 .subvendor      = PCI_ANY_ID,
2221                 .subdevice      = PCI_ANY_ID,
2222                 .init           = pci_quatech_init,
2223                 .setup          = pci_quatech_setup,
2224                 .exit           = pci_quatech_exit,
2225         },
2226         /*
2227          * Panacom
2228          */
2229         {
2230                 .vendor         = PCI_VENDOR_ID_PANACOM,
2231                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2232                 .subvendor      = PCI_ANY_ID,
2233                 .subdevice      = PCI_ANY_ID,
2234                 .init           = pci_plx9050_init,
2235                 .setup          = pci_default_setup,
2236                 .exit           = pci_plx9050_exit,
2237         },
2238         {
2239                 .vendor         = PCI_VENDOR_ID_PANACOM,
2240                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2241                 .subvendor      = PCI_ANY_ID,
2242                 .subdevice      = PCI_ANY_ID,
2243                 .init           = pci_plx9050_init,
2244                 .setup          = pci_default_setup,
2245                 .exit           = pci_plx9050_exit,
2246         },
2247         /*
2248          * Pericom
2249          */
2250         {
2251                 .vendor         = PCI_VENDOR_ID_PERICOM,
2252                 .device         = PCI_ANY_ID,
2253                 .subvendor      = PCI_ANY_ID,
2254                 .subdevice      = PCI_ANY_ID,
2255                 .setup          = pci_pericom_setup,
2256         },
2257         /*
2258          * PLX
2259          */
2260         {
2261                 .vendor         = PCI_VENDOR_ID_PLX,
2262                 .device         = PCI_DEVICE_ID_PLX_9050,
2263                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2264                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2265                 .init           = pci_plx9050_init,
2266                 .setup          = pci_default_setup,
2267                 .exit           = pci_plx9050_exit,
2268         },
2269         {
2270                 .vendor         = PCI_VENDOR_ID_PLX,
2271                 .device         = PCI_DEVICE_ID_PLX_9050,
2272                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2273                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2274                 .init           = pci_plx9050_init,
2275                 .setup          = pci_default_setup,
2276                 .exit           = pci_plx9050_exit,
2277         },
2278         {
2279                 .vendor         = PCI_VENDOR_ID_PLX,
2280                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2281                 .subvendor      = PCI_VENDOR_ID_PLX,
2282                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2283                 .init           = pci_plx9050_init,
2284                 .setup          = pci_default_setup,
2285                 .exit           = pci_plx9050_exit,
2286         },
2287         /*
2288          * SBS Technologies, Inc., PMC-OCTALPRO 232
2289          */
2290         {
2291                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2292                 .device         = PCI_DEVICE_ID_OCTPRO,
2293                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2294                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2295                 .init           = sbs_init,
2296                 .setup          = sbs_setup,
2297                 .exit           = sbs_exit,
2298         },
2299         /*
2300          * SBS Technologies, Inc., PMC-OCTALPRO 422
2301          */
2302         {
2303                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2304                 .device         = PCI_DEVICE_ID_OCTPRO,
2305                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2306                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2307                 .init           = sbs_init,
2308                 .setup          = sbs_setup,
2309                 .exit           = sbs_exit,
2310         },
2311         /*
2312          * SBS Technologies, Inc., P-Octal 232
2313          */
2314         {
2315                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2316                 .device         = PCI_DEVICE_ID_OCTPRO,
2317                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2318                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2319                 .init           = sbs_init,
2320                 .setup          = sbs_setup,
2321                 .exit           = sbs_exit,
2322         },
2323         /*
2324          * SBS Technologies, Inc., P-Octal 422
2325          */
2326         {
2327                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2328                 .device         = PCI_DEVICE_ID_OCTPRO,
2329                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2330                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2331                 .init           = sbs_init,
2332                 .setup          = sbs_setup,
2333                 .exit           = sbs_exit,
2334         },
2335         /*
2336          * SIIG cards - these may be called via parport_serial
2337          */
2338         {
2339                 .vendor         = PCI_VENDOR_ID_SIIG,
2340                 .device         = PCI_ANY_ID,
2341                 .subvendor      = PCI_ANY_ID,
2342                 .subdevice      = PCI_ANY_ID,
2343                 .init           = pci_siig_init,
2344                 .setup          = pci_siig_setup,
2345         },
2346         /*
2347          * Titan cards
2348          */
2349         {
2350                 .vendor         = PCI_VENDOR_ID_TITAN,
2351                 .device         = PCI_DEVICE_ID_TITAN_400L,
2352                 .subvendor      = PCI_ANY_ID,
2353                 .subdevice      = PCI_ANY_ID,
2354                 .setup          = titan_400l_800l_setup,
2355         },
2356         {
2357                 .vendor         = PCI_VENDOR_ID_TITAN,
2358                 .device         = PCI_DEVICE_ID_TITAN_800L,
2359                 .subvendor      = PCI_ANY_ID,
2360                 .subdevice      = PCI_ANY_ID,
2361                 .setup          = titan_400l_800l_setup,
2362         },
2363         /*
2364          * Timedia cards
2365          */
2366         {
2367                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2368                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2369                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2370                 .subdevice      = PCI_ANY_ID,
2371                 .probe          = pci_timedia_probe,
2372                 .init           = pci_timedia_init,
2373                 .setup          = pci_timedia_setup,
2374         },
2375         {
2376                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2377                 .device         = PCI_ANY_ID,
2378                 .subvendor      = PCI_ANY_ID,
2379                 .subdevice      = PCI_ANY_ID,
2380                 .setup          = pci_timedia_setup,
2381         },
2382         /*
2383          * SUNIX (Timedia) cards
2384          * Do not "probe" for these cards as there is at least one combination
2385          * card that should be handled by parport_pc that doesn't match the
2386          * rule in pci_timedia_probe.
2387          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2388          * There are some boards with part number SER5037AL that report
2389          * subdevice ID 0x0002.
2390          */
2391         {
2392                 .vendor         = PCI_VENDOR_ID_SUNIX,
2393                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2394                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2395                 .subdevice      = PCI_ANY_ID,
2396                 .init           = pci_timedia_init,
2397                 .setup          = pci_timedia_setup,
2398         },
2399         /*
2400          * Exar cards
2401          */
2402         {
2403                 .vendor = PCI_VENDOR_ID_EXAR,
2404                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2405                 .subvendor      = PCI_ANY_ID,
2406                 .subdevice      = PCI_ANY_ID,
2407                 .setup          = pci_xr17c154_setup,
2408         },
2409         {
2410                 .vendor = PCI_VENDOR_ID_EXAR,
2411                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2412                 .subvendor      = PCI_ANY_ID,
2413                 .subdevice      = PCI_ANY_ID,
2414                 .setup          = pci_xr17c154_setup,
2415         },
2416         {
2417                 .vendor = PCI_VENDOR_ID_EXAR,
2418                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2419                 .subvendor      = PCI_ANY_ID,
2420                 .subdevice      = PCI_ANY_ID,
2421                 .setup          = pci_xr17c154_setup,
2422         },
2423         {
2424                 .vendor = PCI_VENDOR_ID_EXAR,
2425                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2426                 .subvendor      = PCI_ANY_ID,
2427                 .subdevice      = PCI_ANY_ID,
2428                 .setup          = pci_xr17v35x_setup,
2429         },
2430         {
2431                 .vendor = PCI_VENDOR_ID_EXAR,
2432                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2433                 .subvendor      = PCI_ANY_ID,
2434                 .subdevice      = PCI_ANY_ID,
2435                 .setup          = pci_xr17v35x_setup,
2436         },
2437         {
2438                 .vendor = PCI_VENDOR_ID_EXAR,
2439                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2440                 .subvendor      = PCI_ANY_ID,
2441                 .subdevice      = PCI_ANY_ID,
2442                 .setup          = pci_xr17v35x_setup,
2443         },
2444         {
2445                 .vendor = PCI_VENDOR_ID_EXAR,
2446                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2447                 .subvendor      = PCI_ANY_ID,
2448                 .subdevice      = PCI_ANY_ID,
2449                 .setup          = pci_xr17v35x_setup,
2450         },
2451         {
2452                 .vendor = PCI_VENDOR_ID_EXAR,
2453                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2454                 .subvendor      = PCI_ANY_ID,
2455                 .subdevice      = PCI_ANY_ID,
2456                 .setup          = pci_xr17v35x_setup,
2457         },
2458         /*
2459          * Xircom cards
2460          */
2461         {
2462                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2463                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2464                 .subvendor      = PCI_ANY_ID,
2465                 .subdevice      = PCI_ANY_ID,
2466                 .init           = pci_xircom_init,
2467                 .setup          = pci_default_setup,
2468         },
2469         /*
2470          * Netmos cards - these may be called via parport_serial
2471          */
2472         {
2473                 .vendor         = PCI_VENDOR_ID_NETMOS,
2474                 .device         = PCI_ANY_ID,
2475                 .subvendor      = PCI_ANY_ID,
2476                 .subdevice      = PCI_ANY_ID,
2477                 .init           = pci_netmos_init,
2478                 .setup          = pci_netmos_9900_setup,
2479         },
2480         /*
2481          * EndRun Technologies
2482         */
2483         {
2484                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2485                 .device         = PCI_ANY_ID,
2486                 .subvendor      = PCI_ANY_ID,
2487                 .subdevice      = PCI_ANY_ID,
2488                 .init           = pci_endrun_init,
2489                 .setup          = pci_default_setup,
2490         },
2491         /*
2492          * For Oxford Semiconductor Tornado based devices
2493          */
2494         {
2495                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2496                 .device         = PCI_ANY_ID,
2497                 .subvendor      = PCI_ANY_ID,
2498                 .subdevice      = PCI_ANY_ID,
2499                 .init           = pci_oxsemi_tornado_init,
2500                 .setup          = pci_default_setup,
2501         },
2502         {
2503                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2504                 .device         = PCI_ANY_ID,
2505                 .subvendor      = PCI_ANY_ID,
2506                 .subdevice      = PCI_ANY_ID,
2507                 .init           = pci_oxsemi_tornado_init,
2508                 .setup          = pci_default_setup,
2509         },
2510         {
2511                 .vendor         = PCI_VENDOR_ID_DIGI,
2512                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2513                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2514                 .subdevice              = PCI_ANY_ID,
2515                 .init                   = pci_oxsemi_tornado_init,
2516                 .setup          = pci_default_setup,
2517         },
2518         {
2519                 .vendor         = PCI_VENDOR_ID_INTEL,
2520                 .device         = 0x8811,
2521                 .subvendor      = PCI_ANY_ID,
2522                 .subdevice      = PCI_ANY_ID,
2523                 .init           = pci_eg20t_init,
2524                 .setup          = pci_default_setup,
2525         },
2526         {
2527                 .vendor         = PCI_VENDOR_ID_INTEL,
2528                 .device         = 0x8812,
2529                 .subvendor      = PCI_ANY_ID,
2530                 .subdevice      = PCI_ANY_ID,
2531                 .init           = pci_eg20t_init,
2532                 .setup          = pci_default_setup,
2533         },
2534         {
2535                 .vendor         = PCI_VENDOR_ID_INTEL,
2536                 .device         = 0x8813,
2537                 .subvendor      = PCI_ANY_ID,
2538                 .subdevice      = PCI_ANY_ID,
2539                 .init           = pci_eg20t_init,
2540                 .setup          = pci_default_setup,
2541         },
2542         {
2543                 .vendor         = PCI_VENDOR_ID_INTEL,
2544                 .device         = 0x8814,
2545                 .subvendor      = PCI_ANY_ID,
2546                 .subdevice      = PCI_ANY_ID,
2547                 .init           = pci_eg20t_init,
2548                 .setup          = pci_default_setup,
2549         },
2550         {
2551                 .vendor         = 0x10DB,
2552                 .device         = 0x8027,
2553                 .subvendor      = PCI_ANY_ID,
2554                 .subdevice      = PCI_ANY_ID,
2555                 .init           = pci_eg20t_init,
2556                 .setup          = pci_default_setup,
2557         },
2558         {
2559                 .vendor         = 0x10DB,
2560                 .device         = 0x8028,
2561                 .subvendor      = PCI_ANY_ID,
2562                 .subdevice      = PCI_ANY_ID,
2563                 .init           = pci_eg20t_init,
2564                 .setup          = pci_default_setup,
2565         },
2566         {
2567                 .vendor         = 0x10DB,
2568                 .device         = 0x8029,
2569                 .subvendor      = PCI_ANY_ID,
2570                 .subdevice      = PCI_ANY_ID,
2571                 .init           = pci_eg20t_init,
2572                 .setup          = pci_default_setup,
2573         },
2574         {
2575                 .vendor         = 0x10DB,
2576                 .device         = 0x800C,
2577                 .subvendor      = PCI_ANY_ID,
2578                 .subdevice      = PCI_ANY_ID,
2579                 .init           = pci_eg20t_init,
2580                 .setup          = pci_default_setup,
2581         },
2582         {
2583                 .vendor         = 0x10DB,
2584                 .device         = 0x800D,
2585                 .subvendor      = PCI_ANY_ID,
2586                 .subdevice      = PCI_ANY_ID,
2587                 .init           = pci_eg20t_init,
2588                 .setup          = pci_default_setup,
2589         },
2590         /*
2591          * Cronyx Omega PCI (PLX-chip based)
2592          */
2593         {
2594                 .vendor         = PCI_VENDOR_ID_PLX,
2595                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2596                 .subvendor      = PCI_ANY_ID,
2597                 .subdevice      = PCI_ANY_ID,
2598                 .setup          = pci_omegapci_setup,
2599         },
2600         /* WCH CH353 1S1P card (16550 clone) */
2601         {
2602                 .vendor         = PCI_VENDOR_ID_WCH,
2603                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2604                 .subvendor      = PCI_ANY_ID,
2605                 .subdevice      = PCI_ANY_ID,
2606                 .setup          = pci_wch_ch353_setup,
2607         },
2608         /* WCH CH353 2S1P card (16550 clone) */
2609         {
2610                 .vendor         = PCI_VENDOR_ID_WCH,
2611                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2612                 .subvendor      = PCI_ANY_ID,
2613                 .subdevice      = PCI_ANY_ID,
2614                 .setup          = pci_wch_ch353_setup,
2615         },
2616         /* WCH CH353 4S card (16550 clone) */
2617         {
2618                 .vendor         = PCI_VENDOR_ID_WCH,
2619                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2620                 .subvendor      = PCI_ANY_ID,
2621                 .subdevice      = PCI_ANY_ID,
2622                 .setup          = pci_wch_ch353_setup,
2623         },
2624         /* WCH CH353 2S1PF card (16550 clone) */
2625         {
2626                 .vendor         = PCI_VENDOR_ID_WCH,
2627                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2628                 .subvendor      = PCI_ANY_ID,
2629                 .subdevice      = PCI_ANY_ID,
2630                 .setup          = pci_wch_ch353_setup,
2631         },
2632         /* WCH CH352 2S card (16550 clone) */
2633         {
2634                 .vendor         = PCI_VENDOR_ID_WCH,
2635                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2636                 .subvendor      = PCI_ANY_ID,
2637                 .subdevice      = PCI_ANY_ID,
2638                 .setup          = pci_wch_ch353_setup,
2639         },
2640         /* WCH CH382 2S1P card (16850 clone) */
2641         {
2642                 .vendor         = PCIE_VENDOR_ID_WCH,
2643                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2644                 .subvendor      = PCI_ANY_ID,
2645                 .subdevice      = PCI_ANY_ID,
2646                 .setup          = pci_wch_ch38x_setup,
2647         },
2648         /* WCH CH384 4S card (16850 clone) */
2649         {
2650                 .vendor         = PCIE_VENDOR_ID_WCH,
2651                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2652                 .subvendor      = PCI_ANY_ID,
2653                 .subdevice      = PCI_ANY_ID,
2654                 .setup          = pci_wch_ch38x_setup,
2655         },
2656         /*
2657          * ASIX devices with FIFO bug
2658          */
2659         {
2660                 .vendor         = PCI_VENDOR_ID_ASIX,
2661                 .device         = PCI_ANY_ID,
2662                 .subvendor      = PCI_ANY_ID,
2663                 .subdevice      = PCI_ANY_ID,
2664                 .setup          = pci_asix_setup,
2665         },
2666         /*
2667          * Commtech, Inc. Fastcom adapters
2668          *
2669          */
2670         {
2671                 .vendor = PCI_VENDOR_ID_COMMTECH,
2672                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2673                 .subvendor      = PCI_ANY_ID,
2674                 .subdevice      = PCI_ANY_ID,
2675                 .setup          = pci_fastcom335_setup,
2676         },
2677         {
2678                 .vendor = PCI_VENDOR_ID_COMMTECH,
2679                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2680                 .subvendor      = PCI_ANY_ID,
2681                 .subdevice      = PCI_ANY_ID,
2682                 .setup          = pci_fastcom335_setup,
2683         },
2684         {
2685                 .vendor = PCI_VENDOR_ID_COMMTECH,
2686                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2687                 .subvendor      = PCI_ANY_ID,
2688                 .subdevice      = PCI_ANY_ID,
2689                 .setup          = pci_fastcom335_setup,
2690         },
2691         {
2692                 .vendor = PCI_VENDOR_ID_COMMTECH,
2693                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2694                 .subvendor      = PCI_ANY_ID,
2695                 .subdevice      = PCI_ANY_ID,
2696                 .setup          = pci_fastcom335_setup,
2697         },
2698         {
2699                 .vendor = PCI_VENDOR_ID_COMMTECH,
2700                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2701                 .subvendor      = PCI_ANY_ID,
2702                 .subdevice      = PCI_ANY_ID,
2703                 .setup          = pci_xr17v35x_setup,
2704         },
2705         {
2706                 .vendor = PCI_VENDOR_ID_COMMTECH,
2707                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2708                 .subvendor      = PCI_ANY_ID,
2709                 .subdevice      = PCI_ANY_ID,
2710                 .setup          = pci_xr17v35x_setup,
2711         },
2712         {
2713                 .vendor = PCI_VENDOR_ID_COMMTECH,
2714                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2715                 .subvendor      = PCI_ANY_ID,
2716                 .subdevice      = PCI_ANY_ID,
2717                 .setup          = pci_xr17v35x_setup,
2718         },
2719         /*
2720          * Broadcom TruManage (NetXtreme)
2721          */
2722         {
2723                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2724                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2725                 .subvendor      = PCI_ANY_ID,
2726                 .subdevice      = PCI_ANY_ID,
2727                 .setup          = pci_brcm_trumanage_setup,
2728         },
2729         {
2730                 .vendor         = 0x1c29,
2731                 .device         = 0x1104,
2732                 .subvendor      = PCI_ANY_ID,
2733                 .subdevice      = PCI_ANY_ID,
2734                 .setup          = pci_fintek_setup,
2735                 .init           = pci_fintek_init,
2736         },
2737         {
2738                 .vendor         = 0x1c29,
2739                 .device         = 0x1108,
2740                 .subvendor      = PCI_ANY_ID,
2741                 .subdevice      = PCI_ANY_ID,
2742                 .setup          = pci_fintek_setup,
2743                 .init           = pci_fintek_init,
2744         },
2745         {
2746                 .vendor         = 0x1c29,
2747                 .device         = 0x1112,
2748                 .subvendor      = PCI_ANY_ID,
2749                 .subdevice      = PCI_ANY_ID,
2750                 .setup          = pci_fintek_setup,
2751                 .init           = pci_fintek_init,
2752         },
2753
2754         /*
2755          * Default "match everything" terminator entry
2756          */
2757         {
2758                 .vendor         = PCI_ANY_ID,
2759                 .device         = PCI_ANY_ID,
2760                 .subvendor      = PCI_ANY_ID,
2761                 .subdevice      = PCI_ANY_ID,
2762                 .setup          = pci_default_setup,
2763         }
2764 };
2765
2766 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2767 {
2768         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2769 }
2770
2771 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2772 {
2773         struct pci_serial_quirk *quirk;
2774
2775         for (quirk = pci_serial_quirks; ; quirk++)
2776                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2777                     quirk_id_matches(quirk->device, dev->device) &&
2778                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2779                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2780                         break;
2781         return quirk;
2782 }
2783
2784 static inline int get_pci_irq(struct pci_dev *dev,
2785                                 const struct pciserial_board *board)
2786 {
2787         if (board->flags & FL_NOIRQ)
2788                 return 0;
2789         else
2790                 return dev->irq;
2791 }
2792
2793 /*
2794  * This is the configuration table for all of the PCI serial boards
2795  * which we support.  It is directly indexed by the pci_board_num_t enum
2796  * value, which is encoded in the pci_device_id PCI probe table's
2797  * driver_data member.
2798  *
2799  * The makeup of these names are:
2800  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2801  *
2802  *  bn          = PCI BAR number
2803  *  bt          = Index using PCI BARs
2804  *  n           = number of serial ports
2805  *  baud        = baud rate
2806  *  offsetinhex = offset for each sequential port (in hex)
2807  *
2808  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2809  *
2810  * Please note: in theory if n = 1, _bt infix should make no difference.
2811  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2812  */
2813 enum pci_board_num_t {
2814         pbn_default = 0,
2815
2816         pbn_b0_1_115200,
2817         pbn_b0_2_115200,
2818         pbn_b0_4_115200,
2819         pbn_b0_5_115200,
2820         pbn_b0_8_115200,
2821
2822         pbn_b0_1_921600,
2823         pbn_b0_2_921600,
2824         pbn_b0_4_921600,
2825
2826         pbn_b0_2_1130000,
2827
2828         pbn_b0_4_1152000,
2829
2830         pbn_b0_2_1152000_200,
2831         pbn_b0_4_1152000_200,
2832         pbn_b0_8_1152000_200,
2833
2834         pbn_b0_2_1843200,
2835         pbn_b0_4_1843200,
2836
2837         pbn_b0_2_1843200_200,
2838         pbn_b0_4_1843200_200,
2839         pbn_b0_8_1843200_200,
2840
2841         pbn_b0_1_4000000,
2842
2843         pbn_b0_bt_1_115200,
2844         pbn_b0_bt_2_115200,
2845         pbn_b0_bt_4_115200,
2846         pbn_b0_bt_8_115200,
2847
2848         pbn_b0_bt_1_460800,
2849         pbn_b0_bt_2_460800,
2850         pbn_b0_bt_4_460800,
2851
2852         pbn_b0_bt_1_921600,
2853         pbn_b0_bt_2_921600,
2854         pbn_b0_bt_4_921600,
2855         pbn_b0_bt_8_921600,
2856
2857         pbn_b1_1_115200,
2858         pbn_b1_2_115200,
2859         pbn_b1_4_115200,
2860         pbn_b1_8_115200,
2861         pbn_b1_16_115200,
2862
2863         pbn_b1_1_921600,
2864         pbn_b1_2_921600,
2865         pbn_b1_4_921600,
2866         pbn_b1_8_921600,
2867
2868         pbn_b1_2_1250000,
2869
2870         pbn_b1_bt_1_115200,
2871         pbn_b1_bt_2_115200,
2872         pbn_b1_bt_4_115200,
2873
2874         pbn_b1_bt_2_921600,
2875
2876         pbn_b1_1_1382400,
2877         pbn_b1_2_1382400,
2878         pbn_b1_4_1382400,
2879         pbn_b1_8_1382400,
2880
2881         pbn_b2_1_115200,
2882         pbn_b2_2_115200,
2883         pbn_b2_4_115200,
2884         pbn_b2_8_115200,
2885
2886         pbn_b2_1_460800,
2887         pbn_b2_4_460800,
2888         pbn_b2_8_460800,
2889         pbn_b2_16_460800,
2890
2891         pbn_b2_1_921600,
2892         pbn_b2_4_921600,
2893         pbn_b2_8_921600,
2894
2895         pbn_b2_8_1152000,
2896
2897         pbn_b2_bt_1_115200,
2898         pbn_b2_bt_2_115200,
2899         pbn_b2_bt_4_115200,
2900
2901         pbn_b2_bt_2_921600,
2902         pbn_b2_bt_4_921600,
2903
2904         pbn_b3_2_115200,
2905         pbn_b3_4_115200,
2906         pbn_b3_8_115200,
2907
2908         pbn_b4_bt_2_921600,
2909         pbn_b4_bt_4_921600,
2910         pbn_b4_bt_8_921600,
2911
2912         /*
2913          * Board-specific versions.
2914          */
2915         pbn_panacom,
2916         pbn_panacom2,
2917         pbn_panacom4,
2918         pbn_plx_romulus,
2919         pbn_endrun_2_4000000,
2920         pbn_oxsemi,
2921         pbn_oxsemi_1_4000000,
2922         pbn_oxsemi_2_4000000,
2923         pbn_oxsemi_4_4000000,
2924         pbn_oxsemi_8_4000000,
2925         pbn_intel_i960,
2926         pbn_sgi_ioc3,
2927         pbn_computone_4,
2928         pbn_computone_6,
2929         pbn_computone_8,
2930         pbn_sbsxrsio,
2931         pbn_exar_XR17C152,
2932         pbn_exar_XR17C154,
2933         pbn_exar_XR17C158,
2934         pbn_exar_XR17V352,
2935         pbn_exar_XR17V354,
2936         pbn_exar_XR17V358,
2937         pbn_exar_XR17V4358,
2938         pbn_exar_XR17V8358,
2939         pbn_exar_ibm_saturn,
2940         pbn_pasemi_1682M,
2941         pbn_ni8430_2,
2942         pbn_ni8430_4,
2943         pbn_ni8430_8,
2944         pbn_ni8430_16,
2945         pbn_ADDIDATA_PCIe_1_3906250,
2946         pbn_ADDIDATA_PCIe_2_3906250,
2947         pbn_ADDIDATA_PCIe_4_3906250,
2948         pbn_ADDIDATA_PCIe_8_3906250,
2949         pbn_ce4100_1_115200,
2950         pbn_byt,
2951         pbn_qrk,
2952         pbn_omegapci,
2953         pbn_NETMOS9900_2s_115200,
2954         pbn_brcm_trumanage,
2955         pbn_fintek_4,
2956         pbn_fintek_8,
2957         pbn_fintek_12,
2958         pbn_wch384_4,
2959         pbn_pericom_PI7C9X7951,
2960         pbn_pericom_PI7C9X7952,
2961         pbn_pericom_PI7C9X7954,
2962         pbn_pericom_PI7C9X7958,
2963 };
2964
2965 /*
2966  * uart_offset - the space between channels
2967  * reg_shift   - describes how the UART registers are mapped
2968  *               to PCI memory by the card.
2969  * For example IER register on SBS, Inc. PMC-OctPro is located at
2970  * offset 0x10 from the UART base, while UART_IER is defined as 1
2971  * in include/linux/serial_reg.h,
2972  * see first lines of serial_in() and serial_out() in 8250.c
2973 */
2974
2975 static struct pciserial_board pci_boards[] = {
2976         [pbn_default] = {
2977                 .flags          = FL_BASE0,
2978                 .num_ports      = 1,
2979                 .base_baud      = 115200,
2980                 .uart_offset    = 8,
2981         },
2982         [pbn_b0_1_115200] = {
2983                 .flags          = FL_BASE0,
2984                 .num_ports      = 1,
2985                 .base_baud      = 115200,
2986                 .uart_offset    = 8,
2987         },
2988         [pbn_b0_2_115200] = {
2989                 .flags          = FL_BASE0,
2990                 .num_ports      = 2,
2991                 .base_baud      = 115200,
2992                 .uart_offset    = 8,
2993         },
2994         [pbn_b0_4_115200] = {
2995                 .flags          = FL_BASE0,
2996                 .num_ports      = 4,
2997                 .base_baud      = 115200,
2998                 .uart_offset    = 8,
2999         },
3000         [pbn_b0_5_115200] = {
3001                 .flags          = FL_BASE0,
3002                 .num_ports      = 5,
3003                 .base_baud      = 115200,
3004                 .uart_offset    = 8,
3005         },
3006         [pbn_b0_8_115200] = {
3007                 .flags          = FL_BASE0,
3008                 .num_ports      = 8,
3009                 .base_baud      = 115200,
3010                 .uart_offset    = 8,
3011         },
3012         [pbn_b0_1_921600] = {
3013                 .flags          = FL_BASE0,
3014                 .num_ports      = 1,
3015                 .base_baud      = 921600,
3016                 .uart_offset    = 8,
3017         },
3018         [pbn_b0_2_921600] = {
3019                 .flags          = FL_BASE0,
3020                 .num_ports      = 2,
3021                 .base_baud      = 921600,
3022                 .uart_offset    = 8,
3023         },
3024         [pbn_b0_4_921600] = {
3025                 .flags          = FL_BASE0,
3026                 .num_ports      = 4,
3027                 .base_baud      = 921600,
3028                 .uart_offset    = 8,
3029         },
3030
3031         [pbn_b0_2_1130000] = {
3032                 .flags          = FL_BASE0,
3033                 .num_ports      = 2,
3034                 .base_baud      = 1130000,
3035                 .uart_offset    = 8,
3036         },
3037
3038         [pbn_b0_4_1152000] = {
3039                 .flags          = FL_BASE0,
3040                 .num_ports      = 4,
3041                 .base_baud      = 1152000,
3042                 .uart_offset    = 8,
3043         },
3044
3045         [pbn_b0_2_1152000_200] = {
3046                 .flags          = FL_BASE0,
3047                 .num_ports      = 2,
3048                 .base_baud      = 1152000,
3049                 .uart_offset    = 0x200,
3050         },
3051
3052         [pbn_b0_4_1152000_200] = {
3053                 .flags          = FL_BASE0,
3054                 .num_ports      = 4,
3055                 .base_baud      = 1152000,
3056                 .uart_offset    = 0x200,
3057         },
3058
3059         [pbn_b0_8_1152000_200] = {
3060                 .flags          = FL_BASE0,
3061                 .num_ports      = 8,
3062                 .base_baud      = 1152000,
3063                 .uart_offset    = 0x200,
3064         },
3065
3066         [pbn_b0_2_1843200] = {
3067                 .flags          = FL_BASE0,
3068                 .num_ports      = 2,
3069                 .base_baud      = 1843200,
3070                 .uart_offset    = 8,
3071         },
3072         [pbn_b0_4_1843200] = {
3073                 .flags          = FL_BASE0,
3074                 .num_ports      = 4,
3075                 .base_baud      = 1843200,
3076                 .uart_offset    = 8,
3077         },
3078
3079         [pbn_b0_2_1843200_200] = {
3080                 .flags          = FL_BASE0,
3081                 .num_ports      = 2,
3082                 .base_baud      = 1843200,
3083                 .uart_offset    = 0x200,
3084         },
3085         [pbn_b0_4_1843200_200] = {
3086                 .flags          = FL_BASE0,
3087                 .num_ports      = 4,
3088                 .base_baud      = 1843200,
3089                 .uart_offset    = 0x200,
3090         },
3091         [pbn_b0_8_1843200_200] = {
3092                 .flags          = FL_BASE0,
3093                 .num_ports      = 8,
3094                 .base_baud      = 1843200,
3095                 .uart_offset    = 0x200,
3096         },
3097         [pbn_b0_1_4000000] = {
3098                 .flags          = FL_BASE0,
3099                 .num_ports      = 1,
3100                 .base_baud      = 4000000,
3101                 .uart_offset    = 8,
3102         },
3103
3104         [pbn_b0_bt_1_115200] = {
3105                 .flags          = FL_BASE0|FL_BASE_BARS,
3106                 .num_ports      = 1,
3107                 .base_baud      = 115200,
3108                 .uart_offset    = 8,
3109         },
3110         [pbn_b0_bt_2_115200] = {
3111                 .flags          = FL_BASE0|FL_BASE_BARS,
3112                 .num_ports      = 2,
3113                 .base_baud      = 115200,
3114                 .uart_offset    = 8,
3115         },
3116         [pbn_b0_bt_4_115200] = {
3117                 .flags          = FL_BASE0|FL_BASE_BARS,
3118                 .num_ports      = 4,
3119                 .base_baud      = 115200,
3120                 .uart_offset    = 8,
3121         },
3122         [pbn_b0_bt_8_115200] = {
3123                 .flags          = FL_BASE0|FL_BASE_BARS,
3124                 .num_ports      = 8,
3125                 .base_baud      = 115200,
3126                 .uart_offset    = 8,
3127         },
3128
3129         [pbn_b0_bt_1_460800] = {
3130                 .flags          = FL_BASE0|FL_BASE_BARS,
3131                 .num_ports      = 1,
3132                 .base_baud      = 460800,
3133                 .uart_offset    = 8,
3134         },
3135         [pbn_b0_bt_2_460800] = {
3136                 .flags          = FL_BASE0|FL_BASE_BARS,
3137                 .num_ports      = 2,
3138                 .base_baud      = 460800,
3139                 .uart_offset    = 8,
3140         },
3141         [pbn_b0_bt_4_460800] = {
3142                 .flags          = FL_BASE0|FL_BASE_BARS,
3143                 .num_ports      = 4,
3144                 .base_baud      = 460800,
3145                 .uart_offset    = 8,
3146         },
3147
3148         [pbn_b0_bt_1_921600] = {
3149                 .flags          = FL_BASE0|FL_BASE_BARS,
3150                 .num_ports      = 1,
3151                 .base_baud      = 921600,
3152                 .uart_offset    = 8,
3153         },
3154         [pbn_b0_bt_2_921600] = {
3155                 .flags          = FL_BASE0|FL_BASE_BARS,
3156                 .num_ports      = 2,
3157                 .base_baud      = 921600,
3158                 .uart_offset    = 8,
3159         },
3160         [pbn_b0_bt_4_921600] = {
3161                 .flags          = FL_BASE0|FL_BASE_BARS,
3162                 .num_ports      = 4,
3163                 .base_baud      = 921600,
3164                 .uart_offset    = 8,
3165         },
3166         [pbn_b0_bt_8_921600] = {
3167                 .flags          = FL_BASE0|FL_BASE_BARS,
3168                 .num_ports      = 8,
3169                 .base_baud      = 921600,
3170                 .uart_offset    = 8,
3171         },
3172
3173         [pbn_b1_1_115200] = {
3174                 .flags          = FL_BASE1,
3175                 .num_ports      = 1,
3176                 .base_baud      = 115200,
3177                 .uart_offset    = 8,
3178         },
3179         [pbn_b1_2_115200] = {
3180                 .flags          = FL_BASE1,
3181                 .num_ports      = 2,
3182                 .base_baud      = 115200,
3183                 .uart_offset    = 8,
3184         },
3185         [pbn_b1_4_115200] = {
3186                 .flags          = FL_BASE1,
3187                 .num_ports      = 4,
3188                 .base_baud      = 115200,
3189                 .uart_offset    = 8,
3190         },
3191         [pbn_b1_8_115200] = {
3192                 .flags          = FL_BASE1,
3193                 .num_ports      = 8,
3194                 .base_baud      = 115200,
3195                 .uart_offset    = 8,
3196         },
3197         [pbn_b1_16_115200] = {
3198                 .flags          = FL_BASE1,
3199                 .num_ports      = 16,
3200                 .base_baud      = 115200,
3201                 .uart_offset    = 8,
3202         },
3203
3204         [pbn_b1_1_921600] = {
3205                 .flags          = FL_BASE1,
3206                 .num_ports      = 1,
3207                 .base_baud      = 921600,
3208                 .uart_offset    = 8,
3209         },
3210         [pbn_b1_2_921600] = {
3211                 .flags          = FL_BASE1,
3212                 .num_ports      = 2,
3213                 .base_baud      = 921600,
3214                 .uart_offset    = 8,
3215         },
3216         [pbn_b1_4_921600] = {
3217                 .flags          = FL_BASE1,
3218                 .num_ports      = 4,
3219                 .base_baud      = 921600,
3220                 .uart_offset    = 8,
3221         },
3222         [pbn_b1_8_921600] = {
3223                 .flags          = FL_BASE1,
3224                 .num_ports      = 8,
3225                 .base_baud      = 921600,
3226                 .uart_offset    = 8,
3227         },
3228         [pbn_b1_2_1250000] = {
3229                 .flags          = FL_BASE1,
3230                 .num_ports      = 2,
3231                 .base_baud      = 1250000,
3232                 .uart_offset    = 8,
3233         },
3234
3235         [pbn_b1_bt_1_115200] = {
3236                 .flags          = FL_BASE1|FL_BASE_BARS,
3237                 .num_ports      = 1,
3238                 .base_baud      = 115200,
3239                 .uart_offset    = 8,
3240         },
3241         [pbn_b1_bt_2_115200] = {
3242                 .flags          = FL_BASE1|FL_BASE_BARS,
3243                 .num_ports      = 2,
3244                 .base_baud      = 115200,
3245                 .uart_offset    = 8,
3246         },
3247         [pbn_b1_bt_4_115200] = {
3248                 .flags          = FL_BASE1|FL_BASE_BARS,
3249                 .num_ports      = 4,
3250                 .base_baud      = 115200,
3251                 .uart_offset    = 8,
3252         },
3253
3254         [pbn_b1_bt_2_921600] = {
3255                 .flags          = FL_BASE1|FL_BASE_BARS,
3256                 .num_ports      = 2,
3257                 .base_baud      = 921600,
3258                 .uart_offset    = 8,
3259         },
3260
3261         [pbn_b1_1_1382400] = {
3262                 .flags          = FL_BASE1,
3263                 .num_ports      = 1,
3264                 .base_baud      = 1382400,
3265                 .uart_offset    = 8,
3266         },
3267         [pbn_b1_2_1382400] = {
3268                 .flags          = FL_BASE1,
3269                 .num_ports      = 2,
3270                 .base_baud      = 1382400,
3271                 .uart_offset    = 8,
3272         },
3273         [pbn_b1_4_1382400] = {
3274                 .flags          = FL_BASE1,
3275                 .num_ports      = 4,
3276                 .base_baud      = 1382400,
3277                 .uart_offset    = 8,
3278         },
3279         [pbn_b1_8_1382400] = {
3280                 .flags          = FL_BASE1,
3281                 .num_ports      = 8,
3282                 .base_baud      = 1382400,
3283                 .uart_offset    = 8,
3284         },
3285
3286         [pbn_b2_1_115200] = {
3287                 .flags          = FL_BASE2,
3288                 .num_ports      = 1,
3289                 .base_baud      = 115200,
3290                 .uart_offset    = 8,
3291         },
3292         [pbn_b2_2_115200] = {
3293                 .flags          = FL_BASE2,
3294                 .num_ports      = 2,
3295                 .base_baud      = 115200,
3296                 .uart_offset    = 8,
3297         },
3298         [pbn_b2_4_115200] = {
3299                 .flags          = FL_BASE2,
3300                 .num_ports      = 4,
3301                 .base_baud      = 115200,
3302                 .uart_offset    = 8,
3303         },
3304         [pbn_b2_8_115200] = {
3305                 .flags          = FL_BASE2,
3306                 .num_ports      = 8,
3307                 .base_baud      = 115200,
3308                 .uart_offset    = 8,
3309         },
3310
3311         [pbn_b2_1_460800] = {
3312                 .flags          = FL_BASE2,
3313                 .num_ports      = 1,
3314                 .base_baud      = 460800,
3315                 .uart_offset    = 8,
3316         },
3317         [pbn_b2_4_460800] = {
3318                 .flags          = FL_BASE2,
3319                 .num_ports      = 4,
3320                 .base_baud      = 460800,
3321                 .uart_offset    = 8,
3322         },
3323         [pbn_b2_8_460800] = {
3324                 .flags          = FL_BASE2,
3325                 .num_ports      = 8,
3326                 .base_baud      = 460800,
3327                 .uart_offset    = 8,
3328         },
3329         [pbn_b2_16_460800] = {
3330                 .flags          = FL_BASE2,
3331                 .num_ports      = 16,
3332                 .base_baud      = 460800,
3333                 .uart_offset    = 8,
3334          },
3335
3336         [pbn_b2_1_921600] = {
3337                 .flags          = FL_BASE2,
3338                 .num_ports      = 1,
3339                 .base_baud      = 921600,
3340                 .uart_offset    = 8,
3341         },
3342         [pbn_b2_4_921600] = {
3343                 .flags          = FL_BASE2,
3344                 .num_ports      = 4,
3345                 .base_baud      = 921600,
3346                 .uart_offset    = 8,
3347         },
3348         [pbn_b2_8_921600] = {
3349                 .flags          = FL_BASE2,
3350                 .num_ports      = 8,
3351                 .base_baud      = 921600,
3352                 .uart_offset    = 8,
3353         },
3354
3355         [pbn_b2_8_1152000] = {
3356                 .flags          = FL_BASE2,
3357                 .num_ports      = 8,
3358                 .base_baud      = 1152000,
3359                 .uart_offset    = 8,
3360         },
3361
3362         [pbn_b2_bt_1_115200] = {
3363                 .flags          = FL_BASE2|FL_BASE_BARS,
3364                 .num_ports      = 1,
3365                 .base_baud      = 115200,
3366                 .uart_offset    = 8,
3367         },
3368         [pbn_b2_bt_2_115200] = {
3369                 .flags          = FL_BASE2|FL_BASE_BARS,
3370                 .num_ports      = 2,
3371                 .base_baud      = 115200,
3372                 .uart_offset    = 8,
3373         },
3374         [pbn_b2_bt_4_115200] = {
3375                 .flags          = FL_BASE2|FL_BASE_BARS,
3376                 .num_ports      = 4,
3377                 .base_baud      = 115200,
3378                 .uart_offset    = 8,
3379         },
3380
3381         [pbn_b2_bt_2_921600] = {
3382                 .flags          = FL_BASE2|FL_BASE_BARS,
3383                 .num_ports      = 2,
3384                 .base_baud      = 921600,
3385                 .uart_offset    = 8,
3386         },
3387         [pbn_b2_bt_4_921600] = {
3388                 .flags          = FL_BASE2|FL_BASE_BARS,
3389                 .num_ports      = 4,
3390                 .base_baud      = 921600,
3391                 .uart_offset    = 8,
3392         },
3393
3394         [pbn_b3_2_115200] = {
3395                 .flags          = FL_BASE3,
3396                 .num_ports      = 2,
3397                 .base_baud      = 115200,
3398                 .uart_offset    = 8,
3399         },
3400         [pbn_b3_4_115200] = {
3401                 .flags          = FL_BASE3,
3402                 .num_ports      = 4,
3403                 .base_baud      = 115200,
3404                 .uart_offset    = 8,
3405         },
3406         [pbn_b3_8_115200] = {
3407                 .flags          = FL_BASE3,
3408                 .num_ports      = 8,
3409                 .base_baud      = 115200,
3410                 .uart_offset    = 8,
3411         },
3412
3413         [pbn_b4_bt_2_921600] = {
3414                 .flags          = FL_BASE4,
3415                 .num_ports      = 2,
3416                 .base_baud      = 921600,
3417                 .uart_offset    = 8,
3418         },
3419         [pbn_b4_bt_4_921600] = {
3420                 .flags          = FL_BASE4,
3421                 .num_ports      = 4,
3422                 .base_baud      = 921600,
3423                 .uart_offset    = 8,
3424         },
3425         [pbn_b4_bt_8_921600] = {
3426                 .flags          = FL_BASE4,
3427                 .num_ports      = 8,
3428                 .base_baud      = 921600,
3429                 .uart_offset    = 8,
3430         },
3431
3432         /*
3433          * Entries following this are board-specific.
3434          */
3435
3436         /*
3437          * Panacom - IOMEM
3438          */
3439         [pbn_panacom] = {
3440                 .flags          = FL_BASE2,
3441                 .num_ports      = 2,
3442                 .base_baud      = 921600,
3443                 .uart_offset    = 0x400,
3444                 .reg_shift      = 7,
3445         },
3446         [pbn_panacom2] = {
3447                 .flags          = FL_BASE2|FL_BASE_BARS,
3448                 .num_ports      = 2,
3449                 .base_baud      = 921600,
3450                 .uart_offset    = 0x400,
3451                 .reg_shift      = 7,
3452         },
3453         [pbn_panacom4] = {
3454                 .flags          = FL_BASE2|FL_BASE_BARS,
3455                 .num_ports      = 4,
3456                 .base_baud      = 921600,
3457                 .uart_offset    = 0x400,
3458                 .reg_shift      = 7,
3459         },
3460
3461         /* I think this entry is broken - the first_offset looks wrong --rmk */
3462         [pbn_plx_romulus] = {
3463                 .flags          = FL_BASE2,
3464                 .num_ports      = 4,
3465                 .base_baud      = 921600,
3466                 .uart_offset    = 8 << 2,
3467                 .reg_shift      = 2,
3468                 .first_offset   = 0x03,
3469         },
3470
3471         /*
3472          * EndRun Technologies
3473         * Uses the size of PCI Base region 0 to
3474         * signal now many ports are available
3475         * 2 port 952 Uart support
3476         */
3477         [pbn_endrun_2_4000000] = {
3478                 .flags          = FL_BASE0,
3479                 .num_ports      = 2,
3480                 .base_baud      = 4000000,
3481                 .uart_offset    = 0x200,
3482                 .first_offset   = 0x1000,
3483         },
3484
3485         /*
3486          * This board uses the size of PCI Base region 0 to
3487          * signal now many ports are available
3488          */
3489         [pbn_oxsemi] = {
3490                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3491                 .num_ports      = 32,
3492                 .base_baud      = 115200,
3493                 .uart_offset    = 8,
3494         },
3495         [pbn_oxsemi_1_4000000] = {
3496                 .flags          = FL_BASE0,
3497                 .num_ports      = 1,
3498                 .base_baud      = 4000000,
3499                 .uart_offset    = 0x200,
3500                 .first_offset   = 0x1000,
3501         },
3502         [pbn_oxsemi_2_4000000] = {
3503                 .flags          = FL_BASE0,
3504                 .num_ports      = 2,
3505                 .base_baud      = 4000000,
3506                 .uart_offset    = 0x200,
3507                 .first_offset   = 0x1000,
3508         },
3509         [pbn_oxsemi_4_4000000] = {
3510                 .flags          = FL_BASE0,
3511                 .num_ports      = 4,
3512                 .base_baud      = 4000000,
3513                 .uart_offset    = 0x200,
3514                 .first_offset   = 0x1000,
3515         },
3516         [pbn_oxsemi_8_4000000] = {
3517                 .flags          = FL_BASE0,
3518                 .num_ports      = 8,
3519                 .base_baud      = 4000000,
3520                 .uart_offset    = 0x200,
3521                 .first_offset   = 0x1000,
3522         },
3523
3524
3525         /*
3526          * EKF addition for i960 Boards form EKF with serial port.
3527          * Max 256 ports.
3528          */
3529         [pbn_intel_i960] = {
3530                 .flags          = FL_BASE0,
3531                 .num_ports      = 32,
3532                 .base_baud      = 921600,
3533                 .uart_offset    = 8 << 2,
3534                 .reg_shift      = 2,
3535                 .first_offset   = 0x10000,
3536         },
3537         [pbn_sgi_ioc3] = {
3538                 .flags          = FL_BASE0|FL_NOIRQ,
3539                 .num_ports      = 1,
3540                 .base_baud      = 458333,
3541                 .uart_offset    = 8,
3542                 .reg_shift      = 0,
3543                 .first_offset   = 0x20178,
3544         },
3545
3546         /*
3547          * Computone - uses IOMEM.
3548          */
3549         [pbn_computone_4] = {
3550                 .flags          = FL_BASE0,
3551                 .num_ports      = 4,
3552                 .base_baud      = 921600,
3553                 .uart_offset    = 0x40,
3554                 .reg_shift      = 2,
3555                 .first_offset   = 0x200,
3556         },
3557         [pbn_computone_6] = {
3558                 .flags          = FL_BASE0,
3559                 .num_ports      = 6,
3560                 .base_baud      = 921600,
3561                 .uart_offset    = 0x40,
3562                 .reg_shift      = 2,
3563                 .first_offset   = 0x200,
3564         },
3565         [pbn_computone_8] = {
3566                 .flags          = FL_BASE0,
3567                 .num_ports      = 8,
3568                 .base_baud      = 921600,
3569                 .uart_offset    = 0x40,
3570                 .reg_shift      = 2,
3571                 .first_offset   = 0x200,
3572         },
3573         [pbn_sbsxrsio] = {
3574                 .flags          = FL_BASE0,
3575                 .num_ports      = 8,
3576                 .base_baud      = 460800,
3577                 .uart_offset    = 256,
3578                 .reg_shift      = 4,
3579         },
3580         /*
3581          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3582          *  Only basic 16550A support.
3583          *  XR17C15[24] are not tested, but they should work.
3584          */
3585         [pbn_exar_XR17C152] = {
3586                 .flags          = FL_BASE0,
3587                 .num_ports      = 2,
3588                 .base_baud      = 921600,
3589                 .uart_offset    = 0x200,
3590         },
3591         [pbn_exar_XR17C154] = {
3592                 .flags          = FL_BASE0,
3593                 .num_ports      = 4,
3594                 .base_baud      = 921600,
3595                 .uart_offset    = 0x200,
3596         },
3597         [pbn_exar_XR17C158] = {
3598                 .flags          = FL_BASE0,
3599                 .num_ports      = 8,
3600                 .base_baud      = 921600,
3601                 .uart_offset    = 0x200,
3602         },
3603         [pbn_exar_XR17V352] = {
3604                 .flags          = FL_BASE0,
3605                 .num_ports      = 2,
3606                 .base_baud      = 7812500,
3607                 .uart_offset    = 0x400,
3608                 .reg_shift      = 0,
3609                 .first_offset   = 0,
3610         },
3611         [pbn_exar_XR17V354] = {
3612                 .flags          = FL_BASE0,
3613                 .num_ports      = 4,
3614                 .base_baud      = 7812500,
3615                 .uart_offset    = 0x400,
3616                 .reg_shift      = 0,
3617                 .first_offset   = 0,
3618         },
3619         [pbn_exar_XR17V358] = {
3620                 .flags          = FL_BASE0,
3621                 .num_ports      = 8,
3622                 .base_baud      = 7812500,
3623                 .uart_offset    = 0x400,
3624                 .reg_shift      = 0,
3625                 .first_offset   = 0,
3626         },
3627         [pbn_exar_XR17V4358] = {
3628                 .flags          = FL_BASE0,
3629                 .num_ports      = 12,
3630                 .base_baud      = 7812500,
3631                 .uart_offset    = 0x400,
3632                 .reg_shift      = 0,
3633                 .first_offset   = 0,
3634         },
3635         [pbn_exar_XR17V8358] = {
3636                 .flags          = FL_BASE0,
3637                 .num_ports      = 16,
3638                 .base_baud      = 7812500,
3639                 .uart_offset    = 0x400,
3640                 .reg_shift      = 0,
3641                 .first_offset   = 0,
3642         },
3643         [pbn_exar_ibm_saturn] = {
3644                 .flags          = FL_BASE0,
3645                 .num_ports      = 1,
3646                 .base_baud      = 921600,
3647                 .uart_offset    = 0x200,
3648         },
3649
3650         /*
3651          * PA Semi PWRficient PA6T-1682M on-chip UART
3652          */
3653         [pbn_pasemi_1682M] = {
3654                 .flags          = FL_BASE0,
3655                 .num_ports      = 1,
3656                 .base_baud      = 8333333,
3657         },
3658         /*
3659          * National Instruments 843x
3660          */
3661         [pbn_ni8430_16] = {
3662                 .flags          = FL_BASE0,
3663                 .num_ports      = 16,
3664                 .base_baud      = 3686400,
3665                 .uart_offset    = 0x10,
3666                 .first_offset   = 0x800,
3667         },
3668         [pbn_ni8430_8] = {
3669                 .flags          = FL_BASE0,
3670                 .num_ports      = 8,
3671                 .base_baud      = 3686400,
3672                 .uart_offset    = 0x10,
3673                 .first_offset   = 0x800,
3674         },
3675         [pbn_ni8430_4] = {
3676                 .flags          = FL_BASE0,
3677                 .num_ports      = 4,
3678                 .base_baud      = 3686400,
3679                 .uart_offset    = 0x10,
3680                 .first_offset   = 0x800,
3681         },
3682         [pbn_ni8430_2] = {
3683                 .flags          = FL_BASE0,
3684                 .num_ports      = 2,
3685                 .base_baud      = 3686400,
3686                 .uart_offset    = 0x10,
3687                 .first_offset   = 0x800,
3688         },
3689         /*
3690          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3691          */
3692         [pbn_ADDIDATA_PCIe_1_3906250] = {
3693                 .flags          = FL_BASE0,
3694                 .num_ports      = 1,
3695                 .base_baud      = 3906250,
3696                 .uart_offset    = 0x200,
3697                 .first_offset   = 0x1000,
3698         },
3699         [pbn_ADDIDATA_PCIe_2_3906250] = {
3700                 .flags          = FL_BASE0,
3701                 .num_ports      = 2,
3702                 .base_baud      = 3906250,
3703                 .uart_offset    = 0x200,
3704                 .first_offset   = 0x1000,
3705         },
3706         [pbn_ADDIDATA_PCIe_4_3906250] = {
3707                 .flags          = FL_BASE0,
3708                 .num_ports      = 4,
3709                 .base_baud      = 3906250,
3710                 .uart_offset    = 0x200,
3711                 .first_offset   = 0x1000,
3712         },
3713         [pbn_ADDIDATA_PCIe_8_3906250] = {
3714                 .flags          = FL_BASE0,
3715                 .num_ports      = 8,
3716                 .base_baud      = 3906250,
3717                 .uart_offset    = 0x200,
3718                 .first_offset   = 0x1000,
3719         },
3720         [pbn_ce4100_1_115200] = {
3721                 .flags          = FL_BASE_BARS,
3722                 .num_ports      = 2,
3723                 .base_baud      = 921600,
3724                 .reg_shift      = 2,
3725         },
3726         /*
3727          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3728          * but is overridden by byt_set_termios.
3729          */
3730         [pbn_byt] = {
3731                 .flags          = FL_BASE0,
3732                 .num_ports      = 1,
3733                 .base_baud      = 2764800,
3734                 .uart_offset    = 0x80,
3735                 .reg_shift      = 2,
3736         },
3737         [pbn_qrk] = {
3738                 .flags          = FL_BASE0,
3739                 .num_ports      = 1,
3740                 .base_baud      = 2764800,
3741                 .reg_shift      = 2,
3742         },
3743         [pbn_omegapci] = {
3744                 .flags          = FL_BASE0,
3745                 .num_ports      = 8,
3746                 .base_baud      = 115200,
3747                 .uart_offset    = 0x200,
3748         },
3749         [pbn_NETMOS9900_2s_115200] = {
3750                 .flags          = FL_BASE0,
3751                 .num_ports      = 2,
3752                 .base_baud      = 115200,
3753         },
3754         [pbn_brcm_trumanage] = {
3755                 .flags          = FL_BASE0,
3756                 .num_ports      = 1,
3757                 .reg_shift      = 2,
3758                 .base_baud      = 115200,
3759         },
3760         [pbn_fintek_4] = {
3761                 .num_ports      = 4,
3762                 .uart_offset    = 8,
3763                 .base_baud      = 115200,
3764                 .first_offset   = 0x40,
3765         },
3766         [pbn_fintek_8] = {
3767                 .num_ports      = 8,
3768                 .uart_offset    = 8,
3769                 .base_baud      = 115200,
3770                 .first_offset   = 0x40,
3771         },
3772         [pbn_fintek_12] = {
3773                 .num_ports      = 12,
3774                 .uart_offset    = 8,
3775                 .base_baud      = 115200,
3776                 .first_offset   = 0x40,
3777         },
3778         [pbn_wch384_4] = {
3779                 .flags          = FL_BASE0,
3780                 .num_ports      = 4,
3781                 .base_baud      = 115200,
3782                 .uart_offset    = 8,
3783                 .first_offset   = 0xC0,
3784         },
3785         /*
3786          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3787          */
3788         [pbn_pericom_PI7C9X7951] = {
3789                 .flags          = FL_BASE0,
3790                 .num_ports      = 1,
3791                 .base_baud      = 921600,
3792                 .uart_offset    = 0x8,
3793         },
3794         [pbn_pericom_PI7C9X7952] = {
3795                 .flags          = FL_BASE0,
3796                 .num_ports      = 2,
3797                 .base_baud      = 921600,
3798                 .uart_offset    = 0x8,
3799         },
3800         [pbn_pericom_PI7C9X7954] = {
3801                 .flags          = FL_BASE0,
3802                 .num_ports      = 4,
3803                 .base_baud      = 921600,
3804                 .uart_offset    = 0x8,
3805         },
3806         [pbn_pericom_PI7C9X7958] = {
3807                 .flags          = FL_BASE0,
3808                 .num_ports      = 8,
3809                 .base_baud      = 921600,
3810                 .uart_offset    = 0x8,
3811         },
3812 };
3813
3814 static const struct pci_device_id blacklist[] = {
3815         /* softmodems */
3816         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3817         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3818         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3819
3820         /* multi-io cards handled by parport_serial */
3821         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3822         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3823         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3824         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3825
3826         /* Intel platforms with MID UART */
3827         { PCI_VDEVICE(INTEL, 0x081b), },
3828         { PCI_VDEVICE(INTEL, 0x081c), },
3829         { PCI_VDEVICE(INTEL, 0x081d), },
3830         { PCI_VDEVICE(INTEL, 0x1191), },
3831         { PCI_VDEVICE(INTEL, 0x19d8), },
3832 };
3833
3834 /*
3835  * Given a complete unknown PCI device, try to use some heuristics to
3836  * guess what the configuration might be, based on the pitiful PCI
3837  * serial specs.  Returns 0 on success, 1 on failure.
3838  */
3839 static int
3840 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3841 {
3842         const struct pci_device_id *bldev;
3843         int num_iomem, num_port, first_port = -1, i;
3844
3845         /*
3846          * If it is not a communications device or the programming
3847          * interface is greater than 6, give up.
3848          *
3849          * (Should we try to make guesses for multiport serial devices
3850          * later?)
3851          */
3852         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3853              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3854             (dev->class & 0xff) > 6)
3855                 return -ENODEV;
3856
3857         /*
3858          * Do not access blacklisted devices that are known not to
3859          * feature serial ports or are handled by other modules.
3860          */
3861         for (bldev = blacklist;
3862              bldev < blacklist + ARRAY_SIZE(blacklist);
3863              bldev++) {
3864                 if (dev->vendor == bldev->vendor &&
3865                     dev->device == bldev->device)
3866                         return -ENODEV;
3867         }
3868
3869         num_iomem = num_port = 0;
3870         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3871                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3872                         num_port++;
3873                         if (first_port == -1)
3874                                 first_port = i;
3875                 }
3876                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3877                         num_iomem++;
3878         }
3879
3880         /*
3881          * If there is 1 or 0 iomem regions, and exactly one port,
3882          * use it.  We guess the number of ports based on the IO
3883          * region size.
3884          */
3885         if (num_iomem <= 1 && num_port == 1) {
3886                 board->flags = first_port;
3887                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3888                 return 0;
3889         }
3890
3891         /*
3892          * Now guess if we've got a board which indexes by BARs.
3893          * Each IO BAR should be 8 bytes, and they should follow
3894          * consecutively.
3895          */
3896         first_port = -1;
3897         num_port = 0;
3898         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3899                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3900                     pci_resource_len(dev, i) == 8 &&
3901                     (first_port == -1 || (first_port + num_port) == i)) {
3902                         num_port++;
3903                         if (first_port == -1)
3904                                 first_port = i;
3905                 }
3906         }
3907
3908         if (num_port > 1) {
3909                 board->flags = first_port | FL_BASE_BARS;
3910                 board->num_ports = num_port;
3911                 return 0;
3912         }
3913
3914         return -ENODEV;
3915 }
3916
3917 static inline int
3918 serial_pci_matches(const struct pciserial_board *board,
3919                    const struct pciserial_board *guessed)
3920 {
3921         return
3922             board->num_ports == guessed->num_ports &&
3923             board->base_baud == guessed->base_baud &&
3924             board->uart_offset == guessed->uart_offset &&
3925             board->reg_shift == guessed->reg_shift &&
3926             board->first_offset == guessed->first_offset;
3927 }
3928
3929 struct serial_private *
3930 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3931 {
3932         struct uart_8250_port uart;
3933         struct serial_private *priv;
3934         struct pci_serial_quirk *quirk;
3935         int rc, nr_ports, i;
3936
3937         nr_ports = board->num_ports;
3938
3939         /*
3940          * Find an init and setup quirks.
3941          */
3942         quirk = find_quirk(dev);
3943
3944         /*
3945          * Run the new-style initialization function.
3946          * The initialization function returns:
3947          *  <0  - error
3948          *   0  - use board->num_ports
3949          *  >0  - number of ports
3950          */
3951         if (quirk->init) {
3952                 rc = quirk->init(dev);
3953                 if (rc < 0) {
3954                         priv = ERR_PTR(rc);
3955                         goto err_out;
3956                 }
3957                 if (rc)
3958                         nr_ports = rc;
3959         }
3960
3961         priv = kzalloc(sizeof(struct serial_private) +
3962                        sizeof(unsigned int) * nr_ports,
3963                        GFP_KERNEL);
3964         if (!priv) {
3965                 priv = ERR_PTR(-ENOMEM);
3966                 goto err_deinit;
3967         }
3968
3969         priv->dev = dev;
3970         priv->quirk = quirk;
3971
3972         memset(&uart, 0, sizeof(uart));
3973         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3974         uart.port.uartclk = board->base_baud * 16;
3975         uart.port.irq = get_pci_irq(dev, board);
3976         uart.port.dev = &dev->dev;
3977
3978         for (i = 0; i < nr_ports; i++) {
3979                 if (quirk->setup(priv, board, &uart, i))
3980                         break;
3981
3982                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3983                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3984
3985                 priv->line[i] = serial8250_register_8250_port(&uart);
3986                 if (priv->line[i] < 0) {
3987                         dev_err(&dev->dev,
3988                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3989                                 uart.port.iobase, uart.port.irq,
3990                                 uart.port.iotype, priv->line[i]);
3991                         break;
3992                 }
3993         }
3994         priv->nr = i;
3995         return priv;
3996
3997 err_deinit:
3998         if (quirk->exit)
3999                 quirk->exit(dev);
4000 err_out:
4001         return priv;
4002 }
4003 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4004
4005 void pciserial_remove_ports(struct serial_private *priv)
4006 {
4007         struct pci_serial_quirk *quirk;
4008         int i;
4009
4010         for (i = 0; i < priv->nr; i++)
4011                 serial8250_unregister_port(priv->line[i]);
4012
4013         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4014                 if (priv->remapped_bar[i])
4015                         iounmap(priv->remapped_bar[i]);
4016                 priv->remapped_bar[i] = NULL;
4017         }
4018
4019         /*
4020          * Find the exit quirks.
4021          */
4022         quirk = find_quirk(priv->dev);
4023         if (quirk->exit)
4024                 quirk->exit(priv->dev);
4025
4026         kfree(priv);
4027 }
4028 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4029
4030 void pciserial_suspend_ports(struct serial_private *priv)
4031 {
4032         int i;
4033
4034         for (i = 0; i < priv->nr; i++)
4035                 if (priv->line[i] >= 0)
4036                         serial8250_suspend_port(priv->line[i]);
4037
4038         /*
4039          * Ensure that every init quirk is properly torn down
4040          */
4041         if (priv->quirk->exit)
4042                 priv->quirk->exit(priv->dev);
4043 }
4044 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4045
4046 void pciserial_resume_ports(struct serial_private *priv)
4047 {
4048         int i;
4049
4050         /*
4051          * Ensure that the board is correctly configured.
4052          */
4053         if (priv->quirk->init)
4054                 priv->quirk->init(priv->dev);
4055
4056         for (i = 0; i < priv->nr; i++)
4057                 if (priv->line[i] >= 0)
4058                         serial8250_resume_port(priv->line[i]);
4059 }
4060 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4061
4062 /*
4063  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4064  * to the arrangement of serial ports on a PCI card.
4065  */
4066 static int
4067 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4068 {
4069         struct pci_serial_quirk *quirk;
4070         struct serial_private *priv;
4071         const struct pciserial_board *board;
4072         struct pciserial_board tmp;
4073         int rc;
4074
4075         quirk = find_quirk(dev);
4076         if (quirk->probe) {
4077                 rc = quirk->probe(dev);
4078                 if (rc)
4079                         return rc;
4080         }
4081
4082         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4083                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4084                         ent->driver_data);
4085                 return -EINVAL;
4086         }
4087
4088         board = &pci_boards[ent->driver_data];
4089
4090         rc = pci_enable_device(dev);
4091         pci_save_state(dev);
4092         if (rc)
4093                 return rc;
4094
4095         if (ent->driver_data == pbn_default) {
4096                 /*
4097                  * Use a copy of the pci_board entry for this;
4098                  * avoid changing entries in the table.
4099                  */
4100                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4101                 board = &tmp;
4102
4103                 /*
4104                  * We matched one of our class entries.  Try to
4105                  * determine the parameters of this board.
4106                  */
4107                 rc = serial_pci_guess_board(dev, &tmp);
4108                 if (rc)
4109                         goto disable;
4110         } else {
4111                 /*
4112                  * We matched an explicit entry.  If we are able to
4113                  * detect this boards settings with our heuristic,
4114                  * then we no longer need this entry.
4115                  */
4116                 memcpy(&tmp, &pci_boards[pbn_default],
4117                        sizeof(struct pciserial_board));
4118                 rc = serial_pci_guess_board(dev, &tmp);
4119                 if (rc == 0 && serial_pci_matches(board, &tmp))
4120                         moan_device("Redundant entry in serial pci_table.",
4121                                     dev);
4122         }
4123
4124         priv = pciserial_init_ports(dev, board);
4125         if (!IS_ERR(priv)) {
4126                 pci_set_drvdata(dev, priv);
4127                 return 0;
4128         }
4129
4130         rc = PTR_ERR(priv);
4131
4132  disable:
4133         pci_disable_device(dev);
4134         return rc;
4135 }
4136
4137 static void pciserial_remove_one(struct pci_dev *dev)
4138 {
4139         struct serial_private *priv = pci_get_drvdata(dev);
4140
4141         pciserial_remove_ports(priv);
4142
4143         pci_disable_device(dev);
4144 }
4145
4146 #ifdef CONFIG_PM_SLEEP
4147 static int pciserial_suspend_one(struct device *dev)
4148 {
4149         struct pci_dev *pdev = to_pci_dev(dev);
4150         struct serial_private *priv = pci_get_drvdata(pdev);
4151
4152         if (priv)
4153                 pciserial_suspend_ports(priv);
4154
4155         return 0;
4156 }
4157
4158 static int pciserial_resume_one(struct device *dev)
4159 {
4160         struct pci_dev *pdev = to_pci_dev(dev);
4161         struct serial_private *priv = pci_get_drvdata(pdev);
4162         int err;
4163
4164         if (priv) {
4165                 /*
4166                  * The device may have been disabled.  Re-enable it.
4167                  */
4168                 err = pci_enable_device(pdev);
4169                 /* FIXME: We cannot simply error out here */
4170                 if (err)
4171                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4172                 pciserial_resume_ports(priv);
4173         }
4174         return 0;
4175 }
4176 #endif
4177
4178 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4179                          pciserial_resume_one);
4180
4181 static struct pci_device_id serial_pci_tbl[] = {
4182         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4183         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4184                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4185                 pbn_b2_8_921600 },
4186         /* Advantech also use 0x3618 and 0xf618 */
4187         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4188                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4189                 pbn_b0_4_921600 },
4190         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4191                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4192                 pbn_b0_4_921600 },
4193         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4194                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4195                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4196                 pbn_b1_8_1382400 },
4197         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4198                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4199                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4200                 pbn_b1_4_1382400 },
4201         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4202                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4203                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4204                 pbn_b1_2_1382400 },
4205         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4206                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4207                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4208                 pbn_b1_8_1382400 },
4209         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4210                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4211                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4212                 pbn_b1_4_1382400 },
4213         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4214                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4215                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4216                 pbn_b1_2_1382400 },
4217         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4218                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4219                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4220                 pbn_b1_8_921600 },
4221         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4222                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4223                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4224                 pbn_b1_8_921600 },
4225         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4226                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4227                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4228                 pbn_b1_4_921600 },
4229         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4230                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4231                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4232                 pbn_b1_4_921600 },
4233         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4234                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4235                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4236                 pbn_b1_2_921600 },
4237         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4238                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4239                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4240                 pbn_b1_8_921600 },
4241         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4242                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4243                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4244                 pbn_b1_8_921600 },
4245         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4246                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4247                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4248                 pbn_b1_4_921600 },
4249         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4250                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4251                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4252                 pbn_b1_2_1250000 },
4253         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4254                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4255                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4256                 pbn_b0_2_1843200 },
4257         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4258                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4259                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4260                 pbn_b0_4_1843200 },
4261         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4262                 PCI_VENDOR_ID_AFAVLAB,
4263                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4264                 pbn_b0_4_1152000 },
4265         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4266                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4267                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4268                 pbn_b0_2_1843200_200 },
4269         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4270                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4272                 pbn_b0_4_1843200_200 },
4273         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4274                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4276                 pbn_b0_8_1843200_200 },
4277         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4278                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4280                 pbn_b0_2_1843200_200 },
4281         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4282                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4283                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4284                 pbn_b0_4_1843200_200 },
4285         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4286                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4287                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4288                 pbn_b0_8_1843200_200 },
4289         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4290                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4291                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4292                 pbn_b0_2_1843200_200 },
4293         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4294                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4295                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4296                 pbn_b0_4_1843200_200 },
4297         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4298                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4299                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4300                 pbn_b0_8_1843200_200 },
4301         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4302                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4303                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4304                 pbn_b0_2_1843200_200 },
4305         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4306                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4307                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4308                 pbn_b0_4_1843200_200 },
4309         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4310                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4311                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4312                 pbn_b0_8_1843200_200 },
4313         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4314                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4315                 0, 0, pbn_exar_ibm_saturn },
4316
4317         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319                 pbn_b2_bt_1_115200 },
4320         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322                 pbn_b2_bt_2_115200 },
4323         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325                 pbn_b2_bt_4_115200 },
4326         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328                 pbn_b2_bt_2_115200 },
4329         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331                 pbn_b2_bt_4_115200 },
4332         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334                 pbn_b2_8_115200 },
4335         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337                 pbn_b2_8_460800 },
4338         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340                 pbn_b2_8_115200 },
4341
4342         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344                 pbn_b2_bt_2_115200 },
4345         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347                 pbn_b2_bt_2_921600 },
4348         /*
4349          * VScom SPCOM800, from sl@s.pl
4350          */
4351         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353                 pbn_b2_8_921600 },
4354         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356                 pbn_b2_4_921600 },
4357         /* Unknown card - subdevice 0x1584 */
4358         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4359                 PCI_VENDOR_ID_PLX,
4360                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4361                 pbn_b2_4_115200 },
4362         /* Unknown card - subdevice 0x1588 */
4363         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4364                 PCI_VENDOR_ID_PLX,
4365                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4366                 pbn_b2_8_115200 },
4367         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4368                 PCI_SUBVENDOR_ID_KEYSPAN,
4369                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4370                 pbn_panacom },
4371         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373                 pbn_panacom4 },
4374         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376                 pbn_panacom2 },
4377         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4378                 PCI_VENDOR_ID_ESDGMBH,
4379                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4380                 pbn_b2_4_115200 },
4381         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4382                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4383                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4384                 pbn_b2_4_460800 },
4385         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4386                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4387                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4388                 pbn_b2_8_460800 },
4389         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4390                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4391                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4392                 pbn_b2_16_460800 },
4393         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4394                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4395                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4396                 pbn_b2_16_460800 },
4397         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4398                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4399                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4400                 pbn_b2_4_460800 },
4401         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4402                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4403                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4404                 pbn_b2_8_460800 },
4405         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4406                 PCI_SUBVENDOR_ID_EXSYS,
4407                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4408                 pbn_b2_4_115200 },
4409         /*
4410          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4411          * (Exoray@isys.ca)
4412          */
4413         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4414                 0x10b5, 0x106a, 0, 0,
4415                 pbn_plx_romulus },
4416         /*
4417         * EndRun Technologies. PCI express device range.
4418         *    EndRun PTP/1588 has 2 Native UARTs.
4419         */
4420         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4421                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422                 pbn_endrun_2_4000000 },
4423         /*
4424          * Quatech cards. These actually have configurable clocks but for
4425          * now we just use the default.
4426          *
4427          * 100 series are RS232, 200 series RS422,
4428          */
4429         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4430                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431                 pbn_b1_4_115200 },
4432         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4433                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434                 pbn_b1_2_115200 },
4435         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4436                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437                 pbn_b2_2_115200 },
4438         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4439                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440                 pbn_b1_2_115200 },
4441         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443                 pbn_b2_2_115200 },
4444         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4445                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446                 pbn_b1_4_115200 },
4447         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449                 pbn_b1_8_115200 },
4450         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452                 pbn_b1_8_115200 },
4453         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455                 pbn_b1_4_115200 },
4456         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458                 pbn_b1_2_115200 },
4459         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461                 pbn_b1_4_115200 },
4462         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4463                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464                 pbn_b1_2_115200 },
4465         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467                 pbn_b2_4_115200 },
4468         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4469                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470                 pbn_b2_2_115200 },
4471         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4472                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473                 pbn_b2_1_115200 },
4474         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4475                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476                 pbn_b2_4_115200 },
4477         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4478                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479                 pbn_b2_2_115200 },
4480         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4481                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482                 pbn_b2_1_115200 },
4483         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4484                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485                 pbn_b0_8_115200 },
4486
4487         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4488                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4489                 0, 0,
4490                 pbn_b0_4_921600 },
4491         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4492                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4493                 0, 0,
4494                 pbn_b0_4_1152000 },
4495         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4496                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497                 pbn_b0_bt_2_921600 },
4498
4499                 /*
4500                  * The below card is a little controversial since it is the
4501                  * subject of a PCI vendor/device ID clash.  (See
4502                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4503                  * For now just used the hex ID 0x950a.
4504                  */
4505         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4506                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4507                 0, 0, pbn_b0_2_115200 },
4508         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4509                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4510                 0, 0, pbn_b0_2_115200 },
4511         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513                 pbn_b0_2_1130000 },
4514         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4515                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4516                 pbn_b0_1_921600 },
4517         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519                 pbn_b0_4_115200 },
4520         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522                 pbn_b0_bt_2_921600 },
4523         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4524                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4525                 pbn_b2_8_1152000 },
4526
4527         /*
4528          * Oxford Semiconductor Inc. Tornado PCI express device range.
4529          */
4530         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532                 pbn_b0_1_4000000 },
4533         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535                 pbn_b0_1_4000000 },
4536         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4537                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538                 pbn_oxsemi_1_4000000 },
4539         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541                 pbn_oxsemi_1_4000000 },
4542         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544                 pbn_b0_1_4000000 },
4545         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4546                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547                 pbn_b0_1_4000000 },
4548         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550                 pbn_oxsemi_1_4000000 },
4551         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553                 pbn_oxsemi_1_4000000 },
4554         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556                 pbn_b0_1_4000000 },
4557         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559                 pbn_b0_1_4000000 },
4560         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562                 pbn_b0_1_4000000 },
4563         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565                 pbn_b0_1_4000000 },
4566         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568                 pbn_oxsemi_2_4000000 },
4569         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571                 pbn_oxsemi_2_4000000 },
4572         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574                 pbn_oxsemi_4_4000000 },
4575         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577                 pbn_oxsemi_4_4000000 },
4578         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580                 pbn_oxsemi_8_4000000 },
4581         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583                 pbn_oxsemi_8_4000000 },
4584         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586                 pbn_oxsemi_1_4000000 },
4587         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589                 pbn_oxsemi_1_4000000 },
4590         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592                 pbn_oxsemi_1_4000000 },
4593         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595                 pbn_oxsemi_1_4000000 },
4596         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598                 pbn_oxsemi_1_4000000 },
4599         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601                 pbn_oxsemi_1_4000000 },
4602         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4603                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604                 pbn_oxsemi_1_4000000 },
4605         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4606                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607                 pbn_oxsemi_1_4000000 },
4608         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610                 pbn_oxsemi_1_4000000 },
4611         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613                 pbn_oxsemi_1_4000000 },
4614         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616                 pbn_oxsemi_1_4000000 },
4617         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619                 pbn_oxsemi_1_4000000 },
4620         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622                 pbn_oxsemi_1_4000000 },
4623         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625                 pbn_oxsemi_1_4000000 },
4626         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4627                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628                 pbn_oxsemi_1_4000000 },
4629         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4630                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631                 pbn_oxsemi_1_4000000 },
4632         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4633                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634                 pbn_oxsemi_1_4000000 },
4635         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4636                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637                 pbn_oxsemi_1_4000000 },
4638         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4639                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640                 pbn_oxsemi_1_4000000 },
4641         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4642                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643                 pbn_oxsemi_1_4000000 },
4644         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646                 pbn_oxsemi_1_4000000 },
4647         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649                 pbn_oxsemi_1_4000000 },
4650         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652                 pbn_oxsemi_1_4000000 },
4653         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655                 pbn_oxsemi_1_4000000 },
4656         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658                 pbn_oxsemi_1_4000000 },
4659         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661                 pbn_oxsemi_1_4000000 },
4662         /*
4663          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4664          */
4665         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4666                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4667                 pbn_oxsemi_1_4000000 },
4668         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4669                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4670                 pbn_oxsemi_2_4000000 },
4671         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4672                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4673                 pbn_oxsemi_4_4000000 },
4674         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4675                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4676                 pbn_oxsemi_8_4000000 },
4677
4678         /*
4679          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4680          */
4681         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4682                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4683                 pbn_oxsemi_2_4000000 },
4684
4685         /*
4686          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4687          * from skokodyn@yahoo.com
4688          */
4689         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4690                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4691                 pbn_sbsxrsio },
4692         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4693                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4694                 pbn_sbsxrsio },
4695         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4696                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4697                 pbn_sbsxrsio },
4698         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4699                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4700                 pbn_sbsxrsio },
4701
4702         /*
4703          * Digitan DS560-558, from jimd@esoft.com
4704          */
4705         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707                 pbn_b1_1_115200 },
4708
4709         /*
4710          * Titan Electronic cards
4711          *  The 400L and 800L have a custom setup quirk.
4712          */
4713         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4714                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715                 pbn_b0_1_921600 },
4716         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4717                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718                 pbn_b0_2_921600 },
4719         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4720                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721                 pbn_b0_4_921600 },
4722         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4723                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724                 pbn_b0_4_921600 },
4725         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4726                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727                 pbn_b1_1_921600 },
4728         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4729                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730                 pbn_b1_bt_2_921600 },
4731         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733                 pbn_b0_bt_4_921600 },
4734         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4735                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736                 pbn_b0_bt_8_921600 },
4737         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739                 pbn_b4_bt_2_921600 },
4740         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4741                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742                 pbn_b4_bt_4_921600 },
4743         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4744                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745                 pbn_b4_bt_8_921600 },
4746         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4747                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748                 pbn_b0_4_921600 },
4749         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4750                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751                 pbn_b0_4_921600 },
4752         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4753                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754                 pbn_b0_4_921600 },
4755         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4756                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757                 pbn_oxsemi_1_4000000 },
4758         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4759                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760                 pbn_oxsemi_2_4000000 },
4761         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4762                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763                 pbn_oxsemi_4_4000000 },
4764         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4765                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766                 pbn_oxsemi_8_4000000 },
4767         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4768                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769                 pbn_oxsemi_2_4000000 },
4770         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4771                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772                 pbn_oxsemi_2_4000000 },
4773         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4774                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775                 pbn_b0_bt_2_921600 },
4776         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4777                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778                 pbn_b0_4_921600 },
4779         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4780                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781                 pbn_b0_4_921600 },
4782         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784                 pbn_b0_4_921600 },
4785         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787                 pbn_b0_4_921600 },
4788
4789         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791                 pbn_b2_1_460800 },
4792         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794                 pbn_b2_1_460800 },
4795         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4796                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797                 pbn_b2_1_460800 },
4798         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800                 pbn_b2_bt_2_921600 },
4801         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803                 pbn_b2_bt_2_921600 },
4804         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806                 pbn_b2_bt_2_921600 },
4807         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4808                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809                 pbn_b2_bt_4_921600 },
4810         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4811                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812                 pbn_b2_bt_4_921600 },
4813         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4814                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815                 pbn_b2_bt_4_921600 },
4816         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818                 pbn_b0_1_921600 },
4819         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4821                 pbn_b0_1_921600 },
4822         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824                 pbn_b0_1_921600 },
4825         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827                 pbn_b0_bt_2_921600 },
4828         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830                 pbn_b0_bt_2_921600 },
4831         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833                 pbn_b0_bt_2_921600 },
4834         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836                 pbn_b0_bt_4_921600 },
4837         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839                 pbn_b0_bt_4_921600 },
4840         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842                 pbn_b0_bt_4_921600 },
4843         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845                 pbn_b0_bt_8_921600 },
4846         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848                 pbn_b0_bt_8_921600 },
4849         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851                 pbn_b0_bt_8_921600 },
4852
4853         /*
4854          * Computone devices submitted by Doug McNash dmcnash@computone.com
4855          */
4856         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4857                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4858                 0, 0, pbn_computone_4 },
4859         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4860                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4861                 0, 0, pbn_computone_8 },
4862         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4863                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4864                 0, 0, pbn_computone_6 },
4865
4866         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4867                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868                 pbn_oxsemi },
4869         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4870                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4871                 pbn_b0_bt_1_921600 },
4872
4873         /*
4874          * SUNIX (TIMEDIA)
4875          */
4876         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4877                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4878                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4879                 pbn_b0_bt_1_921600 },
4880
4881         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4882                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4883                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4884                 pbn_b0_bt_1_921600 },
4885
4886         /*
4887          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4888          */
4889         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891                 pbn_b0_bt_8_115200 },
4892         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894                 pbn_b0_bt_8_115200 },
4895
4896         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4897                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898                 pbn_b0_bt_2_115200 },
4899         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4900                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901                 pbn_b0_bt_2_115200 },
4902         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4903                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904                 pbn_b0_bt_2_115200 },
4905         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4906                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907                 pbn_b0_bt_2_115200 },
4908         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910                 pbn_b0_bt_2_115200 },
4911         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913                 pbn_b0_bt_4_460800 },
4914         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916                 pbn_b0_bt_4_460800 },
4917         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4918                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919                 pbn_b0_bt_2_460800 },
4920         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922                 pbn_b0_bt_2_460800 },
4923         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925                 pbn_b0_bt_2_460800 },
4926         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4927                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928                 pbn_b0_bt_1_115200 },
4929         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931                 pbn_b0_bt_1_460800 },
4932
4933         /*
4934          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4935          * Cards are identified by their subsystem vendor IDs, which
4936          * (in hex) match the model number.
4937          *
4938          * Note that JC140x are RS422/485 cards which require ox950
4939          * ACR = 0x10, and as such are not currently fully supported.
4940          */
4941         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4942                 0x1204, 0x0004, 0, 0,
4943                 pbn_b0_4_921600 },
4944         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4945                 0x1208, 0x0004, 0, 0,
4946                 pbn_b0_4_921600 },
4947 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4948                 0x1402, 0x0002, 0, 0,
4949                 pbn_b0_2_921600 }, */
4950 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4951                 0x1404, 0x0004, 0, 0,
4952                 pbn_b0_4_921600 }, */
4953         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4954                 0x1208, 0x0004, 0, 0,
4955                 pbn_b0_4_921600 },
4956
4957         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4958                 0x1204, 0x0004, 0, 0,
4959                 pbn_b0_4_921600 },
4960         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4961                 0x1208, 0x0004, 0, 0,
4962                 pbn_b0_4_921600 },
4963         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4964                 0x1208, 0x0004, 0, 0,
4965                 pbn_b0_4_921600 },
4966         /*
4967          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4968          */
4969         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971                 pbn_b1_1_1382400 },
4972
4973         /*
4974          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4975          */
4976         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978                 pbn_b1_1_1382400 },
4979
4980         /*
4981          * RAStel 2 port modem, gerg@moreton.com.au
4982          */
4983         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985                 pbn_b2_bt_2_115200 },
4986
4987         /*
4988          * EKF addition for i960 Boards form EKF with serial port
4989          */
4990         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4991                 0xE4BF, PCI_ANY_ID, 0, 0,
4992                 pbn_intel_i960 },
4993
4994         /*
4995          * Xircom Cardbus/Ethernet combos
4996          */
4997         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999                 pbn_b0_1_115200 },
5000         /*
5001          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5002          */
5003         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005                 pbn_b0_1_115200 },
5006
5007         /*
5008          * Untested PCI modems, sent in from various folks...
5009          */
5010
5011         /*
5012          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5013          */
5014         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5015                 0x1048, 0x1500, 0, 0,
5016                 pbn_b1_1_115200 },
5017
5018         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5019                 0xFF00, 0, 0, 0,
5020                 pbn_sgi_ioc3 },
5021
5022         /*
5023          * HP Diva card
5024          */
5025         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5026                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5027                 pbn_b1_1_115200 },
5028         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5030                 pbn_b0_5_115200 },
5031         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5032                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5033                 pbn_b2_1_115200 },
5034
5035         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5037                 pbn_b3_2_115200 },
5038         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040                 pbn_b3_4_115200 },
5041         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043                 pbn_b3_8_115200 },
5044
5045         /*
5046          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5047          */
5048         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5049                 PCI_ANY_ID, PCI_ANY_ID,
5050                 0,
5051                 0, pbn_exar_XR17C152 },
5052         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5053                 PCI_ANY_ID, PCI_ANY_ID,
5054                 0,
5055                 0, pbn_exar_XR17C154 },
5056         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5057                 PCI_ANY_ID, PCI_ANY_ID,
5058                 0,
5059                 0, pbn_exar_XR17C158 },
5060         /*
5061          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5062          */
5063         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5064                 PCI_ANY_ID, PCI_ANY_ID,
5065                 0,
5066                 0, pbn_exar_XR17V352 },
5067         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5068                 PCI_ANY_ID, PCI_ANY_ID,
5069                 0,
5070                 0, pbn_exar_XR17V354 },
5071         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5072                 PCI_ANY_ID, PCI_ANY_ID,
5073                 0,
5074                 0, pbn_exar_XR17V358 },
5075         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5076                 PCI_ANY_ID, PCI_ANY_ID,
5077                 0,
5078                 0, pbn_exar_XR17V4358 },
5079         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5080                 PCI_ANY_ID, PCI_ANY_ID,
5081                 0,
5082                 0, pbn_exar_XR17V8358 },
5083         /*
5084          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5085          */
5086         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5087                 PCI_ANY_ID, PCI_ANY_ID,
5088                 0,
5089                 0, pbn_pericom_PI7C9X7951 },
5090         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5091                 PCI_ANY_ID, PCI_ANY_ID,
5092                 0,
5093                 0, pbn_pericom_PI7C9X7952 },
5094         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5095                 PCI_ANY_ID, PCI_ANY_ID,
5096                 0,
5097                 0, pbn_pericom_PI7C9X7954 },
5098         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5099                 PCI_ANY_ID, PCI_ANY_ID,
5100                 0,
5101                 0, pbn_pericom_PI7C9X7958 },
5102         /*
5103          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5104          */
5105         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5107                 pbn_b0_1_115200 },
5108         /*
5109          * ITE
5110          */
5111         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5112                 PCI_ANY_ID, PCI_ANY_ID,
5113                 0, 0,
5114                 pbn_b1_bt_1_115200 },
5115
5116         /*
5117          * IntaShield IS-200
5118          */
5119         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5121                 pbn_b2_2_115200 },
5122         /*
5123          * IntaShield IS-400
5124          */
5125         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5126                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5127                 pbn_b2_4_115200 },
5128         /*
5129          * Perle PCI-RAS cards
5130          */
5131         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5132                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5133                 0, 0, pbn_b2_4_921600 },
5134         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5135                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5136                 0, 0, pbn_b2_8_921600 },
5137
5138         /*
5139          * Mainpine series cards: Fairly standard layout but fools
5140          * parts of the autodetect in some cases and uses otherwise
5141          * unmatched communications subclasses in the PCI Express case
5142          */
5143
5144         {       /* RockForceDUO */
5145                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5146                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5147                 0, 0, pbn_b0_2_115200 },
5148         {       /* RockForceQUATRO */
5149                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5150                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5151                 0, 0, pbn_b0_4_115200 },
5152         {       /* RockForceDUO+ */
5153                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5154                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5155                 0, 0, pbn_b0_2_115200 },
5156         {       /* RockForceQUATRO+ */
5157                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5158                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5159                 0, 0, pbn_b0_4_115200 },
5160         {       /* RockForce+ */
5161                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5162                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5163                 0, 0, pbn_b0_2_115200 },
5164         {       /* RockForce+ */
5165                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5166                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5167                 0, 0, pbn_b0_4_115200 },
5168         {       /* RockForceOCTO+ */
5169                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5170                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5171                 0, 0, pbn_b0_8_115200 },
5172         {       /* RockForceDUO+ */
5173                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5174                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5175                 0, 0, pbn_b0_2_115200 },
5176         {       /* RockForceQUARTRO+ */
5177                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5178                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5179                 0, 0, pbn_b0_4_115200 },
5180         {       /* RockForceOCTO+ */
5181                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5182                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5183                 0, 0, pbn_b0_8_115200 },
5184         {       /* RockForceD1 */
5185                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5186                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5187                 0, 0, pbn_b0_1_115200 },
5188         {       /* RockForceF1 */
5189                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5190                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5191                 0, 0, pbn_b0_1_115200 },
5192         {       /* RockForceD2 */
5193                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5194                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5195                 0, 0, pbn_b0_2_115200 },
5196         {       /* RockForceF2 */
5197                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5198                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5199                 0, 0, pbn_b0_2_115200 },
5200         {       /* RockForceD4 */
5201                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5202                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5203                 0, 0, pbn_b0_4_115200 },
5204         {       /* RockForceF4 */
5205                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5206                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5207                 0, 0, pbn_b0_4_115200 },
5208         {       /* RockForceD8 */
5209                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5210                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5211                 0, 0, pbn_b0_8_115200 },
5212         {       /* RockForceF8 */
5213                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5214                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5215                 0, 0, pbn_b0_8_115200 },
5216         {       /* IQ Express D1 */
5217                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5218                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5219                 0, 0, pbn_b0_1_115200 },
5220         {       /* IQ Express F1 */
5221                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5222                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5223                 0, 0, pbn_b0_1_115200 },
5224         {       /* IQ Express D2 */
5225                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5226                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5227                 0, 0, pbn_b0_2_115200 },
5228         {       /* IQ Express F2 */
5229                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5230                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5231                 0, 0, pbn_b0_2_115200 },
5232         {       /* IQ Express D4 */
5233                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5234                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5235                 0, 0, pbn_b0_4_115200 },
5236         {       /* IQ Express F4 */
5237                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5238                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5239                 0, 0, pbn_b0_4_115200 },
5240         {       /* IQ Express D8 */
5241                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5242                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5243                 0, 0, pbn_b0_8_115200 },
5244         {       /* IQ Express F8 */
5245                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5246                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5247                 0, 0, pbn_b0_8_115200 },
5248
5249
5250         /*
5251          * PA Semi PA6T-1682M on-chip UART
5252          */
5253         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255                 pbn_pasemi_1682M },
5256
5257         /*
5258          * National Instruments
5259          */
5260         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5262                 pbn_b1_16_115200 },
5263         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5265                 pbn_b1_8_115200 },
5266         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5268                 pbn_b1_bt_4_115200 },
5269         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5271                 pbn_b1_bt_2_115200 },
5272         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5274                 pbn_b1_bt_4_115200 },
5275         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5277                 pbn_b1_bt_2_115200 },
5278         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5280                 pbn_b1_16_115200 },
5281         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5283                 pbn_b1_8_115200 },
5284         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5286                 pbn_b1_bt_4_115200 },
5287         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5289                 pbn_b1_bt_2_115200 },
5290         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5292                 pbn_b1_bt_4_115200 },
5293         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5295                 pbn_b1_bt_2_115200 },
5296         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5298                 pbn_ni8430_2 },
5299         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5301                 pbn_ni8430_2 },
5302         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5304                 pbn_ni8430_4 },
5305         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5307                 pbn_ni8430_4 },
5308         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5310                 pbn_ni8430_8 },
5311         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5313                 pbn_ni8430_8 },
5314         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5316                 pbn_ni8430_16 },
5317         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5319                 pbn_ni8430_16 },
5320         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5322                 pbn_ni8430_2 },
5323         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5325                 pbn_ni8430_2 },
5326         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5328                 pbn_ni8430_4 },
5329         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5331                 pbn_ni8430_4 },
5332
5333         /*
5334         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5335         */
5336         {       PCI_VENDOR_ID_ADDIDATA,
5337                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5338                 PCI_ANY_ID,
5339                 PCI_ANY_ID,
5340                 0,
5341                 0,
5342                 pbn_b0_4_115200 },
5343
5344         {       PCI_VENDOR_ID_ADDIDATA,
5345                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5346                 PCI_ANY_ID,
5347                 PCI_ANY_ID,
5348                 0,
5349                 0,
5350                 pbn_b0_2_115200 },
5351
5352         {       PCI_VENDOR_ID_ADDIDATA,
5353                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5354                 PCI_ANY_ID,
5355                 PCI_ANY_ID,
5356                 0,
5357                 0,
5358                 pbn_b0_1_115200 },
5359
5360         {       PCI_VENDOR_ID_AMCC,
5361                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5362                 PCI_ANY_ID,
5363                 PCI_ANY_ID,
5364                 0,
5365                 0,
5366                 pbn_b1_8_115200 },
5367
5368         {       PCI_VENDOR_ID_ADDIDATA,
5369                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5370                 PCI_ANY_ID,
5371                 PCI_ANY_ID,
5372                 0,
5373                 0,
5374                 pbn_b0_4_115200 },
5375
5376         {       PCI_VENDOR_ID_ADDIDATA,
5377                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5378                 PCI_ANY_ID,
5379                 PCI_ANY_ID,
5380                 0,
5381                 0,
5382                 pbn_b0_2_115200 },
5383
5384         {       PCI_VENDOR_ID_ADDIDATA,
5385                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5386                 PCI_ANY_ID,
5387                 PCI_ANY_ID,
5388                 0,
5389                 0,
5390                 pbn_b0_1_115200 },
5391
5392         {       PCI_VENDOR_ID_ADDIDATA,
5393                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5394                 PCI_ANY_ID,
5395                 PCI_ANY_ID,
5396                 0,
5397                 0,
5398                 pbn_b0_4_115200 },
5399
5400         {       PCI_VENDOR_ID_ADDIDATA,
5401                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5402                 PCI_ANY_ID,
5403                 PCI_ANY_ID,
5404                 0,
5405                 0,
5406                 pbn_b0_2_115200 },
5407
5408         {       PCI_VENDOR_ID_ADDIDATA,
5409                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5410                 PCI_ANY_ID,
5411                 PCI_ANY_ID,
5412                 0,
5413                 0,
5414                 pbn_b0_1_115200 },
5415
5416         {       PCI_VENDOR_ID_ADDIDATA,
5417                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5418                 PCI_ANY_ID,
5419                 PCI_ANY_ID,
5420                 0,
5421                 0,
5422                 pbn_b0_8_115200 },
5423
5424         {       PCI_VENDOR_ID_ADDIDATA,
5425                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5426                 PCI_ANY_ID,
5427                 PCI_ANY_ID,
5428                 0,
5429                 0,
5430                 pbn_ADDIDATA_PCIe_4_3906250 },
5431
5432         {       PCI_VENDOR_ID_ADDIDATA,
5433                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5434                 PCI_ANY_ID,
5435                 PCI_ANY_ID,
5436                 0,
5437                 0,
5438                 pbn_ADDIDATA_PCIe_2_3906250 },
5439
5440         {       PCI_VENDOR_ID_ADDIDATA,
5441                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5442                 PCI_ANY_ID,
5443                 PCI_ANY_ID,
5444                 0,
5445                 0,
5446                 pbn_ADDIDATA_PCIe_1_3906250 },
5447
5448         {       PCI_VENDOR_ID_ADDIDATA,
5449                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5450                 PCI_ANY_ID,
5451                 PCI_ANY_ID,
5452                 0,
5453                 0,
5454                 pbn_ADDIDATA_PCIe_8_3906250 },
5455
5456         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5457                 PCI_VENDOR_ID_IBM, 0x0299,
5458                 0, 0, pbn_b0_bt_2_115200 },
5459
5460         /*
5461          * other NetMos 9835 devices are most likely handled by the
5462          * parport_serial driver, check drivers/parport/parport_serial.c
5463          * before adding them here.
5464          */
5465
5466         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5467                 0xA000, 0x1000,
5468                 0, 0, pbn_b0_1_115200 },
5469
5470         /* the 9901 is a rebranded 9912 */
5471         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5472                 0xA000, 0x1000,
5473                 0, 0, pbn_b0_1_115200 },
5474
5475         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5476                 0xA000, 0x1000,
5477                 0, 0, pbn_b0_1_115200 },
5478
5479         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5480                 0xA000, 0x1000,
5481                 0, 0, pbn_b0_1_115200 },
5482
5483         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5484                 0xA000, 0x1000,
5485                 0, 0, pbn_b0_1_115200 },
5486
5487         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5488                 0xA000, 0x3002,
5489                 0, 0, pbn_NETMOS9900_2s_115200 },
5490
5491         /*
5492          * Best Connectivity and Rosewill PCI Multi I/O cards
5493          */
5494
5495         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5496                 0xA000, 0x1000,
5497                 0, 0, pbn_b0_1_115200 },
5498
5499         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5500                 0xA000, 0x3002,
5501                 0, 0, pbn_b0_bt_2_115200 },
5502
5503         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5504                 0xA000, 0x3004,
5505                 0, 0, pbn_b0_bt_4_115200 },
5506         /* Intel CE4100 */
5507         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5508                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5509                 pbn_ce4100_1_115200 },
5510         /* Intel BayTrail */
5511         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5512                 PCI_ANY_ID,  PCI_ANY_ID,
5513                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5514                 pbn_byt },
5515         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5516                 PCI_ANY_ID,  PCI_ANY_ID,
5517                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5518                 pbn_byt },
5519         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5520                 PCI_ANY_ID,  PCI_ANY_ID,
5521                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5522                 pbn_byt },
5523         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5524                 PCI_ANY_ID,  PCI_ANY_ID,
5525                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5526                 pbn_byt },
5527
5528         /* Intel Broadwell */
5529         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5530                 PCI_ANY_ID,  PCI_ANY_ID,
5531                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5532                 pbn_byt },
5533         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5534                 PCI_ANY_ID,  PCI_ANY_ID,
5535                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5536                 pbn_byt },
5537
5538         /*
5539          * Intel Quark x1000
5540          */
5541         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5542                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5543                 pbn_qrk },
5544         /*
5545          * Cronyx Omega PCI
5546          */
5547         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5549                 pbn_omegapci },
5550
5551         /*
5552          * Broadcom TruManage
5553          */
5554         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5556                 pbn_brcm_trumanage },
5557
5558         /*
5559          * AgeStar as-prs2-009
5560          */
5561         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5562                 PCI_ANY_ID, PCI_ANY_ID,
5563                 0, 0, pbn_b0_bt_2_115200 },
5564
5565         /*
5566          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5567          * so not listed here.
5568          */
5569         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5570                 PCI_ANY_ID, PCI_ANY_ID,
5571                 0, 0, pbn_b0_bt_4_115200 },
5572
5573         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5574                 PCI_ANY_ID, PCI_ANY_ID,
5575                 0, 0, pbn_b0_bt_2_115200 },
5576
5577         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5578                 PCI_ANY_ID, PCI_ANY_ID,
5579                 0, 0, pbn_wch384_4 },
5580
5581         /*
5582          * Commtech, Inc. Fastcom adapters
5583          */
5584         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5585                 PCI_ANY_ID, PCI_ANY_ID,
5586                 0,
5587                 0, pbn_b0_2_1152000_200 },
5588         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5589                 PCI_ANY_ID, PCI_ANY_ID,
5590                 0,
5591                 0, pbn_b0_4_1152000_200 },
5592         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5593                 PCI_ANY_ID, PCI_ANY_ID,
5594                 0,
5595                 0, pbn_b0_4_1152000_200 },
5596         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5597                 PCI_ANY_ID, PCI_ANY_ID,
5598                 0,
5599                 0, pbn_b0_8_1152000_200 },
5600         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5601                 PCI_ANY_ID, PCI_ANY_ID,
5602                 0,
5603                 0, pbn_exar_XR17V352 },
5604         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5605                 PCI_ANY_ID, PCI_ANY_ID,
5606                 0,
5607                 0, pbn_exar_XR17V354 },
5608         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5609                 PCI_ANY_ID, PCI_ANY_ID,
5610                 0,
5611                 0, pbn_exar_XR17V358 },
5612
5613         /* Fintek PCI serial cards */
5614         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5615         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5616         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5617
5618         /*
5619          * These entries match devices with class COMMUNICATION_SERIAL,
5620          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5621          */
5622         {       PCI_ANY_ID, PCI_ANY_ID,
5623                 PCI_ANY_ID, PCI_ANY_ID,
5624                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5625                 0xffff00, pbn_default },
5626         {       PCI_ANY_ID, PCI_ANY_ID,
5627                 PCI_ANY_ID, PCI_ANY_ID,
5628                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5629                 0xffff00, pbn_default },
5630         {       PCI_ANY_ID, PCI_ANY_ID,
5631                 PCI_ANY_ID, PCI_ANY_ID,
5632                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5633                 0xffff00, pbn_default },
5634         { 0, }
5635 };
5636
5637 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5638                                                 pci_channel_state_t state)
5639 {
5640         struct serial_private *priv = pci_get_drvdata(dev);
5641
5642         if (state == pci_channel_io_perm_failure)
5643                 return PCI_ERS_RESULT_DISCONNECT;
5644
5645         if (priv)
5646                 pciserial_suspend_ports(priv);
5647
5648         pci_disable_device(dev);
5649
5650         return PCI_ERS_RESULT_NEED_RESET;
5651 }
5652
5653 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5654 {
5655         int rc;
5656
5657         rc = pci_enable_device(dev);
5658
5659         if (rc)
5660                 return PCI_ERS_RESULT_DISCONNECT;
5661
5662         pci_restore_state(dev);
5663         pci_save_state(dev);
5664
5665         return PCI_ERS_RESULT_RECOVERED;
5666 }
5667
5668 static void serial8250_io_resume(struct pci_dev *dev)
5669 {
5670         struct serial_private *priv = pci_get_drvdata(dev);
5671
5672         if (priv)
5673                 pciserial_resume_ports(priv);
5674 }
5675
5676 static const struct pci_error_handlers serial8250_err_handler = {
5677         .error_detected = serial8250_io_error_detected,
5678         .slot_reset = serial8250_io_slot_reset,
5679         .resume = serial8250_io_resume,
5680 };
5681
5682 static struct pci_driver serial_pci_driver = {
5683         .name           = "serial",
5684         .probe          = pciserial_init_one,
5685         .remove         = pciserial_remove_one,
5686         .driver         = {
5687                 .pm     = &pciserial_pm_ops,
5688         },
5689         .id_table       = serial_pci_tbl,
5690         .err_handler    = &serial8250_err_handler,
5691 };
5692
5693 module_pci_driver(serial_pci_driver);
5694
5695 MODULE_LICENSE("GPL");
5696 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5697 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);