2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
50 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
52 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
58 * Here we define the default xmit fifo size used for each type of UART.
60 static const struct serial8250_config uart_config[] = {
85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
86 .rxtrig_bytes = {1, 4, 8, 14},
87 .flags = UART_CAP_FIFO,
98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 .rxtrig_bytes = {8, 16, 24, 28},
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 .rxtrig_bytes = {1, 16, 32, 56},
116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
124 .name = "16C950/954",
127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 .rxtrig_bytes = {8, 16, 56, 60},
138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
152 .flags = UART_CAP_FIFO,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_NATSEMI,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
180 .flags = UART_CAP_FIFO | UART_CAP_AFE,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO | UART_CAP_AFE,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 .rxtrig_bytes = {1, 4, 8, 14},
196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO,
223 [PORT_BRCM_TRUMANAGE] = {
227 .flags = UART_CAP_HFIFO,
232 [PORT_ALTR_16550_F32] = {
233 .name = "Altera 16550 FIFO32",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
254 workaround of errata A-008006 which states that tx_loadsz should be
255 configured less than Maximum supported fifo bytes */
256 [PORT_16550A_FSL64] = {
257 .name = "16550A_FSL64",
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
262 .flags = UART_CAP_FIFO,
265 .name = "Palmchip BK-3103",
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .rxtrig_bytes = {1, 4, 8, 14},
270 .flags = UART_CAP_FIFO,
274 /* Uart divisor latch read */
275 static int default_serial_dl_read(struct uart_8250_port *up)
277 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
280 /* Uart divisor latch write */
281 static void default_serial_dl_write(struct uart_8250_port *up, int value)
283 serial_out(up, UART_DLL, value & 0xff);
284 serial_out(up, UART_DLM, value >> 8 & 0xff);
287 #ifdef CONFIG_SERIAL_8250_RT288X
289 /* Au1x00/RT288x UART hardware has a weird register layout */
290 static const s8 au_io_in_map[8] = {
298 -1, /* UART_SCR (unmapped) */
301 static const s8 au_io_out_map[8] = {
307 -1, /* UART_LSR (unmapped) */
308 -1, /* UART_MSR (unmapped) */
309 -1, /* UART_SCR (unmapped) */
312 static unsigned int au_serial_in(struct uart_port *p, int offset)
314 if (offset >= ARRAY_SIZE(au_io_in_map))
316 offset = au_io_in_map[offset];
319 return __raw_readl(p->membase + (offset << p->regshift));
322 static void au_serial_out(struct uart_port *p, int offset, int value)
324 if (offset >= ARRAY_SIZE(au_io_out_map))
326 offset = au_io_out_map[offset];
329 __raw_writel(value, p->membase + (offset << p->regshift));
332 /* Au1x00 haven't got a standard divisor latch */
333 static int au_serial_dl_read(struct uart_8250_port *up)
335 return __raw_readl(up->port.membase + 0x28);
338 static void au_serial_dl_write(struct uart_8250_port *up, int value)
340 __raw_writel(value, up->port.membase + 0x28);
345 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
347 offset = offset << p->regshift;
348 outb(p->hub6 - 1 + offset, p->iobase);
349 return inb(p->iobase + 1);
352 static void hub6_serial_out(struct uart_port *p, int offset, int value)
354 offset = offset << p->regshift;
355 outb(p->hub6 - 1 + offset, p->iobase);
356 outb(value, p->iobase + 1);
359 static unsigned int mem_serial_in(struct uart_port *p, int offset)
361 offset = offset << p->regshift;
362 return readb(p->membase + offset);
365 static void mem_serial_out(struct uart_port *p, int offset, int value)
367 offset = offset << p->regshift;
368 writeb(value, p->membase + offset);
371 static void mem16_serial_out(struct uart_port *p, int offset, int value)
373 offset = offset << p->regshift;
374 writew(value, p->membase + offset);
377 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
379 offset = offset << p->regshift;
380 return readw(p->membase + offset);
383 static void mem32_serial_out(struct uart_port *p, int offset, int value)
385 offset = offset << p->regshift;
386 writel(value, p->membase + offset);
389 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
391 offset = offset << p->regshift;
392 return readl(p->membase + offset);
395 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
397 offset = offset << p->regshift;
398 iowrite32be(value, p->membase + offset);
401 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
403 offset = offset << p->regshift;
404 return ioread32be(p->membase + offset);
407 static unsigned int io_serial_in(struct uart_port *p, int offset)
409 offset = offset << p->regshift;
410 return inb(p->iobase + offset);
413 static void io_serial_out(struct uart_port *p, int offset, int value)
415 offset = offset << p->regshift;
416 outb(value, p->iobase + offset);
419 static int serial8250_default_handle_irq(struct uart_port *port);
420 static int exar_handle_irq(struct uart_port *port);
422 static void set_io_from_upio(struct uart_port *p)
424 struct uart_8250_port *up = up_to_u8250p(p);
426 up->dl_read = default_serial_dl_read;
427 up->dl_write = default_serial_dl_write;
431 p->serial_in = hub6_serial_in;
432 p->serial_out = hub6_serial_out;
436 p->serial_in = mem_serial_in;
437 p->serial_out = mem_serial_out;
441 p->serial_in = mem16_serial_in;
442 p->serial_out = mem16_serial_out;
446 p->serial_in = mem32_serial_in;
447 p->serial_out = mem32_serial_out;
451 p->serial_in = mem32be_serial_in;
452 p->serial_out = mem32be_serial_out;
455 #ifdef CONFIG_SERIAL_8250_RT288X
457 p->serial_in = au_serial_in;
458 p->serial_out = au_serial_out;
459 up->dl_read = au_serial_dl_read;
460 up->dl_write = au_serial_dl_write;
465 p->serial_in = io_serial_in;
466 p->serial_out = io_serial_out;
469 /* Remember loaded iotype */
470 up->cur_iotype = p->iotype;
471 p->handle_irq = serial8250_default_handle_irq;
475 serial_port_out_sync(struct uart_port *p, int offset, int value)
483 p->serial_out(p, offset, value);
484 p->serial_in(p, UART_LCR); /* safe, no side-effects */
487 p->serial_out(p, offset, value);
494 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
496 serial_out(up, UART_SCR, offset);
497 serial_out(up, UART_ICR, value);
500 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
504 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
505 serial_out(up, UART_SCR, offset);
506 value = serial_in(up, UART_ICR);
507 serial_icr_write(up, UART_ACR, up->acr);
515 static void serial8250_clear_fifos(struct uart_8250_port *p)
517 if (p->capabilities & UART_CAP_FIFO) {
518 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
519 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
520 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
521 serial_out(p, UART_FCR, 0);
525 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
527 serial8250_clear_fifos(p);
528 serial_out(p, UART_FCR, p->fcr);
530 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
532 void serial8250_rpm_get(struct uart_8250_port *p)
534 if (!(p->capabilities & UART_CAP_RPM))
536 pm_runtime_get_sync(p->port.dev);
538 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
540 void serial8250_rpm_put(struct uart_8250_port *p)
542 if (!(p->capabilities & UART_CAP_RPM))
544 pm_runtime_mark_last_busy(p->port.dev);
545 pm_runtime_put_autosuspend(p->port.dev);
547 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
550 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
551 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
552 * empty and the HW can idle again.
554 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
556 unsigned char rpm_active;
558 if (!(p->capabilities & UART_CAP_RPM))
561 rpm_active = xchg(&p->rpm_tx_active, 1);
564 pm_runtime_get_sync(p->port.dev);
567 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
569 unsigned char rpm_active;
571 if (!(p->capabilities & UART_CAP_RPM))
574 rpm_active = xchg(&p->rpm_tx_active, 0);
577 pm_runtime_mark_last_busy(p->port.dev);
578 pm_runtime_put_autosuspend(p->port.dev);
582 * IER sleep support. UARTs which have EFRs need the "extended
583 * capability" bit enabled. Note that on XR16C850s, we need to
584 * reset LCR to write to IER.
586 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
588 unsigned char lcr = 0, efr = 0;
590 * Exar UARTs have a SLEEP register that enables or disables
591 * each UART to enter sleep mode separately. On the XR17V35x the
592 * register is accessible to each UART at the UART_EXAR_SLEEP
593 * offset but the UART channel may only write to the corresponding
596 serial8250_rpm_get(p);
597 if ((p->port.type == PORT_XR17V35X) ||
598 (p->port.type == PORT_XR17D15X)) {
599 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
603 if (p->capabilities & UART_CAP_SLEEP) {
604 if (p->capabilities & UART_CAP_EFR) {
605 lcr = serial_in(p, UART_LCR);
606 efr = serial_in(p, UART_EFR);
607 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
608 serial_out(p, UART_EFR, UART_EFR_ECB);
609 serial_out(p, UART_LCR, 0);
611 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
612 if (p->capabilities & UART_CAP_EFR) {
613 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
614 serial_out(p, UART_EFR, efr);
615 serial_out(p, UART_LCR, lcr);
619 serial8250_rpm_put(p);
622 #ifdef CONFIG_SERIAL_8250_RSA
624 * Attempts to turn on the RSA FIFO. Returns zero on failure.
625 * We set the port uart clock rate if we succeed.
627 static int __enable_rsa(struct uart_8250_port *up)
632 mode = serial_in(up, UART_RSA_MSR);
633 result = mode & UART_RSA_MSR_FIFO;
636 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
637 mode = serial_in(up, UART_RSA_MSR);
638 result = mode & UART_RSA_MSR_FIFO;
642 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
647 static void enable_rsa(struct uart_8250_port *up)
649 if (up->port.type == PORT_RSA) {
650 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
651 spin_lock_irq(&up->port.lock);
653 spin_unlock_irq(&up->port.lock);
655 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
656 serial_out(up, UART_RSA_FRR, 0);
661 * Attempts to turn off the RSA FIFO. Returns zero on failure.
662 * It is unknown why interrupts were disabled in here. However,
663 * the caller is expected to preserve this behaviour by grabbing
664 * the spinlock before calling this function.
666 static void disable_rsa(struct uart_8250_port *up)
671 if (up->port.type == PORT_RSA &&
672 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
673 spin_lock_irq(&up->port.lock);
675 mode = serial_in(up, UART_RSA_MSR);
676 result = !(mode & UART_RSA_MSR_FIFO);
679 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
680 mode = serial_in(up, UART_RSA_MSR);
681 result = !(mode & UART_RSA_MSR_FIFO);
685 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
686 spin_unlock_irq(&up->port.lock);
689 #endif /* CONFIG_SERIAL_8250_RSA */
692 * This is a quickie test to see how big the FIFO is.
693 * It doesn't work at all the time, more's the pity.
695 static int size_fifo(struct uart_8250_port *up)
697 unsigned char old_fcr, old_mcr, old_lcr;
698 unsigned short old_dl;
701 old_lcr = serial_in(up, UART_LCR);
702 serial_out(up, UART_LCR, 0);
703 old_fcr = serial_in(up, UART_FCR);
704 old_mcr = serial_in(up, UART_MCR);
705 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
706 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
707 serial_out(up, UART_MCR, UART_MCR_LOOP);
708 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
709 old_dl = serial_dl_read(up);
710 serial_dl_write(up, 0x0001);
711 serial_out(up, UART_LCR, 0x03);
712 for (count = 0; count < 256; count++)
713 serial_out(up, UART_TX, count);
714 mdelay(20);/* FIXME - schedule_timeout */
715 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
716 (count < 256); count++)
717 serial_in(up, UART_RX);
718 serial_out(up, UART_FCR, old_fcr);
719 serial_out(up, UART_MCR, old_mcr);
720 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
721 serial_dl_write(up, old_dl);
722 serial_out(up, UART_LCR, old_lcr);
728 * Read UART ID using the divisor method - set DLL and DLM to zero
729 * and the revision will be in DLL and device type in DLM. We
730 * preserve the device state across this.
732 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
734 unsigned char old_dll, old_dlm, old_lcr;
737 old_lcr = serial_in(p, UART_LCR);
738 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
740 old_dll = serial_in(p, UART_DLL);
741 old_dlm = serial_in(p, UART_DLM);
743 serial_out(p, UART_DLL, 0);
744 serial_out(p, UART_DLM, 0);
746 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
748 serial_out(p, UART_DLL, old_dll);
749 serial_out(p, UART_DLM, old_dlm);
750 serial_out(p, UART_LCR, old_lcr);
756 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
757 * When this function is called we know it is at least a StarTech
758 * 16650 V2, but it might be one of several StarTech UARTs, or one of
759 * its clones. (We treat the broken original StarTech 16650 V1 as a
760 * 16550, and why not? Startech doesn't seem to even acknowledge its
763 * What evil have men's minds wrought...
765 static void autoconfig_has_efr(struct uart_8250_port *up)
767 unsigned int id1, id2, id3, rev;
770 * Everything with an EFR has SLEEP
772 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
775 * First we check to see if it's an Oxford Semiconductor UART.
777 * If we have to do this here because some non-National
778 * Semiconductor clone chips lock up if you try writing to the
779 * LSR register (which serial_icr_read does)
783 * Check for Oxford Semiconductor 16C950.
785 * EFR [4] must be set else this test fails.
787 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
788 * claims that it's needed for 952 dual UART's (which are not
789 * recommended for new designs).
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
793 serial_out(up, UART_EFR, UART_EFR_ECB);
794 serial_out(up, UART_LCR, 0x00);
795 id1 = serial_icr_read(up, UART_ID1);
796 id2 = serial_icr_read(up, UART_ID2);
797 id3 = serial_icr_read(up, UART_ID3);
798 rev = serial_icr_read(up, UART_REV);
800 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
802 if (id1 == 0x16 && id2 == 0xC9 &&
803 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
804 up->port.type = PORT_16C950;
807 * Enable work around for the Oxford Semiconductor 952 rev B
808 * chip which causes it to seriously miscalculate baud rates
811 if (id3 == 0x52 && rev == 0x01)
812 up->bugs |= UART_BUG_QUOT;
817 * We check for a XR16C850 by setting DLL and DLM to 0, and then
818 * reading back DLL and DLM. The chip type depends on the DLM
820 * 0x10 - XR16C850 and the DLL contains the chip revision.
824 id1 = autoconfig_read_divisor_id(up);
825 DEBUG_AUTOCONF("850id=%04x ", id1);
828 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
829 up->port.type = PORT_16850;
834 * It wasn't an XR16C850.
836 * We distinguish between the '654 and the '650 by counting
837 * how many bytes are in the FIFO. I'm using this for now,
838 * since that's the technique that was sent to me in the
839 * serial driver update, but I'm not convinced this works.
840 * I've had problems doing this in the past. -TYT
842 if (size_fifo(up) == 64)
843 up->port.type = PORT_16654;
845 up->port.type = PORT_16650V2;
849 * We detected a chip without a FIFO. Only two fall into
850 * this category - the original 8250 and the 16450. The
851 * 16450 has a scratch register (accessible with LCR=0)
853 static void autoconfig_8250(struct uart_8250_port *up)
855 unsigned char scratch, status1, status2;
857 up->port.type = PORT_8250;
859 scratch = serial_in(up, UART_SCR);
860 serial_out(up, UART_SCR, 0xa5);
861 status1 = serial_in(up, UART_SCR);
862 serial_out(up, UART_SCR, 0x5a);
863 status2 = serial_in(up, UART_SCR);
864 serial_out(up, UART_SCR, scratch);
866 if (status1 == 0xa5 && status2 == 0x5a)
867 up->port.type = PORT_16450;
870 static int broken_efr(struct uart_8250_port *up)
873 * Exar ST16C2550 "A2" devices incorrectly detect as
874 * having an EFR, and report an ID of 0x0201. See
875 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
877 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
884 * We know that the chip has FIFOs. Does it have an EFR? The
885 * EFR is located in the same register position as the IIR and
886 * we know the top two bits of the IIR are currently set. The
887 * EFR should contain zero. Try to read the EFR.
889 static void autoconfig_16550a(struct uart_8250_port *up)
891 unsigned char status1, status2;
892 unsigned int iersave;
894 up->port.type = PORT_16550A;
895 up->capabilities |= UART_CAP_FIFO;
898 * XR17V35x UARTs have an extra divisor register, DLD
899 * that gets enabled with when DLAB is set which will
900 * cause the device to incorrectly match and assign
901 * port type to PORT_16650. The EFR for this UART is
902 * found at offset 0x09. Instead check the Deice ID (DVID)
903 * register for a 2, 4 or 8 port UART.
905 if (up->port.flags & UPF_EXAR_EFR) {
906 status1 = serial_in(up, UART_EXAR_DVID);
907 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
908 DEBUG_AUTOCONF("Exar XR17V35x ");
909 up->port.type = PORT_XR17V35X;
910 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
919 * Check for presence of the EFR when DLAB is set.
920 * Only ST16C650V1 UARTs pass this test.
922 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
923 if (serial_in(up, UART_EFR) == 0) {
924 serial_out(up, UART_EFR, 0xA8);
925 if (serial_in(up, UART_EFR) != 0) {
926 DEBUG_AUTOCONF("EFRv1 ");
927 up->port.type = PORT_16650;
928 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
930 serial_out(up, UART_LCR, 0);
931 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
933 status1 = serial_in(up, UART_IIR) >> 5;
934 serial_out(up, UART_FCR, 0);
935 serial_out(up, UART_LCR, 0);
938 up->port.type = PORT_16550A_FSL64;
940 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
942 serial_out(up, UART_EFR, 0);
947 * Maybe it requires 0xbf to be written to the LCR.
948 * (other ST16C650V2 UARTs, TI16C752A, etc)
950 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
951 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
952 DEBUG_AUTOCONF("EFRv2 ");
953 autoconfig_has_efr(up);
958 * Check for a National Semiconductor SuperIO chip.
959 * Attempt to switch to bank 2, read the value of the LOOP bit
960 * from EXCR1. Switch back to bank 0, change it in MCR. Then
961 * switch back to bank 2, read it from EXCR1 again and check
962 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
964 serial_out(up, UART_LCR, 0);
965 status1 = serial_in(up, UART_MCR);
966 serial_out(up, UART_LCR, 0xE0);
967 status2 = serial_in(up, 0x02); /* EXCR1 */
969 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
970 serial_out(up, UART_LCR, 0);
971 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
972 serial_out(up, UART_LCR, 0xE0);
973 status2 = serial_in(up, 0x02); /* EXCR1 */
974 serial_out(up, UART_LCR, 0);
975 serial_out(up, UART_MCR, status1);
977 if ((status2 ^ status1) & UART_MCR_LOOP) {
980 serial_out(up, UART_LCR, 0xE0);
982 quot = serial_dl_read(up);
985 if (ns16550a_goto_highspeed(up))
986 serial_dl_write(up, quot);
988 serial_out(up, UART_LCR, 0);
990 up->port.uartclk = 921600*16;
991 up->port.type = PORT_NS16550A;
992 up->capabilities |= UART_NATSEMI;
998 * No EFR. Try to detect a TI16750, which only sets bit 5 of
999 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1000 * Try setting it with and without DLAB set. Cheap clones
1001 * set bit 5 without DLAB set.
1003 serial_out(up, UART_LCR, 0);
1004 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1005 status1 = serial_in(up, UART_IIR) >> 5;
1006 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1007 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1008 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1009 status2 = serial_in(up, UART_IIR) >> 5;
1010 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1011 serial_out(up, UART_LCR, 0);
1013 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1015 if (status1 == 6 && status2 == 7) {
1016 up->port.type = PORT_16750;
1017 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1022 * Try writing and reading the UART_IER_UUE bit (b6).
1023 * If it works, this is probably one of the Xscale platform's
1025 * We're going to explicitly set the UUE bit to 0 before
1026 * trying to write and read a 1 just to make sure it's not
1027 * already a 1 and maybe locked there before we even start start.
1029 iersave = serial_in(up, UART_IER);
1030 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1031 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1033 * OK it's in a known zero state, try writing and reading
1034 * without disturbing the current state of the other bits.
1036 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1037 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1040 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1042 DEBUG_AUTOCONF("Xscale ");
1043 up->port.type = PORT_XSCALE;
1044 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1049 * If we got here we couldn't force the IER_UUE bit to 0.
1050 * Log it and continue.
1052 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1054 serial_out(up, UART_IER, iersave);
1057 * Exar uarts have EFR in a weird location
1059 if (up->port.flags & UPF_EXAR_EFR) {
1060 DEBUG_AUTOCONF("Exar XR17D15x ");
1061 up->port.type = PORT_XR17D15X;
1062 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1069 * We distinguish between 16550A and U6 16550A by counting
1070 * how many bytes are in the FIFO.
1072 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1073 up->port.type = PORT_U6_16550A;
1074 up->capabilities |= UART_CAP_AFE;
1079 * This routine is called by rs_init() to initialize a specific serial
1080 * port. It determines what type of UART chip this serial port is
1081 * using: 8250, 16450, 16550, 16550A. The important question is
1082 * whether or not this UART is a 16550A or not, since this will
1083 * determine whether or not we can use its FIFO features or not.
1085 static void autoconfig(struct uart_8250_port *up)
1087 unsigned char status1, scratch, scratch2, scratch3;
1088 unsigned char save_lcr, save_mcr;
1089 struct uart_port *port = &up->port;
1090 unsigned long flags;
1091 unsigned int old_capabilities;
1093 if (!port->iobase && !port->mapbase && !port->membase)
1096 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1097 serial_index(port), port->iobase, port->membase);
1100 * We really do need global IRQs disabled here - we're going to
1101 * be frobbing the chips IRQ enable register to see if it exists.
1103 spin_lock_irqsave(&port->lock, flags);
1105 up->capabilities = 0;
1108 if (!(port->flags & UPF_BUGGY_UART)) {
1110 * Do a simple existence test first; if we fail this,
1111 * there's no point trying anything else.
1113 * 0x80 is used as a nonsense port to prevent against
1114 * false positives due to ISA bus float. The
1115 * assumption is that 0x80 is a non-existent port;
1116 * which should be safe since include/asm/io.h also
1117 * makes this assumption.
1119 * Note: this is safe as long as MCR bit 4 is clear
1120 * and the device is in "PC" mode.
1122 scratch = serial_in(up, UART_IER);
1123 serial_out(up, UART_IER, 0);
1128 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1129 * 16C754B) allow only to modify them if an EFR bit is set.
1131 scratch2 = serial_in(up, UART_IER) & 0x0f;
1132 serial_out(up, UART_IER, 0x0F);
1136 scratch3 = serial_in(up, UART_IER) & 0x0f;
1137 serial_out(up, UART_IER, scratch);
1138 if (scratch2 != 0 || scratch3 != 0x0F) {
1140 * We failed; there's nothing here
1142 spin_unlock_irqrestore(&port->lock, flags);
1143 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1144 scratch2, scratch3);
1149 save_mcr = serial_in(up, UART_MCR);
1150 save_lcr = serial_in(up, UART_LCR);
1153 * Check to see if a UART is really there. Certain broken
1154 * internal modems based on the Rockwell chipset fail this
1155 * test, because they apparently don't implement the loopback
1156 * test mode. So this test is skipped on the COM 1 through
1157 * COM 4 ports. This *should* be safe, since no board
1158 * manufacturer would be stupid enough to design a board
1159 * that conflicts with COM 1-4 --- we hope!
1161 if (!(port->flags & UPF_SKIP_TEST)) {
1162 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1163 status1 = serial_in(up, UART_MSR) & 0xF0;
1164 serial_out(up, UART_MCR, save_mcr);
1165 if (status1 != 0x90) {
1166 spin_unlock_irqrestore(&port->lock, flags);
1167 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1174 * We're pretty sure there's a port here. Lets find out what
1175 * type of port it is. The IIR top two bits allows us to find
1176 * out if it's 8250 or 16450, 16550, 16550A or later. This
1177 * determines what we test for next.
1179 * We also initialise the EFR (if any) to zero for later. The
1180 * EFR occupies the same register location as the FCR and IIR.
1182 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1183 serial_out(up, UART_EFR, 0);
1184 serial_out(up, UART_LCR, 0);
1186 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1187 scratch = serial_in(up, UART_IIR) >> 6;
1191 autoconfig_8250(up);
1194 port->type = PORT_UNKNOWN;
1197 port->type = PORT_16550;
1200 autoconfig_16550a(up);
1204 #ifdef CONFIG_SERIAL_8250_RSA
1206 * Only probe for RSA ports if we got the region.
1208 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1210 port->type = PORT_RSA;
1213 serial_out(up, UART_LCR, save_lcr);
1215 port->fifosize = uart_config[up->port.type].fifo_size;
1216 old_capabilities = up->capabilities;
1217 up->capabilities = uart_config[port->type].flags;
1218 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1220 if (port->type == PORT_UNKNOWN)
1226 #ifdef CONFIG_SERIAL_8250_RSA
1227 if (port->type == PORT_RSA)
1228 serial_out(up, UART_RSA_FRR, 0);
1230 serial_out(up, UART_MCR, save_mcr);
1231 serial8250_clear_fifos(up);
1232 serial_in(up, UART_RX);
1233 if (up->capabilities & UART_CAP_UUE)
1234 serial_out(up, UART_IER, UART_IER_UUE);
1236 serial_out(up, UART_IER, 0);
1239 spin_unlock_irqrestore(&port->lock, flags);
1240 if (up->capabilities != old_capabilities) {
1242 "ttyS%d: detected caps %08x should be %08x\n",
1243 serial_index(port), old_capabilities,
1247 DEBUG_AUTOCONF("iir=%d ", scratch);
1248 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1251 static void autoconfig_irq(struct uart_8250_port *up)
1253 struct uart_port *port = &up->port;
1254 unsigned char save_mcr, save_ier;
1255 unsigned char save_ICP = 0;
1256 unsigned int ICP = 0;
1260 if (port->flags & UPF_FOURPORT) {
1261 ICP = (port->iobase & 0xfe0) | 0x1f;
1262 save_ICP = inb_p(ICP);
1267 if (uart_console(port))
1270 /* forget possible initially masked and pending IRQ */
1271 probe_irq_off(probe_irq_on());
1272 save_mcr = serial_in(up, UART_MCR);
1273 save_ier = serial_in(up, UART_IER);
1274 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1276 irqs = probe_irq_on();
1277 serial_out(up, UART_MCR, 0);
1279 if (port->flags & UPF_FOURPORT) {
1280 serial_out(up, UART_MCR,
1281 UART_MCR_DTR | UART_MCR_RTS);
1283 serial_out(up, UART_MCR,
1284 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1286 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1287 serial_in(up, UART_LSR);
1288 serial_in(up, UART_RX);
1289 serial_in(up, UART_IIR);
1290 serial_in(up, UART_MSR);
1291 serial_out(up, UART_TX, 0xFF);
1293 irq = probe_irq_off(irqs);
1295 serial_out(up, UART_MCR, save_mcr);
1296 serial_out(up, UART_IER, save_ier);
1298 if (port->flags & UPF_FOURPORT)
1299 outb_p(save_ICP, ICP);
1301 if (uart_console(port))
1304 port->irq = (irq > 0) ? irq : 0;
1307 static inline void __stop_tx(struct uart_8250_port *p)
1309 if (p->ier & UART_IER_THRI) {
1310 p->ier &= ~UART_IER_THRI;
1311 serial_out(p, UART_IER, p->ier);
1312 serial8250_rpm_put_tx(p);
1316 static void serial8250_stop_tx(struct uart_port *port)
1318 struct uart_8250_port *up = up_to_u8250p(port);
1320 serial8250_rpm_get(up);
1324 * We really want to stop the transmitter from sending.
1326 if (port->type == PORT_16C950) {
1327 up->acr |= UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1330 serial8250_rpm_put(up);
1333 static void serial8250_start_tx(struct uart_port *port)
1335 struct uart_8250_port *up = up_to_u8250p(port);
1337 serial8250_rpm_get_tx(up);
1339 if (up->dma && !up->dma->tx_dma(up))
1342 if (!(up->ier & UART_IER_THRI)) {
1343 up->ier |= UART_IER_THRI;
1344 serial_port_out(port, UART_IER, up->ier);
1346 if (up->bugs & UART_BUG_TXEN) {
1348 lsr = serial_in(up, UART_LSR);
1349 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1350 if (lsr & UART_LSR_THRE)
1351 serial8250_tx_chars(up);
1356 * Re-enable the transmitter if we disabled it.
1358 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1359 up->acr &= ~UART_ACR_TXDIS;
1360 serial_icr_write(up, UART_ACR, up->acr);
1364 static void serial8250_throttle(struct uart_port *port)
1366 port->throttle(port);
1369 static void serial8250_unthrottle(struct uart_port *port)
1371 port->unthrottle(port);
1374 static void serial8250_stop_rx(struct uart_port *port)
1376 struct uart_8250_port *up = up_to_u8250p(port);
1378 serial8250_rpm_get(up);
1380 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1381 up->port.read_status_mask &= ~UART_LSR_DR;
1382 serial_port_out(port, UART_IER, up->ier);
1384 serial8250_rpm_put(up);
1387 static void serial8250_disable_ms(struct uart_port *port)
1389 struct uart_8250_port *up =
1390 container_of(port, struct uart_8250_port, port);
1392 /* no MSR capabilities */
1393 if (up->bugs & UART_BUG_NOMSR)
1396 up->ier &= ~UART_IER_MSI;
1397 serial_port_out(port, UART_IER, up->ier);
1400 static void serial8250_enable_ms(struct uart_port *port)
1402 struct uart_8250_port *up = up_to_u8250p(port);
1404 /* no MSR capabilities */
1405 if (up->bugs & UART_BUG_NOMSR)
1408 up->ier |= UART_IER_MSI;
1410 serial8250_rpm_get(up);
1411 serial_port_out(port, UART_IER, up->ier);
1412 serial8250_rpm_put(up);
1415 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1417 struct uart_port *port = &up->port;
1419 char flag = TTY_NORMAL;
1421 if (likely(lsr & UART_LSR_DR))
1422 ch = serial_in(up, UART_RX);
1425 * Intel 82571 has a Serial Over Lan device that will
1426 * set UART_LSR_BI without setting UART_LSR_DR when
1427 * it receives a break. To avoid reading from the
1428 * receive buffer without UART_LSR_DR bit set, we
1429 * just force the read character to be 0
1435 lsr |= up->lsr_saved_flags;
1436 up->lsr_saved_flags = 0;
1438 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1439 if (lsr & UART_LSR_BI) {
1440 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1443 * We do the SysRQ and SAK checking
1444 * here because otherwise the break
1445 * may get masked by ignore_status_mask
1446 * or read_status_mask.
1448 if (uart_handle_break(port))
1450 } else if (lsr & UART_LSR_PE)
1451 port->icount.parity++;
1452 else if (lsr & UART_LSR_FE)
1453 port->icount.frame++;
1454 if (lsr & UART_LSR_OE)
1455 port->icount.overrun++;
1458 * Mask off conditions which should be ignored.
1460 lsr &= port->read_status_mask;
1462 if (lsr & UART_LSR_BI) {
1463 DEBUG_INTR("handling break....");
1465 } else if (lsr & UART_LSR_PE)
1467 else if (lsr & UART_LSR_FE)
1470 if (uart_handle_sysrq_char(port, ch))
1473 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1477 * serial8250_rx_chars: processes according to the passed in LSR
1478 * value, and returns the remaining LSR bits not handled
1479 * by this Rx routine.
1481 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1483 struct uart_port *port = &up->port;
1484 int max_count = 256;
1487 serial8250_read_char(up, lsr);
1488 if (--max_count == 0)
1490 lsr = serial_in(up, UART_LSR);
1491 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1493 tty_flip_buffer_push(&port->state->port);
1496 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1498 void serial8250_tx_chars(struct uart_8250_port *up)
1500 struct uart_port *port = &up->port;
1501 struct circ_buf *xmit = &port->state->xmit;
1505 serial_out(up, UART_TX, port->x_char);
1510 if (uart_tx_stopped(port)) {
1511 serial8250_stop_tx(port);
1514 if (uart_circ_empty(xmit)) {
1519 count = up->tx_loadsz;
1521 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1522 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1524 if (uart_circ_empty(xmit))
1526 if (up->capabilities & UART_CAP_HFIFO) {
1527 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1531 } while (--count > 0);
1533 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1534 uart_write_wakeup(port);
1536 DEBUG_INTR("THRE...");
1539 * With RPM enabled, we have to wait until the FIFO is empty before the
1540 * HW can go idle. So we get here once again with empty FIFO and disable
1541 * the interrupt and RPM in __stop_tx()
1543 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1546 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1548 /* Caller holds uart port lock */
1549 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1551 struct uart_port *port = &up->port;
1552 unsigned int status = serial_in(up, UART_MSR);
1554 status |= up->msr_saved_flags;
1555 up->msr_saved_flags = 0;
1556 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1557 port->state != NULL) {
1558 if (status & UART_MSR_TERI)
1560 if (status & UART_MSR_DDSR)
1562 if (status & UART_MSR_DDCD)
1563 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1564 if (status & UART_MSR_DCTS)
1565 uart_handle_cts_change(port, status & UART_MSR_CTS);
1567 wake_up_interruptible(&port->state->port.delta_msr_wait);
1572 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1575 * This handles the interrupt from one port.
1577 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1579 unsigned char status;
1580 unsigned long flags;
1581 struct uart_8250_port *up = up_to_u8250p(port);
1584 if (iir & UART_IIR_NO_INT)
1587 spin_lock_irqsave(&port->lock, flags);
1589 status = serial_port_in(port, UART_LSR);
1591 DEBUG_INTR("status = %x...", status);
1593 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1595 dma_err = up->dma->rx_dma(up, iir);
1597 if (!up->dma || dma_err)
1598 status = serial8250_rx_chars(up, status);
1600 serial8250_modem_status(up);
1601 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1602 (status & UART_LSR_THRE))
1603 serial8250_tx_chars(up);
1605 spin_unlock_irqrestore(&port->lock, flags);
1608 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1610 static int serial8250_default_handle_irq(struct uart_port *port)
1612 struct uart_8250_port *up = up_to_u8250p(port);
1616 serial8250_rpm_get(up);
1618 iir = serial_port_in(port, UART_IIR);
1619 ret = serial8250_handle_irq(port, iir);
1621 serial8250_rpm_put(up);
1626 * These Exar UARTs have an extra interrupt indicator that could
1627 * fire for a few unimplemented interrupts. One of which is a
1628 * wakeup event when coming out of sleep. Put this here just
1629 * to be on the safe side that these interrupts don't go unhandled.
1631 static int exar_handle_irq(struct uart_port *port)
1633 unsigned char int0, int1, int2, int3;
1634 unsigned int iir = serial_port_in(port, UART_IIR);
1637 ret = serial8250_handle_irq(port, iir);
1639 if ((port->type == PORT_XR17V35X) ||
1640 (port->type == PORT_XR17D15X)) {
1641 int0 = serial_port_in(port, 0x80);
1642 int1 = serial_port_in(port, 0x81);
1643 int2 = serial_port_in(port, 0x82);
1644 int3 = serial_port_in(port, 0x83);
1650 static unsigned int serial8250_tx_empty(struct uart_port *port)
1652 struct uart_8250_port *up = up_to_u8250p(port);
1653 unsigned long flags;
1656 serial8250_rpm_get(up);
1658 spin_lock_irqsave(&port->lock, flags);
1659 lsr = serial_port_in(port, UART_LSR);
1660 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1661 spin_unlock_irqrestore(&port->lock, flags);
1663 serial8250_rpm_put(up);
1665 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1668 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1670 struct uart_8250_port *up = up_to_u8250p(port);
1671 unsigned int status;
1674 serial8250_rpm_get(up);
1675 status = serial8250_modem_status(up);
1676 serial8250_rpm_put(up);
1679 if (status & UART_MSR_DCD)
1681 if (status & UART_MSR_RI)
1683 if (status & UART_MSR_DSR)
1685 if (status & UART_MSR_CTS)
1690 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1692 struct uart_8250_port *up = up_to_u8250p(port);
1693 unsigned char mcr = 0;
1695 if (mctrl & TIOCM_RTS)
1696 mcr |= UART_MCR_RTS;
1697 if (mctrl & TIOCM_DTR)
1698 mcr |= UART_MCR_DTR;
1699 if (mctrl & TIOCM_OUT1)
1700 mcr |= UART_MCR_OUT1;
1701 if (mctrl & TIOCM_OUT2)
1702 mcr |= UART_MCR_OUT2;
1703 if (mctrl & TIOCM_LOOP)
1704 mcr |= UART_MCR_LOOP;
1706 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1708 serial_port_out(port, UART_MCR, mcr);
1710 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1712 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1714 if (port->set_mctrl)
1715 port->set_mctrl(port, mctrl);
1717 serial8250_do_set_mctrl(port, mctrl);
1720 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1722 struct uart_8250_port *up = up_to_u8250p(port);
1723 unsigned long flags;
1725 serial8250_rpm_get(up);
1726 spin_lock_irqsave(&port->lock, flags);
1727 if (break_state == -1)
1728 up->lcr |= UART_LCR_SBC;
1730 up->lcr &= ~UART_LCR_SBC;
1731 serial_port_out(port, UART_LCR, up->lcr);
1732 spin_unlock_irqrestore(&port->lock, flags);
1733 serial8250_rpm_put(up);
1737 * Wait for transmitter & holding register to empty
1739 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1741 unsigned int status, tmout = 10000;
1743 /* Wait up to 10ms for the character(s) to be sent. */
1745 status = serial_in(up, UART_LSR);
1747 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1749 if ((status & bits) == bits)
1756 /* Wait up to 1s for flow control if necessary */
1757 if (up->port.flags & UPF_CONS_FLOW) {
1759 for (tmout = 1000000; tmout; tmout--) {
1760 unsigned int msr = serial_in(up, UART_MSR);
1761 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1762 if (msr & UART_MSR_CTS)
1765 touch_nmi_watchdog();
1770 #ifdef CONFIG_CONSOLE_POLL
1772 * Console polling routines for writing and reading from the uart while
1773 * in an interrupt or debug context.
1776 static int serial8250_get_poll_char(struct uart_port *port)
1778 struct uart_8250_port *up = up_to_u8250p(port);
1782 serial8250_rpm_get(up);
1784 lsr = serial_port_in(port, UART_LSR);
1786 if (!(lsr & UART_LSR_DR)) {
1787 status = NO_POLL_CHAR;
1791 status = serial_port_in(port, UART_RX);
1793 serial8250_rpm_put(up);
1798 static void serial8250_put_poll_char(struct uart_port *port,
1802 struct uart_8250_port *up = up_to_u8250p(port);
1804 serial8250_rpm_get(up);
1806 * First save the IER then disable the interrupts
1808 ier = serial_port_in(port, UART_IER);
1809 if (up->capabilities & UART_CAP_UUE)
1810 serial_port_out(port, UART_IER, UART_IER_UUE);
1812 serial_port_out(port, UART_IER, 0);
1814 wait_for_xmitr(up, BOTH_EMPTY);
1816 * Send the character out.
1818 serial_port_out(port, UART_TX, c);
1821 * Finally, wait for transmitter to become empty
1822 * and restore the IER
1824 wait_for_xmitr(up, BOTH_EMPTY);
1825 serial_port_out(port, UART_IER, ier);
1826 serial8250_rpm_put(up);
1829 #endif /* CONFIG_CONSOLE_POLL */
1831 int serial8250_do_startup(struct uart_port *port)
1833 struct uart_8250_port *up = up_to_u8250p(port);
1834 unsigned long flags;
1835 unsigned char lsr, iir;
1838 if (!port->fifosize)
1839 port->fifosize = uart_config[port->type].fifo_size;
1841 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1842 if (!up->capabilities)
1843 up->capabilities = uart_config[port->type].flags;
1846 if (port->iotype != up->cur_iotype)
1847 set_io_from_upio(port);
1849 serial8250_rpm_get(up);
1850 if (port->type == PORT_16C950) {
1851 /* Wake up and initialize UART */
1853 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1854 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1855 serial_port_out(port, UART_IER, 0);
1856 serial_port_out(port, UART_LCR, 0);
1857 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1858 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1859 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1860 serial_port_out(port, UART_LCR, 0);
1863 #ifdef CONFIG_SERIAL_8250_RSA
1865 * If this is an RSA port, see if we can kick it up to the
1866 * higher speed clock.
1871 if (port->type == PORT_XR17V35X) {
1873 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1874 * MCR [7:5] and MSR [7:0]
1876 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1879 * Make sure all interrups are masked until initialization is
1880 * complete and the FIFOs are cleared
1882 serial_port_out(port, UART_IER, 0);
1886 * Clear the FIFO buffers and disable them.
1887 * (they will be reenabled in set_termios())
1889 serial8250_clear_fifos(up);
1892 * Clear the interrupt registers.
1894 serial_port_in(port, UART_LSR);
1895 serial_port_in(port, UART_RX);
1896 serial_port_in(port, UART_IIR);
1897 serial_port_in(port, UART_MSR);
1900 * At this point, there's no way the LSR could still be 0xff;
1901 * if it is, then bail out, because there's likely no UART
1904 if (!(port->flags & UPF_BUGGY_UART) &&
1905 (serial_port_in(port, UART_LSR) == 0xff)) {
1906 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1907 serial_index(port));
1913 * For a XR16C850, we need to set the trigger levels
1915 if (port->type == PORT_16850) {
1918 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1920 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1921 serial_port_out(port, UART_FCTR,
1922 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1923 serial_port_out(port, UART_TRG, UART_TRG_96);
1924 serial_port_out(port, UART_FCTR,
1925 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1926 serial_port_out(port, UART_TRG, UART_TRG_96);
1928 serial_port_out(port, UART_LCR, 0);
1934 * Test for UARTs that do not reassert THRE when the
1935 * transmitter is idle and the interrupt has already
1936 * been cleared. Real 16550s should always reassert
1937 * this interrupt whenever the transmitter is idle and
1938 * the interrupt is enabled. Delays are necessary to
1939 * allow register changes to become visible.
1941 spin_lock_irqsave(&port->lock, flags);
1942 if (up->port.irqflags & IRQF_SHARED)
1943 disable_irq_nosync(port->irq);
1945 wait_for_xmitr(up, UART_LSR_THRE);
1946 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1947 udelay(1); /* allow THRE to set */
1948 iir1 = serial_port_in(port, UART_IIR);
1949 serial_port_out(port, UART_IER, 0);
1950 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1951 udelay(1); /* allow a working UART time to re-assert THRE */
1952 iir = serial_port_in(port, UART_IIR);
1953 serial_port_out(port, UART_IER, 0);
1955 if (port->irqflags & IRQF_SHARED)
1956 enable_irq(port->irq);
1957 spin_unlock_irqrestore(&port->lock, flags);
1960 * If the interrupt is not reasserted, or we otherwise
1961 * don't trust the iir, setup a timer to kick the UART
1962 * on a regular basis.
1964 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1965 up->port.flags & UPF_BUG_THRE) {
1966 up->bugs |= UART_BUG_THRE;
1970 retval = up->ops->setup_irq(up);
1975 * Now, initialize the UART
1977 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1979 spin_lock_irqsave(&port->lock, flags);
1980 if (up->port.flags & UPF_FOURPORT) {
1982 up->port.mctrl |= TIOCM_OUT1;
1985 * Most PC uarts need OUT2 raised to enable interrupts.
1988 up->port.mctrl |= TIOCM_OUT2;
1990 serial8250_set_mctrl(port, port->mctrl);
1992 /* Serial over Lan (SoL) hack:
1993 Intel 8257x Gigabit ethernet chips have a
1994 16550 emulation, to be used for Serial Over Lan.
1995 Those chips take a longer time than a normal
1996 serial device to signalize that a transmission
1997 data was queued. Due to that, the above test generally
1998 fails. One solution would be to delay the reading of
1999 iir. However, this is not reliable, since the timeout
2000 is variable. So, let's just don't test if we receive
2001 TX irq. This way, we'll never enable UART_BUG_TXEN.
2003 if (up->port.flags & UPF_NO_TXEN_TEST)
2004 goto dont_test_tx_en;
2007 * Do a quick test to see if we receive an
2008 * interrupt when we enable the TX irq.
2010 serial_port_out(port, UART_IER, UART_IER_THRI);
2011 lsr = serial_port_in(port, UART_LSR);
2012 iir = serial_port_in(port, UART_IIR);
2013 serial_port_out(port, UART_IER, 0);
2015 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2016 if (!(up->bugs & UART_BUG_TXEN)) {
2017 up->bugs |= UART_BUG_TXEN;
2018 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2019 serial_index(port));
2022 up->bugs &= ~UART_BUG_TXEN;
2026 spin_unlock_irqrestore(&port->lock, flags);
2029 * Clear the interrupt registers again for luck, and clear the
2030 * saved flags to avoid getting false values from polling
2031 * routines or the previous session.
2033 serial_port_in(port, UART_LSR);
2034 serial_port_in(port, UART_RX);
2035 serial_port_in(port, UART_IIR);
2036 serial_port_in(port, UART_MSR);
2037 up->lsr_saved_flags = 0;
2038 up->msr_saved_flags = 0;
2041 * Request DMA channels for both RX and TX.
2044 retval = serial8250_request_dma(up);
2046 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2047 serial_index(port));
2053 * Set the IER shadow for rx interrupts but defer actual interrupt
2054 * enable until after the FIFOs are enabled; otherwise, an already-
2055 * active sender can swamp the interrupt handler with "too much work".
2057 up->ier = UART_IER_RLSI | UART_IER_RDI;
2059 if (port->flags & UPF_FOURPORT) {
2062 * Enable interrupts on the AST Fourport board
2064 icp = (port->iobase & 0xfe0) | 0x01f;
2070 serial8250_rpm_put(up);
2073 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2075 static int serial8250_startup(struct uart_port *port)
2078 return port->startup(port);
2079 return serial8250_do_startup(port);
2082 void serial8250_do_shutdown(struct uart_port *port)
2084 struct uart_8250_port *up = up_to_u8250p(port);
2085 unsigned long flags;
2087 serial8250_rpm_get(up);
2089 * Disable interrupts from this port
2091 spin_lock_irqsave(&port->lock, flags);
2093 serial_port_out(port, UART_IER, 0);
2094 spin_unlock_irqrestore(&port->lock, flags);
2096 synchronize_irq(port->irq);
2099 serial8250_release_dma(up);
2101 spin_lock_irqsave(&port->lock, flags);
2102 if (port->flags & UPF_FOURPORT) {
2103 /* reset interrupts on the AST Fourport board */
2104 inb((port->iobase & 0xfe0) | 0x1f);
2105 port->mctrl |= TIOCM_OUT1;
2107 port->mctrl &= ~TIOCM_OUT2;
2109 serial8250_set_mctrl(port, port->mctrl);
2110 spin_unlock_irqrestore(&port->lock, flags);
2113 * Disable break condition and FIFOs
2115 serial_port_out(port, UART_LCR,
2116 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2117 serial8250_clear_fifos(up);
2119 #ifdef CONFIG_SERIAL_8250_RSA
2121 * Reset the RSA board back to 115kbps compat mode.
2127 * Read data port to reset things, and then unlink from
2130 serial_port_in(port, UART_RX);
2131 serial8250_rpm_put(up);
2133 up->ops->release_irq(up);
2135 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2137 static void serial8250_shutdown(struct uart_port *port)
2140 port->shutdown(port);
2142 serial8250_do_shutdown(port);
2146 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2147 * Calculate divisor with extra 4-bit fractional portion
2149 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2153 struct uart_port *port = &up->port;
2154 unsigned int quot_16;
2156 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2157 *frac = quot_16 & 0x0f;
2159 return quot_16 >> 4;
2162 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2166 struct uart_port *port = &up->port;
2170 * Handle magic divisors for baud rates above baud_base on
2171 * SMSC SuperIO chips.
2174 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2175 baud == (port->uartclk/4))
2177 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2178 baud == (port->uartclk/8))
2180 else if (up->port.type == PORT_XR17V35X)
2181 quot = xr17v35x_get_divisor(up, baud, frac);
2183 quot = uart_get_divisor(port, baud);
2186 * Oxford Semi 952 rev B workaround
2188 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2194 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2199 switch (c_cflag & CSIZE) {
2201 cval = UART_LCR_WLEN5;
2204 cval = UART_LCR_WLEN6;
2207 cval = UART_LCR_WLEN7;
2211 cval = UART_LCR_WLEN8;
2215 if (c_cflag & CSTOPB)
2216 cval |= UART_LCR_STOP;
2217 if (c_cflag & PARENB) {
2218 cval |= UART_LCR_PARITY;
2219 if (up->bugs & UART_BUG_PARITY)
2220 up->fifo_bug = true;
2222 if (!(c_cflag & PARODD))
2223 cval |= UART_LCR_EPAR;
2225 if (c_cflag & CMSPAR)
2226 cval |= UART_LCR_SPAR;
2232 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2233 unsigned int quot, unsigned int quot_frac)
2235 struct uart_8250_port *up = up_to_u8250p(port);
2237 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2238 if (is_omap1510_8250(up)) {
2239 if (baud == 115200) {
2241 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2243 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2247 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2248 * otherwise just set DLAB
2250 if (up->capabilities & UART_NATSEMI)
2251 serial_port_out(port, UART_LCR, 0xe0);
2253 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2255 serial_dl_write(up, quot);
2257 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2258 if (up->port.type == PORT_XR17V35X)
2259 serial_port_out(port, 0x2, quot_frac);
2263 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2264 struct ktermios *old)
2266 unsigned int tolerance = port->uartclk / 100;
2269 * Ask the core to calculate the divisor for us.
2270 * Allow 1% tolerance at the upper limit so uart clks marginally
2271 * slower than nominal still match standard baud rates without
2272 * causing transmission errors.
2274 return uart_get_baud_rate(port, termios, old,
2275 port->uartclk / 16 / 0xffff,
2276 (port->uartclk + tolerance) / 16);
2280 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2281 struct ktermios *old)
2283 struct uart_8250_port *up = up_to_u8250p(port);
2285 unsigned long flags;
2286 unsigned int baud, quot, frac = 0;
2288 cval = serial8250_compute_lcr(up, termios->c_cflag);
2290 baud = serial8250_get_baud_rate(port, termios, old);
2291 quot = serial8250_get_divisor(up, baud, &frac);
2294 * Ok, we're now changing the port state. Do it with
2295 * interrupts disabled.
2297 serial8250_rpm_get(up);
2298 spin_lock_irqsave(&port->lock, flags);
2300 up->lcr = cval; /* Save computed LCR */
2302 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2303 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2304 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2305 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2306 up->fcr |= UART_FCR_TRIGGER_1;
2311 * MCR-based auto flow control. When AFE is enabled, RTS will be
2312 * deasserted when the receive FIFO contains more characters than
2313 * the trigger, or the MCR RTS bit is cleared. In the case where
2314 * the remote UART is not using CTS auto flow control, we must
2315 * have sufficient FIFO entries for the latency of the remote
2316 * UART to respond. IOW, at least 32 bytes of FIFO.
2318 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2319 up->mcr &= ~UART_MCR_AFE;
2320 if (termios->c_cflag & CRTSCTS)
2321 up->mcr |= UART_MCR_AFE;
2325 * Update the per-port timeout.
2327 uart_update_timeout(port, termios->c_cflag, baud);
2329 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2330 if (termios->c_iflag & INPCK)
2331 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2332 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2333 port->read_status_mask |= UART_LSR_BI;
2336 * Characteres to ignore
2338 port->ignore_status_mask = 0;
2339 if (termios->c_iflag & IGNPAR)
2340 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2341 if (termios->c_iflag & IGNBRK) {
2342 port->ignore_status_mask |= UART_LSR_BI;
2344 * If we're ignoring parity and break indicators,
2345 * ignore overruns too (for real raw support).
2347 if (termios->c_iflag & IGNPAR)
2348 port->ignore_status_mask |= UART_LSR_OE;
2352 * ignore all characters if CREAD is not set
2354 if ((termios->c_cflag & CREAD) == 0)
2355 port->ignore_status_mask |= UART_LSR_DR;
2358 * CTS flow control flag and modem status interrupts
2360 up->ier &= ~UART_IER_MSI;
2361 if (!(up->bugs & UART_BUG_NOMSR) &&
2362 UART_ENABLE_MS(&up->port, termios->c_cflag))
2363 up->ier |= UART_IER_MSI;
2364 if (up->capabilities & UART_CAP_UUE)
2365 up->ier |= UART_IER_UUE;
2366 if (up->capabilities & UART_CAP_RTOIE)
2367 up->ier |= UART_IER_RTOIE;
2369 serial_port_out(port, UART_IER, up->ier);
2371 if (up->capabilities & UART_CAP_EFR) {
2372 unsigned char efr = 0;
2374 * TI16C752/Startech hardware flow control. FIXME:
2375 * - TI16C752 requires control thresholds to be set.
2376 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2378 if (termios->c_cflag & CRTSCTS)
2379 efr |= UART_EFR_CTS;
2381 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2382 if (port->flags & UPF_EXAR_EFR)
2383 serial_port_out(port, UART_XR_EFR, efr);
2385 serial_port_out(port, UART_EFR, efr);
2388 serial8250_set_divisor(port, baud, quot, frac);
2391 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2392 * is written without DLAB set, this mode will be disabled.
2394 if (port->type == PORT_16750)
2395 serial_port_out(port, UART_FCR, up->fcr);
2397 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2398 if (port->type != PORT_16750) {
2399 /* emulated UARTs (Lucent Venus 167x) need two steps */
2400 if (up->fcr & UART_FCR_ENABLE_FIFO)
2401 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2402 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2404 serial8250_set_mctrl(port, port->mctrl);
2405 spin_unlock_irqrestore(&port->lock, flags);
2406 serial8250_rpm_put(up);
2408 /* Don't rewrite B0 */
2409 if (tty_termios_baud_rate(termios))
2410 tty_termios_encode_baud_rate(termios, baud, baud);
2412 EXPORT_SYMBOL(serial8250_do_set_termios);
2415 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2416 struct ktermios *old)
2418 if (port->set_termios)
2419 port->set_termios(port, termios, old);
2421 serial8250_do_set_termios(port, termios, old);
2425 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2427 if (termios->c_line == N_PPS) {
2428 port->flags |= UPF_HARDPPS_CD;
2429 spin_lock_irq(&port->lock);
2430 serial8250_enable_ms(port);
2431 spin_unlock_irq(&port->lock);
2433 port->flags &= ~UPF_HARDPPS_CD;
2434 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2435 spin_lock_irq(&port->lock);
2436 serial8250_disable_ms(port);
2437 spin_unlock_irq(&port->lock);
2443 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2444 unsigned int oldstate)
2446 struct uart_8250_port *p = up_to_u8250p(port);
2448 serial8250_set_sleep(p, state != 0);
2450 EXPORT_SYMBOL(serial8250_do_pm);
2453 serial8250_pm(struct uart_port *port, unsigned int state,
2454 unsigned int oldstate)
2457 port->pm(port, state, oldstate);
2459 serial8250_do_pm(port, state, oldstate);
2462 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2464 if (pt->port.mapsize)
2465 return pt->port.mapsize;
2466 if (pt->port.iotype == UPIO_AU) {
2467 if (pt->port.type == PORT_RT2880)
2471 if (is_omap1_8250(pt))
2472 return 0x16 << pt->port.regshift;
2474 return 8 << pt->port.regshift;
2478 * Resource handling.
2480 static int serial8250_request_std_resource(struct uart_8250_port *up)
2482 unsigned int size = serial8250_port_size(up);
2483 struct uart_port *port = &up->port;
2486 switch (port->iotype) {
2496 if (!request_mem_region(port->mapbase, size, "serial")) {
2501 if (port->flags & UPF_IOREMAP) {
2502 port->membase = ioremap_nocache(port->mapbase, size);
2503 if (!port->membase) {
2504 release_mem_region(port->mapbase, size);
2512 if (!request_region(port->iobase, size, "serial"))
2519 static void serial8250_release_std_resource(struct uart_8250_port *up)
2521 unsigned int size = serial8250_port_size(up);
2522 struct uart_port *port = &up->port;
2524 switch (port->iotype) {
2534 if (port->flags & UPF_IOREMAP) {
2535 iounmap(port->membase);
2536 port->membase = NULL;
2539 release_mem_region(port->mapbase, size);
2544 release_region(port->iobase, size);
2549 static void serial8250_release_port(struct uart_port *port)
2551 struct uart_8250_port *up = up_to_u8250p(port);
2553 serial8250_release_std_resource(up);
2556 static int serial8250_request_port(struct uart_port *port)
2558 struct uart_8250_port *up = up_to_u8250p(port);
2560 return serial8250_request_std_resource(up);
2563 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2565 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2566 unsigned char bytes;
2568 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2570 return bytes ? bytes : -EOPNOTSUPP;
2573 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2575 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2578 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2581 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2582 if (bytes < conf_type->rxtrig_bytes[i])
2583 /* Use the nearest lower value */
2584 return (--i) << UART_FCR_R_TRIG_SHIFT;
2587 return UART_FCR_R_TRIG_11;
2590 static int do_get_rxtrig(struct tty_port *port)
2592 struct uart_state *state = container_of(port, struct uart_state, port);
2593 struct uart_port *uport = state->uart_port;
2594 struct uart_8250_port *up =
2595 container_of(uport, struct uart_8250_port, port);
2597 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2600 return fcr_get_rxtrig_bytes(up);
2603 static int do_serial8250_get_rxtrig(struct tty_port *port)
2607 mutex_lock(&port->mutex);
2608 rxtrig_bytes = do_get_rxtrig(port);
2609 mutex_unlock(&port->mutex);
2611 return rxtrig_bytes;
2614 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2615 struct device_attribute *attr, char *buf)
2617 struct tty_port *port = dev_get_drvdata(dev);
2620 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2621 if (rxtrig_bytes < 0)
2622 return rxtrig_bytes;
2624 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2627 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2629 struct uart_state *state = container_of(port, struct uart_state, port);
2630 struct uart_port *uport = state->uart_port;
2631 struct uart_8250_port *up =
2632 container_of(uport, struct uart_8250_port, port);
2635 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2639 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2643 serial8250_clear_fifos(up);
2644 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2645 up->fcr |= (unsigned char)rxtrig;
2646 serial_out(up, UART_FCR, up->fcr);
2650 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2654 mutex_lock(&port->mutex);
2655 ret = do_set_rxtrig(port, bytes);
2656 mutex_unlock(&port->mutex);
2661 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2662 struct device_attribute *attr, const char *buf, size_t count)
2664 struct tty_port *port = dev_get_drvdata(dev);
2665 unsigned char bytes;
2671 ret = kstrtou8(buf, 10, &bytes);
2675 ret = do_serial8250_set_rxtrig(port, bytes);
2682 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2683 serial8250_get_attr_rx_trig_bytes,
2684 serial8250_set_attr_rx_trig_bytes);
2686 static struct attribute *serial8250_dev_attrs[] = {
2687 &dev_attr_rx_trig_bytes.attr,
2691 static struct attribute_group serial8250_dev_attr_group = {
2692 .attrs = serial8250_dev_attrs,
2695 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2697 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2699 if (conf_type->rxtrig_bytes[0])
2700 up->port.attr_group = &serial8250_dev_attr_group;
2703 static void serial8250_config_port(struct uart_port *port, int flags)
2705 struct uart_8250_port *up = up_to_u8250p(port);
2709 * Find the region that we can probe for. This in turn
2710 * tells us whether we can probe for the type of port.
2712 ret = serial8250_request_std_resource(up);
2716 if (port->iotype != up->cur_iotype)
2717 set_io_from_upio(port);
2719 if (flags & UART_CONFIG_TYPE)
2722 /* if access method is AU, it is a 16550 with a quirk */
2723 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2724 up->bugs |= UART_BUG_NOMSR;
2726 /* HW bugs may trigger IRQ while IIR == NO_INT */
2727 if (port->type == PORT_TEGRA)
2728 up->bugs |= UART_BUG_NOMSR;
2730 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2733 if (port->type == PORT_UNKNOWN)
2734 serial8250_release_std_resource(up);
2736 /* Fixme: probably not the best place for this */
2737 if ((port->type == PORT_XR17V35X) ||
2738 (port->type == PORT_XR17D15X))
2739 port->handle_irq = exar_handle_irq;
2741 register_dev_spec_attr_grp(up);
2742 up->fcr = uart_config[up->port.type].fcr;
2746 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2748 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2749 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2750 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2751 ser->type == PORT_STARTECH)
2757 serial8250_type(struct uart_port *port)
2759 int type = port->type;
2761 if (type >= ARRAY_SIZE(uart_config))
2763 return uart_config[type].name;
2766 static const struct uart_ops serial8250_pops = {
2767 .tx_empty = serial8250_tx_empty,
2768 .set_mctrl = serial8250_set_mctrl,
2769 .get_mctrl = serial8250_get_mctrl,
2770 .stop_tx = serial8250_stop_tx,
2771 .start_tx = serial8250_start_tx,
2772 .throttle = serial8250_throttle,
2773 .unthrottle = serial8250_unthrottle,
2774 .stop_rx = serial8250_stop_rx,
2775 .enable_ms = serial8250_enable_ms,
2776 .break_ctl = serial8250_break_ctl,
2777 .startup = serial8250_startup,
2778 .shutdown = serial8250_shutdown,
2779 .set_termios = serial8250_set_termios,
2780 .set_ldisc = serial8250_set_ldisc,
2781 .pm = serial8250_pm,
2782 .type = serial8250_type,
2783 .release_port = serial8250_release_port,
2784 .request_port = serial8250_request_port,
2785 .config_port = serial8250_config_port,
2786 .verify_port = serial8250_verify_port,
2787 #ifdef CONFIG_CONSOLE_POLL
2788 .poll_get_char = serial8250_get_poll_char,
2789 .poll_put_char = serial8250_put_poll_char,
2793 void serial8250_init_port(struct uart_8250_port *up)
2795 struct uart_port *port = &up->port;
2797 spin_lock_init(&port->lock);
2798 port->ops = &serial8250_pops;
2800 up->cur_iotype = 0xFF;
2802 EXPORT_SYMBOL_GPL(serial8250_init_port);
2804 void serial8250_set_defaults(struct uart_8250_port *up)
2806 struct uart_port *port = &up->port;
2808 if (up->port.flags & UPF_FIXED_TYPE) {
2809 unsigned int type = up->port.type;
2811 if (!up->port.fifosize)
2812 up->port.fifosize = uart_config[type].fifo_size;
2814 up->tx_loadsz = uart_config[type].tx_loadsz;
2815 if (!up->capabilities)
2816 up->capabilities = uart_config[type].flags;
2819 set_io_from_upio(port);
2821 /* default dma handlers */
2823 if (!up->dma->tx_dma)
2824 up->dma->tx_dma = serial8250_tx_dma;
2825 if (!up->dma->rx_dma)
2826 up->dma->rx_dma = serial8250_rx_dma;
2829 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2831 #ifdef CONFIG_SERIAL_8250_CONSOLE
2833 static void serial8250_console_putchar(struct uart_port *port, int ch)
2835 struct uart_8250_port *up = up_to_u8250p(port);
2837 wait_for_xmitr(up, UART_LSR_THRE);
2838 serial_port_out(port, UART_TX, ch);
2842 * Restore serial console when h/w power-off detected
2844 static void serial8250_console_restore(struct uart_8250_port *up)
2846 struct uart_port *port = &up->port;
2847 struct ktermios termios;
2848 unsigned int baud, quot, frac = 0;
2850 termios.c_cflag = port->cons->cflag;
2851 if (port->state->port.tty && termios.c_cflag == 0)
2852 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2854 baud = serial8250_get_baud_rate(port, &termios, NULL);
2855 quot = serial8250_get_divisor(up, baud, &frac);
2857 serial8250_set_divisor(port, baud, quot, frac);
2858 serial_port_out(port, UART_LCR, up->lcr);
2859 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2863 * Print a string to the serial port trying not to disturb
2864 * any possible real use of the port...
2866 * The console_lock must be held when we get here.
2868 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2871 struct uart_port *port = &up->port;
2872 unsigned long flags;
2876 touch_nmi_watchdog();
2878 serial8250_rpm_get(up);
2882 else if (oops_in_progress)
2883 locked = spin_trylock_irqsave(&port->lock, flags);
2885 spin_lock_irqsave(&port->lock, flags);
2888 * First save the IER then disable the interrupts
2890 ier = serial_port_in(port, UART_IER);
2892 if (up->capabilities & UART_CAP_UUE)
2893 serial_port_out(port, UART_IER, UART_IER_UUE);
2895 serial_port_out(port, UART_IER, 0);
2897 /* check scratch reg to see if port powered off during system sleep */
2898 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2899 serial8250_console_restore(up);
2903 uart_console_write(port, s, count, serial8250_console_putchar);
2906 * Finally, wait for transmitter to become empty
2907 * and restore the IER
2909 wait_for_xmitr(up, BOTH_EMPTY);
2910 serial_port_out(port, UART_IER, ier);
2913 * The receive handling will happen properly because the
2914 * receive ready bit will still be set; it is not cleared
2915 * on read. However, modem control will not, we must
2916 * call it if we have saved something in the saved flags
2917 * while processing with interrupts off.
2919 if (up->msr_saved_flags)
2920 serial8250_modem_status(up);
2923 spin_unlock_irqrestore(&port->lock, flags);
2924 serial8250_rpm_put(up);
2927 static unsigned int probe_baud(struct uart_port *port)
2929 unsigned char lcr, dll, dlm;
2932 lcr = serial_port_in(port, UART_LCR);
2933 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2934 dll = serial_port_in(port, UART_DLL);
2935 dlm = serial_port_in(port, UART_DLM);
2936 serial_port_out(port, UART_LCR, lcr);
2938 quot = (dlm << 8) | dll;
2939 return (port->uartclk / 16) / quot;
2942 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2949 if (!port->iobase && !port->membase)
2953 uart_parse_options(options, &baud, &parity, &bits, &flow);
2955 baud = probe_baud(port);
2957 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2960 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2962 MODULE_LICENSE("GPL");