2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
48 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
50 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
51 #define UART_EXAR_DVID 0x8d /* Device identification */
57 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
59 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
62 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
65 * Here we define the default xmit fifo size used for each type of UART.
67 static const struct serial8250_config uart_config[] = {
92 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
93 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
94 .rxtrig_bytes = {1, 4, 8, 14},
95 .flags = UART_CAP_FIFO,
106 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
112 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
114 .rxtrig_bytes = {8, 16, 24, 28},
115 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
121 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
123 .rxtrig_bytes = {1, 16, 32, 56},
124 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
132 .name = "16C950/954",
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
136 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
137 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
145 .rxtrig_bytes = {8, 16, 56, 60},
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
153 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
160 .flags = UART_CAP_FIFO,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_NATSEMI,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 .flags = UART_CAP_FIFO,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
188 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
195 .flags = UART_CAP_FIFO | UART_CAP_AFE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
203 .rxtrig_bytes = {1, 4, 8, 14},
204 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
220 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
227 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
228 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
229 .flags = UART_CAP_FIFO,
231 [PORT_BRCM_TRUMANAGE] = {
235 .flags = UART_CAP_HFIFO,
240 [PORT_ALTR_16550_F32] = {
241 .name = "Altera 16550 FIFO32",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F64] = {
248 .name = "Altera 16550 FIFO64",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 [PORT_ALTR_16550_F128] = {
255 .name = "Altera 16550 FIFO128",
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
263 * workaround of errata A-008006 which states that tx_loadsz should
264 * be configured less than Maximum supported fifo bytes.
266 [PORT_16550A_FSL64] = {
267 .name = "16550A_FSL64",
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
272 .flags = UART_CAP_FIFO,
275 .name = "Palmchip BK-3103",
278 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
279 .rxtrig_bytes = {1, 4, 8, 14},
280 .flags = UART_CAP_FIFO,
283 .name = "TI DA8xx/66AK2x",
286 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
288 .rxtrig_bytes = {1, 4, 8, 14},
289 .flags = UART_CAP_FIFO | UART_CAP_AFE,
293 /* Uart divisor latch read */
294 static int default_serial_dl_read(struct uart_8250_port *up)
296 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
299 /* Uart divisor latch write */
300 static void default_serial_dl_write(struct uart_8250_port *up, int value)
302 serial_out(up, UART_DLL, value & 0xff);
303 serial_out(up, UART_DLM, value >> 8 & 0xff);
306 #ifdef CONFIG_SERIAL_8250_RT288X
308 /* Au1x00/RT288x UART hardware has a weird register layout */
309 static const s8 au_io_in_map[8] = {
317 -1, /* UART_SCR (unmapped) */
320 static const s8 au_io_out_map[8] = {
326 -1, /* UART_LSR (unmapped) */
327 -1, /* UART_MSR (unmapped) */
328 -1, /* UART_SCR (unmapped) */
331 static unsigned int au_serial_in(struct uart_port *p, int offset)
333 if (offset >= ARRAY_SIZE(au_io_in_map))
335 offset = au_io_in_map[offset];
338 return __raw_readl(p->membase + (offset << p->regshift));
341 static void au_serial_out(struct uart_port *p, int offset, int value)
343 if (offset >= ARRAY_SIZE(au_io_out_map))
345 offset = au_io_out_map[offset];
348 __raw_writel(value, p->membase + (offset << p->regshift));
351 /* Au1x00 haven't got a standard divisor latch */
352 static int au_serial_dl_read(struct uart_8250_port *up)
354 return __raw_readl(up->port.membase + 0x28);
357 static void au_serial_dl_write(struct uart_8250_port *up, int value)
359 __raw_writel(value, up->port.membase + 0x28);
364 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
366 offset = offset << p->regshift;
367 outb(p->hub6 - 1 + offset, p->iobase);
368 return inb(p->iobase + 1);
371 static void hub6_serial_out(struct uart_port *p, int offset, int value)
373 offset = offset << p->regshift;
374 outb(p->hub6 - 1 + offset, p->iobase);
375 outb(value, p->iobase + 1);
378 static unsigned int mem_serial_in(struct uart_port *p, int offset)
380 offset = offset << p->regshift;
381 return readb(p->membase + offset);
384 static void mem_serial_out(struct uart_port *p, int offset, int value)
386 offset = offset << p->regshift;
387 writeb(value, p->membase + offset);
390 static void mem16_serial_out(struct uart_port *p, int offset, int value)
392 offset = offset << p->regshift;
393 writew(value, p->membase + offset);
396 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
398 offset = offset << p->regshift;
399 return readw(p->membase + offset);
402 static void mem32_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 writel(value, p->membase + offset);
408 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
410 offset = offset << p->regshift;
411 return readl(p->membase + offset);
414 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
416 offset = offset << p->regshift;
417 iowrite32be(value, p->membase + offset);
420 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
422 offset = offset << p->regshift;
423 return ioread32be(p->membase + offset);
426 static unsigned int io_serial_in(struct uart_port *p, int offset)
428 offset = offset << p->regshift;
429 return inb(p->iobase + offset);
432 static void io_serial_out(struct uart_port *p, int offset, int value)
434 offset = offset << p->regshift;
435 outb(value, p->iobase + offset);
438 static int serial8250_default_handle_irq(struct uart_port *port);
439 static int exar_handle_irq(struct uart_port *port);
441 static void set_io_from_upio(struct uart_port *p)
443 struct uart_8250_port *up = up_to_u8250p(p);
445 up->dl_read = default_serial_dl_read;
446 up->dl_write = default_serial_dl_write;
450 p->serial_in = hub6_serial_in;
451 p->serial_out = hub6_serial_out;
455 p->serial_in = mem_serial_in;
456 p->serial_out = mem_serial_out;
460 p->serial_in = mem16_serial_in;
461 p->serial_out = mem16_serial_out;
465 p->serial_in = mem32_serial_in;
466 p->serial_out = mem32_serial_out;
470 p->serial_in = mem32be_serial_in;
471 p->serial_out = mem32be_serial_out;
474 #ifdef CONFIG_SERIAL_8250_RT288X
476 p->serial_in = au_serial_in;
477 p->serial_out = au_serial_out;
478 up->dl_read = au_serial_dl_read;
479 up->dl_write = au_serial_dl_write;
484 p->serial_in = io_serial_in;
485 p->serial_out = io_serial_out;
488 /* Remember loaded iotype */
489 up->cur_iotype = p->iotype;
490 p->handle_irq = serial8250_default_handle_irq;
494 serial_port_out_sync(struct uart_port *p, int offset, int value)
502 p->serial_out(p, offset, value);
503 p->serial_in(p, UART_LCR); /* safe, no side-effects */
506 p->serial_out(p, offset, value);
513 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
515 serial_out(up, UART_SCR, offset);
516 serial_out(up, UART_ICR, value);
519 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
523 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
524 serial_out(up, UART_SCR, offset);
525 value = serial_in(up, UART_ICR);
526 serial_icr_write(up, UART_ACR, up->acr);
534 static void serial8250_clear_fifos(struct uart_8250_port *p)
536 if (p->capabilities & UART_CAP_FIFO) {
537 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
538 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
539 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
540 serial_out(p, UART_FCR, 0);
544 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
546 unsigned char mcr = serial8250_in_MCR(p);
548 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
551 mcr &= ~UART_MCR_RTS;
552 serial8250_out_MCR(p, mcr);
555 static void serial8250_em485_handle_start_tx(unsigned long arg);
556 static void serial8250_em485_handle_stop_tx(unsigned long arg);
558 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
560 serial8250_clear_fifos(p);
561 serial_out(p, UART_FCR, p->fcr);
563 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
565 void serial8250_rpm_get(struct uart_8250_port *p)
567 if (!(p->capabilities & UART_CAP_RPM))
569 pm_runtime_get_sync(p->port.dev);
571 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
573 void serial8250_rpm_put(struct uart_8250_port *p)
575 if (!(p->capabilities & UART_CAP_RPM))
577 pm_runtime_mark_last_busy(p->port.dev);
578 pm_runtime_put_autosuspend(p->port.dev);
580 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
583 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
584 * @p: uart_8250_port port instance
586 * The function is used to start rs485 software emulating on the
587 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
588 * transmission. The function is idempotent, so it is safe to call it
591 * The caller MUST enable interrupt on empty shift register before
592 * calling serial8250_em485_init(). This interrupt is not a part of
593 * 8250 standard, but implementation defined.
595 * The function is supposed to be called from .rs485_config callback
596 * or from any other callback protected with p->port.lock spinlock.
598 * See also serial8250_em485_destroy()
600 * Return 0 - success, -errno - otherwise
602 int serial8250_em485_init(struct uart_8250_port *p)
607 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
611 setup_timer(&p->em485->stop_tx_timer,
612 serial8250_em485_handle_stop_tx, (unsigned long)p);
613 setup_timer(&p->em485->start_tx_timer,
614 serial8250_em485_handle_start_tx, (unsigned long)p);
615 p->em485->active_timer = NULL;
617 serial8250_em485_rts_after_send(p);
621 EXPORT_SYMBOL_GPL(serial8250_em485_init);
624 * serial8250_em485_destroy() - put uart_8250_port into normal state
625 * @p: uart_8250_port port instance
627 * The function is used to stop rs485 software emulating on the
628 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
629 * call it multiple times.
631 * The function is supposed to be called from .rs485_config callback
632 * or from any other callback protected with p->port.lock spinlock.
634 * See also serial8250_em485_init()
636 void serial8250_em485_destroy(struct uart_8250_port *p)
641 del_timer(&p->em485->start_tx_timer);
642 del_timer(&p->em485->stop_tx_timer);
647 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
650 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
651 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
652 * empty and the HW can idle again.
654 void serial8250_rpm_get_tx(struct uart_8250_port *p)
656 unsigned char rpm_active;
658 if (!(p->capabilities & UART_CAP_RPM))
661 rpm_active = xchg(&p->rpm_tx_active, 1);
664 pm_runtime_get_sync(p->port.dev);
666 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
668 void serial8250_rpm_put_tx(struct uart_8250_port *p)
670 unsigned char rpm_active;
672 if (!(p->capabilities & UART_CAP_RPM))
675 rpm_active = xchg(&p->rpm_tx_active, 0);
678 pm_runtime_mark_last_busy(p->port.dev);
679 pm_runtime_put_autosuspend(p->port.dev);
681 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
684 * IER sleep support. UARTs which have EFRs need the "extended
685 * capability" bit enabled. Note that on XR16C850s, we need to
686 * reset LCR to write to IER.
688 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
690 unsigned char lcr = 0, efr = 0;
692 * Exar UARTs have a SLEEP register that enables or disables
693 * each UART to enter sleep mode separately. On the XR17V35x the
694 * register is accessible to each UART at the UART_EXAR_SLEEP
695 * offset but the UART channel may only write to the corresponding
698 serial8250_rpm_get(p);
699 if ((p->port.type == PORT_XR17V35X) ||
700 (p->port.type == PORT_XR17D15X)) {
701 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
705 if (p->capabilities & UART_CAP_SLEEP) {
706 if (p->capabilities & UART_CAP_EFR) {
707 lcr = serial_in(p, UART_LCR);
708 efr = serial_in(p, UART_EFR);
709 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
710 serial_out(p, UART_EFR, UART_EFR_ECB);
711 serial_out(p, UART_LCR, 0);
713 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
714 if (p->capabilities & UART_CAP_EFR) {
715 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
716 serial_out(p, UART_EFR, efr);
717 serial_out(p, UART_LCR, lcr);
721 serial8250_rpm_put(p);
724 #ifdef CONFIG_SERIAL_8250_RSA
726 * Attempts to turn on the RSA FIFO. Returns zero on failure.
727 * We set the port uart clock rate if we succeed.
729 static int __enable_rsa(struct uart_8250_port *up)
734 mode = serial_in(up, UART_RSA_MSR);
735 result = mode & UART_RSA_MSR_FIFO;
738 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
739 mode = serial_in(up, UART_RSA_MSR);
740 result = mode & UART_RSA_MSR_FIFO;
744 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
749 static void enable_rsa(struct uart_8250_port *up)
751 if (up->port.type == PORT_RSA) {
752 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
753 spin_lock_irq(&up->port.lock);
755 spin_unlock_irq(&up->port.lock);
757 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
758 serial_out(up, UART_RSA_FRR, 0);
763 * Attempts to turn off the RSA FIFO. Returns zero on failure.
764 * It is unknown why interrupts were disabled in here. However,
765 * the caller is expected to preserve this behaviour by grabbing
766 * the spinlock before calling this function.
768 static void disable_rsa(struct uart_8250_port *up)
773 if (up->port.type == PORT_RSA &&
774 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
775 spin_lock_irq(&up->port.lock);
777 mode = serial_in(up, UART_RSA_MSR);
778 result = !(mode & UART_RSA_MSR_FIFO);
781 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
782 mode = serial_in(up, UART_RSA_MSR);
783 result = !(mode & UART_RSA_MSR_FIFO);
787 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
788 spin_unlock_irq(&up->port.lock);
791 #endif /* CONFIG_SERIAL_8250_RSA */
794 * This is a quickie test to see how big the FIFO is.
795 * It doesn't work at all the time, more's the pity.
797 static int size_fifo(struct uart_8250_port *up)
799 unsigned char old_fcr, old_mcr, old_lcr;
800 unsigned short old_dl;
803 old_lcr = serial_in(up, UART_LCR);
804 serial_out(up, UART_LCR, 0);
805 old_fcr = serial_in(up, UART_FCR);
806 old_mcr = serial8250_in_MCR(up);
807 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
808 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
809 serial8250_out_MCR(up, UART_MCR_LOOP);
810 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
811 old_dl = serial_dl_read(up);
812 serial_dl_write(up, 0x0001);
813 serial_out(up, UART_LCR, 0x03);
814 for (count = 0; count < 256; count++)
815 serial_out(up, UART_TX, count);
816 mdelay(20);/* FIXME - schedule_timeout */
817 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
818 (count < 256); count++)
819 serial_in(up, UART_RX);
820 serial_out(up, UART_FCR, old_fcr);
821 serial8250_out_MCR(up, old_mcr);
822 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
823 serial_dl_write(up, old_dl);
824 serial_out(up, UART_LCR, old_lcr);
830 * Read UART ID using the divisor method - set DLL and DLM to zero
831 * and the revision will be in DLL and device type in DLM. We
832 * preserve the device state across this.
834 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
836 unsigned char old_lcr;
837 unsigned int id, old_dl;
839 old_lcr = serial_in(p, UART_LCR);
840 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
841 old_dl = serial_dl_read(p);
842 serial_dl_write(p, 0);
843 id = serial_dl_read(p);
844 serial_dl_write(p, old_dl);
846 serial_out(p, UART_LCR, old_lcr);
852 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
853 * When this function is called we know it is at least a StarTech
854 * 16650 V2, but it might be one of several StarTech UARTs, or one of
855 * its clones. (We treat the broken original StarTech 16650 V1 as a
856 * 16550, and why not? Startech doesn't seem to even acknowledge its
859 * What evil have men's minds wrought...
861 static void autoconfig_has_efr(struct uart_8250_port *up)
863 unsigned int id1, id2, id3, rev;
866 * Everything with an EFR has SLEEP
868 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
871 * First we check to see if it's an Oxford Semiconductor UART.
873 * If we have to do this here because some non-National
874 * Semiconductor clone chips lock up if you try writing to the
875 * LSR register (which serial_icr_read does)
879 * Check for Oxford Semiconductor 16C950.
881 * EFR [4] must be set else this test fails.
883 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
884 * claims that it's needed for 952 dual UART's (which are not
885 * recommended for new designs).
888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
889 serial_out(up, UART_EFR, UART_EFR_ECB);
890 serial_out(up, UART_LCR, 0x00);
891 id1 = serial_icr_read(up, UART_ID1);
892 id2 = serial_icr_read(up, UART_ID2);
893 id3 = serial_icr_read(up, UART_ID3);
894 rev = serial_icr_read(up, UART_REV);
896 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
898 if (id1 == 0x16 && id2 == 0xC9 &&
899 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
900 up->port.type = PORT_16C950;
903 * Enable work around for the Oxford Semiconductor 952 rev B
904 * chip which causes it to seriously miscalculate baud rates
907 if (id3 == 0x52 && rev == 0x01)
908 up->bugs |= UART_BUG_QUOT;
913 * We check for a XR16C850 by setting DLL and DLM to 0, and then
914 * reading back DLL and DLM. The chip type depends on the DLM
916 * 0x10 - XR16C850 and the DLL contains the chip revision.
920 id1 = autoconfig_read_divisor_id(up);
921 DEBUG_AUTOCONF("850id=%04x ", id1);
924 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
925 up->port.type = PORT_16850;
930 * It wasn't an XR16C850.
932 * We distinguish between the '654 and the '650 by counting
933 * how many bytes are in the FIFO. I'm using this for now,
934 * since that's the technique that was sent to me in the
935 * serial driver update, but I'm not convinced this works.
936 * I've had problems doing this in the past. -TYT
938 if (size_fifo(up) == 64)
939 up->port.type = PORT_16654;
941 up->port.type = PORT_16650V2;
945 * We detected a chip without a FIFO. Only two fall into
946 * this category - the original 8250 and the 16450. The
947 * 16450 has a scratch register (accessible with LCR=0)
949 static void autoconfig_8250(struct uart_8250_port *up)
951 unsigned char scratch, status1, status2;
953 up->port.type = PORT_8250;
955 scratch = serial_in(up, UART_SCR);
956 serial_out(up, UART_SCR, 0xa5);
957 status1 = serial_in(up, UART_SCR);
958 serial_out(up, UART_SCR, 0x5a);
959 status2 = serial_in(up, UART_SCR);
960 serial_out(up, UART_SCR, scratch);
962 if (status1 == 0xa5 && status2 == 0x5a)
963 up->port.type = PORT_16450;
966 static int broken_efr(struct uart_8250_port *up)
969 * Exar ST16C2550 "A2" devices incorrectly detect as
970 * having an EFR, and report an ID of 0x0201. See
971 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
973 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
980 * We know that the chip has FIFOs. Does it have an EFR? The
981 * EFR is located in the same register position as the IIR and
982 * we know the top two bits of the IIR are currently set. The
983 * EFR should contain zero. Try to read the EFR.
985 static void autoconfig_16550a(struct uart_8250_port *up)
987 unsigned char status1, status2;
988 unsigned int iersave;
990 up->port.type = PORT_16550A;
991 up->capabilities |= UART_CAP_FIFO;
994 * XR17V35x UARTs have an extra divisor register, DLD
995 * that gets enabled with when DLAB is set which will
996 * cause the device to incorrectly match and assign
997 * port type to PORT_16650. The EFR for this UART is
998 * found at offset 0x09. Instead check the Deice ID (DVID)
999 * register for a 2, 4 or 8 port UART.
1001 if (up->port.flags & UPF_EXAR_EFR) {
1002 status1 = serial_in(up, UART_EXAR_DVID);
1003 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1004 DEBUG_AUTOCONF("Exar XR17V35x ");
1005 up->port.type = PORT_XR17V35X;
1006 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1015 * Check for presence of the EFR when DLAB is set.
1016 * Only ST16C650V1 UARTs pass this test.
1018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1019 if (serial_in(up, UART_EFR) == 0) {
1020 serial_out(up, UART_EFR, 0xA8);
1021 if (serial_in(up, UART_EFR) != 0) {
1022 DEBUG_AUTOCONF("EFRv1 ");
1023 up->port.type = PORT_16650;
1024 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1026 serial_out(up, UART_LCR, 0);
1027 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1029 status1 = serial_in(up, UART_IIR) >> 5;
1030 serial_out(up, UART_FCR, 0);
1031 serial_out(up, UART_LCR, 0);
1034 up->port.type = PORT_16550A_FSL64;
1036 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1038 serial_out(up, UART_EFR, 0);
1043 * Maybe it requires 0xbf to be written to the LCR.
1044 * (other ST16C650V2 UARTs, TI16C752A, etc)
1046 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1047 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1048 DEBUG_AUTOCONF("EFRv2 ");
1049 autoconfig_has_efr(up);
1054 * Check for a National Semiconductor SuperIO chip.
1055 * Attempt to switch to bank 2, read the value of the LOOP bit
1056 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1057 * switch back to bank 2, read it from EXCR1 again and check
1058 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1060 serial_out(up, UART_LCR, 0);
1061 status1 = serial8250_in_MCR(up);
1062 serial_out(up, UART_LCR, 0xE0);
1063 status2 = serial_in(up, 0x02); /* EXCR1 */
1065 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1066 serial_out(up, UART_LCR, 0);
1067 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1068 serial_out(up, UART_LCR, 0xE0);
1069 status2 = serial_in(up, 0x02); /* EXCR1 */
1070 serial_out(up, UART_LCR, 0);
1071 serial8250_out_MCR(up, status1);
1073 if ((status2 ^ status1) & UART_MCR_LOOP) {
1074 unsigned short quot;
1076 serial_out(up, UART_LCR, 0xE0);
1078 quot = serial_dl_read(up);
1081 if (ns16550a_goto_highspeed(up))
1082 serial_dl_write(up, quot);
1084 serial_out(up, UART_LCR, 0);
1086 up->port.uartclk = 921600*16;
1087 up->port.type = PORT_NS16550A;
1088 up->capabilities |= UART_NATSEMI;
1094 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1095 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1096 * Try setting it with and without DLAB set. Cheap clones
1097 * set bit 5 without DLAB set.
1099 serial_out(up, UART_LCR, 0);
1100 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1101 status1 = serial_in(up, UART_IIR) >> 5;
1102 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1103 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1104 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1105 status2 = serial_in(up, UART_IIR) >> 5;
1106 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1107 serial_out(up, UART_LCR, 0);
1109 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1111 if (status1 == 6 && status2 == 7) {
1112 up->port.type = PORT_16750;
1113 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1118 * Try writing and reading the UART_IER_UUE bit (b6).
1119 * If it works, this is probably one of the Xscale platform's
1121 * We're going to explicitly set the UUE bit to 0 before
1122 * trying to write and read a 1 just to make sure it's not
1123 * already a 1 and maybe locked there before we even start start.
1125 iersave = serial_in(up, UART_IER);
1126 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1127 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1129 * OK it's in a known zero state, try writing and reading
1130 * without disturbing the current state of the other bits.
1132 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1133 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1136 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1138 DEBUG_AUTOCONF("Xscale ");
1139 up->port.type = PORT_XSCALE;
1140 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1145 * If we got here we couldn't force the IER_UUE bit to 0.
1146 * Log it and continue.
1148 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1150 serial_out(up, UART_IER, iersave);
1153 * Exar uarts have EFR in a weird location
1155 if (up->port.flags & UPF_EXAR_EFR) {
1156 DEBUG_AUTOCONF("Exar XR17D15x ");
1157 up->port.type = PORT_XR17D15X;
1158 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1165 * We distinguish between 16550A and U6 16550A by counting
1166 * how many bytes are in the FIFO.
1168 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1169 up->port.type = PORT_U6_16550A;
1170 up->capabilities |= UART_CAP_AFE;
1175 * This routine is called by rs_init() to initialize a specific serial
1176 * port. It determines what type of UART chip this serial port is
1177 * using: 8250, 16450, 16550, 16550A. The important question is
1178 * whether or not this UART is a 16550A or not, since this will
1179 * determine whether or not we can use its FIFO features or not.
1181 static void autoconfig(struct uart_8250_port *up)
1183 unsigned char status1, scratch, scratch2, scratch3;
1184 unsigned char save_lcr, save_mcr;
1185 struct uart_port *port = &up->port;
1186 unsigned long flags;
1187 unsigned int old_capabilities;
1189 if (!port->iobase && !port->mapbase && !port->membase)
1192 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1193 serial_index(port), port->iobase, port->membase);
1196 * We really do need global IRQs disabled here - we're going to
1197 * be frobbing the chips IRQ enable register to see if it exists.
1199 spin_lock_irqsave(&port->lock, flags);
1201 up->capabilities = 0;
1204 if (!(port->flags & UPF_BUGGY_UART)) {
1206 * Do a simple existence test first; if we fail this,
1207 * there's no point trying anything else.
1209 * 0x80 is used as a nonsense port to prevent against
1210 * false positives due to ISA bus float. The
1211 * assumption is that 0x80 is a non-existent port;
1212 * which should be safe since include/asm/io.h also
1213 * makes this assumption.
1215 * Note: this is safe as long as MCR bit 4 is clear
1216 * and the device is in "PC" mode.
1218 scratch = serial_in(up, UART_IER);
1219 serial_out(up, UART_IER, 0);
1224 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1225 * 16C754B) allow only to modify them if an EFR bit is set.
1227 scratch2 = serial_in(up, UART_IER) & 0x0f;
1228 serial_out(up, UART_IER, 0x0F);
1232 scratch3 = serial_in(up, UART_IER) & 0x0f;
1233 serial_out(up, UART_IER, scratch);
1234 if (scratch2 != 0 || scratch3 != 0x0F) {
1236 * We failed; there's nothing here
1238 spin_unlock_irqrestore(&port->lock, flags);
1239 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1240 scratch2, scratch3);
1245 save_mcr = serial8250_in_MCR(up);
1246 save_lcr = serial_in(up, UART_LCR);
1249 * Check to see if a UART is really there. Certain broken
1250 * internal modems based on the Rockwell chipset fail this
1251 * test, because they apparently don't implement the loopback
1252 * test mode. So this test is skipped on the COM 1 through
1253 * COM 4 ports. This *should* be safe, since no board
1254 * manufacturer would be stupid enough to design a board
1255 * that conflicts with COM 1-4 --- we hope!
1257 if (!(port->flags & UPF_SKIP_TEST)) {
1258 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1259 status1 = serial_in(up, UART_MSR) & 0xF0;
1260 serial8250_out_MCR(up, save_mcr);
1261 if (status1 != 0x90) {
1262 spin_unlock_irqrestore(&port->lock, flags);
1263 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1270 * We're pretty sure there's a port here. Lets find out what
1271 * type of port it is. The IIR top two bits allows us to find
1272 * out if it's 8250 or 16450, 16550, 16550A or later. This
1273 * determines what we test for next.
1275 * We also initialise the EFR (if any) to zero for later. The
1276 * EFR occupies the same register location as the FCR and IIR.
1278 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1279 serial_out(up, UART_EFR, 0);
1280 serial_out(up, UART_LCR, 0);
1282 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1283 scratch = serial_in(up, UART_IIR) >> 6;
1287 autoconfig_8250(up);
1290 port->type = PORT_UNKNOWN;
1293 port->type = PORT_16550;
1296 autoconfig_16550a(up);
1300 #ifdef CONFIG_SERIAL_8250_RSA
1302 * Only probe for RSA ports if we got the region.
1304 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1306 port->type = PORT_RSA;
1309 serial_out(up, UART_LCR, save_lcr);
1311 port->fifosize = uart_config[up->port.type].fifo_size;
1312 old_capabilities = up->capabilities;
1313 up->capabilities = uart_config[port->type].flags;
1314 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1316 if (port->type == PORT_UNKNOWN)
1322 #ifdef CONFIG_SERIAL_8250_RSA
1323 if (port->type == PORT_RSA)
1324 serial_out(up, UART_RSA_FRR, 0);
1326 serial8250_out_MCR(up, save_mcr);
1327 serial8250_clear_fifos(up);
1328 serial_in(up, UART_RX);
1329 if (up->capabilities & UART_CAP_UUE)
1330 serial_out(up, UART_IER, UART_IER_UUE);
1332 serial_out(up, UART_IER, 0);
1335 spin_unlock_irqrestore(&port->lock, flags);
1338 * Check if the device is a Fintek F81216A
1340 if (port->type == PORT_16550A)
1341 fintek_8250_probe(up);
1343 if (up->capabilities != old_capabilities) {
1344 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1345 serial_index(port), old_capabilities,
1349 DEBUG_AUTOCONF("iir=%d ", scratch);
1350 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1353 static void autoconfig_irq(struct uart_8250_port *up)
1355 struct uart_port *port = &up->port;
1356 unsigned char save_mcr, save_ier;
1357 unsigned char save_ICP = 0;
1358 unsigned int ICP = 0;
1362 if (port->flags & UPF_FOURPORT) {
1363 ICP = (port->iobase & 0xfe0) | 0x1f;
1364 save_ICP = inb_p(ICP);
1369 if (uart_console(port))
1372 /* forget possible initially masked and pending IRQ */
1373 probe_irq_off(probe_irq_on());
1374 save_mcr = serial8250_in_MCR(up);
1375 save_ier = serial_in(up, UART_IER);
1376 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1378 irqs = probe_irq_on();
1379 serial8250_out_MCR(up, 0);
1381 if (port->flags & UPF_FOURPORT) {
1382 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1384 serial8250_out_MCR(up,
1385 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1387 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1388 serial_in(up, UART_LSR);
1389 serial_in(up, UART_RX);
1390 serial_in(up, UART_IIR);
1391 serial_in(up, UART_MSR);
1392 serial_out(up, UART_TX, 0xFF);
1394 irq = probe_irq_off(irqs);
1396 serial8250_out_MCR(up, save_mcr);
1397 serial_out(up, UART_IER, save_ier);
1399 if (port->flags & UPF_FOURPORT)
1400 outb_p(save_ICP, ICP);
1402 if (uart_console(port))
1405 port->irq = (irq > 0) ? irq : 0;
1408 static void serial8250_stop_rx(struct uart_port *port)
1410 struct uart_8250_port *up = up_to_u8250p(port);
1412 serial8250_rpm_get(up);
1414 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1415 up->port.read_status_mask &= ~UART_LSR_DR;
1416 serial_port_out(port, UART_IER, up->ier);
1418 serial8250_rpm_put(up);
1421 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1423 serial8250_em485_rts_after_send(p);
1426 * Empty the RX FIFO, we are not interested in anything
1427 * received during the half-duplex transmission.
1428 * Enable previously disabled RX interrupts.
1430 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1431 serial8250_clear_and_reinit_fifos(p);
1433 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1434 serial_port_out(&p->port, UART_IER, p->ier);
1438 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1440 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1441 struct uart_8250_em485 *em485 = p->em485;
1442 unsigned long flags;
1444 serial8250_rpm_get(p);
1445 spin_lock_irqsave(&p->port.lock, flags);
1447 em485->active_timer == &em485->stop_tx_timer) {
1448 __do_stop_tx_rs485(p);
1449 em485->active_timer = NULL;
1451 spin_unlock_irqrestore(&p->port.lock, flags);
1452 serial8250_rpm_put(p);
1455 static void __stop_tx_rs485(struct uart_8250_port *p)
1457 struct uart_8250_em485 *em485 = p->em485;
1460 * __do_stop_tx_rs485 is going to set RTS according to config
1461 * AND flush RX FIFO if required.
1463 if (p->port.rs485.delay_rts_after_send > 0) {
1464 em485->active_timer = &em485->stop_tx_timer;
1465 mod_timer(&em485->stop_tx_timer, jiffies +
1466 p->port.rs485.delay_rts_after_send * HZ / 1000);
1468 __do_stop_tx_rs485(p);
1472 static inline void __do_stop_tx(struct uart_8250_port *p)
1474 if (p->ier & UART_IER_THRI) {
1475 p->ier &= ~UART_IER_THRI;
1476 serial_out(p, UART_IER, p->ier);
1477 serial8250_rpm_put_tx(p);
1481 static inline void __stop_tx(struct uart_8250_port *p)
1483 struct uart_8250_em485 *em485 = p->em485;
1486 unsigned char lsr = serial_in(p, UART_LSR);
1488 * To provide required timeing and allow FIFO transfer,
1489 * __stop_tx_rs485() must be called only when both FIFO and
1490 * shift register are empty. It is for device driver to enable
1491 * interrupt on TEMT.
1493 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1496 del_timer(&em485->start_tx_timer);
1497 em485->active_timer = NULL;
1504 static void serial8250_stop_tx(struct uart_port *port)
1506 struct uart_8250_port *up = up_to_u8250p(port);
1508 serial8250_rpm_get(up);
1512 * We really want to stop the transmitter from sending.
1514 if (port->type == PORT_16C950) {
1515 up->acr |= UART_ACR_TXDIS;
1516 serial_icr_write(up, UART_ACR, up->acr);
1518 serial8250_rpm_put(up);
1521 static inline void __start_tx(struct uart_port *port)
1523 struct uart_8250_port *up = up_to_u8250p(port);
1525 if (up->dma && !up->dma->tx_dma(up))
1528 if (!(up->ier & UART_IER_THRI)) {
1529 up->ier |= UART_IER_THRI;
1530 serial_port_out(port, UART_IER, up->ier);
1532 if (up->bugs & UART_BUG_TXEN) {
1535 lsr = serial_in(up, UART_LSR);
1536 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1537 if (lsr & UART_LSR_THRE)
1538 serial8250_tx_chars(up);
1543 * Re-enable the transmitter if we disabled it.
1545 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1546 up->acr &= ~UART_ACR_TXDIS;
1547 serial_icr_write(up, UART_ACR, up->acr);
1551 static inline void start_tx_rs485(struct uart_port *port)
1553 struct uart_8250_port *up = up_to_u8250p(port);
1554 struct uart_8250_em485 *em485 = up->em485;
1557 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1558 serial8250_stop_rx(&up->port);
1560 del_timer(&em485->stop_tx_timer);
1561 em485->active_timer = NULL;
1563 mcr = serial8250_in_MCR(up);
1564 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1565 !!(mcr & UART_MCR_RTS)) {
1566 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1567 mcr |= UART_MCR_RTS;
1569 mcr &= ~UART_MCR_RTS;
1570 serial8250_out_MCR(up, mcr);
1572 if (up->port.rs485.delay_rts_before_send > 0) {
1573 em485->active_timer = &em485->start_tx_timer;
1574 mod_timer(&em485->start_tx_timer, jiffies +
1575 up->port.rs485.delay_rts_before_send * HZ / 1000);
1583 static void serial8250_em485_handle_start_tx(unsigned long arg)
1585 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1586 struct uart_8250_em485 *em485 = p->em485;
1587 unsigned long flags;
1589 spin_lock_irqsave(&p->port.lock, flags);
1591 em485->active_timer == &em485->start_tx_timer) {
1592 __start_tx(&p->port);
1593 em485->active_timer = NULL;
1595 spin_unlock_irqrestore(&p->port.lock, flags);
1598 static void serial8250_start_tx(struct uart_port *port)
1600 struct uart_8250_port *up = up_to_u8250p(port);
1601 struct uart_8250_em485 *em485 = up->em485;
1603 serial8250_rpm_get_tx(up);
1606 em485->active_timer == &em485->start_tx_timer)
1610 start_tx_rs485(port);
1615 static void serial8250_throttle(struct uart_port *port)
1617 port->throttle(port);
1620 static void serial8250_unthrottle(struct uart_port *port)
1622 port->unthrottle(port);
1625 static void serial8250_disable_ms(struct uart_port *port)
1627 struct uart_8250_port *up = up_to_u8250p(port);
1629 /* no MSR capabilities */
1630 if (up->bugs & UART_BUG_NOMSR)
1633 up->ier &= ~UART_IER_MSI;
1634 serial_port_out(port, UART_IER, up->ier);
1637 static void serial8250_enable_ms(struct uart_port *port)
1639 struct uart_8250_port *up = up_to_u8250p(port);
1641 /* no MSR capabilities */
1642 if (up->bugs & UART_BUG_NOMSR)
1645 up->ier |= UART_IER_MSI;
1647 serial8250_rpm_get(up);
1648 serial_port_out(port, UART_IER, up->ier);
1649 serial8250_rpm_put(up);
1652 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1654 struct uart_port *port = &up->port;
1656 char flag = TTY_NORMAL;
1658 if (likely(lsr & UART_LSR_DR))
1659 ch = serial_in(up, UART_RX);
1662 * Intel 82571 has a Serial Over Lan device that will
1663 * set UART_LSR_BI without setting UART_LSR_DR when
1664 * it receives a break. To avoid reading from the
1665 * receive buffer without UART_LSR_DR bit set, we
1666 * just force the read character to be 0
1672 lsr |= up->lsr_saved_flags;
1673 up->lsr_saved_flags = 0;
1675 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1676 if (lsr & UART_LSR_BI) {
1677 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1680 * We do the SysRQ and SAK checking
1681 * here because otherwise the break
1682 * may get masked by ignore_status_mask
1683 * or read_status_mask.
1685 if (uart_handle_break(port))
1687 } else if (lsr & UART_LSR_PE)
1688 port->icount.parity++;
1689 else if (lsr & UART_LSR_FE)
1690 port->icount.frame++;
1691 if (lsr & UART_LSR_OE)
1692 port->icount.overrun++;
1695 * Mask off conditions which should be ignored.
1697 lsr &= port->read_status_mask;
1699 if (lsr & UART_LSR_BI) {
1700 pr_debug("%s: handling break\n", __func__);
1702 } else if (lsr & UART_LSR_PE)
1704 else if (lsr & UART_LSR_FE)
1707 if (uart_handle_sysrq_char(port, ch))
1710 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1714 * serial8250_rx_chars: processes according to the passed in LSR
1715 * value, and returns the remaining LSR bits not handled
1716 * by this Rx routine.
1718 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1720 struct uart_port *port = &up->port;
1721 int max_count = 256;
1724 serial8250_read_char(up, lsr);
1725 if (--max_count == 0)
1727 lsr = serial_in(up, UART_LSR);
1728 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1730 tty_flip_buffer_push(&port->state->port);
1733 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1735 void serial8250_tx_chars(struct uart_8250_port *up)
1737 struct uart_port *port = &up->port;
1738 struct circ_buf *xmit = &port->state->xmit;
1742 serial_out(up, UART_TX, port->x_char);
1747 if (uart_tx_stopped(port)) {
1748 serial8250_stop_tx(port);
1751 if (uart_circ_empty(xmit)) {
1756 count = up->tx_loadsz;
1758 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1759 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1761 if (uart_circ_empty(xmit))
1763 if ((up->capabilities & UART_CAP_HFIFO) &&
1764 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1766 } while (--count > 0);
1768 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1769 uart_write_wakeup(port);
1772 * With RPM enabled, we have to wait until the FIFO is empty before the
1773 * HW can go idle. So we get here once again with empty FIFO and disable
1774 * the interrupt and RPM in __stop_tx()
1776 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1779 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1781 /* Caller holds uart port lock */
1782 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1784 struct uart_port *port = &up->port;
1785 unsigned int status = serial_in(up, UART_MSR);
1787 status |= up->msr_saved_flags;
1788 up->msr_saved_flags = 0;
1789 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1790 port->state != NULL) {
1791 if (status & UART_MSR_TERI)
1793 if (status & UART_MSR_DDSR)
1795 if (status & UART_MSR_DDCD)
1796 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1797 if (status & UART_MSR_DCTS)
1798 uart_handle_cts_change(port, status & UART_MSR_CTS);
1800 wake_up_interruptible(&port->state->port.delta_msr_wait);
1805 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1807 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1809 switch (iir & 0x3f) {
1810 case UART_IIR_RX_TIMEOUT:
1811 serial8250_rx_dma_flush(up);
1816 return up->dma->rx_dma(up);
1820 * This handles the interrupt from one port.
1822 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1824 unsigned char status;
1825 unsigned long flags;
1826 struct uart_8250_port *up = up_to_u8250p(port);
1828 if (iir & UART_IIR_NO_INT)
1831 spin_lock_irqsave(&port->lock, flags);
1833 status = serial_port_in(port, UART_LSR);
1835 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1836 if (!up->dma || handle_rx_dma(up, iir))
1837 status = serial8250_rx_chars(up, status);
1839 serial8250_modem_status(up);
1840 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1841 serial8250_tx_chars(up);
1843 spin_unlock_irqrestore(&port->lock, flags);
1846 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1848 static int serial8250_default_handle_irq(struct uart_port *port)
1850 struct uart_8250_port *up = up_to_u8250p(port);
1854 serial8250_rpm_get(up);
1856 iir = serial_port_in(port, UART_IIR);
1857 ret = serial8250_handle_irq(port, iir);
1859 serial8250_rpm_put(up);
1864 * These Exar UARTs have an extra interrupt indicator that could
1865 * fire for a few unimplemented interrupts. One of which is a
1866 * wakeup event when coming out of sleep. Put this here just
1867 * to be on the safe side that these interrupts don't go unhandled.
1869 static int exar_handle_irq(struct uart_port *port)
1871 unsigned int iir = serial_port_in(port, UART_IIR);
1874 ret = serial8250_handle_irq(port, iir);
1876 if ((port->type == PORT_XR17V35X) ||
1877 (port->type == PORT_XR17D15X)) {
1878 serial_port_in(port, 0x80);
1879 serial_port_in(port, 0x81);
1880 serial_port_in(port, 0x82);
1881 serial_port_in(port, 0x83);
1888 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1889 * have a programmable TX threshold that triggers the THRE interrupt in
1890 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1891 * has space available. Load it up with tx_loadsz bytes.
1893 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1895 unsigned long flags;
1896 unsigned int iir = serial_port_in(port, UART_IIR);
1898 /* TX Threshold IRQ triggered so load up FIFO */
1899 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1900 struct uart_8250_port *up = up_to_u8250p(port);
1902 spin_lock_irqsave(&port->lock, flags);
1903 serial8250_tx_chars(up);
1904 spin_unlock_irqrestore(&port->lock, flags);
1907 iir = serial_port_in(port, UART_IIR);
1908 return serial8250_handle_irq(port, iir);
1911 static unsigned int serial8250_tx_empty(struct uart_port *port)
1913 struct uart_8250_port *up = up_to_u8250p(port);
1914 unsigned long flags;
1917 serial8250_rpm_get(up);
1919 spin_lock_irqsave(&port->lock, flags);
1920 lsr = serial_port_in(port, UART_LSR);
1921 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1922 spin_unlock_irqrestore(&port->lock, flags);
1924 serial8250_rpm_put(up);
1926 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1929 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1931 struct uart_8250_port *up = up_to_u8250p(port);
1932 unsigned int status;
1935 serial8250_rpm_get(up);
1936 status = serial8250_modem_status(up);
1937 serial8250_rpm_put(up);
1940 if (status & UART_MSR_DCD)
1942 if (status & UART_MSR_RI)
1944 if (status & UART_MSR_DSR)
1946 if (status & UART_MSR_CTS)
1950 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1952 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1954 if (port->get_mctrl)
1955 return port->get_mctrl(port);
1956 return serial8250_do_get_mctrl(port);
1959 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1961 struct uart_8250_port *up = up_to_u8250p(port);
1962 unsigned char mcr = 0;
1964 if (mctrl & TIOCM_RTS)
1965 mcr |= UART_MCR_RTS;
1966 if (mctrl & TIOCM_DTR)
1967 mcr |= UART_MCR_DTR;
1968 if (mctrl & TIOCM_OUT1)
1969 mcr |= UART_MCR_OUT1;
1970 if (mctrl & TIOCM_OUT2)
1971 mcr |= UART_MCR_OUT2;
1972 if (mctrl & TIOCM_LOOP)
1973 mcr |= UART_MCR_LOOP;
1975 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1977 serial8250_out_MCR(up, mcr);
1979 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1981 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1983 if (port->set_mctrl)
1984 port->set_mctrl(port, mctrl);
1986 serial8250_do_set_mctrl(port, mctrl);
1989 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1991 struct uart_8250_port *up = up_to_u8250p(port);
1992 unsigned long flags;
1994 serial8250_rpm_get(up);
1995 spin_lock_irqsave(&port->lock, flags);
1996 if (break_state == -1)
1997 up->lcr |= UART_LCR_SBC;
1999 up->lcr &= ~UART_LCR_SBC;
2000 serial_port_out(port, UART_LCR, up->lcr);
2001 spin_unlock_irqrestore(&port->lock, flags);
2002 serial8250_rpm_put(up);
2006 * Wait for transmitter & holding register to empty
2008 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2010 unsigned int status, tmout = 10000;
2012 /* Wait up to 10ms for the character(s) to be sent. */
2014 status = serial_in(up, UART_LSR);
2016 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2018 if ((status & bits) == bits)
2023 touch_nmi_watchdog();
2026 /* Wait up to 1s for flow control if necessary */
2027 if (up->port.flags & UPF_CONS_FLOW) {
2028 for (tmout = 1000000; tmout; tmout--) {
2029 unsigned int msr = serial_in(up, UART_MSR);
2030 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2031 if (msr & UART_MSR_CTS)
2034 touch_nmi_watchdog();
2039 #ifdef CONFIG_CONSOLE_POLL
2041 * Console polling routines for writing and reading from the uart while
2042 * in an interrupt or debug context.
2045 static int serial8250_get_poll_char(struct uart_port *port)
2047 struct uart_8250_port *up = up_to_u8250p(port);
2051 serial8250_rpm_get(up);
2053 lsr = serial_port_in(port, UART_LSR);
2055 if (!(lsr & UART_LSR_DR)) {
2056 status = NO_POLL_CHAR;
2060 status = serial_port_in(port, UART_RX);
2062 serial8250_rpm_put(up);
2067 static void serial8250_put_poll_char(struct uart_port *port,
2071 struct uart_8250_port *up = up_to_u8250p(port);
2073 serial8250_rpm_get(up);
2075 * First save the IER then disable the interrupts
2077 ier = serial_port_in(port, UART_IER);
2078 if (up->capabilities & UART_CAP_UUE)
2079 serial_port_out(port, UART_IER, UART_IER_UUE);
2081 serial_port_out(port, UART_IER, 0);
2083 wait_for_xmitr(up, BOTH_EMPTY);
2085 * Send the character out.
2087 serial_port_out(port, UART_TX, c);
2090 * Finally, wait for transmitter to become empty
2091 * and restore the IER
2093 wait_for_xmitr(up, BOTH_EMPTY);
2094 serial_port_out(port, UART_IER, ier);
2095 serial8250_rpm_put(up);
2098 #endif /* CONFIG_CONSOLE_POLL */
2100 int serial8250_do_startup(struct uart_port *port)
2102 struct uart_8250_port *up = up_to_u8250p(port);
2103 unsigned long flags;
2104 unsigned char lsr, iir;
2107 if (!port->fifosize)
2108 port->fifosize = uart_config[port->type].fifo_size;
2110 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2111 if (!up->capabilities)
2112 up->capabilities = uart_config[port->type].flags;
2115 if (port->iotype != up->cur_iotype)
2116 set_io_from_upio(port);
2118 serial8250_rpm_get(up);
2119 if (port->type == PORT_16C950) {
2120 /* Wake up and initialize UART */
2122 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2123 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2124 serial_port_out(port, UART_IER, 0);
2125 serial_port_out(port, UART_LCR, 0);
2126 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2127 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2128 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2129 serial_port_out(port, UART_LCR, 0);
2132 if (port->type == PORT_DA830) {
2133 /* Reset the port */
2134 serial_port_out(port, UART_IER, 0);
2135 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2138 /* Enable Tx, Rx and free run mode */
2139 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2140 UART_DA830_PWREMU_MGMT_UTRST |
2141 UART_DA830_PWREMU_MGMT_URRST |
2142 UART_DA830_PWREMU_MGMT_FREE);
2145 #ifdef CONFIG_SERIAL_8250_RSA
2147 * If this is an RSA port, see if we can kick it up to the
2148 * higher speed clock.
2153 if (port->type == PORT_XR17V35X) {
2155 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2156 * MCR [7:5] and MSR [7:0]
2158 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2161 * Make sure all interrups are masked until initialization is
2162 * complete and the FIFOs are cleared
2164 serial_port_out(port, UART_IER, 0);
2168 * Clear the FIFO buffers and disable them.
2169 * (they will be reenabled in set_termios())
2171 serial8250_clear_fifos(up);
2174 * Clear the interrupt registers.
2176 serial_port_in(port, UART_LSR);
2177 serial_port_in(port, UART_RX);
2178 serial_port_in(port, UART_IIR);
2179 serial_port_in(port, UART_MSR);
2182 * At this point, there's no way the LSR could still be 0xff;
2183 * if it is, then bail out, because there's likely no UART
2186 if (!(port->flags & UPF_BUGGY_UART) &&
2187 (serial_port_in(port, UART_LSR) == 0xff)) {
2188 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2189 serial_index(port));
2195 * For a XR16C850, we need to set the trigger levels
2197 if (port->type == PORT_16850) {
2200 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2202 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2203 serial_port_out(port, UART_FCTR,
2204 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2205 serial_port_out(port, UART_TRG, UART_TRG_96);
2206 serial_port_out(port, UART_FCTR,
2207 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2208 serial_port_out(port, UART_TRG, UART_TRG_96);
2210 serial_port_out(port, UART_LCR, 0);
2214 * For the Altera 16550 variants, set TX threshold trigger level.
2216 if (((port->type == PORT_ALTR_16550_F32) ||
2217 (port->type == PORT_ALTR_16550_F64) ||
2218 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2219 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2220 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2221 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2222 serial_index(port));
2224 serial_port_out(port, UART_ALTR_AFR,
2225 UART_ALTR_EN_TXFIFO_LW);
2226 serial_port_out(port, UART_ALTR_TX_LOW,
2227 port->fifosize - up->tx_loadsz);
2228 port->handle_irq = serial8250_tx_threshold_handle_irq;
2235 * Test for UARTs that do not reassert THRE when the
2236 * transmitter is idle and the interrupt has already
2237 * been cleared. Real 16550s should always reassert
2238 * this interrupt whenever the transmitter is idle and
2239 * the interrupt is enabled. Delays are necessary to
2240 * allow register changes to become visible.
2242 spin_lock_irqsave(&port->lock, flags);
2243 if (up->port.irqflags & IRQF_SHARED)
2244 disable_irq_nosync(port->irq);
2246 wait_for_xmitr(up, UART_LSR_THRE);
2247 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2248 udelay(1); /* allow THRE to set */
2249 iir1 = serial_port_in(port, UART_IIR);
2250 serial_port_out(port, UART_IER, 0);
2251 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2252 udelay(1); /* allow a working UART time to re-assert THRE */
2253 iir = serial_port_in(port, UART_IIR);
2254 serial_port_out(port, UART_IER, 0);
2256 if (port->irqflags & IRQF_SHARED)
2257 enable_irq(port->irq);
2258 spin_unlock_irqrestore(&port->lock, flags);
2261 * If the interrupt is not reasserted, or we otherwise
2262 * don't trust the iir, setup a timer to kick the UART
2263 * on a regular basis.
2265 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2266 up->port.flags & UPF_BUG_THRE) {
2267 up->bugs |= UART_BUG_THRE;
2271 retval = up->ops->setup_irq(up);
2276 * Now, initialize the UART
2278 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2280 spin_lock_irqsave(&port->lock, flags);
2281 if (up->port.flags & UPF_FOURPORT) {
2283 up->port.mctrl |= TIOCM_OUT1;
2286 * Most PC uarts need OUT2 raised to enable interrupts.
2289 up->port.mctrl |= TIOCM_OUT2;
2291 serial8250_set_mctrl(port, port->mctrl);
2294 * Serial over Lan (SoL) hack:
2295 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2296 * used for Serial Over Lan. Those chips take a longer time than a
2297 * normal serial device to signalize that a transmission data was
2298 * queued. Due to that, the above test generally fails. One solution
2299 * would be to delay the reading of iir. However, this is not
2300 * reliable, since the timeout is variable. So, let's just don't
2301 * test if we receive TX irq. This way, we'll never enable
2304 if (up->port.flags & UPF_NO_TXEN_TEST)
2305 goto dont_test_tx_en;
2308 * Do a quick test to see if we receive an interrupt when we enable
2311 serial_port_out(port, UART_IER, UART_IER_THRI);
2312 lsr = serial_port_in(port, UART_LSR);
2313 iir = serial_port_in(port, UART_IIR);
2314 serial_port_out(port, UART_IER, 0);
2316 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2317 if (!(up->bugs & UART_BUG_TXEN)) {
2318 up->bugs |= UART_BUG_TXEN;
2319 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2320 serial_index(port));
2323 up->bugs &= ~UART_BUG_TXEN;
2327 spin_unlock_irqrestore(&port->lock, flags);
2330 * Clear the interrupt registers again for luck, and clear the
2331 * saved flags to avoid getting false values from polling
2332 * routines or the previous session.
2334 serial_port_in(port, UART_LSR);
2335 serial_port_in(port, UART_RX);
2336 serial_port_in(port, UART_IIR);
2337 serial_port_in(port, UART_MSR);
2338 up->lsr_saved_flags = 0;
2339 up->msr_saved_flags = 0;
2342 * Request DMA channels for both RX and TX.
2345 retval = serial8250_request_dma(up);
2347 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2348 serial_index(port));
2354 * Set the IER shadow for rx interrupts but defer actual interrupt
2355 * enable until after the FIFOs are enabled; otherwise, an already-
2356 * active sender can swamp the interrupt handler with "too much work".
2358 up->ier = UART_IER_RLSI | UART_IER_RDI;
2360 if (port->flags & UPF_FOURPORT) {
2363 * Enable interrupts on the AST Fourport board
2365 icp = (port->iobase & 0xfe0) | 0x01f;
2371 serial8250_rpm_put(up);
2374 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2376 static int serial8250_startup(struct uart_port *port)
2379 return port->startup(port);
2380 return serial8250_do_startup(port);
2383 void serial8250_do_shutdown(struct uart_port *port)
2385 struct uart_8250_port *up = up_to_u8250p(port);
2386 unsigned long flags;
2388 serial8250_rpm_get(up);
2390 * Disable interrupts from this port
2392 spin_lock_irqsave(&port->lock, flags);
2394 serial_port_out(port, UART_IER, 0);
2395 spin_unlock_irqrestore(&port->lock, flags);
2397 synchronize_irq(port->irq);
2400 serial8250_release_dma(up);
2402 spin_lock_irqsave(&port->lock, flags);
2403 if (port->flags & UPF_FOURPORT) {
2404 /* reset interrupts on the AST Fourport board */
2405 inb((port->iobase & 0xfe0) | 0x1f);
2406 port->mctrl |= TIOCM_OUT1;
2408 port->mctrl &= ~TIOCM_OUT2;
2410 serial8250_set_mctrl(port, port->mctrl);
2411 spin_unlock_irqrestore(&port->lock, flags);
2414 * Disable break condition and FIFOs
2416 serial_port_out(port, UART_LCR,
2417 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2418 serial8250_clear_fifos(up);
2420 #ifdef CONFIG_SERIAL_8250_RSA
2422 * Reset the RSA board back to 115kbps compat mode.
2428 * Read data port to reset things, and then unlink from
2431 serial_port_in(port, UART_RX);
2432 serial8250_rpm_put(up);
2434 up->ops->release_irq(up);
2436 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2438 static void serial8250_shutdown(struct uart_port *port)
2441 port->shutdown(port);
2443 serial8250_do_shutdown(port);
2447 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2448 * Calculate divisor with extra 4-bit fractional portion
2450 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2454 struct uart_port *port = &up->port;
2455 unsigned int quot_16;
2457 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2458 *frac = quot_16 & 0x0f;
2460 return quot_16 >> 4;
2463 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2467 struct uart_port *port = &up->port;
2471 * Handle magic divisors for baud rates above baud_base on
2472 * SMSC SuperIO chips.
2475 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2476 baud == (port->uartclk/4))
2478 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2479 baud == (port->uartclk/8))
2481 else if (up->port.type == PORT_XR17V35X)
2482 quot = xr17v35x_get_divisor(up, baud, frac);
2484 quot = uart_get_divisor(port, baud);
2487 * Oxford Semi 952 rev B workaround
2489 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2495 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2500 switch (c_cflag & CSIZE) {
2502 cval = UART_LCR_WLEN5;
2505 cval = UART_LCR_WLEN6;
2508 cval = UART_LCR_WLEN7;
2512 cval = UART_LCR_WLEN8;
2516 if (c_cflag & CSTOPB)
2517 cval |= UART_LCR_STOP;
2518 if (c_cflag & PARENB) {
2519 cval |= UART_LCR_PARITY;
2520 if (up->bugs & UART_BUG_PARITY)
2521 up->fifo_bug = true;
2523 if (!(c_cflag & PARODD))
2524 cval |= UART_LCR_EPAR;
2526 if (c_cflag & CMSPAR)
2527 cval |= UART_LCR_SPAR;
2533 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2534 unsigned int quot, unsigned int quot_frac)
2536 struct uart_8250_port *up = up_to_u8250p(port);
2538 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2539 if (is_omap1510_8250(up)) {
2540 if (baud == 115200) {
2542 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2544 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2548 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2549 * otherwise just set DLAB
2551 if (up->capabilities & UART_NATSEMI)
2552 serial_port_out(port, UART_LCR, 0xe0);
2554 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2556 serial_dl_write(up, quot);
2558 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2559 if (up->port.type == PORT_XR17V35X)
2560 serial_port_out(port, 0x2, quot_frac);
2563 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2564 struct ktermios *termios,
2565 struct ktermios *old)
2568 * Ask the core to calculate the divisor for us.
2569 * Allow 1% tolerance at the upper limit so uart clks marginally
2570 * slower than nominal still match standard baud rates without
2571 * causing transmission errors.
2573 return uart_get_baud_rate(port, termios, old,
2574 port->uartclk / 16 / 0xffff,
2579 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2580 struct ktermios *old)
2582 struct uart_8250_port *up = up_to_u8250p(port);
2584 unsigned long flags;
2585 unsigned int baud, quot, frac = 0;
2587 cval = serial8250_compute_lcr(up, termios->c_cflag);
2589 baud = serial8250_get_baud_rate(port, termios, old);
2590 quot = serial8250_get_divisor(up, baud, &frac);
2593 * Ok, we're now changing the port state. Do it with
2594 * interrupts disabled.
2596 serial8250_rpm_get(up);
2597 spin_lock_irqsave(&port->lock, flags);
2599 up->lcr = cval; /* Save computed LCR */
2601 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2602 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2603 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2604 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2605 up->fcr |= UART_FCR_TRIGGER_1;
2610 * MCR-based auto flow control. When AFE is enabled, RTS will be
2611 * deasserted when the receive FIFO contains more characters than
2612 * the trigger, or the MCR RTS bit is cleared.
2614 if (up->capabilities & UART_CAP_AFE) {
2615 up->mcr &= ~UART_MCR_AFE;
2616 if (termios->c_cflag & CRTSCTS)
2617 up->mcr |= UART_MCR_AFE;
2621 * Update the per-port timeout.
2623 uart_update_timeout(port, termios->c_cflag, baud);
2625 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2626 if (termios->c_iflag & INPCK)
2627 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2628 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2629 port->read_status_mask |= UART_LSR_BI;
2632 * Characteres to ignore
2634 port->ignore_status_mask = 0;
2635 if (termios->c_iflag & IGNPAR)
2636 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2637 if (termios->c_iflag & IGNBRK) {
2638 port->ignore_status_mask |= UART_LSR_BI;
2640 * If we're ignoring parity and break indicators,
2641 * ignore overruns too (for real raw support).
2643 if (termios->c_iflag & IGNPAR)
2644 port->ignore_status_mask |= UART_LSR_OE;
2648 * ignore all characters if CREAD is not set
2650 if ((termios->c_cflag & CREAD) == 0)
2651 port->ignore_status_mask |= UART_LSR_DR;
2654 * CTS flow control flag and modem status interrupts
2656 up->ier &= ~UART_IER_MSI;
2657 if (!(up->bugs & UART_BUG_NOMSR) &&
2658 UART_ENABLE_MS(&up->port, termios->c_cflag))
2659 up->ier |= UART_IER_MSI;
2660 if (up->capabilities & UART_CAP_UUE)
2661 up->ier |= UART_IER_UUE;
2662 if (up->capabilities & UART_CAP_RTOIE)
2663 up->ier |= UART_IER_RTOIE;
2665 serial_port_out(port, UART_IER, up->ier);
2667 if (up->capabilities & UART_CAP_EFR) {
2668 unsigned char efr = 0;
2670 * TI16C752/Startech hardware flow control. FIXME:
2671 * - TI16C752 requires control thresholds to be set.
2672 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2674 if (termios->c_cflag & CRTSCTS)
2675 efr |= UART_EFR_CTS;
2677 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2678 if (port->flags & UPF_EXAR_EFR)
2679 serial_port_out(port, UART_XR_EFR, efr);
2681 serial_port_out(port, UART_EFR, efr);
2684 serial8250_set_divisor(port, baud, quot, frac);
2687 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2688 * is written without DLAB set, this mode will be disabled.
2690 if (port->type == PORT_16750)
2691 serial_port_out(port, UART_FCR, up->fcr);
2693 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2694 if (port->type != PORT_16750) {
2695 /* emulated UARTs (Lucent Venus 167x) need two steps */
2696 if (up->fcr & UART_FCR_ENABLE_FIFO)
2697 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2698 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2700 serial8250_set_mctrl(port, port->mctrl);
2701 spin_unlock_irqrestore(&port->lock, flags);
2702 serial8250_rpm_put(up);
2704 /* Don't rewrite B0 */
2705 if (tty_termios_baud_rate(termios))
2706 tty_termios_encode_baud_rate(termios, baud, baud);
2708 EXPORT_SYMBOL(serial8250_do_set_termios);
2711 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2712 struct ktermios *old)
2714 if (port->set_termios)
2715 port->set_termios(port, termios, old);
2717 serial8250_do_set_termios(port, termios, old);
2720 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2722 if (termios->c_line == N_PPS) {
2723 port->flags |= UPF_HARDPPS_CD;
2724 spin_lock_irq(&port->lock);
2725 serial8250_enable_ms(port);
2726 spin_unlock_irq(&port->lock);
2728 port->flags &= ~UPF_HARDPPS_CD;
2729 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2730 spin_lock_irq(&port->lock);
2731 serial8250_disable_ms(port);
2732 spin_unlock_irq(&port->lock);
2736 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2739 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2741 if (port->set_ldisc)
2742 port->set_ldisc(port, termios);
2744 serial8250_do_set_ldisc(port, termios);
2747 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2748 unsigned int oldstate)
2750 struct uart_8250_port *p = up_to_u8250p(port);
2752 serial8250_set_sleep(p, state != 0);
2754 EXPORT_SYMBOL(serial8250_do_pm);
2757 serial8250_pm(struct uart_port *port, unsigned int state,
2758 unsigned int oldstate)
2761 port->pm(port, state, oldstate);
2763 serial8250_do_pm(port, state, oldstate);
2766 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2768 if (pt->port.mapsize)
2769 return pt->port.mapsize;
2770 if (pt->port.iotype == UPIO_AU) {
2771 if (pt->port.type == PORT_RT2880)
2775 if (is_omap1_8250(pt))
2776 return 0x16 << pt->port.regshift;
2778 return 8 << pt->port.regshift;
2782 * Resource handling.
2784 static int serial8250_request_std_resource(struct uart_8250_port *up)
2786 unsigned int size = serial8250_port_size(up);
2787 struct uart_port *port = &up->port;
2790 switch (port->iotype) {
2800 if (!request_mem_region(port->mapbase, size, "serial")) {
2805 if (port->flags & UPF_IOREMAP) {
2806 port->membase = ioremap_nocache(port->mapbase, size);
2807 if (!port->membase) {
2808 release_mem_region(port->mapbase, size);
2816 if (!request_region(port->iobase, size, "serial"))
2823 static void serial8250_release_std_resource(struct uart_8250_port *up)
2825 unsigned int size = serial8250_port_size(up);
2826 struct uart_port *port = &up->port;
2828 switch (port->iotype) {
2838 if (port->flags & UPF_IOREMAP) {
2839 iounmap(port->membase);
2840 port->membase = NULL;
2843 release_mem_region(port->mapbase, size);
2848 release_region(port->iobase, size);
2853 static void serial8250_release_port(struct uart_port *port)
2855 struct uart_8250_port *up = up_to_u8250p(port);
2857 serial8250_release_std_resource(up);
2860 static int serial8250_request_port(struct uart_port *port)
2862 struct uart_8250_port *up = up_to_u8250p(port);
2864 return serial8250_request_std_resource(up);
2867 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2869 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2870 unsigned char bytes;
2872 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2874 return bytes ? bytes : -EOPNOTSUPP;
2877 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2879 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2882 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2885 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2886 if (bytes < conf_type->rxtrig_bytes[i])
2887 /* Use the nearest lower value */
2888 return (--i) << UART_FCR_R_TRIG_SHIFT;
2891 return UART_FCR_R_TRIG_11;
2894 static int do_get_rxtrig(struct tty_port *port)
2896 struct uart_state *state = container_of(port, struct uart_state, port);
2897 struct uart_port *uport = state->uart_port;
2898 struct uart_8250_port *up = up_to_u8250p(uport);
2900 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2903 return fcr_get_rxtrig_bytes(up);
2906 static int do_serial8250_get_rxtrig(struct tty_port *port)
2910 mutex_lock(&port->mutex);
2911 rxtrig_bytes = do_get_rxtrig(port);
2912 mutex_unlock(&port->mutex);
2914 return rxtrig_bytes;
2917 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2918 struct device_attribute *attr, char *buf)
2920 struct tty_port *port = dev_get_drvdata(dev);
2923 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2924 if (rxtrig_bytes < 0)
2925 return rxtrig_bytes;
2927 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2930 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2932 struct uart_state *state = container_of(port, struct uart_state, port);
2933 struct uart_port *uport = state->uart_port;
2934 struct uart_8250_port *up = up_to_u8250p(uport);
2937 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2941 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2945 serial8250_clear_fifos(up);
2946 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2947 up->fcr |= (unsigned char)rxtrig;
2948 serial_out(up, UART_FCR, up->fcr);
2952 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2956 mutex_lock(&port->mutex);
2957 ret = do_set_rxtrig(port, bytes);
2958 mutex_unlock(&port->mutex);
2963 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2964 struct device_attribute *attr, const char *buf, size_t count)
2966 struct tty_port *port = dev_get_drvdata(dev);
2967 unsigned char bytes;
2973 ret = kstrtou8(buf, 10, &bytes);
2977 ret = do_serial8250_set_rxtrig(port, bytes);
2984 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2985 serial8250_get_attr_rx_trig_bytes,
2986 serial8250_set_attr_rx_trig_bytes);
2988 static struct attribute *serial8250_dev_attrs[] = {
2989 &dev_attr_rx_trig_bytes.attr,
2993 static struct attribute_group serial8250_dev_attr_group = {
2994 .attrs = serial8250_dev_attrs,
2997 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2999 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3001 if (conf_type->rxtrig_bytes[0])
3002 up->port.attr_group = &serial8250_dev_attr_group;
3005 static void serial8250_config_port(struct uart_port *port, int flags)
3007 struct uart_8250_port *up = up_to_u8250p(port);
3011 * Find the region that we can probe for. This in turn
3012 * tells us whether we can probe for the type of port.
3014 ret = serial8250_request_std_resource(up);
3018 if (port->iotype != up->cur_iotype)
3019 set_io_from_upio(port);
3021 if (flags & UART_CONFIG_TYPE)
3024 /* if access method is AU, it is a 16550 with a quirk */
3025 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3026 up->bugs |= UART_BUG_NOMSR;
3028 /* HW bugs may trigger IRQ while IIR == NO_INT */
3029 if (port->type == PORT_TEGRA)
3030 up->bugs |= UART_BUG_NOMSR;
3032 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3035 if (port->type == PORT_UNKNOWN)
3036 serial8250_release_std_resource(up);
3038 /* Fixme: probably not the best place for this */
3039 if ((port->type == PORT_XR17V35X) ||
3040 (port->type == PORT_XR17D15X))
3041 port->handle_irq = exar_handle_irq;
3043 register_dev_spec_attr_grp(up);
3044 up->fcr = uart_config[up->port.type].fcr;
3048 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3050 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3051 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3052 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3053 ser->type == PORT_STARTECH)
3058 static const char *serial8250_type(struct uart_port *port)
3060 int type = port->type;
3062 if (type >= ARRAY_SIZE(uart_config))
3064 return uart_config[type].name;
3067 static const struct uart_ops serial8250_pops = {
3068 .tx_empty = serial8250_tx_empty,
3069 .set_mctrl = serial8250_set_mctrl,
3070 .get_mctrl = serial8250_get_mctrl,
3071 .stop_tx = serial8250_stop_tx,
3072 .start_tx = serial8250_start_tx,
3073 .throttle = serial8250_throttle,
3074 .unthrottle = serial8250_unthrottle,
3075 .stop_rx = serial8250_stop_rx,
3076 .enable_ms = serial8250_enable_ms,
3077 .break_ctl = serial8250_break_ctl,
3078 .startup = serial8250_startup,
3079 .shutdown = serial8250_shutdown,
3080 .set_termios = serial8250_set_termios,
3081 .set_ldisc = serial8250_set_ldisc,
3082 .pm = serial8250_pm,
3083 .type = serial8250_type,
3084 .release_port = serial8250_release_port,
3085 .request_port = serial8250_request_port,
3086 .config_port = serial8250_config_port,
3087 .verify_port = serial8250_verify_port,
3088 #ifdef CONFIG_CONSOLE_POLL
3089 .poll_get_char = serial8250_get_poll_char,
3090 .poll_put_char = serial8250_put_poll_char,
3094 void serial8250_init_port(struct uart_8250_port *up)
3096 struct uart_port *port = &up->port;
3098 spin_lock_init(&port->lock);
3099 port->ops = &serial8250_pops;
3101 up->cur_iotype = 0xFF;
3103 EXPORT_SYMBOL_GPL(serial8250_init_port);
3105 void serial8250_set_defaults(struct uart_8250_port *up)
3107 struct uart_port *port = &up->port;
3109 if (up->port.flags & UPF_FIXED_TYPE) {
3110 unsigned int type = up->port.type;
3112 if (!up->port.fifosize)
3113 up->port.fifosize = uart_config[type].fifo_size;
3115 up->tx_loadsz = uart_config[type].tx_loadsz;
3116 if (!up->capabilities)
3117 up->capabilities = uart_config[type].flags;
3120 set_io_from_upio(port);
3122 /* default dma handlers */
3124 if (!up->dma->tx_dma)
3125 up->dma->tx_dma = serial8250_tx_dma;
3126 if (!up->dma->rx_dma)
3127 up->dma->rx_dma = serial8250_rx_dma;
3130 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3132 #ifdef CONFIG_SERIAL_8250_CONSOLE
3134 static void serial8250_console_putchar(struct uart_port *port, int ch)
3136 struct uart_8250_port *up = up_to_u8250p(port);
3138 wait_for_xmitr(up, UART_LSR_THRE);
3139 serial_port_out(port, UART_TX, ch);
3143 * Restore serial console when h/w power-off detected
3145 static void serial8250_console_restore(struct uart_8250_port *up)
3147 struct uart_port *port = &up->port;
3148 struct ktermios termios;
3149 unsigned int baud, quot, frac = 0;
3151 termios.c_cflag = port->cons->cflag;
3152 if (port->state->port.tty && termios.c_cflag == 0)
3153 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3155 baud = serial8250_get_baud_rate(port, &termios, NULL);
3156 quot = serial8250_get_divisor(up, baud, &frac);
3158 serial8250_set_divisor(port, baud, quot, frac);
3159 serial_port_out(port, UART_LCR, up->lcr);
3160 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3164 * Print a string to the serial port trying not to disturb
3165 * any possible real use of the port...
3167 * The console_lock must be held when we get here.
3169 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3172 struct uart_port *port = &up->port;
3173 unsigned long flags;
3177 touch_nmi_watchdog();
3179 serial8250_rpm_get(up);
3183 else if (oops_in_progress)
3184 locked = spin_trylock_irqsave(&port->lock, flags);
3186 spin_lock_irqsave(&port->lock, flags);
3189 * First save the IER then disable the interrupts
3191 ier = serial_port_in(port, UART_IER);
3193 if (up->capabilities & UART_CAP_UUE)
3194 serial_port_out(port, UART_IER, UART_IER_UUE);
3196 serial_port_out(port, UART_IER, 0);
3198 /* check scratch reg to see if port powered off during system sleep */
3199 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3200 serial8250_console_restore(up);
3204 uart_console_write(port, s, count, serial8250_console_putchar);
3207 * Finally, wait for transmitter to become empty
3208 * and restore the IER
3210 wait_for_xmitr(up, BOTH_EMPTY);
3211 serial_port_out(port, UART_IER, ier);
3214 * The receive handling will happen properly because the
3215 * receive ready bit will still be set; it is not cleared
3216 * on read. However, modem control will not, we must
3217 * call it if we have saved something in the saved flags
3218 * while processing with interrupts off.
3220 if (up->msr_saved_flags)
3221 serial8250_modem_status(up);
3224 spin_unlock_irqrestore(&port->lock, flags);
3225 serial8250_rpm_put(up);
3228 static unsigned int probe_baud(struct uart_port *port)
3230 unsigned char lcr, dll, dlm;
3233 lcr = serial_port_in(port, UART_LCR);
3234 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3235 dll = serial_port_in(port, UART_DLL);
3236 dlm = serial_port_in(port, UART_DLM);
3237 serial_port_out(port, UART_LCR, lcr);
3239 quot = (dlm << 8) | dll;
3240 return (port->uartclk / 16) / quot;
3243 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3250 if (!port->iobase && !port->membase)
3254 uart_parse_options(options, &baud, &parity, &bits, &flow);
3256 baud = probe_baud(port);
3258 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3261 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3263 MODULE_LICENSE("GPL");