2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
50 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
52 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
58 * Here we define the default xmit fifo size used for each type of UART.
60 static const struct serial8250_config uart_config[] = {
85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
86 .rxtrig_bytes = {1, 4, 8, 14},
87 .flags = UART_CAP_FIFO,
98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 .rxtrig_bytes = {8, 16, 24, 28},
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 .rxtrig_bytes = {1, 16, 32, 56},
116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
124 .name = "16C950/954",
127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 .rxtrig_bytes = {8, 16, 56, 60},
138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
152 .flags = UART_CAP_FIFO,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_NATSEMI,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
180 .flags = UART_CAP_FIFO | UART_CAP_AFE,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO | UART_CAP_AFE,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 .rxtrig_bytes = {1, 4, 8, 14},
196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO,
223 [PORT_BRCM_TRUMANAGE] = {
227 .flags = UART_CAP_HFIFO,
232 [PORT_ALTR_16550_F32] = {
233 .name = "Altera 16550 FIFO32",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
254 workaround of errata A-008006 which states that tx_loadsz should be
255 configured less than Maximum supported fifo bytes */
256 [PORT_16550A_FSL64] = {
257 .name = "16550A_FSL64",
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
262 .flags = UART_CAP_FIFO,
266 /* Uart divisor latch read */
267 static int default_serial_dl_read(struct uart_8250_port *up)
269 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
272 /* Uart divisor latch write */
273 static void default_serial_dl_write(struct uart_8250_port *up, int value)
275 serial_out(up, UART_DLL, value & 0xff);
276 serial_out(up, UART_DLM, value >> 8 & 0xff);
279 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
281 /* Au1x00/RT288x UART hardware has a weird register layout */
282 static const s8 au_io_in_map[8] = {
290 -1, /* UART_SCR (unmapped) */
293 static const s8 au_io_out_map[8] = {
299 -1, /* UART_LSR (unmapped) */
300 -1, /* UART_MSR (unmapped) */
301 -1, /* UART_SCR (unmapped) */
304 static unsigned int au_serial_in(struct uart_port *p, int offset)
306 if (offset >= ARRAY_SIZE(au_io_in_map))
308 offset = au_io_in_map[offset];
311 return __raw_readl(p->membase + (offset << p->regshift));
314 static void au_serial_out(struct uart_port *p, int offset, int value)
316 if (offset >= ARRAY_SIZE(au_io_out_map))
318 offset = au_io_out_map[offset];
321 __raw_writel(value, p->membase + (offset << p->regshift));
324 /* Au1x00 haven't got a standard divisor latch */
325 static int au_serial_dl_read(struct uart_8250_port *up)
327 return __raw_readl(up->port.membase + 0x28);
330 static void au_serial_dl_write(struct uart_8250_port *up, int value)
332 __raw_writel(value, up->port.membase + 0x28);
337 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
339 offset = offset << p->regshift;
340 outb(p->hub6 - 1 + offset, p->iobase);
341 return inb(p->iobase + 1);
344 static void hub6_serial_out(struct uart_port *p, int offset, int value)
346 offset = offset << p->regshift;
347 outb(p->hub6 - 1 + offset, p->iobase);
348 outb(value, p->iobase + 1);
351 static unsigned int mem_serial_in(struct uart_port *p, int offset)
353 offset = offset << p->regshift;
354 return readb(p->membase + offset);
357 static void mem_serial_out(struct uart_port *p, int offset, int value)
359 offset = offset << p->regshift;
360 writeb(value, p->membase + offset);
363 static void mem32_serial_out(struct uart_port *p, int offset, int value)
365 offset = offset << p->regshift;
366 writel(value, p->membase + offset);
369 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
371 offset = offset << p->regshift;
372 return readl(p->membase + offset);
375 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
377 offset = offset << p->regshift;
378 iowrite32be(value, p->membase + offset);
381 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
383 offset = offset << p->regshift;
384 return ioread32be(p->membase + offset);
387 static unsigned int io_serial_in(struct uart_port *p, int offset)
389 offset = offset << p->regshift;
390 return inb(p->iobase + offset);
393 static void io_serial_out(struct uart_port *p, int offset, int value)
395 offset = offset << p->regshift;
396 outb(value, p->iobase + offset);
399 static int serial8250_default_handle_irq(struct uart_port *port);
400 static int exar_handle_irq(struct uart_port *port);
402 static void set_io_from_upio(struct uart_port *p)
404 struct uart_8250_port *up = up_to_u8250p(p);
406 up->dl_read = default_serial_dl_read;
407 up->dl_write = default_serial_dl_write;
411 p->serial_in = hub6_serial_in;
412 p->serial_out = hub6_serial_out;
416 p->serial_in = mem_serial_in;
417 p->serial_out = mem_serial_out;
421 p->serial_in = mem32_serial_in;
422 p->serial_out = mem32_serial_out;
426 p->serial_in = mem32be_serial_in;
427 p->serial_out = mem32be_serial_out;
430 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
432 p->serial_in = au_serial_in;
433 p->serial_out = au_serial_out;
434 up->dl_read = au_serial_dl_read;
435 up->dl_write = au_serial_dl_write;
440 p->serial_in = io_serial_in;
441 p->serial_out = io_serial_out;
444 /* Remember loaded iotype */
445 up->cur_iotype = p->iotype;
446 p->handle_irq = serial8250_default_handle_irq;
450 serial_port_out_sync(struct uart_port *p, int offset, int value)
457 p->serial_out(p, offset, value);
458 p->serial_in(p, UART_LCR); /* safe, no side-effects */
461 p->serial_out(p, offset, value);
468 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
470 serial_out(up, UART_SCR, offset);
471 serial_out(up, UART_ICR, value);
474 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
478 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
479 serial_out(up, UART_SCR, offset);
480 value = serial_in(up, UART_ICR);
481 serial_icr_write(up, UART_ACR, up->acr);
489 static void serial8250_clear_fifos(struct uart_8250_port *p)
491 if (p->capabilities & UART_CAP_FIFO) {
492 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
493 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
494 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
495 serial_out(p, UART_FCR, 0);
499 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
501 serial8250_clear_fifos(p);
502 serial_out(p, UART_FCR, p->fcr);
504 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
506 void serial8250_rpm_get(struct uart_8250_port *p)
508 if (!(p->capabilities & UART_CAP_RPM))
510 pm_runtime_get_sync(p->port.dev);
512 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
514 void serial8250_rpm_put(struct uart_8250_port *p)
516 if (!(p->capabilities & UART_CAP_RPM))
518 pm_runtime_mark_last_busy(p->port.dev);
519 pm_runtime_put_autosuspend(p->port.dev);
521 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
524 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
525 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
526 * empty and the HW can idle again.
528 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
530 unsigned char rpm_active;
532 if (!(p->capabilities & UART_CAP_RPM))
535 rpm_active = xchg(&p->rpm_tx_active, 1);
538 pm_runtime_get_sync(p->port.dev);
541 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
543 unsigned char rpm_active;
545 if (!(p->capabilities & UART_CAP_RPM))
548 rpm_active = xchg(&p->rpm_tx_active, 0);
551 pm_runtime_mark_last_busy(p->port.dev);
552 pm_runtime_put_autosuspend(p->port.dev);
556 * IER sleep support. UARTs which have EFRs need the "extended
557 * capability" bit enabled. Note that on XR16C850s, we need to
558 * reset LCR to write to IER.
560 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
562 unsigned char lcr = 0, efr = 0;
564 * Exar UARTs have a SLEEP register that enables or disables
565 * each UART to enter sleep mode separately. On the XR17V35x the
566 * register is accessible to each UART at the UART_EXAR_SLEEP
567 * offset but the UART channel may only write to the corresponding
570 serial8250_rpm_get(p);
571 if ((p->port.type == PORT_XR17V35X) ||
572 (p->port.type == PORT_XR17D15X)) {
573 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
577 if (p->capabilities & UART_CAP_SLEEP) {
578 if (p->capabilities & UART_CAP_EFR) {
579 lcr = serial_in(p, UART_LCR);
580 efr = serial_in(p, UART_EFR);
581 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
582 serial_out(p, UART_EFR, UART_EFR_ECB);
583 serial_out(p, UART_LCR, 0);
585 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
586 if (p->capabilities & UART_CAP_EFR) {
587 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
588 serial_out(p, UART_EFR, efr);
589 serial_out(p, UART_LCR, lcr);
593 serial8250_rpm_put(p);
596 #ifdef CONFIG_SERIAL_8250_RSA
598 * Attempts to turn on the RSA FIFO. Returns zero on failure.
599 * We set the port uart clock rate if we succeed.
601 static int __enable_rsa(struct uart_8250_port *up)
606 mode = serial_in(up, UART_RSA_MSR);
607 result = mode & UART_RSA_MSR_FIFO;
610 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
611 mode = serial_in(up, UART_RSA_MSR);
612 result = mode & UART_RSA_MSR_FIFO;
616 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
621 static void enable_rsa(struct uart_8250_port *up)
623 if (up->port.type == PORT_RSA) {
624 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
625 spin_lock_irq(&up->port.lock);
627 spin_unlock_irq(&up->port.lock);
629 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
630 serial_out(up, UART_RSA_FRR, 0);
635 * Attempts to turn off the RSA FIFO. Returns zero on failure.
636 * It is unknown why interrupts were disabled in here. However,
637 * the caller is expected to preserve this behaviour by grabbing
638 * the spinlock before calling this function.
640 static void disable_rsa(struct uart_8250_port *up)
645 if (up->port.type == PORT_RSA &&
646 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
647 spin_lock_irq(&up->port.lock);
649 mode = serial_in(up, UART_RSA_MSR);
650 result = !(mode & UART_RSA_MSR_FIFO);
653 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
654 mode = serial_in(up, UART_RSA_MSR);
655 result = !(mode & UART_RSA_MSR_FIFO);
659 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
660 spin_unlock_irq(&up->port.lock);
663 #endif /* CONFIG_SERIAL_8250_RSA */
666 * This is a quickie test to see how big the FIFO is.
667 * It doesn't work at all the time, more's the pity.
669 static int size_fifo(struct uart_8250_port *up)
671 unsigned char old_fcr, old_mcr, old_lcr;
672 unsigned short old_dl;
675 old_lcr = serial_in(up, UART_LCR);
676 serial_out(up, UART_LCR, 0);
677 old_fcr = serial_in(up, UART_FCR);
678 old_mcr = serial_in(up, UART_MCR);
679 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
680 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
681 serial_out(up, UART_MCR, UART_MCR_LOOP);
682 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
683 old_dl = serial_dl_read(up);
684 serial_dl_write(up, 0x0001);
685 serial_out(up, UART_LCR, 0x03);
686 for (count = 0; count < 256; count++)
687 serial_out(up, UART_TX, count);
688 mdelay(20);/* FIXME - schedule_timeout */
689 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
690 (count < 256); count++)
691 serial_in(up, UART_RX);
692 serial_out(up, UART_FCR, old_fcr);
693 serial_out(up, UART_MCR, old_mcr);
694 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
695 serial_dl_write(up, old_dl);
696 serial_out(up, UART_LCR, old_lcr);
702 * Read UART ID using the divisor method - set DLL and DLM to zero
703 * and the revision will be in DLL and device type in DLM. We
704 * preserve the device state across this.
706 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
708 unsigned char old_dll, old_dlm, old_lcr;
711 old_lcr = serial_in(p, UART_LCR);
712 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
714 old_dll = serial_in(p, UART_DLL);
715 old_dlm = serial_in(p, UART_DLM);
717 serial_out(p, UART_DLL, 0);
718 serial_out(p, UART_DLM, 0);
720 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
722 serial_out(p, UART_DLL, old_dll);
723 serial_out(p, UART_DLM, old_dlm);
724 serial_out(p, UART_LCR, old_lcr);
730 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
731 * When this function is called we know it is at least a StarTech
732 * 16650 V2, but it might be one of several StarTech UARTs, or one of
733 * its clones. (We treat the broken original StarTech 16650 V1 as a
734 * 16550, and why not? Startech doesn't seem to even acknowledge its
737 * What evil have men's minds wrought...
739 static void autoconfig_has_efr(struct uart_8250_port *up)
741 unsigned int id1, id2, id3, rev;
744 * Everything with an EFR has SLEEP
746 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
749 * First we check to see if it's an Oxford Semiconductor UART.
751 * If we have to do this here because some non-National
752 * Semiconductor clone chips lock up if you try writing to the
753 * LSR register (which serial_icr_read does)
757 * Check for Oxford Semiconductor 16C950.
759 * EFR [4] must be set else this test fails.
761 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
762 * claims that it's needed for 952 dual UART's (which are not
763 * recommended for new designs).
766 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
767 serial_out(up, UART_EFR, UART_EFR_ECB);
768 serial_out(up, UART_LCR, 0x00);
769 id1 = serial_icr_read(up, UART_ID1);
770 id2 = serial_icr_read(up, UART_ID2);
771 id3 = serial_icr_read(up, UART_ID3);
772 rev = serial_icr_read(up, UART_REV);
774 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
776 if (id1 == 0x16 && id2 == 0xC9 &&
777 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
778 up->port.type = PORT_16C950;
781 * Enable work around for the Oxford Semiconductor 952 rev B
782 * chip which causes it to seriously miscalculate baud rates
785 if (id3 == 0x52 && rev == 0x01)
786 up->bugs |= UART_BUG_QUOT;
791 * We check for a XR16C850 by setting DLL and DLM to 0, and then
792 * reading back DLL and DLM. The chip type depends on the DLM
794 * 0x10 - XR16C850 and the DLL contains the chip revision.
798 id1 = autoconfig_read_divisor_id(up);
799 DEBUG_AUTOCONF("850id=%04x ", id1);
802 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
803 up->port.type = PORT_16850;
808 * It wasn't an XR16C850.
810 * We distinguish between the '654 and the '650 by counting
811 * how many bytes are in the FIFO. I'm using this for now,
812 * since that's the technique that was sent to me in the
813 * serial driver update, but I'm not convinced this works.
814 * I've had problems doing this in the past. -TYT
816 if (size_fifo(up) == 64)
817 up->port.type = PORT_16654;
819 up->port.type = PORT_16650V2;
823 * We detected a chip without a FIFO. Only two fall into
824 * this category - the original 8250 and the 16450. The
825 * 16450 has a scratch register (accessible with LCR=0)
827 static void autoconfig_8250(struct uart_8250_port *up)
829 unsigned char scratch, status1, status2;
831 up->port.type = PORT_8250;
833 scratch = serial_in(up, UART_SCR);
834 serial_out(up, UART_SCR, 0xa5);
835 status1 = serial_in(up, UART_SCR);
836 serial_out(up, UART_SCR, 0x5a);
837 status2 = serial_in(up, UART_SCR);
838 serial_out(up, UART_SCR, scratch);
840 if (status1 == 0xa5 && status2 == 0x5a)
841 up->port.type = PORT_16450;
844 static int broken_efr(struct uart_8250_port *up)
847 * Exar ST16C2550 "A2" devices incorrectly detect as
848 * having an EFR, and report an ID of 0x0201. See
849 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
851 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
858 * We know that the chip has FIFOs. Does it have an EFR? The
859 * EFR is located in the same register position as the IIR and
860 * we know the top two bits of the IIR are currently set. The
861 * EFR should contain zero. Try to read the EFR.
863 static void autoconfig_16550a(struct uart_8250_port *up)
865 unsigned char status1, status2;
866 unsigned int iersave;
868 up->port.type = PORT_16550A;
869 up->capabilities |= UART_CAP_FIFO;
872 * XR17V35x UARTs have an extra divisor register, DLD
873 * that gets enabled with when DLAB is set which will
874 * cause the device to incorrectly match and assign
875 * port type to PORT_16650. The EFR for this UART is
876 * found at offset 0x09. Instead check the Deice ID (DVID)
877 * register for a 2, 4 or 8 port UART.
879 if (up->port.flags & UPF_EXAR_EFR) {
880 status1 = serial_in(up, UART_EXAR_DVID);
881 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
882 DEBUG_AUTOCONF("Exar XR17V35x ");
883 up->port.type = PORT_XR17V35X;
884 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
893 * Check for presence of the EFR when DLAB is set.
894 * Only ST16C650V1 UARTs pass this test.
896 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
897 if (serial_in(up, UART_EFR) == 0) {
898 serial_out(up, UART_EFR, 0xA8);
899 if (serial_in(up, UART_EFR) != 0) {
900 DEBUG_AUTOCONF("EFRv1 ");
901 up->port.type = PORT_16650;
902 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
904 serial_out(up, UART_LCR, 0);
905 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
907 status1 = serial_in(up, UART_IIR) >> 5;
908 serial_out(up, UART_FCR, 0);
909 serial_out(up, UART_LCR, 0);
912 up->port.type = PORT_16550A_FSL64;
914 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
916 serial_out(up, UART_EFR, 0);
921 * Maybe it requires 0xbf to be written to the LCR.
922 * (other ST16C650V2 UARTs, TI16C752A, etc)
924 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
925 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
926 DEBUG_AUTOCONF("EFRv2 ");
927 autoconfig_has_efr(up);
932 * Check for a National Semiconductor SuperIO chip.
933 * Attempt to switch to bank 2, read the value of the LOOP bit
934 * from EXCR1. Switch back to bank 0, change it in MCR. Then
935 * switch back to bank 2, read it from EXCR1 again and check
936 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
938 serial_out(up, UART_LCR, 0);
939 status1 = serial_in(up, UART_MCR);
940 serial_out(up, UART_LCR, 0xE0);
941 status2 = serial_in(up, 0x02); /* EXCR1 */
943 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
944 serial_out(up, UART_LCR, 0);
945 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
946 serial_out(up, UART_LCR, 0xE0);
947 status2 = serial_in(up, 0x02); /* EXCR1 */
948 serial_out(up, UART_LCR, 0);
949 serial_out(up, UART_MCR, status1);
951 if ((status2 ^ status1) & UART_MCR_LOOP) {
954 serial_out(up, UART_LCR, 0xE0);
956 quot = serial_dl_read(up);
959 if (ns16550a_goto_highspeed(up))
960 serial_dl_write(up, quot);
962 serial_out(up, UART_LCR, 0);
964 up->port.uartclk = 921600*16;
965 up->port.type = PORT_NS16550A;
966 up->capabilities |= UART_NATSEMI;
972 * No EFR. Try to detect a TI16750, which only sets bit 5 of
973 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
974 * Try setting it with and without DLAB set. Cheap clones
975 * set bit 5 without DLAB set.
977 serial_out(up, UART_LCR, 0);
978 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
979 status1 = serial_in(up, UART_IIR) >> 5;
980 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
981 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
982 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
983 status2 = serial_in(up, UART_IIR) >> 5;
984 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
985 serial_out(up, UART_LCR, 0);
987 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
989 if (status1 == 6 && status2 == 7) {
990 up->port.type = PORT_16750;
991 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
996 * Try writing and reading the UART_IER_UUE bit (b6).
997 * If it works, this is probably one of the Xscale platform's
999 * We're going to explicitly set the UUE bit to 0 before
1000 * trying to write and read a 1 just to make sure it's not
1001 * already a 1 and maybe locked there before we even start start.
1003 iersave = serial_in(up, UART_IER);
1004 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1005 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1007 * OK it's in a known zero state, try writing and reading
1008 * without disturbing the current state of the other bits.
1010 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1011 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1014 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1016 DEBUG_AUTOCONF("Xscale ");
1017 up->port.type = PORT_XSCALE;
1018 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1023 * If we got here we couldn't force the IER_UUE bit to 0.
1024 * Log it and continue.
1026 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1028 serial_out(up, UART_IER, iersave);
1031 * Exar uarts have EFR in a weird location
1033 if (up->port.flags & UPF_EXAR_EFR) {
1034 DEBUG_AUTOCONF("Exar XR17D15x ");
1035 up->port.type = PORT_XR17D15X;
1036 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1043 * We distinguish between 16550A and U6 16550A by counting
1044 * how many bytes are in the FIFO.
1046 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1047 up->port.type = PORT_U6_16550A;
1048 up->capabilities |= UART_CAP_AFE;
1053 * This routine is called by rs_init() to initialize a specific serial
1054 * port. It determines what type of UART chip this serial port is
1055 * using: 8250, 16450, 16550, 16550A. The important question is
1056 * whether or not this UART is a 16550A or not, since this will
1057 * determine whether or not we can use its FIFO features or not.
1059 static void autoconfig(struct uart_8250_port *up)
1061 unsigned char status1, scratch, scratch2, scratch3;
1062 unsigned char save_lcr, save_mcr;
1063 struct uart_port *port = &up->port;
1064 unsigned long flags;
1065 unsigned int old_capabilities;
1067 if (!port->iobase && !port->mapbase && !port->membase)
1070 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1071 serial_index(port), port->iobase, port->membase);
1074 * We really do need global IRQs disabled here - we're going to
1075 * be frobbing the chips IRQ enable register to see if it exists.
1077 spin_lock_irqsave(&port->lock, flags);
1079 up->capabilities = 0;
1082 if (!(port->flags & UPF_BUGGY_UART)) {
1084 * Do a simple existence test first; if we fail this,
1085 * there's no point trying anything else.
1087 * 0x80 is used as a nonsense port to prevent against
1088 * false positives due to ISA bus float. The
1089 * assumption is that 0x80 is a non-existent port;
1090 * which should be safe since include/asm/io.h also
1091 * makes this assumption.
1093 * Note: this is safe as long as MCR bit 4 is clear
1094 * and the device is in "PC" mode.
1096 scratch = serial_in(up, UART_IER);
1097 serial_out(up, UART_IER, 0);
1102 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1103 * 16C754B) allow only to modify them if an EFR bit is set.
1105 scratch2 = serial_in(up, UART_IER) & 0x0f;
1106 serial_out(up, UART_IER, 0x0F);
1110 scratch3 = serial_in(up, UART_IER) & 0x0f;
1111 serial_out(up, UART_IER, scratch);
1112 if (scratch2 != 0 || scratch3 != 0x0F) {
1114 * We failed; there's nothing here
1116 spin_unlock_irqrestore(&port->lock, flags);
1117 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1118 scratch2, scratch3);
1123 save_mcr = serial_in(up, UART_MCR);
1124 save_lcr = serial_in(up, UART_LCR);
1127 * Check to see if a UART is really there. Certain broken
1128 * internal modems based on the Rockwell chipset fail this
1129 * test, because they apparently don't implement the loopback
1130 * test mode. So this test is skipped on the COM 1 through
1131 * COM 4 ports. This *should* be safe, since no board
1132 * manufacturer would be stupid enough to design a board
1133 * that conflicts with COM 1-4 --- we hope!
1135 if (!(port->flags & UPF_SKIP_TEST)) {
1136 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1137 status1 = serial_in(up, UART_MSR) & 0xF0;
1138 serial_out(up, UART_MCR, save_mcr);
1139 if (status1 != 0x90) {
1140 spin_unlock_irqrestore(&port->lock, flags);
1141 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1148 * We're pretty sure there's a port here. Lets find out what
1149 * type of port it is. The IIR top two bits allows us to find
1150 * out if it's 8250 or 16450, 16550, 16550A or later. This
1151 * determines what we test for next.
1153 * We also initialise the EFR (if any) to zero for later. The
1154 * EFR occupies the same register location as the FCR and IIR.
1156 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1157 serial_out(up, UART_EFR, 0);
1158 serial_out(up, UART_LCR, 0);
1160 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1161 scratch = serial_in(up, UART_IIR) >> 6;
1165 autoconfig_8250(up);
1168 port->type = PORT_UNKNOWN;
1171 port->type = PORT_16550;
1174 autoconfig_16550a(up);
1178 #ifdef CONFIG_SERIAL_8250_RSA
1180 * Only probe for RSA ports if we got the region.
1182 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1184 port->type = PORT_RSA;
1187 serial_out(up, UART_LCR, save_lcr);
1189 port->fifosize = uart_config[up->port.type].fifo_size;
1190 old_capabilities = up->capabilities;
1191 up->capabilities = uart_config[port->type].flags;
1192 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1194 if (port->type == PORT_UNKNOWN)
1200 #ifdef CONFIG_SERIAL_8250_RSA
1201 if (port->type == PORT_RSA)
1202 serial_out(up, UART_RSA_FRR, 0);
1204 serial_out(up, UART_MCR, save_mcr);
1205 serial8250_clear_fifos(up);
1206 serial_in(up, UART_RX);
1207 if (up->capabilities & UART_CAP_UUE)
1208 serial_out(up, UART_IER, UART_IER_UUE);
1210 serial_out(up, UART_IER, 0);
1213 spin_unlock_irqrestore(&port->lock, flags);
1214 if (up->capabilities != old_capabilities) {
1216 "ttyS%d: detected caps %08x should be %08x\n",
1217 serial_index(port), old_capabilities,
1221 DEBUG_AUTOCONF("iir=%d ", scratch);
1222 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1225 static void autoconfig_irq(struct uart_8250_port *up)
1227 struct uart_port *port = &up->port;
1228 unsigned char save_mcr, save_ier;
1229 unsigned char save_ICP = 0;
1230 unsigned int ICP = 0;
1234 if (port->flags & UPF_FOURPORT) {
1235 ICP = (port->iobase & 0xfe0) | 0x1f;
1236 save_ICP = inb_p(ICP);
1241 if (uart_console(port))
1244 /* forget possible initially masked and pending IRQ */
1245 probe_irq_off(probe_irq_on());
1246 save_mcr = serial_in(up, UART_MCR);
1247 save_ier = serial_in(up, UART_IER);
1248 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1250 irqs = probe_irq_on();
1251 serial_out(up, UART_MCR, 0);
1253 if (port->flags & UPF_FOURPORT) {
1254 serial_out(up, UART_MCR,
1255 UART_MCR_DTR | UART_MCR_RTS);
1257 serial_out(up, UART_MCR,
1258 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1261 serial_in(up, UART_LSR);
1262 serial_in(up, UART_RX);
1263 serial_in(up, UART_IIR);
1264 serial_in(up, UART_MSR);
1265 serial_out(up, UART_TX, 0xFF);
1267 irq = probe_irq_off(irqs);
1269 serial_out(up, UART_MCR, save_mcr);
1270 serial_out(up, UART_IER, save_ier);
1272 if (port->flags & UPF_FOURPORT)
1273 outb_p(save_ICP, ICP);
1275 if (uart_console(port))
1278 port->irq = (irq > 0) ? irq : 0;
1281 static inline void __stop_tx(struct uart_8250_port *p)
1283 if (p->ier & UART_IER_THRI) {
1284 p->ier &= ~UART_IER_THRI;
1285 serial_out(p, UART_IER, p->ier);
1286 serial8250_rpm_put_tx(p);
1290 static void serial8250_stop_tx(struct uart_port *port)
1292 struct uart_8250_port *up = up_to_u8250p(port);
1294 serial8250_rpm_get(up);
1298 * We really want to stop the transmitter from sending.
1300 if (port->type == PORT_16C950) {
1301 up->acr |= UART_ACR_TXDIS;
1302 serial_icr_write(up, UART_ACR, up->acr);
1304 serial8250_rpm_put(up);
1307 static void serial8250_start_tx(struct uart_port *port)
1309 struct uart_8250_port *up = up_to_u8250p(port);
1311 serial8250_rpm_get_tx(up);
1313 if (up->dma && !up->dma->tx_dma(up))
1316 if (!(up->ier & UART_IER_THRI)) {
1317 up->ier |= UART_IER_THRI;
1318 serial_port_out(port, UART_IER, up->ier);
1320 if (up->bugs & UART_BUG_TXEN) {
1322 lsr = serial_in(up, UART_LSR);
1323 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1324 if (lsr & UART_LSR_THRE)
1325 serial8250_tx_chars(up);
1330 * Re-enable the transmitter if we disabled it.
1332 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1333 up->acr &= ~UART_ACR_TXDIS;
1334 serial_icr_write(up, UART_ACR, up->acr);
1338 static void serial8250_throttle(struct uart_port *port)
1340 port->throttle(port);
1343 static void serial8250_unthrottle(struct uart_port *port)
1345 port->unthrottle(port);
1348 static void serial8250_stop_rx(struct uart_port *port)
1350 struct uart_8250_port *up = up_to_u8250p(port);
1352 serial8250_rpm_get(up);
1354 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1355 up->port.read_status_mask &= ~UART_LSR_DR;
1356 serial_port_out(port, UART_IER, up->ier);
1358 serial8250_rpm_put(up);
1361 static void serial8250_disable_ms(struct uart_port *port)
1363 struct uart_8250_port *up =
1364 container_of(port, struct uart_8250_port, port);
1366 /* no MSR capabilities */
1367 if (up->bugs & UART_BUG_NOMSR)
1370 up->ier &= ~UART_IER_MSI;
1371 serial_port_out(port, UART_IER, up->ier);
1374 static void serial8250_enable_ms(struct uart_port *port)
1376 struct uart_8250_port *up = up_to_u8250p(port);
1378 /* no MSR capabilities */
1379 if (up->bugs & UART_BUG_NOMSR)
1382 up->ier |= UART_IER_MSI;
1384 serial8250_rpm_get(up);
1385 serial_port_out(port, UART_IER, up->ier);
1386 serial8250_rpm_put(up);
1390 * serial8250_rx_chars: processes according to the passed in LSR
1391 * value, and returns the remaining LSR bits not handled
1392 * by this Rx routine.
1395 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1397 struct uart_port *port = &up->port;
1399 int max_count = 256;
1403 if (likely(lsr & UART_LSR_DR))
1404 ch = serial_in(up, UART_RX);
1407 * Intel 82571 has a Serial Over Lan device that will
1408 * set UART_LSR_BI without setting UART_LSR_DR when
1409 * it receives a break. To avoid reading from the
1410 * receive buffer without UART_LSR_DR bit set, we
1411 * just force the read character to be 0
1418 lsr |= up->lsr_saved_flags;
1419 up->lsr_saved_flags = 0;
1421 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1422 if (lsr & UART_LSR_BI) {
1423 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1426 * We do the SysRQ and SAK checking
1427 * here because otherwise the break
1428 * may get masked by ignore_status_mask
1429 * or read_status_mask.
1431 if (uart_handle_break(port))
1433 } else if (lsr & UART_LSR_PE)
1434 port->icount.parity++;
1435 else if (lsr & UART_LSR_FE)
1436 port->icount.frame++;
1437 if (lsr & UART_LSR_OE)
1438 port->icount.overrun++;
1441 * Mask off conditions which should be ignored.
1443 lsr &= port->read_status_mask;
1445 if (lsr & UART_LSR_BI) {
1446 DEBUG_INTR("handling break....");
1448 } else if (lsr & UART_LSR_PE)
1450 else if (lsr & UART_LSR_FE)
1453 if (uart_handle_sysrq_char(port, ch))
1456 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1459 lsr = serial_in(up, UART_LSR);
1460 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1461 spin_unlock(&port->lock);
1462 tty_flip_buffer_push(&port->state->port);
1463 spin_lock(&port->lock);
1466 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1468 void serial8250_tx_chars(struct uart_8250_port *up)
1470 struct uart_port *port = &up->port;
1471 struct circ_buf *xmit = &port->state->xmit;
1475 serial_out(up, UART_TX, port->x_char);
1480 if (uart_tx_stopped(port)) {
1481 serial8250_stop_tx(port);
1484 if (uart_circ_empty(xmit)) {
1489 count = up->tx_loadsz;
1491 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1492 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1494 if (uart_circ_empty(xmit))
1496 if (up->capabilities & UART_CAP_HFIFO) {
1497 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1501 } while (--count > 0);
1503 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1504 uart_write_wakeup(port);
1506 DEBUG_INTR("THRE...");
1509 * With RPM enabled, we have to wait until the FIFO is empty before the
1510 * HW can go idle. So we get here once again with empty FIFO and disable
1511 * the interrupt and RPM in __stop_tx()
1513 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1516 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1518 /* Caller holds uart port lock */
1519 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1521 struct uart_port *port = &up->port;
1522 unsigned int status = serial_in(up, UART_MSR);
1524 status |= up->msr_saved_flags;
1525 up->msr_saved_flags = 0;
1526 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1527 port->state != NULL) {
1528 if (status & UART_MSR_TERI)
1530 if (status & UART_MSR_DDSR)
1532 if (status & UART_MSR_DDCD)
1533 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1534 if (status & UART_MSR_DCTS)
1535 uart_handle_cts_change(port, status & UART_MSR_CTS);
1537 wake_up_interruptible(&port->state->port.delta_msr_wait);
1542 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1545 * This handles the interrupt from one port.
1547 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1549 unsigned char status;
1550 unsigned long flags;
1551 struct uart_8250_port *up = up_to_u8250p(port);
1554 if (iir & UART_IIR_NO_INT)
1557 spin_lock_irqsave(&port->lock, flags);
1559 status = serial_port_in(port, UART_LSR);
1561 DEBUG_INTR("status = %x...", status);
1563 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1565 dma_err = up->dma->rx_dma(up, iir);
1567 if (!up->dma || dma_err)
1568 status = serial8250_rx_chars(up, status);
1570 serial8250_modem_status(up);
1571 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1572 (status & UART_LSR_THRE))
1573 serial8250_tx_chars(up);
1575 spin_unlock_irqrestore(&port->lock, flags);
1578 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1580 static int serial8250_default_handle_irq(struct uart_port *port)
1582 struct uart_8250_port *up = up_to_u8250p(port);
1586 serial8250_rpm_get(up);
1588 iir = serial_port_in(port, UART_IIR);
1589 ret = serial8250_handle_irq(port, iir);
1591 serial8250_rpm_put(up);
1596 * These Exar UARTs have an extra interrupt indicator that could
1597 * fire for a few unimplemented interrupts. One of which is a
1598 * wakeup event when coming out of sleep. Put this here just
1599 * to be on the safe side that these interrupts don't go unhandled.
1601 static int exar_handle_irq(struct uart_port *port)
1603 unsigned char int0, int1, int2, int3;
1604 unsigned int iir = serial_port_in(port, UART_IIR);
1607 ret = serial8250_handle_irq(port, iir);
1609 if ((port->type == PORT_XR17V35X) ||
1610 (port->type == PORT_XR17D15X)) {
1611 int0 = serial_port_in(port, 0x80);
1612 int1 = serial_port_in(port, 0x81);
1613 int2 = serial_port_in(port, 0x82);
1614 int3 = serial_port_in(port, 0x83);
1620 static unsigned int serial8250_tx_empty(struct uart_port *port)
1622 struct uart_8250_port *up = up_to_u8250p(port);
1623 unsigned long flags;
1626 serial8250_rpm_get(up);
1628 spin_lock_irqsave(&port->lock, flags);
1629 lsr = serial_port_in(port, UART_LSR);
1630 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1631 spin_unlock_irqrestore(&port->lock, flags);
1633 serial8250_rpm_put(up);
1635 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1638 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1640 struct uart_8250_port *up = up_to_u8250p(port);
1641 unsigned int status;
1644 serial8250_rpm_get(up);
1645 status = serial8250_modem_status(up);
1646 serial8250_rpm_put(up);
1649 if (status & UART_MSR_DCD)
1651 if (status & UART_MSR_RI)
1653 if (status & UART_MSR_DSR)
1655 if (status & UART_MSR_CTS)
1660 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1662 struct uart_8250_port *up = up_to_u8250p(port);
1663 unsigned char mcr = 0;
1665 if (mctrl & TIOCM_RTS)
1666 mcr |= UART_MCR_RTS;
1667 if (mctrl & TIOCM_DTR)
1668 mcr |= UART_MCR_DTR;
1669 if (mctrl & TIOCM_OUT1)
1670 mcr |= UART_MCR_OUT1;
1671 if (mctrl & TIOCM_OUT2)
1672 mcr |= UART_MCR_OUT2;
1673 if (mctrl & TIOCM_LOOP)
1674 mcr |= UART_MCR_LOOP;
1676 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1678 serial_port_out(port, UART_MCR, mcr);
1680 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1682 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1684 if (port->set_mctrl)
1685 port->set_mctrl(port, mctrl);
1687 serial8250_do_set_mctrl(port, mctrl);
1690 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1692 struct uart_8250_port *up = up_to_u8250p(port);
1693 unsigned long flags;
1695 serial8250_rpm_get(up);
1696 spin_lock_irqsave(&port->lock, flags);
1697 if (break_state == -1)
1698 up->lcr |= UART_LCR_SBC;
1700 up->lcr &= ~UART_LCR_SBC;
1701 serial_port_out(port, UART_LCR, up->lcr);
1702 spin_unlock_irqrestore(&port->lock, flags);
1703 serial8250_rpm_put(up);
1707 * Wait for transmitter & holding register to empty
1709 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1711 unsigned int status, tmout = 10000;
1713 /* Wait up to 10ms for the character(s) to be sent. */
1715 status = serial_in(up, UART_LSR);
1717 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1719 if ((status & bits) == bits)
1726 /* Wait up to 1s for flow control if necessary */
1727 if (up->port.flags & UPF_CONS_FLOW) {
1729 for (tmout = 1000000; tmout; tmout--) {
1730 unsigned int msr = serial_in(up, UART_MSR);
1731 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1732 if (msr & UART_MSR_CTS)
1735 touch_nmi_watchdog();
1740 #ifdef CONFIG_CONSOLE_POLL
1742 * Console polling routines for writing and reading from the uart while
1743 * in an interrupt or debug context.
1746 static int serial8250_get_poll_char(struct uart_port *port)
1748 struct uart_8250_port *up = up_to_u8250p(port);
1752 serial8250_rpm_get(up);
1754 lsr = serial_port_in(port, UART_LSR);
1756 if (!(lsr & UART_LSR_DR)) {
1757 status = NO_POLL_CHAR;
1761 status = serial_port_in(port, UART_RX);
1763 serial8250_rpm_put(up);
1768 static void serial8250_put_poll_char(struct uart_port *port,
1772 struct uart_8250_port *up = up_to_u8250p(port);
1774 serial8250_rpm_get(up);
1776 * First save the IER then disable the interrupts
1778 ier = serial_port_in(port, UART_IER);
1779 if (up->capabilities & UART_CAP_UUE)
1780 serial_port_out(port, UART_IER, UART_IER_UUE);
1782 serial_port_out(port, UART_IER, 0);
1784 wait_for_xmitr(up, BOTH_EMPTY);
1786 * Send the character out.
1788 serial_port_out(port, UART_TX, c);
1791 * Finally, wait for transmitter to become empty
1792 * and restore the IER
1794 wait_for_xmitr(up, BOTH_EMPTY);
1795 serial_port_out(port, UART_IER, ier);
1796 serial8250_rpm_put(up);
1799 #endif /* CONFIG_CONSOLE_POLL */
1801 int serial8250_do_startup(struct uart_port *port)
1803 struct uart_8250_port *up = up_to_u8250p(port);
1804 unsigned long flags;
1805 unsigned char lsr, iir;
1808 if (!port->fifosize)
1809 port->fifosize = uart_config[port->type].fifo_size;
1811 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1812 if (!up->capabilities)
1813 up->capabilities = uart_config[port->type].flags;
1816 if (port->iotype != up->cur_iotype)
1817 set_io_from_upio(port);
1819 serial8250_rpm_get(up);
1820 if (port->type == PORT_16C950) {
1821 /* Wake up and initialize UART */
1823 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1824 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1825 serial_port_out(port, UART_IER, 0);
1826 serial_port_out(port, UART_LCR, 0);
1827 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1828 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1829 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1830 serial_port_out(port, UART_LCR, 0);
1833 #ifdef CONFIG_SERIAL_8250_RSA
1835 * If this is an RSA port, see if we can kick it up to the
1836 * higher speed clock.
1841 if (port->type == PORT_XR17V35X) {
1843 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1844 * MCR [7:5] and MSR [7:0]
1846 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1849 * Make sure all interrups are masked until initialization is
1850 * complete and the FIFOs are cleared
1852 serial_port_out(port, UART_IER, 0);
1856 * Clear the FIFO buffers and disable them.
1857 * (they will be reenabled in set_termios())
1859 serial8250_clear_fifos(up);
1862 * Clear the interrupt registers.
1864 serial_port_in(port, UART_LSR);
1865 serial_port_in(port, UART_RX);
1866 serial_port_in(port, UART_IIR);
1867 serial_port_in(port, UART_MSR);
1870 * At this point, there's no way the LSR could still be 0xff;
1871 * if it is, then bail out, because there's likely no UART
1874 if (!(port->flags & UPF_BUGGY_UART) &&
1875 (serial_port_in(port, UART_LSR) == 0xff)) {
1876 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1877 serial_index(port));
1883 * For a XR16C850, we need to set the trigger levels
1885 if (port->type == PORT_16850) {
1888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1890 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1891 serial_port_out(port, UART_FCTR,
1892 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1893 serial_port_out(port, UART_TRG, UART_TRG_96);
1894 serial_port_out(port, UART_FCTR,
1895 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1896 serial_port_out(port, UART_TRG, UART_TRG_96);
1898 serial_port_out(port, UART_LCR, 0);
1904 * Test for UARTs that do not reassert THRE when the
1905 * transmitter is idle and the interrupt has already
1906 * been cleared. Real 16550s should always reassert
1907 * this interrupt whenever the transmitter is idle and
1908 * the interrupt is enabled. Delays are necessary to
1909 * allow register changes to become visible.
1911 spin_lock_irqsave(&port->lock, flags);
1912 if (up->port.irqflags & IRQF_SHARED)
1913 disable_irq_nosync(port->irq);
1915 wait_for_xmitr(up, UART_LSR_THRE);
1916 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1917 udelay(1); /* allow THRE to set */
1918 iir1 = serial_port_in(port, UART_IIR);
1919 serial_port_out(port, UART_IER, 0);
1920 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1921 udelay(1); /* allow a working UART time to re-assert THRE */
1922 iir = serial_port_in(port, UART_IIR);
1923 serial_port_out(port, UART_IER, 0);
1925 if (port->irqflags & IRQF_SHARED)
1926 enable_irq(port->irq);
1927 spin_unlock_irqrestore(&port->lock, flags);
1930 * If the interrupt is not reasserted, or we otherwise
1931 * don't trust the iir, setup a timer to kick the UART
1932 * on a regular basis.
1934 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1935 up->port.flags & UPF_BUG_THRE) {
1936 up->bugs |= UART_BUG_THRE;
1940 retval = up->ops->setup_irq(up);
1945 * Now, initialize the UART
1947 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1949 spin_lock_irqsave(&port->lock, flags);
1950 if (up->port.flags & UPF_FOURPORT) {
1952 up->port.mctrl |= TIOCM_OUT1;
1955 * Most PC uarts need OUT2 raised to enable interrupts.
1958 up->port.mctrl |= TIOCM_OUT2;
1960 serial8250_set_mctrl(port, port->mctrl);
1962 /* Serial over Lan (SoL) hack:
1963 Intel 8257x Gigabit ethernet chips have a
1964 16550 emulation, to be used for Serial Over Lan.
1965 Those chips take a longer time than a normal
1966 serial device to signalize that a transmission
1967 data was queued. Due to that, the above test generally
1968 fails. One solution would be to delay the reading of
1969 iir. However, this is not reliable, since the timeout
1970 is variable. So, let's just don't test if we receive
1971 TX irq. This way, we'll never enable UART_BUG_TXEN.
1973 if (up->port.flags & UPF_NO_TXEN_TEST)
1974 goto dont_test_tx_en;
1977 * Do a quick test to see if we receive an
1978 * interrupt when we enable the TX irq.
1980 serial_port_out(port, UART_IER, UART_IER_THRI);
1981 lsr = serial_port_in(port, UART_LSR);
1982 iir = serial_port_in(port, UART_IIR);
1983 serial_port_out(port, UART_IER, 0);
1985 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1986 if (!(up->bugs & UART_BUG_TXEN)) {
1987 up->bugs |= UART_BUG_TXEN;
1988 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1989 serial_index(port));
1992 up->bugs &= ~UART_BUG_TXEN;
1996 spin_unlock_irqrestore(&port->lock, flags);
1999 * Clear the interrupt registers again for luck, and clear the
2000 * saved flags to avoid getting false values from polling
2001 * routines or the previous session.
2003 serial_port_in(port, UART_LSR);
2004 serial_port_in(port, UART_RX);
2005 serial_port_in(port, UART_IIR);
2006 serial_port_in(port, UART_MSR);
2007 up->lsr_saved_flags = 0;
2008 up->msr_saved_flags = 0;
2011 * Request DMA channels for both RX and TX.
2014 retval = serial8250_request_dma(up);
2016 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2017 serial_index(port));
2023 * Set the IER shadow for rx interrupts but defer actual interrupt
2024 * enable until after the FIFOs are enabled; otherwise, an already-
2025 * active sender can swamp the interrupt handler with "too much work".
2027 up->ier = UART_IER_RLSI | UART_IER_RDI;
2029 if (port->flags & UPF_FOURPORT) {
2032 * Enable interrupts on the AST Fourport board
2034 icp = (port->iobase & 0xfe0) | 0x01f;
2040 serial8250_rpm_put(up);
2043 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2045 static int serial8250_startup(struct uart_port *port)
2048 return port->startup(port);
2049 return serial8250_do_startup(port);
2052 void serial8250_do_shutdown(struct uart_port *port)
2054 struct uart_8250_port *up = up_to_u8250p(port);
2055 unsigned long flags;
2057 serial8250_rpm_get(up);
2059 * Disable interrupts from this port
2062 serial_port_out(port, UART_IER, 0);
2065 serial8250_release_dma(up);
2067 spin_lock_irqsave(&port->lock, flags);
2068 if (port->flags & UPF_FOURPORT) {
2069 /* reset interrupts on the AST Fourport board */
2070 inb((port->iobase & 0xfe0) | 0x1f);
2071 port->mctrl |= TIOCM_OUT1;
2073 port->mctrl &= ~TIOCM_OUT2;
2075 serial8250_set_mctrl(port, port->mctrl);
2076 spin_unlock_irqrestore(&port->lock, flags);
2079 * Disable break condition and FIFOs
2081 serial_port_out(port, UART_LCR,
2082 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2083 serial8250_clear_fifos(up);
2085 #ifdef CONFIG_SERIAL_8250_RSA
2087 * Reset the RSA board back to 115kbps compat mode.
2093 * Read data port to reset things, and then unlink from
2096 serial_port_in(port, UART_RX);
2097 serial8250_rpm_put(up);
2099 up->ops->release_irq(up);
2101 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2103 static void serial8250_shutdown(struct uart_port *port)
2106 port->shutdown(port);
2108 serial8250_do_shutdown(port);
2112 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2113 * Calculate divisor with extra 4-bit fractional portion
2115 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2119 struct uart_port *port = &up->port;
2120 unsigned int quot_16;
2122 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2123 *frac = quot_16 & 0x0f;
2125 return quot_16 >> 4;
2128 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2132 struct uart_port *port = &up->port;
2136 * Handle magic divisors for baud rates above baud_base on
2137 * SMSC SuperIO chips.
2140 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2141 baud == (port->uartclk/4))
2143 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2144 baud == (port->uartclk/8))
2146 else if (up->port.type == PORT_XR17V35X)
2147 quot = xr17v35x_get_divisor(up, baud, frac);
2149 quot = uart_get_divisor(port, baud);
2152 * Oxford Semi 952 rev B workaround
2154 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2160 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2165 switch (c_cflag & CSIZE) {
2167 cval = UART_LCR_WLEN5;
2170 cval = UART_LCR_WLEN6;
2173 cval = UART_LCR_WLEN7;
2177 cval = UART_LCR_WLEN8;
2181 if (c_cflag & CSTOPB)
2182 cval |= UART_LCR_STOP;
2183 if (c_cflag & PARENB) {
2184 cval |= UART_LCR_PARITY;
2185 if (up->bugs & UART_BUG_PARITY)
2186 up->fifo_bug = true;
2188 if (!(c_cflag & PARODD))
2189 cval |= UART_LCR_EPAR;
2191 if (c_cflag & CMSPAR)
2192 cval |= UART_LCR_SPAR;
2198 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2199 unsigned int quot, unsigned int quot_frac)
2201 struct uart_8250_port *up = up_to_u8250p(port);
2203 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2204 if (is_omap1510_8250(up)) {
2205 if (baud == 115200) {
2207 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2209 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2213 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2214 * otherwise just set DLAB
2216 if (up->capabilities & UART_NATSEMI)
2217 serial_port_out(port, UART_LCR, 0xe0);
2219 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2221 serial_dl_write(up, quot);
2223 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2224 if (up->port.type == PORT_XR17V35X)
2225 serial_port_out(port, 0x2, quot_frac);
2229 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2230 struct ktermios *old)
2232 struct uart_8250_port *up = up_to_u8250p(port);
2234 unsigned long flags;
2235 unsigned int baud, quot, frac = 0;
2237 cval = serial8250_compute_lcr(up, termios->c_cflag);
2240 * Ask the core to calculate the divisor for us.
2242 baud = uart_get_baud_rate(port, termios, old,
2243 port->uartclk / 16 / 0xffff,
2244 port->uartclk / 16);
2245 quot = serial8250_get_divisor(up, baud, &frac);
2248 * Ok, we're now changing the port state. Do it with
2249 * interrupts disabled.
2251 serial8250_rpm_get(up);
2252 spin_lock_irqsave(&port->lock, flags);
2254 up->lcr = cval; /* Save computed LCR */
2256 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2257 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2258 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2259 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2260 up->fcr |= UART_FCR_TRIGGER_1;
2265 * MCR-based auto flow control. When AFE is enabled, RTS will be
2266 * deasserted when the receive FIFO contains more characters than
2267 * the trigger, or the MCR RTS bit is cleared. In the case where
2268 * the remote UART is not using CTS auto flow control, we must
2269 * have sufficient FIFO entries for the latency of the remote
2270 * UART to respond. IOW, at least 32 bytes of FIFO.
2272 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2273 up->mcr &= ~UART_MCR_AFE;
2274 if (termios->c_cflag & CRTSCTS)
2275 up->mcr |= UART_MCR_AFE;
2279 * Update the per-port timeout.
2281 uart_update_timeout(port, termios->c_cflag, baud);
2283 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2284 if (termios->c_iflag & INPCK)
2285 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2286 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2287 port->read_status_mask |= UART_LSR_BI;
2290 * Characteres to ignore
2292 port->ignore_status_mask = 0;
2293 if (termios->c_iflag & IGNPAR)
2294 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2295 if (termios->c_iflag & IGNBRK) {
2296 port->ignore_status_mask |= UART_LSR_BI;
2298 * If we're ignoring parity and break indicators,
2299 * ignore overruns too (for real raw support).
2301 if (termios->c_iflag & IGNPAR)
2302 port->ignore_status_mask |= UART_LSR_OE;
2306 * ignore all characters if CREAD is not set
2308 if ((termios->c_cflag & CREAD) == 0)
2309 port->ignore_status_mask |= UART_LSR_DR;
2312 * CTS flow control flag and modem status interrupts
2314 up->ier &= ~UART_IER_MSI;
2315 if (!(up->bugs & UART_BUG_NOMSR) &&
2316 UART_ENABLE_MS(&up->port, termios->c_cflag))
2317 up->ier |= UART_IER_MSI;
2318 if (up->capabilities & UART_CAP_UUE)
2319 up->ier |= UART_IER_UUE;
2320 if (up->capabilities & UART_CAP_RTOIE)
2321 up->ier |= UART_IER_RTOIE;
2323 serial_port_out(port, UART_IER, up->ier);
2325 if (up->capabilities & UART_CAP_EFR) {
2326 unsigned char efr = 0;
2328 * TI16C752/Startech hardware flow control. FIXME:
2329 * - TI16C752 requires control thresholds to be set.
2330 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2332 if (termios->c_cflag & CRTSCTS)
2333 efr |= UART_EFR_CTS;
2335 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2336 if (port->flags & UPF_EXAR_EFR)
2337 serial_port_out(port, UART_XR_EFR, efr);
2339 serial_port_out(port, UART_EFR, efr);
2342 serial8250_set_divisor(port, baud, quot, frac);
2345 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2346 * is written without DLAB set, this mode will be disabled.
2348 if (port->type == PORT_16750)
2349 serial_port_out(port, UART_FCR, up->fcr);
2351 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2352 if (port->type != PORT_16750) {
2353 /* emulated UARTs (Lucent Venus 167x) need two steps */
2354 if (up->fcr & UART_FCR_ENABLE_FIFO)
2355 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2356 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2358 serial8250_set_mctrl(port, port->mctrl);
2359 spin_unlock_irqrestore(&port->lock, flags);
2360 serial8250_rpm_put(up);
2362 /* Don't rewrite B0 */
2363 if (tty_termios_baud_rate(termios))
2364 tty_termios_encode_baud_rate(termios, baud, baud);
2366 EXPORT_SYMBOL(serial8250_do_set_termios);
2369 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2370 struct ktermios *old)
2372 if (port->set_termios)
2373 port->set_termios(port, termios, old);
2375 serial8250_do_set_termios(port, termios, old);
2379 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2381 if (termios->c_line == N_PPS) {
2382 port->flags |= UPF_HARDPPS_CD;
2383 spin_lock_irq(&port->lock);
2384 serial8250_enable_ms(port);
2385 spin_unlock_irq(&port->lock);
2387 port->flags &= ~UPF_HARDPPS_CD;
2388 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2389 spin_lock_irq(&port->lock);
2390 serial8250_disable_ms(port);
2391 spin_unlock_irq(&port->lock);
2397 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2398 unsigned int oldstate)
2400 struct uart_8250_port *p = up_to_u8250p(port);
2402 serial8250_set_sleep(p, state != 0);
2404 EXPORT_SYMBOL(serial8250_do_pm);
2407 serial8250_pm(struct uart_port *port, unsigned int state,
2408 unsigned int oldstate)
2411 port->pm(port, state, oldstate);
2413 serial8250_do_pm(port, state, oldstate);
2416 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2418 if (pt->port.mapsize)
2419 return pt->port.mapsize;
2420 if (pt->port.iotype == UPIO_AU) {
2421 if (pt->port.type == PORT_RT2880)
2425 if (is_omap1_8250(pt))
2426 return 0x16 << pt->port.regshift;
2428 return 8 << pt->port.regshift;
2432 * Resource handling.
2434 static int serial8250_request_std_resource(struct uart_8250_port *up)
2436 unsigned int size = serial8250_port_size(up);
2437 struct uart_port *port = &up->port;
2440 switch (port->iotype) {
2449 if (!request_mem_region(port->mapbase, size, "serial")) {
2454 if (port->flags & UPF_IOREMAP) {
2455 port->membase = ioremap_nocache(port->mapbase, size);
2456 if (!port->membase) {
2457 release_mem_region(port->mapbase, size);
2465 if (!request_region(port->iobase, size, "serial"))
2472 static void serial8250_release_std_resource(struct uart_8250_port *up)
2474 unsigned int size = serial8250_port_size(up);
2475 struct uart_port *port = &up->port;
2477 switch (port->iotype) {
2486 if (port->flags & UPF_IOREMAP) {
2487 iounmap(port->membase);
2488 port->membase = NULL;
2491 release_mem_region(port->mapbase, size);
2496 release_region(port->iobase, size);
2501 static void serial8250_release_port(struct uart_port *port)
2503 struct uart_8250_port *up = up_to_u8250p(port);
2505 serial8250_release_std_resource(up);
2508 static int serial8250_request_port(struct uart_port *port)
2510 struct uart_8250_port *up = up_to_u8250p(port);
2512 return serial8250_request_std_resource(up);
2515 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2517 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2518 unsigned char bytes;
2520 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2522 return bytes ? bytes : -EOPNOTSUPP;
2525 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2527 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2530 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2533 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2534 if (bytes < conf_type->rxtrig_bytes[i])
2535 /* Use the nearest lower value */
2536 return (--i) << UART_FCR_R_TRIG_SHIFT;
2539 return UART_FCR_R_TRIG_11;
2542 static int do_get_rxtrig(struct tty_port *port)
2544 struct uart_state *state = container_of(port, struct uart_state, port);
2545 struct uart_port *uport = state->uart_port;
2546 struct uart_8250_port *up =
2547 container_of(uport, struct uart_8250_port, port);
2549 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2552 return fcr_get_rxtrig_bytes(up);
2555 static int do_serial8250_get_rxtrig(struct tty_port *port)
2559 mutex_lock(&port->mutex);
2560 rxtrig_bytes = do_get_rxtrig(port);
2561 mutex_unlock(&port->mutex);
2563 return rxtrig_bytes;
2566 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2567 struct device_attribute *attr, char *buf)
2569 struct tty_port *port = dev_get_drvdata(dev);
2572 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2573 if (rxtrig_bytes < 0)
2574 return rxtrig_bytes;
2576 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2579 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2581 struct uart_state *state = container_of(port, struct uart_state, port);
2582 struct uart_port *uport = state->uart_port;
2583 struct uart_8250_port *up =
2584 container_of(uport, struct uart_8250_port, port);
2587 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2591 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2595 serial8250_clear_fifos(up);
2596 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2597 up->fcr |= (unsigned char)rxtrig;
2598 serial_out(up, UART_FCR, up->fcr);
2602 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2606 mutex_lock(&port->mutex);
2607 ret = do_set_rxtrig(port, bytes);
2608 mutex_unlock(&port->mutex);
2613 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2614 struct device_attribute *attr, const char *buf, size_t count)
2616 struct tty_port *port = dev_get_drvdata(dev);
2617 unsigned char bytes;
2623 ret = kstrtou8(buf, 10, &bytes);
2627 ret = do_serial8250_set_rxtrig(port, bytes);
2634 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2635 serial8250_get_attr_rx_trig_bytes,
2636 serial8250_set_attr_rx_trig_bytes);
2638 static struct attribute *serial8250_dev_attrs[] = {
2639 &dev_attr_rx_trig_bytes.attr,
2643 static struct attribute_group serial8250_dev_attr_group = {
2644 .attrs = serial8250_dev_attrs,
2647 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2649 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2651 if (conf_type->rxtrig_bytes[0])
2652 up->port.attr_group = &serial8250_dev_attr_group;
2655 static void serial8250_config_port(struct uart_port *port, int flags)
2657 struct uart_8250_port *up = up_to_u8250p(port);
2661 * Find the region that we can probe for. This in turn
2662 * tells us whether we can probe for the type of port.
2664 ret = serial8250_request_std_resource(up);
2668 if (port->iotype != up->cur_iotype)
2669 set_io_from_upio(port);
2671 if (flags & UART_CONFIG_TYPE)
2674 /* if access method is AU, it is a 16550 with a quirk */
2675 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2676 up->bugs |= UART_BUG_NOMSR;
2678 /* HW bugs may trigger IRQ while IIR == NO_INT */
2679 if (port->type == PORT_TEGRA)
2680 up->bugs |= UART_BUG_NOMSR;
2682 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2685 if (port->type == PORT_UNKNOWN)
2686 serial8250_release_std_resource(up);
2688 /* Fixme: probably not the best place for this */
2689 if ((port->type == PORT_XR17V35X) ||
2690 (port->type == PORT_XR17D15X))
2691 port->handle_irq = exar_handle_irq;
2693 register_dev_spec_attr_grp(up);
2694 up->fcr = uart_config[up->port.type].fcr;
2698 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2700 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2701 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2702 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2703 ser->type == PORT_STARTECH)
2709 serial8250_type(struct uart_port *port)
2711 int type = port->type;
2713 if (type >= ARRAY_SIZE(uart_config))
2715 return uart_config[type].name;
2718 static const struct uart_ops serial8250_pops = {
2719 .tx_empty = serial8250_tx_empty,
2720 .set_mctrl = serial8250_set_mctrl,
2721 .get_mctrl = serial8250_get_mctrl,
2722 .stop_tx = serial8250_stop_tx,
2723 .start_tx = serial8250_start_tx,
2724 .throttle = serial8250_throttle,
2725 .unthrottle = serial8250_unthrottle,
2726 .stop_rx = serial8250_stop_rx,
2727 .enable_ms = serial8250_enable_ms,
2728 .break_ctl = serial8250_break_ctl,
2729 .startup = serial8250_startup,
2730 .shutdown = serial8250_shutdown,
2731 .set_termios = serial8250_set_termios,
2732 .set_ldisc = serial8250_set_ldisc,
2733 .pm = serial8250_pm,
2734 .type = serial8250_type,
2735 .release_port = serial8250_release_port,
2736 .request_port = serial8250_request_port,
2737 .config_port = serial8250_config_port,
2738 .verify_port = serial8250_verify_port,
2739 #ifdef CONFIG_CONSOLE_POLL
2740 .poll_get_char = serial8250_get_poll_char,
2741 .poll_put_char = serial8250_put_poll_char,
2745 void serial8250_init_port(struct uart_8250_port *up)
2747 struct uart_port *port = &up->port;
2749 spin_lock_init(&port->lock);
2750 port->ops = &serial8250_pops;
2752 up->cur_iotype = 0xFF;
2754 EXPORT_SYMBOL_GPL(serial8250_init_port);
2756 void serial8250_set_defaults(struct uart_8250_port *up)
2758 struct uart_port *port = &up->port;
2760 if (up->port.flags & UPF_FIXED_TYPE) {
2761 unsigned int type = up->port.type;
2763 if (!up->port.fifosize)
2764 up->port.fifosize = uart_config[type].fifo_size;
2766 up->tx_loadsz = uart_config[type].tx_loadsz;
2767 if (!up->capabilities)
2768 up->capabilities = uart_config[type].flags;
2771 set_io_from_upio(port);
2773 /* default dma handlers */
2775 if (!up->dma->tx_dma)
2776 up->dma->tx_dma = serial8250_tx_dma;
2777 if (!up->dma->rx_dma)
2778 up->dma->rx_dma = serial8250_rx_dma;
2781 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2783 #ifdef CONFIG_SERIAL_8250_CONSOLE
2785 static void serial8250_console_putchar(struct uart_port *port, int ch)
2787 struct uart_8250_port *up = up_to_u8250p(port);
2789 wait_for_xmitr(up, UART_LSR_THRE);
2790 serial_port_out(port, UART_TX, ch);
2794 * Print a string to the serial port trying not to disturb
2795 * any possible real use of the port...
2797 * The console_lock must be held when we get here.
2799 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2802 struct uart_port *port = &up->port;
2803 unsigned long flags;
2807 touch_nmi_watchdog();
2809 serial8250_rpm_get(up);
2813 else if (oops_in_progress)
2814 locked = spin_trylock_irqsave(&port->lock, flags);
2816 spin_lock_irqsave(&port->lock, flags);
2819 * First save the IER then disable the interrupts
2821 ier = serial_port_in(port, UART_IER);
2823 if (up->capabilities & UART_CAP_UUE)
2824 serial_port_out(port, UART_IER, UART_IER_UUE);
2826 serial_port_out(port, UART_IER, 0);
2828 /* check scratch reg to see if port powered off during system sleep */
2829 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2830 struct ktermios termios;
2831 unsigned int baud, quot, frac = 0;
2833 termios.c_cflag = port->cons->cflag;
2834 if (port->state->port.tty && termios.c_cflag == 0)
2835 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2837 baud = uart_get_baud_rate(port, &termios, NULL,
2838 port->uartclk / 16 / 0xffff,
2839 port->uartclk / 16);
2840 quot = serial8250_get_divisor(up, baud, &frac);
2842 serial8250_set_divisor(port, baud, quot, frac);
2843 serial_port_out(port, UART_LCR, up->lcr);
2844 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2849 uart_console_write(port, s, count, serial8250_console_putchar);
2852 * Finally, wait for transmitter to become empty
2853 * and restore the IER
2855 wait_for_xmitr(up, BOTH_EMPTY);
2856 serial_port_out(port, UART_IER, ier);
2859 * The receive handling will happen properly because the
2860 * receive ready bit will still be set; it is not cleared
2861 * on read. However, modem control will not, we must
2862 * call it if we have saved something in the saved flags
2863 * while processing with interrupts off.
2865 if (up->msr_saved_flags)
2866 serial8250_modem_status(up);
2869 spin_unlock_irqrestore(&port->lock, flags);
2870 serial8250_rpm_put(up);
2873 static unsigned int probe_baud(struct uart_port *port)
2875 unsigned char lcr, dll, dlm;
2878 lcr = serial_port_in(port, UART_LCR);
2879 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2880 dll = serial_port_in(port, UART_DLL);
2881 dlm = serial_port_in(port, UART_DLM);
2882 serial_port_out(port, UART_LCR, lcr);
2884 quot = (dlm << 8) | dll;
2885 return (port->uartclk / 16) / quot;
2888 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2895 if (!port->iobase && !port->membase)
2899 uart_parse_options(options, &baud, &parity, &bits, &flow);
2901 baud = probe_baud(port);
2903 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2906 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2908 MODULE_LICENSE("GPL");