2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * A note about mapbase / membase
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/ratelimit.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_reg.h>
37 #include <linux/serial_core.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/nmi.h>
41 #include <linux/mutex.h>
42 #include <linux/slab.h>
55 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
56 * is unsafe when used on edge-triggered interrupts.
58 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
60 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
62 static struct uart_driver serial8250_reg;
64 static int serial_index(struct uart_port *port)
66 return (serial8250_reg.minor - 64) + port->line;
69 static unsigned int skip_txen_test; /* force skip of txen test at init time */
75 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
77 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
81 #define DEBUG_INTR(fmt...) printk(fmt)
83 #define DEBUG_INTR(fmt...) do { } while (0)
86 #define PASS_LIMIT 256
88 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
92 * We default to IRQ0 for the "no irq" hack. Some
93 * machine types want others as well - they're free
94 * to redefine this in their header file.
96 #define is_real_interrupt(irq) ((irq) != 0)
98 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
99 #define CONFIG_SERIAL_DETECT_IRQ 1
101 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
102 #define CONFIG_SERIAL_MANY_PORTS 1
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
109 #define CONFIG_HUB6 1
111 #include <asm/serial.h>
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
117 #ifndef SERIAL_PORT_DFNS
118 #define SERIAL_PORT_DFNS
121 static const struct old_serial_port old_serial_port[] = {
122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
125 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
127 #ifdef CONFIG_SERIAL_8250_RSA
129 #define PORT_RSA_MAX 4
130 static unsigned long probe_rsa[PORT_RSA_MAX];
131 static unsigned int probe_rsa_count;
132 #endif /* CONFIG_SERIAL_8250_RSA */
134 struct uart_8250_port {
135 struct uart_port port;
136 struct timer_list timer; /* "no irq" timer */
137 struct list_head list; /* ports on this IRQ */
138 unsigned short capabilities; /* port capabilities */
139 unsigned short bugs; /* port bugs */
140 unsigned int tx_loadsz; /* transmit fifo load size */
145 unsigned char mcr_mask; /* mask of user bits */
146 unsigned char mcr_force; /* mask of forced bits */
147 unsigned char cur_iotype; /* Running I/O type */
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read but the bits will not
152 * be immediately processed.
154 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
155 unsigned char lsr_saved_flags;
156 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
157 unsigned char msr_saved_flags;
161 struct hlist_node node;
163 spinlock_t lock; /* Protects list not the hash */
164 struct list_head *head;
167 #define NR_IRQ_HASH 32 /* Can be adjusted later */
168 static struct hlist_head irq_lists[NR_IRQ_HASH];
169 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
172 * Here we define the default xmit fifo size used for each type of UART.
174 static const struct serial8250_config uart_config[] = {
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO,
211 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
227 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
235 .name = "16C950/954",
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
240 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
248 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
262 .flags = UART_CAP_FIFO,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .flags = UART_CAP_FIFO | UART_NATSEMI,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_UUE,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO,
289 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
290 .flags = UART_CAP_FIFO,
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
297 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
304 .flags = UART_CAP_FIFO | UART_CAP_AFE,
308 #if defined(CONFIG_MIPS_ALCHEMY)
310 /* Au1x00 UART hardware has a weird register layout */
311 static const u8 au_io_in_map[] = {
321 static const u8 au_io_out_map[] = {
329 /* sane hardware needs no mapping */
330 static inline int map_8250_in_reg(struct uart_port *p, int offset)
332 if (p->iotype != UPIO_AU)
334 return au_io_in_map[offset];
337 static inline int map_8250_out_reg(struct uart_port *p, int offset)
339 if (p->iotype != UPIO_AU)
341 return au_io_out_map[offset];
344 #elif defined(CONFIG_SERIAL_8250_RM9K)
368 static inline int map_8250_in_reg(struct uart_port *p, int offset)
370 if (p->iotype != UPIO_RM9000)
372 return regmap_in[offset];
375 static inline int map_8250_out_reg(struct uart_port *p, int offset)
377 if (p->iotype != UPIO_RM9000)
379 return regmap_out[offset];
384 /* sane hardware needs no mapping */
385 #define map_8250_in_reg(up, offset) (offset)
386 #define map_8250_out_reg(up, offset) (offset)
390 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
392 offset = map_8250_in_reg(p, offset) << p->regshift;
393 outb(p->hub6 - 1 + offset, p->iobase);
394 return inb(p->iobase + 1);
397 static void hub6_serial_out(struct uart_port *p, int offset, int value)
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 outb(p->hub6 - 1 + offset, p->iobase);
401 outb(value, p->iobase + 1);
404 static unsigned int mem_serial_in(struct uart_port *p, int offset)
406 offset = map_8250_in_reg(p, offset) << p->regshift;
407 return readb(p->membase + offset);
410 static void mem_serial_out(struct uart_port *p, int offset, int value)
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 writeb(value, p->membase + offset);
416 static void mem32_serial_out(struct uart_port *p, int offset, int value)
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writel(value, p->membase + offset);
422 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
424 offset = map_8250_in_reg(p, offset) << p->regshift;
425 return readl(p->membase + offset);
428 static unsigned int au_serial_in(struct uart_port *p, int offset)
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return __raw_readl(p->membase + offset);
434 static void au_serial_out(struct uart_port *p, int offset, int value)
436 offset = map_8250_out_reg(p, offset) << p->regshift;
437 __raw_writel(value, p->membase + offset);
440 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 if (offset == UART_IIR) {
445 tmp = readl(p->membase + (UART_IIR & ~3));
446 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
448 return readb(p->membase + offset);
451 static void tsi_serial_out(struct uart_port *p, int offset, int value)
453 offset = map_8250_out_reg(p, offset) << p->regshift;
454 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
455 writeb(value, p->membase + offset);
458 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
459 static inline void dwapb_save_out_value(struct uart_port *p, int offset,
462 struct uart_8250_port *up =
463 container_of(p, struct uart_8250_port, port);
465 if (offset == UART_LCR)
469 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */
470 static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
472 if (offset == UART_TX || offset == UART_IER)
473 p->serial_in(p, UART_IER);
476 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
478 int save_offset = offset;
479 offset = map_8250_out_reg(p, offset) << p->regshift;
480 dwapb_save_out_value(p, save_offset, value);
481 writeb(value, p->membase + offset);
482 dwapb_check_clear_ier(p, save_offset);
485 static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
487 int save_offset = offset;
488 offset = map_8250_out_reg(p, offset) << p->regshift;
489 dwapb_save_out_value(p, save_offset, value);
490 writel(value, p->membase + offset);
491 dwapb_check_clear_ier(p, save_offset);
494 static unsigned int io_serial_in(struct uart_port *p, int offset)
496 offset = map_8250_in_reg(p, offset) << p->regshift;
497 return inb(p->iobase + offset);
500 static void io_serial_out(struct uart_port *p, int offset, int value)
502 offset = map_8250_out_reg(p, offset) << p->regshift;
503 outb(value, p->iobase + offset);
506 static void set_io_from_upio(struct uart_port *p)
508 struct uart_8250_port *up =
509 container_of(p, struct uart_8250_port, port);
512 p->serial_in = hub6_serial_in;
513 p->serial_out = hub6_serial_out;
517 p->serial_in = mem_serial_in;
518 p->serial_out = mem_serial_out;
523 p->serial_in = mem32_serial_in;
524 p->serial_out = mem32_serial_out;
528 p->serial_in = au_serial_in;
529 p->serial_out = au_serial_out;
533 p->serial_in = tsi_serial_in;
534 p->serial_out = tsi_serial_out;
538 p->serial_in = mem_serial_in;
539 p->serial_out = dwapb_serial_out;
543 p->serial_in = mem32_serial_in;
544 p->serial_out = dwapb32_serial_out;
548 p->serial_in = io_serial_in;
549 p->serial_out = io_serial_out;
552 /* Remember loaded iotype */
553 up->cur_iotype = p->iotype;
557 serial_out_sync(struct uart_8250_port *up, int offset, int value)
559 struct uart_port *p = &up->port;
566 p->serial_out(p, offset, value);
567 p->serial_in(p, UART_LCR); /* safe, no side-effects */
570 p->serial_out(p, offset, value);
574 #define serial_in(up, offset) \
575 (up->port.serial_in(&(up)->port, (offset)))
576 #define serial_out(up, offset, value) \
577 (up->port.serial_out(&(up)->port, (offset), (value)))
579 * We used to support using pause I/O for certain machines. We
580 * haven't supported this for a while, but just in case it's badly
581 * needed for certain old 386 machines, I've left these #define's
584 #define serial_inp(up, offset) serial_in(up, offset)
585 #define serial_outp(up, offset, value) serial_out(up, offset, value)
587 /* Uart divisor latch read */
588 static inline int _serial_dl_read(struct uart_8250_port *up)
590 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
593 /* Uart divisor latch write */
594 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
596 serial_outp(up, UART_DLL, value & 0xff);
597 serial_outp(up, UART_DLM, value >> 8 & 0xff);
600 #if defined(CONFIG_MIPS_ALCHEMY)
601 /* Au1x00 haven't got a standard divisor latch */
602 static int serial_dl_read(struct uart_8250_port *up)
604 if (up->port.iotype == UPIO_AU)
605 return __raw_readl(up->port.membase + 0x28);
607 return _serial_dl_read(up);
610 static void serial_dl_write(struct uart_8250_port *up, int value)
612 if (up->port.iotype == UPIO_AU)
613 __raw_writel(value, up->port.membase + 0x28);
615 _serial_dl_write(up, value);
617 #elif defined(CONFIG_SERIAL_8250_RM9K)
618 static int serial_dl_read(struct uart_8250_port *up)
620 return (up->port.iotype == UPIO_RM9000) ?
621 (((__raw_readl(up->port.membase + 0x10) << 8) |
622 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
626 static void serial_dl_write(struct uart_8250_port *up, int value)
628 if (up->port.iotype == UPIO_RM9000) {
629 __raw_writel(value, up->port.membase + 0x08);
630 __raw_writel(value >> 8, up->port.membase + 0x10);
632 _serial_dl_write(up, value);
636 #define serial_dl_read(up) _serial_dl_read(up)
637 #define serial_dl_write(up, value) _serial_dl_write(up, value)
643 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
645 serial_out(up, UART_SCR, offset);
646 serial_out(up, UART_ICR, value);
649 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
653 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
654 serial_out(up, UART_SCR, offset);
655 value = serial_in(up, UART_ICR);
656 serial_icr_write(up, UART_ACR, up->acr);
664 static void serial8250_clear_fifos(struct uart_8250_port *p)
666 if (p->capabilities & UART_CAP_FIFO) {
667 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
668 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
669 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
670 serial_outp(p, UART_FCR, 0);
675 * IER sleep support. UARTs which have EFRs need the "extended
676 * capability" bit enabled. Note that on XR16C850s, we need to
677 * reset LCR to write to IER.
679 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
681 if (p->capabilities & UART_CAP_SLEEP) {
682 if (p->capabilities & UART_CAP_EFR) {
683 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
684 serial_outp(p, UART_EFR, UART_EFR_ECB);
685 serial_outp(p, UART_LCR, 0);
687 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
688 if (p->capabilities & UART_CAP_EFR) {
689 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
690 serial_outp(p, UART_EFR, 0);
691 serial_outp(p, UART_LCR, 0);
696 #ifdef CONFIG_SERIAL_8250_RSA
698 * Attempts to turn on the RSA FIFO. Returns zero on failure.
699 * We set the port uart clock rate if we succeed.
701 static int __enable_rsa(struct uart_8250_port *up)
706 mode = serial_inp(up, UART_RSA_MSR);
707 result = mode & UART_RSA_MSR_FIFO;
710 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
711 mode = serial_inp(up, UART_RSA_MSR);
712 result = mode & UART_RSA_MSR_FIFO;
716 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
721 static void enable_rsa(struct uart_8250_port *up)
723 if (up->port.type == PORT_RSA) {
724 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
725 spin_lock_irq(&up->port.lock);
727 spin_unlock_irq(&up->port.lock);
729 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
730 serial_outp(up, UART_RSA_FRR, 0);
735 * Attempts to turn off the RSA FIFO. Returns zero on failure.
736 * It is unknown why interrupts were disabled in here. However,
737 * the caller is expected to preserve this behaviour by grabbing
738 * the spinlock before calling this function.
740 static void disable_rsa(struct uart_8250_port *up)
745 if (up->port.type == PORT_RSA &&
746 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
747 spin_lock_irq(&up->port.lock);
749 mode = serial_inp(up, UART_RSA_MSR);
750 result = !(mode & UART_RSA_MSR_FIFO);
753 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
754 mode = serial_inp(up, UART_RSA_MSR);
755 result = !(mode & UART_RSA_MSR_FIFO);
759 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
760 spin_unlock_irq(&up->port.lock);
763 #endif /* CONFIG_SERIAL_8250_RSA */
766 * This is a quickie test to see how big the FIFO is.
767 * It doesn't work at all the time, more's the pity.
769 static int size_fifo(struct uart_8250_port *up)
771 unsigned char old_fcr, old_mcr, old_lcr;
772 unsigned short old_dl;
775 old_lcr = serial_inp(up, UART_LCR);
776 serial_outp(up, UART_LCR, 0);
777 old_fcr = serial_inp(up, UART_FCR);
778 old_mcr = serial_inp(up, UART_MCR);
779 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
780 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
781 serial_outp(up, UART_MCR, UART_MCR_LOOP);
782 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
783 old_dl = serial_dl_read(up);
784 serial_dl_write(up, 0x0001);
785 serial_outp(up, UART_LCR, 0x03);
786 for (count = 0; count < 256; count++)
787 serial_outp(up, UART_TX, count);
788 mdelay(20);/* FIXME - schedule_timeout */
789 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
790 (count < 256); count++)
791 serial_inp(up, UART_RX);
792 serial_outp(up, UART_FCR, old_fcr);
793 serial_outp(up, UART_MCR, old_mcr);
794 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
795 serial_dl_write(up, old_dl);
796 serial_outp(up, UART_LCR, old_lcr);
802 * Read UART ID using the divisor method - set DLL and DLM to zero
803 * and the revision will be in DLL and device type in DLM. We
804 * preserve the device state across this.
806 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
808 unsigned char old_dll, old_dlm, old_lcr;
811 old_lcr = serial_inp(p, UART_LCR);
812 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
814 old_dll = serial_inp(p, UART_DLL);
815 old_dlm = serial_inp(p, UART_DLM);
817 serial_outp(p, UART_DLL, 0);
818 serial_outp(p, UART_DLM, 0);
820 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
822 serial_outp(p, UART_DLL, old_dll);
823 serial_outp(p, UART_DLM, old_dlm);
824 serial_outp(p, UART_LCR, old_lcr);
830 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
831 * When this function is called we know it is at least a StarTech
832 * 16650 V2, but it might be one of several StarTech UARTs, or one of
833 * its clones. (We treat the broken original StarTech 16650 V1 as a
834 * 16550, and why not? Startech doesn't seem to even acknowledge its
837 * What evil have men's minds wrought...
839 static void autoconfig_has_efr(struct uart_8250_port *up)
841 unsigned int id1, id2, id3, rev;
844 * Everything with an EFR has SLEEP
846 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
849 * First we check to see if it's an Oxford Semiconductor UART.
851 * If we have to do this here because some non-National
852 * Semiconductor clone chips lock up if you try writing to the
853 * LSR register (which serial_icr_read does)
857 * Check for Oxford Semiconductor 16C950.
859 * EFR [4] must be set else this test fails.
861 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
862 * claims that it's needed for 952 dual UART's (which are not
863 * recommended for new designs).
866 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
867 serial_out(up, UART_EFR, UART_EFR_ECB);
868 serial_out(up, UART_LCR, 0x00);
869 id1 = serial_icr_read(up, UART_ID1);
870 id2 = serial_icr_read(up, UART_ID2);
871 id3 = serial_icr_read(up, UART_ID3);
872 rev = serial_icr_read(up, UART_REV);
874 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
876 if (id1 == 0x16 && id2 == 0xC9 &&
877 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
878 up->port.type = PORT_16C950;
881 * Enable work around for the Oxford Semiconductor 952 rev B
882 * chip which causes it to seriously miscalculate baud rates
885 if (id3 == 0x52 && rev == 0x01)
886 up->bugs |= UART_BUG_QUOT;
891 * We check for a XR16C850 by setting DLL and DLM to 0, and then
892 * reading back DLL and DLM. The chip type depends on the DLM
894 * 0x10 - XR16C850 and the DLL contains the chip revision.
898 id1 = autoconfig_read_divisor_id(up);
899 DEBUG_AUTOCONF("850id=%04x ", id1);
902 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
903 up->port.type = PORT_16850;
908 * It wasn't an XR16C850.
910 * We distinguish between the '654 and the '650 by counting
911 * how many bytes are in the FIFO. I'm using this for now,
912 * since that's the technique that was sent to me in the
913 * serial driver update, but I'm not convinced this works.
914 * I've had problems doing this in the past. -TYT
916 if (size_fifo(up) == 64)
917 up->port.type = PORT_16654;
919 up->port.type = PORT_16650V2;
923 * We detected a chip without a FIFO. Only two fall into
924 * this category - the original 8250 and the 16450. The
925 * 16450 has a scratch register (accessible with LCR=0)
927 static void autoconfig_8250(struct uart_8250_port *up)
929 unsigned char scratch, status1, status2;
931 up->port.type = PORT_8250;
933 scratch = serial_in(up, UART_SCR);
934 serial_outp(up, UART_SCR, 0xa5);
935 status1 = serial_in(up, UART_SCR);
936 serial_outp(up, UART_SCR, 0x5a);
937 status2 = serial_in(up, UART_SCR);
938 serial_outp(up, UART_SCR, scratch);
940 if (status1 == 0xa5 && status2 == 0x5a)
941 up->port.type = PORT_16450;
944 static int broken_efr(struct uart_8250_port *up)
947 * Exar ST16C2550 "A2" devices incorrectly detect as
948 * having an EFR, and report an ID of 0x0201. See
949 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
951 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
958 * We know that the chip has FIFOs. Does it have an EFR? The
959 * EFR is located in the same register position as the IIR and
960 * we know the top two bits of the IIR are currently set. The
961 * EFR should contain zero. Try to read the EFR.
963 static void autoconfig_16550a(struct uart_8250_port *up)
965 unsigned char status1, status2;
966 unsigned int iersave;
968 up->port.type = PORT_16550A;
969 up->capabilities |= UART_CAP_FIFO;
972 * Check for presence of the EFR when DLAB is set.
973 * Only ST16C650V1 UARTs pass this test.
975 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
976 if (serial_in(up, UART_EFR) == 0) {
977 serial_outp(up, UART_EFR, 0xA8);
978 if (serial_in(up, UART_EFR) != 0) {
979 DEBUG_AUTOCONF("EFRv1 ");
980 up->port.type = PORT_16650;
981 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
983 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
985 serial_outp(up, UART_EFR, 0);
990 * Maybe it requires 0xbf to be written to the LCR.
991 * (other ST16C650V2 UARTs, TI16C752A, etc)
993 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
994 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
995 DEBUG_AUTOCONF("EFRv2 ");
996 autoconfig_has_efr(up);
1001 * Check for a National Semiconductor SuperIO chip.
1002 * Attempt to switch to bank 2, read the value of the LOOP bit
1003 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1004 * switch back to bank 2, read it from EXCR1 again and check
1005 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1007 serial_outp(up, UART_LCR, 0);
1008 status1 = serial_in(up, UART_MCR);
1009 serial_outp(up, UART_LCR, 0xE0);
1010 status2 = serial_in(up, 0x02); /* EXCR1 */
1012 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1013 serial_outp(up, UART_LCR, 0);
1014 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1015 serial_outp(up, UART_LCR, 0xE0);
1016 status2 = serial_in(up, 0x02); /* EXCR1 */
1017 serial_outp(up, UART_LCR, 0);
1018 serial_outp(up, UART_MCR, status1);
1020 if ((status2 ^ status1) & UART_MCR_LOOP) {
1021 unsigned short quot;
1023 serial_outp(up, UART_LCR, 0xE0);
1025 quot = serial_dl_read(up);
1028 status1 = serial_in(up, 0x04); /* EXCR2 */
1029 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1030 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1031 serial_outp(up, 0x04, status1);
1033 serial_dl_write(up, quot);
1035 serial_outp(up, UART_LCR, 0);
1037 up->port.uartclk = 921600*16;
1038 up->port.type = PORT_NS16550A;
1039 up->capabilities |= UART_NATSEMI;
1045 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1046 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1047 * Try setting it with and without DLAB set. Cheap clones
1048 * set bit 5 without DLAB set.
1050 serial_outp(up, UART_LCR, 0);
1051 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1052 status1 = serial_in(up, UART_IIR) >> 5;
1053 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1054 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1055 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1056 status2 = serial_in(up, UART_IIR) >> 5;
1057 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1058 serial_outp(up, UART_LCR, 0);
1060 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1062 if (status1 == 6 && status2 == 7) {
1063 up->port.type = PORT_16750;
1064 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1069 * Try writing and reading the UART_IER_UUE bit (b6).
1070 * If it works, this is probably one of the Xscale platform's
1072 * We're going to explicitly set the UUE bit to 0 before
1073 * trying to write and read a 1 just to make sure it's not
1074 * already a 1 and maybe locked there before we even start start.
1076 iersave = serial_in(up, UART_IER);
1077 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1078 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1080 * OK it's in a known zero state, try writing and reading
1081 * without disturbing the current state of the other bits.
1083 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1084 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1087 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1089 DEBUG_AUTOCONF("Xscale ");
1090 up->port.type = PORT_XSCALE;
1091 up->capabilities |= UART_CAP_UUE;
1096 * If we got here we couldn't force the IER_UUE bit to 0.
1097 * Log it and continue.
1099 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1101 serial_outp(up, UART_IER, iersave);
1104 * We distinguish between 16550A and U6 16550A by counting
1105 * how many bytes are in the FIFO.
1107 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1108 up->port.type = PORT_U6_16550A;
1109 up->capabilities |= UART_CAP_AFE;
1114 * This routine is called by rs_init() to initialize a specific serial
1115 * port. It determines what type of UART chip this serial port is
1116 * using: 8250, 16450, 16550, 16550A. The important question is
1117 * whether or not this UART is a 16550A or not, since this will
1118 * determine whether or not we can use its FIFO features or not.
1120 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1122 unsigned char status1, scratch, scratch2, scratch3;
1123 unsigned char save_lcr, save_mcr;
1124 unsigned long flags;
1126 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1129 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1130 serial_index(&up->port), up->port.iobase, up->port.membase);
1133 * We really do need global IRQs disabled here - we're going to
1134 * be frobbing the chips IRQ enable register to see if it exists.
1136 spin_lock_irqsave(&up->port.lock, flags);
1138 up->capabilities = 0;
1141 if (!(up->port.flags & UPF_BUGGY_UART)) {
1143 * Do a simple existence test first; if we fail this,
1144 * there's no point trying anything else.
1146 * 0x80 is used as a nonsense port to prevent against
1147 * false positives due to ISA bus float. The
1148 * assumption is that 0x80 is a non-existent port;
1149 * which should be safe since include/asm/io.h also
1150 * makes this assumption.
1152 * Note: this is safe as long as MCR bit 4 is clear
1153 * and the device is in "PC" mode.
1155 scratch = serial_inp(up, UART_IER);
1156 serial_outp(up, UART_IER, 0);
1161 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1162 * 16C754B) allow only to modify them if an EFR bit is set.
1164 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1165 serial_outp(up, UART_IER, 0x0F);
1169 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1170 serial_outp(up, UART_IER, scratch);
1171 if (scratch2 != 0 || scratch3 != 0x0F) {
1173 * We failed; there's nothing here
1175 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1176 scratch2, scratch3);
1181 save_mcr = serial_in(up, UART_MCR);
1182 save_lcr = serial_in(up, UART_LCR);
1185 * Check to see if a UART is really there. Certain broken
1186 * internal modems based on the Rockwell chipset fail this
1187 * test, because they apparently don't implement the loopback
1188 * test mode. So this test is skipped on the COM 1 through
1189 * COM 4 ports. This *should* be safe, since no board
1190 * manufacturer would be stupid enough to design a board
1191 * that conflicts with COM 1-4 --- we hope!
1193 if (!(up->port.flags & UPF_SKIP_TEST)) {
1194 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1195 status1 = serial_inp(up, UART_MSR) & 0xF0;
1196 serial_outp(up, UART_MCR, save_mcr);
1197 if (status1 != 0x90) {
1198 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1205 * We're pretty sure there's a port here. Lets find out what
1206 * type of port it is. The IIR top two bits allows us to find
1207 * out if it's 8250 or 16450, 16550, 16550A or later. This
1208 * determines what we test for next.
1210 * We also initialise the EFR (if any) to zero for later. The
1211 * EFR occupies the same register location as the FCR and IIR.
1213 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1214 serial_outp(up, UART_EFR, 0);
1215 serial_outp(up, UART_LCR, 0);
1217 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1218 scratch = serial_in(up, UART_IIR) >> 6;
1220 DEBUG_AUTOCONF("iir=%d ", scratch);
1224 autoconfig_8250(up);
1227 up->port.type = PORT_UNKNOWN;
1230 up->port.type = PORT_16550;
1233 autoconfig_16550a(up);
1237 #ifdef CONFIG_SERIAL_8250_RSA
1239 * Only probe for RSA ports if we got the region.
1241 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1244 for (i = 0 ; i < probe_rsa_count; ++i) {
1245 if (probe_rsa[i] == up->port.iobase &&
1247 up->port.type = PORT_RSA;
1254 serial_outp(up, UART_LCR, save_lcr);
1256 if (up->capabilities != uart_config[up->port.type].flags) {
1258 "ttyS%d: detected caps %08x should be %08x\n",
1259 serial_index(&up->port), up->capabilities,
1260 uart_config[up->port.type].flags);
1263 up->port.fifosize = uart_config[up->port.type].fifo_size;
1264 up->capabilities = uart_config[up->port.type].flags;
1265 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1267 if (up->port.type == PORT_UNKNOWN)
1273 #ifdef CONFIG_SERIAL_8250_RSA
1274 if (up->port.type == PORT_RSA)
1275 serial_outp(up, UART_RSA_FRR, 0);
1277 serial_outp(up, UART_MCR, save_mcr);
1278 serial8250_clear_fifos(up);
1279 serial_in(up, UART_RX);
1280 if (up->capabilities & UART_CAP_UUE)
1281 serial_outp(up, UART_IER, UART_IER_UUE);
1283 serial_outp(up, UART_IER, 0);
1286 spin_unlock_irqrestore(&up->port.lock, flags);
1287 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1290 static void autoconfig_irq(struct uart_8250_port *up)
1292 unsigned char save_mcr, save_ier;
1293 unsigned char save_ICP = 0;
1294 unsigned int ICP = 0;
1298 if (up->port.flags & UPF_FOURPORT) {
1299 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1300 save_ICP = inb_p(ICP);
1305 /* forget possible initially masked and pending IRQ */
1306 probe_irq_off(probe_irq_on());
1307 save_mcr = serial_inp(up, UART_MCR);
1308 save_ier = serial_inp(up, UART_IER);
1309 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1311 irqs = probe_irq_on();
1312 serial_outp(up, UART_MCR, 0);
1314 if (up->port.flags & UPF_FOURPORT) {
1315 serial_outp(up, UART_MCR,
1316 UART_MCR_DTR | UART_MCR_RTS);
1318 serial_outp(up, UART_MCR,
1319 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1321 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1322 (void)serial_inp(up, UART_LSR);
1323 (void)serial_inp(up, UART_RX);
1324 (void)serial_inp(up, UART_IIR);
1325 (void)serial_inp(up, UART_MSR);
1326 serial_outp(up, UART_TX, 0xFF);
1328 irq = probe_irq_off(irqs);
1330 serial_outp(up, UART_MCR, save_mcr);
1331 serial_outp(up, UART_IER, save_ier);
1333 if (up->port.flags & UPF_FOURPORT)
1334 outb_p(save_ICP, ICP);
1336 up->port.irq = (irq > 0) ? irq : 0;
1339 static inline void __stop_tx(struct uart_8250_port *p)
1341 if (p->ier & UART_IER_THRI) {
1342 p->ier &= ~UART_IER_THRI;
1343 serial_out(p, UART_IER, p->ier);
1347 static void serial8250_stop_tx(struct uart_port *port)
1349 struct uart_8250_port *up =
1350 container_of(port, struct uart_8250_port, port);
1355 * We really want to stop the transmitter from sending.
1357 if (up->port.type == PORT_16C950) {
1358 up->acr |= UART_ACR_TXDIS;
1359 serial_icr_write(up, UART_ACR, up->acr);
1363 static void transmit_chars(struct uart_8250_port *up);
1365 static void serial8250_start_tx(struct uart_port *port)
1367 struct uart_8250_port *up =
1368 container_of(port, struct uart_8250_port, port);
1370 if (!(up->ier & UART_IER_THRI)) {
1371 up->ier |= UART_IER_THRI;
1372 serial_out(up, UART_IER, up->ier);
1374 if (up->bugs & UART_BUG_TXEN) {
1376 lsr = serial_in(up, UART_LSR);
1377 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1378 if ((up->port.type == PORT_RM9000) ?
1379 (lsr & UART_LSR_THRE) :
1380 (lsr & UART_LSR_TEMT))
1386 * Re-enable the transmitter if we disabled it.
1388 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1389 up->acr &= ~UART_ACR_TXDIS;
1390 serial_icr_write(up, UART_ACR, up->acr);
1394 static void serial8250_stop_rx(struct uart_port *port)
1396 struct uart_8250_port *up =
1397 container_of(port, struct uart_8250_port, port);
1399 up->ier &= ~UART_IER_RLSI;
1400 up->port.read_status_mask &= ~UART_LSR_DR;
1401 serial_out(up, UART_IER, up->ier);
1404 static void serial8250_enable_ms(struct uart_port *port)
1406 struct uart_8250_port *up =
1407 container_of(port, struct uart_8250_port, port);
1409 /* no MSR capabilities */
1410 if (up->bugs & UART_BUG_NOMSR)
1413 up->ier |= UART_IER_MSI;
1414 serial_out(up, UART_IER, up->ier);
1418 receive_chars(struct uart_8250_port *up, unsigned int *status)
1420 struct tty_struct *tty = up->port.state->port.tty;
1421 unsigned char ch, lsr = *status;
1422 int max_count = 256;
1426 if (likely(lsr & UART_LSR_DR))
1427 ch = serial_inp(up, UART_RX);
1430 * Intel 82571 has a Serial Over Lan device that will
1431 * set UART_LSR_BI without setting UART_LSR_DR when
1432 * it receives a break. To avoid reading from the
1433 * receive buffer without UART_LSR_DR bit set, we
1434 * just force the read character to be 0
1439 up->port.icount.rx++;
1441 lsr |= up->lsr_saved_flags;
1442 up->lsr_saved_flags = 0;
1444 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1446 * For statistics only
1448 if (lsr & UART_LSR_BI) {
1449 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1450 up->port.icount.brk++;
1452 * We do the SysRQ and SAK checking
1453 * here because otherwise the break
1454 * may get masked by ignore_status_mask
1455 * or read_status_mask.
1457 if (uart_handle_break(&up->port))
1459 } else if (lsr & UART_LSR_PE)
1460 up->port.icount.parity++;
1461 else if (lsr & UART_LSR_FE)
1462 up->port.icount.frame++;
1463 if (lsr & UART_LSR_OE)
1464 up->port.icount.overrun++;
1467 * Mask off conditions which should be ignored.
1469 lsr &= up->port.read_status_mask;
1471 if (lsr & UART_LSR_BI) {
1472 DEBUG_INTR("handling break....");
1474 } else if (lsr & UART_LSR_PE)
1476 else if (lsr & UART_LSR_FE)
1479 if (uart_handle_sysrq_char(&up->port, ch))
1482 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1485 lsr = serial_inp(up, UART_LSR);
1486 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1487 spin_unlock(&up->port.lock);
1488 tty_flip_buffer_push(tty);
1489 spin_lock(&up->port.lock);
1493 static void transmit_chars(struct uart_8250_port *up)
1495 struct circ_buf *xmit = &up->port.state->xmit;
1498 if (up->port.x_char) {
1499 serial_outp(up, UART_TX, up->port.x_char);
1500 up->port.icount.tx++;
1501 up->port.x_char = 0;
1504 if (uart_tx_stopped(&up->port)) {
1505 serial8250_stop_tx(&up->port);
1508 if (uart_circ_empty(xmit)) {
1513 count = up->tx_loadsz;
1515 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1516 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1517 up->port.icount.tx++;
1518 if (uart_circ_empty(xmit))
1520 } while (--count > 0);
1522 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1523 uart_write_wakeup(&up->port);
1525 DEBUG_INTR("THRE...");
1527 if (uart_circ_empty(xmit))
1531 static unsigned int check_modem_status(struct uart_8250_port *up)
1533 unsigned int status = serial_in(up, UART_MSR);
1535 status |= up->msr_saved_flags;
1536 up->msr_saved_flags = 0;
1537 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1538 up->port.state != NULL) {
1539 if (status & UART_MSR_TERI)
1540 up->port.icount.rng++;
1541 if (status & UART_MSR_DDSR)
1542 up->port.icount.dsr++;
1543 if (status & UART_MSR_DDCD)
1544 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1545 if (status & UART_MSR_DCTS)
1546 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1548 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1555 * This handles the interrupt from one port.
1557 static void serial8250_handle_port(struct uart_8250_port *up)
1559 unsigned int status;
1560 unsigned long flags;
1562 spin_lock_irqsave(&up->port.lock, flags);
1564 status = serial_inp(up, UART_LSR);
1566 DEBUG_INTR("status = %x...", status);
1568 if (status & (UART_LSR_DR | UART_LSR_BI))
1569 receive_chars(up, &status);
1570 check_modem_status(up);
1571 if (status & UART_LSR_THRE)
1574 spin_unlock_irqrestore(&up->port.lock, flags);
1578 * This is the serial driver's interrupt routine.
1580 * Arjan thinks the old way was overly complex, so it got simplified.
1581 * Alan disagrees, saying that need the complexity to handle the weird
1582 * nature of ISA shared interrupts. (This is a special exception.)
1584 * In order to handle ISA shared interrupts properly, we need to check
1585 * that all ports have been serviced, and therefore the ISA interrupt
1586 * line has been de-asserted.
1588 * This means we need to loop through all ports. checking that they
1589 * don't have an interrupt pending.
1591 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1593 struct irq_info *i = dev_id;
1594 struct list_head *l, *end = NULL;
1595 int pass_counter = 0, handled = 0;
1597 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1599 spin_lock(&i->lock);
1603 struct uart_8250_port *up;
1606 up = list_entry(l, struct uart_8250_port, list);
1608 iir = serial_in(up, UART_IIR);
1609 if (!(iir & UART_IIR_NO_INT)) {
1610 serial8250_handle_port(up);
1615 } else if ((up->port.iotype == UPIO_DWAPB ||
1616 up->port.iotype == UPIO_DWAPB32) &&
1617 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1618 /* The DesignWare APB UART has an Busy Detect (0x07)
1619 * interrupt meaning an LCR write attempt occured while the
1620 * UART was busy. The interrupt must be cleared by reading
1621 * the UART status register (USR) and the LCR re-written. */
1622 unsigned int status;
1623 status = *(volatile u32 *)up->port.private_data;
1624 serial_out(up, UART_LCR, up->lcr);
1629 } else if (end == NULL)
1634 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1635 /* If we hit this, we're dead. */
1636 printk_ratelimited(KERN_ERR
1637 "serial8250: too much work for irq%d\n", irq);
1642 spin_unlock(&i->lock);
1644 DEBUG_INTR("end.\n");
1646 return IRQ_RETVAL(handled);
1650 * To support ISA shared interrupts, we need to have one interrupt
1651 * handler that ensures that the IRQ line has been deasserted
1652 * before returning. Failing to do this will result in the IRQ
1653 * line being stuck active, and, since ISA irqs are edge triggered,
1654 * no more IRQs will be seen.
1656 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1658 spin_lock_irq(&i->lock);
1660 if (!list_empty(i->head)) {
1661 if (i->head == &up->list)
1662 i->head = i->head->next;
1663 list_del(&up->list);
1665 BUG_ON(i->head != &up->list);
1668 spin_unlock_irq(&i->lock);
1669 /* List empty so throw away the hash node */
1670 if (i->head == NULL) {
1671 hlist_del(&i->node);
1676 static int serial_link_irq_chain(struct uart_8250_port *up)
1678 struct hlist_head *h;
1679 struct hlist_node *n;
1681 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1683 mutex_lock(&hash_mutex);
1685 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1687 hlist_for_each(n, h) {
1688 i = hlist_entry(n, struct irq_info, node);
1689 if (i->irq == up->port.irq)
1694 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1696 mutex_unlock(&hash_mutex);
1699 spin_lock_init(&i->lock);
1700 i->irq = up->port.irq;
1701 hlist_add_head(&i->node, h);
1703 mutex_unlock(&hash_mutex);
1705 spin_lock_irq(&i->lock);
1708 list_add(&up->list, i->head);
1709 spin_unlock_irq(&i->lock);
1713 INIT_LIST_HEAD(&up->list);
1714 i->head = &up->list;
1715 spin_unlock_irq(&i->lock);
1716 irq_flags |= up->port.irqflags;
1717 ret = request_irq(up->port.irq, serial8250_interrupt,
1718 irq_flags, "serial", i);
1720 serial_do_unlink(i, up);
1726 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1729 struct hlist_node *n;
1730 struct hlist_head *h;
1732 mutex_lock(&hash_mutex);
1734 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1736 hlist_for_each(n, h) {
1737 i = hlist_entry(n, struct irq_info, node);
1738 if (i->irq == up->port.irq)
1743 BUG_ON(i->head == NULL);
1745 if (list_empty(i->head))
1746 free_irq(up->port.irq, i);
1748 serial_do_unlink(i, up);
1749 mutex_unlock(&hash_mutex);
1753 * This function is used to handle ports that do not have an
1754 * interrupt. This doesn't work very well for 16450's, but gives
1755 * barely passable results for a 16550A. (Although at the expense
1756 * of much CPU overhead).
1758 static void serial8250_timeout(unsigned long data)
1760 struct uart_8250_port *up = (struct uart_8250_port *)data;
1763 iir = serial_in(up, UART_IIR);
1764 if (!(iir & UART_IIR_NO_INT))
1765 serial8250_handle_port(up);
1766 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1769 static void serial8250_backup_timeout(unsigned long data)
1771 struct uart_8250_port *up = (struct uart_8250_port *)data;
1772 unsigned int iir, ier = 0, lsr;
1773 unsigned long flags;
1776 * Must disable interrupts or else we risk racing with the interrupt
1779 if (is_real_interrupt(up->port.irq)) {
1780 ier = serial_in(up, UART_IER);
1781 serial_out(up, UART_IER, 0);
1784 iir = serial_in(up, UART_IIR);
1787 * This should be a safe test for anyone who doesn't trust the
1788 * IIR bits on their UART, but it's specifically designed for
1789 * the "Diva" UART used on the management processor on many HP
1790 * ia64 and parisc boxes.
1792 spin_lock_irqsave(&up->port.lock, flags);
1793 lsr = serial_in(up, UART_LSR);
1794 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1795 spin_unlock_irqrestore(&up->port.lock, flags);
1796 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1797 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1798 (lsr & UART_LSR_THRE)) {
1799 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1800 iir |= UART_IIR_THRI;
1803 if (!(iir & UART_IIR_NO_INT))
1804 serial8250_handle_port(up);
1806 if (is_real_interrupt(up->port.irq))
1807 serial_out(up, UART_IER, ier);
1809 /* Standard timer interval plus 0.2s to keep the port running */
1810 mod_timer(&up->timer,
1811 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1814 static unsigned int serial8250_tx_empty(struct uart_port *port)
1816 struct uart_8250_port *up =
1817 container_of(port, struct uart_8250_port, port);
1818 unsigned long flags;
1821 spin_lock_irqsave(&up->port.lock, flags);
1822 lsr = serial_in(up, UART_LSR);
1823 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1824 spin_unlock_irqrestore(&up->port.lock, flags);
1826 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1829 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1831 struct uart_8250_port *up =
1832 container_of(port, struct uart_8250_port, port);
1833 unsigned int status;
1836 status = check_modem_status(up);
1839 if (status & UART_MSR_DCD)
1841 if (status & UART_MSR_RI)
1843 if (status & UART_MSR_DSR)
1845 if (status & UART_MSR_CTS)
1850 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1852 struct uart_8250_port *up =
1853 container_of(port, struct uart_8250_port, port);
1854 unsigned char mcr = 0;
1856 if (mctrl & TIOCM_RTS)
1857 mcr |= UART_MCR_RTS;
1858 if (mctrl & TIOCM_DTR)
1859 mcr |= UART_MCR_DTR;
1860 if (mctrl & TIOCM_OUT1)
1861 mcr |= UART_MCR_OUT1;
1862 if (mctrl & TIOCM_OUT2)
1863 mcr |= UART_MCR_OUT2;
1864 if (mctrl & TIOCM_LOOP)
1865 mcr |= UART_MCR_LOOP;
1867 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1869 serial_out(up, UART_MCR, mcr);
1872 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1874 struct uart_8250_port *up =
1875 container_of(port, struct uart_8250_port, port);
1876 unsigned long flags;
1878 spin_lock_irqsave(&up->port.lock, flags);
1879 if (break_state == -1)
1880 up->lcr |= UART_LCR_SBC;
1882 up->lcr &= ~UART_LCR_SBC;
1883 serial_out(up, UART_LCR, up->lcr);
1884 spin_unlock_irqrestore(&up->port.lock, flags);
1888 * Wait for transmitter & holding register to empty
1890 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1892 unsigned int status, tmout = 10000;
1894 /* Wait up to 10ms for the character(s) to be sent. */
1896 status = serial_in(up, UART_LSR);
1898 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1900 if ((status & bits) == bits)
1907 /* Wait up to 1s for flow control if necessary */
1908 if (up->port.flags & UPF_CONS_FLOW) {
1910 for (tmout = 1000000; tmout; tmout--) {
1911 unsigned int msr = serial_in(up, UART_MSR);
1912 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1913 if (msr & UART_MSR_CTS)
1916 touch_nmi_watchdog();
1921 #ifdef CONFIG_CONSOLE_POLL
1923 * Console polling routines for writing and reading from the uart while
1924 * in an interrupt or debug context.
1927 static int serial8250_get_poll_char(struct uart_port *port)
1929 struct uart_8250_port *up =
1930 container_of(port, struct uart_8250_port, port);
1931 unsigned char lsr = serial_inp(up, UART_LSR);
1933 if (!(lsr & UART_LSR_DR))
1934 return NO_POLL_CHAR;
1936 return serial_inp(up, UART_RX);
1940 static void serial8250_put_poll_char(struct uart_port *port,
1944 struct uart_8250_port *up =
1945 container_of(port, struct uart_8250_port, port);
1948 * First save the IER then disable the interrupts
1950 ier = serial_in(up, UART_IER);
1951 if (up->capabilities & UART_CAP_UUE)
1952 serial_out(up, UART_IER, UART_IER_UUE);
1954 serial_out(up, UART_IER, 0);
1956 wait_for_xmitr(up, BOTH_EMPTY);
1958 * Send the character out.
1959 * If a LF, also do CR...
1961 serial_out(up, UART_TX, c);
1963 wait_for_xmitr(up, BOTH_EMPTY);
1964 serial_out(up, UART_TX, 13);
1968 * Finally, wait for transmitter to become empty
1969 * and restore the IER
1971 wait_for_xmitr(up, BOTH_EMPTY);
1972 serial_out(up, UART_IER, ier);
1975 #endif /* CONFIG_CONSOLE_POLL */
1977 static int serial8250_startup(struct uart_port *port)
1979 struct uart_8250_port *up =
1980 container_of(port, struct uart_8250_port, port);
1981 unsigned long flags;
1982 unsigned char lsr, iir;
1985 up->port.fifosize = uart_config[up->port.type].fifo_size;
1986 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1987 up->capabilities = uart_config[up->port.type].flags;
1990 if (up->port.iotype != up->cur_iotype)
1991 set_io_from_upio(port);
1993 if (up->port.type == PORT_16C950) {
1994 /* Wake up and initialize UART */
1996 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1997 serial_outp(up, UART_EFR, UART_EFR_ECB);
1998 serial_outp(up, UART_IER, 0);
1999 serial_outp(up, UART_LCR, 0);
2000 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2001 serial_outp(up, UART_LCR, 0xBF);
2002 serial_outp(up, UART_EFR, UART_EFR_ECB);
2003 serial_outp(up, UART_LCR, 0);
2006 #ifdef CONFIG_SERIAL_8250_RSA
2008 * If this is an RSA port, see if we can kick it up to the
2009 * higher speed clock.
2015 * Clear the FIFO buffers and disable them.
2016 * (they will be reenabled in set_termios())
2018 serial8250_clear_fifos(up);
2021 * Clear the interrupt registers.
2023 (void) serial_inp(up, UART_LSR);
2024 (void) serial_inp(up, UART_RX);
2025 (void) serial_inp(up, UART_IIR);
2026 (void) serial_inp(up, UART_MSR);
2029 * At this point, there's no way the LSR could still be 0xff;
2030 * if it is, then bail out, because there's likely no UART
2033 if (!(up->port.flags & UPF_BUGGY_UART) &&
2034 (serial_inp(up, UART_LSR) == 0xff)) {
2035 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2036 serial_index(&up->port));
2041 * For a XR16C850, we need to set the trigger levels
2043 if (up->port.type == PORT_16850) {
2046 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2048 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2049 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2050 serial_outp(up, UART_TRG, UART_TRG_96);
2051 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2052 serial_outp(up, UART_TRG, UART_TRG_96);
2054 serial_outp(up, UART_LCR, 0);
2057 if (is_real_interrupt(up->port.irq)) {
2060 * Test for UARTs that do not reassert THRE when the
2061 * transmitter is idle and the interrupt has already
2062 * been cleared. Real 16550s should always reassert
2063 * this interrupt whenever the transmitter is idle and
2064 * the interrupt is enabled. Delays are necessary to
2065 * allow register changes to become visible.
2067 spin_lock_irqsave(&up->port.lock, flags);
2068 if (up->port.irqflags & IRQF_SHARED)
2069 disable_irq_nosync(up->port.irq);
2071 wait_for_xmitr(up, UART_LSR_THRE);
2072 serial_out_sync(up, UART_IER, UART_IER_THRI);
2073 udelay(1); /* allow THRE to set */
2074 iir1 = serial_in(up, UART_IIR);
2075 serial_out(up, UART_IER, 0);
2076 serial_out_sync(up, UART_IER, UART_IER_THRI);
2077 udelay(1); /* allow a working UART time to re-assert THRE */
2078 iir = serial_in(up, UART_IIR);
2079 serial_out(up, UART_IER, 0);
2081 if (up->port.irqflags & IRQF_SHARED)
2082 enable_irq(up->port.irq);
2083 spin_unlock_irqrestore(&up->port.lock, flags);
2086 * If the interrupt is not reasserted, setup a timer to
2087 * kick the UART on a regular basis.
2089 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2090 up->bugs |= UART_BUG_THRE;
2091 pr_debug("ttyS%d - using backup timer\n",
2092 serial_index(port));
2097 * The above check will only give an accurate result the first time
2098 * the port is opened so this value needs to be preserved.
2100 if (up->bugs & UART_BUG_THRE) {
2101 up->timer.function = serial8250_backup_timeout;
2102 up->timer.data = (unsigned long)up;
2103 mod_timer(&up->timer, jiffies +
2104 uart_poll_timeout(port) + HZ / 5);
2108 * If the "interrupt" for this port doesn't correspond with any
2109 * hardware interrupt, we use a timer-based system. The original
2110 * driver used to do this with IRQ0.
2112 if (!is_real_interrupt(up->port.irq)) {
2113 up->timer.data = (unsigned long)up;
2114 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2116 retval = serial_link_irq_chain(up);
2122 * Now, initialize the UART
2124 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2126 spin_lock_irqsave(&up->port.lock, flags);
2127 if (up->port.flags & UPF_FOURPORT) {
2128 if (!is_real_interrupt(up->port.irq))
2129 up->port.mctrl |= TIOCM_OUT1;
2132 * Most PC uarts need OUT2 raised to enable interrupts.
2134 if (is_real_interrupt(up->port.irq))
2135 up->port.mctrl |= TIOCM_OUT2;
2137 serial8250_set_mctrl(&up->port, up->port.mctrl);
2139 /* Serial over Lan (SoL) hack:
2140 Intel 8257x Gigabit ethernet chips have a
2141 16550 emulation, to be used for Serial Over Lan.
2142 Those chips take a longer time than a normal
2143 serial device to signalize that a transmission
2144 data was queued. Due to that, the above test generally
2145 fails. One solution would be to delay the reading of
2146 iir. However, this is not reliable, since the timeout
2147 is variable. So, let's just don't test if we receive
2148 TX irq. This way, we'll never enable UART_BUG_TXEN.
2150 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2151 goto dont_test_tx_en;
2154 * Do a quick test to see if we receive an
2155 * interrupt when we enable the TX irq.
2157 serial_outp(up, UART_IER, UART_IER_THRI);
2158 lsr = serial_in(up, UART_LSR);
2159 iir = serial_in(up, UART_IIR);
2160 serial_outp(up, UART_IER, 0);
2162 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2163 if (!(up->bugs & UART_BUG_TXEN)) {
2164 up->bugs |= UART_BUG_TXEN;
2165 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2166 serial_index(port));
2169 up->bugs &= ~UART_BUG_TXEN;
2173 spin_unlock_irqrestore(&up->port.lock, flags);
2176 * Clear the interrupt registers again for luck, and clear the
2177 * saved flags to avoid getting false values from polling
2178 * routines or the previous session.
2180 serial_inp(up, UART_LSR);
2181 serial_inp(up, UART_RX);
2182 serial_inp(up, UART_IIR);
2183 serial_inp(up, UART_MSR);
2184 up->lsr_saved_flags = 0;
2185 up->msr_saved_flags = 0;
2188 * Finally, enable interrupts. Note: Modem status interrupts
2189 * are set via set_termios(), which will be occurring imminently
2190 * anyway, so we don't enable them here.
2192 up->ier = UART_IER_RLSI | UART_IER_RDI;
2193 serial_outp(up, UART_IER, up->ier);
2195 if (up->port.flags & UPF_FOURPORT) {
2198 * Enable interrupts on the AST Fourport board
2200 icp = (up->port.iobase & 0xfe0) | 0x01f;
2208 static void serial8250_shutdown(struct uart_port *port)
2210 struct uart_8250_port *up =
2211 container_of(port, struct uart_8250_port, port);
2212 unsigned long flags;
2215 * Disable interrupts from this port
2218 serial_outp(up, UART_IER, 0);
2220 spin_lock_irqsave(&up->port.lock, flags);
2221 if (up->port.flags & UPF_FOURPORT) {
2222 /* reset interrupts on the AST Fourport board */
2223 inb((up->port.iobase & 0xfe0) | 0x1f);
2224 up->port.mctrl |= TIOCM_OUT1;
2226 up->port.mctrl &= ~TIOCM_OUT2;
2228 serial8250_set_mctrl(&up->port, up->port.mctrl);
2229 spin_unlock_irqrestore(&up->port.lock, flags);
2232 * Disable break condition and FIFOs
2234 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2235 serial8250_clear_fifos(up);
2237 #ifdef CONFIG_SERIAL_8250_RSA
2239 * Reset the RSA board back to 115kbps compat mode.
2245 * Read data port to reset things, and then unlink from
2248 (void) serial_in(up, UART_RX);
2250 del_timer_sync(&up->timer);
2251 up->timer.function = serial8250_timeout;
2252 if (is_real_interrupt(up->port.irq))
2253 serial_unlink_irq_chain(up);
2256 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2261 * Handle magic divisors for baud rates above baud_base on
2262 * SMSC SuperIO chips.
2264 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2265 baud == (port->uartclk/4))
2267 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2268 baud == (port->uartclk/8))
2271 quot = uart_get_divisor(port, baud);
2277 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2278 struct ktermios *old)
2280 struct uart_8250_port *up =
2281 container_of(port, struct uart_8250_port, port);
2282 unsigned char cval, fcr = 0;
2283 unsigned long flags;
2284 unsigned int baud, quot;
2286 switch (termios->c_cflag & CSIZE) {
2288 cval = UART_LCR_WLEN5;
2291 cval = UART_LCR_WLEN6;
2294 cval = UART_LCR_WLEN7;
2298 cval = UART_LCR_WLEN8;
2302 if (termios->c_cflag & CSTOPB)
2303 cval |= UART_LCR_STOP;
2304 if (termios->c_cflag & PARENB)
2305 cval |= UART_LCR_PARITY;
2306 if (!(termios->c_cflag & PARODD))
2307 cval |= UART_LCR_EPAR;
2309 if (termios->c_cflag & CMSPAR)
2310 cval |= UART_LCR_SPAR;
2314 * Ask the core to calculate the divisor for us.
2316 baud = uart_get_baud_rate(port, termios, old,
2317 port->uartclk / 16 / 0xffff,
2318 port->uartclk / 16);
2319 quot = serial8250_get_divisor(port, baud);
2322 * Oxford Semi 952 rev B workaround
2324 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2327 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2329 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2331 fcr = uart_config[up->port.type].fcr;
2335 * MCR-based auto flow control. When AFE is enabled, RTS will be
2336 * deasserted when the receive FIFO contains more characters than
2337 * the trigger, or the MCR RTS bit is cleared. In the case where
2338 * the remote UART is not using CTS auto flow control, we must
2339 * have sufficient FIFO entries for the latency of the remote
2340 * UART to respond. IOW, at least 32 bytes of FIFO.
2342 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2343 up->mcr &= ~UART_MCR_AFE;
2344 if (termios->c_cflag & CRTSCTS)
2345 up->mcr |= UART_MCR_AFE;
2349 * Ok, we're now changing the port state. Do it with
2350 * interrupts disabled.
2352 spin_lock_irqsave(&up->port.lock, flags);
2355 * Update the per-port timeout.
2357 uart_update_timeout(port, termios->c_cflag, baud);
2359 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2360 if (termios->c_iflag & INPCK)
2361 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2362 if (termios->c_iflag & (BRKINT | PARMRK))
2363 up->port.read_status_mask |= UART_LSR_BI;
2366 * Characteres to ignore
2368 up->port.ignore_status_mask = 0;
2369 if (termios->c_iflag & IGNPAR)
2370 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2371 if (termios->c_iflag & IGNBRK) {
2372 up->port.ignore_status_mask |= UART_LSR_BI;
2374 * If we're ignoring parity and break indicators,
2375 * ignore overruns too (for real raw support).
2377 if (termios->c_iflag & IGNPAR)
2378 up->port.ignore_status_mask |= UART_LSR_OE;
2382 * ignore all characters if CREAD is not set
2384 if ((termios->c_cflag & CREAD) == 0)
2385 up->port.ignore_status_mask |= UART_LSR_DR;
2388 * CTS flow control flag and modem status interrupts
2390 up->ier &= ~UART_IER_MSI;
2391 if (!(up->bugs & UART_BUG_NOMSR) &&
2392 UART_ENABLE_MS(&up->port, termios->c_cflag))
2393 up->ier |= UART_IER_MSI;
2394 if (up->capabilities & UART_CAP_UUE)
2395 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2397 serial_out(up, UART_IER, up->ier);
2399 if (up->capabilities & UART_CAP_EFR) {
2400 unsigned char efr = 0;
2402 * TI16C752/Startech hardware flow control. FIXME:
2403 * - TI16C752 requires control thresholds to be set.
2404 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2406 if (termios->c_cflag & CRTSCTS)
2407 efr |= UART_EFR_CTS;
2409 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2410 serial_outp(up, UART_EFR, efr);
2413 #ifdef CONFIG_ARCH_OMAP
2414 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2415 if (cpu_is_omap1510() && is_omap_port(up)) {
2416 if (baud == 115200) {
2418 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2420 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2424 if (up->capabilities & UART_NATSEMI) {
2425 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2426 serial_outp(up, UART_LCR, 0xe0);
2428 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2431 serial_dl_write(up, quot);
2434 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2435 * is written without DLAB set, this mode will be disabled.
2437 if (up->port.type == PORT_16750)
2438 serial_outp(up, UART_FCR, fcr);
2440 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2441 up->lcr = cval; /* Save LCR */
2442 if (up->port.type != PORT_16750) {
2443 if (fcr & UART_FCR_ENABLE_FIFO) {
2444 /* emulated UARTs (Lucent Venus 167x) need two steps */
2445 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2447 serial_outp(up, UART_FCR, fcr); /* set fcr */
2449 serial8250_set_mctrl(&up->port, up->port.mctrl);
2450 spin_unlock_irqrestore(&up->port.lock, flags);
2451 /* Don't rewrite B0 */
2452 if (tty_termios_baud_rate(termios))
2453 tty_termios_encode_baud_rate(termios, baud, baud);
2455 EXPORT_SYMBOL(serial8250_do_set_termios);
2458 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2459 struct ktermios *old)
2461 if (port->set_termios)
2462 port->set_termios(port, termios, old);
2464 serial8250_do_set_termios(port, termios, old);
2468 serial8250_set_ldisc(struct uart_port *port, int new)
2471 port->flags |= UPF_HARDPPS_CD;
2472 serial8250_enable_ms(port);
2474 port->flags &= ~UPF_HARDPPS_CD;
2478 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2479 unsigned int oldstate)
2481 struct uart_8250_port *p =
2482 container_of(port, struct uart_8250_port, port);
2484 serial8250_set_sleep(p, state != 0);
2486 EXPORT_SYMBOL(serial8250_do_pm);
2489 serial8250_pm(struct uart_port *port, unsigned int state,
2490 unsigned int oldstate)
2493 port->pm(port, state, oldstate);
2495 serial8250_do_pm(port, state, oldstate);
2498 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2500 if (pt->port.iotype == UPIO_AU)
2502 #ifdef CONFIG_ARCH_OMAP
2503 if (is_omap_port(pt))
2504 return 0x16 << pt->port.regshift;
2506 return 8 << pt->port.regshift;
2510 * Resource handling.
2512 static int serial8250_request_std_resource(struct uart_8250_port *up)
2514 unsigned int size = serial8250_port_size(up);
2517 switch (up->port.iotype) {
2524 if (!up->port.mapbase)
2527 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2532 if (up->port.flags & UPF_IOREMAP) {
2533 up->port.membase = ioremap_nocache(up->port.mapbase,
2535 if (!up->port.membase) {
2536 release_mem_region(up->port.mapbase, size);
2544 if (!request_region(up->port.iobase, size, "serial"))
2551 static void serial8250_release_std_resource(struct uart_8250_port *up)
2553 unsigned int size = serial8250_port_size(up);
2555 switch (up->port.iotype) {
2562 if (!up->port.mapbase)
2565 if (up->port.flags & UPF_IOREMAP) {
2566 iounmap(up->port.membase);
2567 up->port.membase = NULL;
2570 release_mem_region(up->port.mapbase, size);
2575 release_region(up->port.iobase, size);
2580 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2582 unsigned long start = UART_RSA_BASE << up->port.regshift;
2583 unsigned int size = 8 << up->port.regshift;
2586 switch (up->port.iotype) {
2589 start += up->port.iobase;
2590 if (request_region(start, size, "serial-rsa"))
2600 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2602 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2603 unsigned int size = 8 << up->port.regshift;
2605 switch (up->port.iotype) {
2608 release_region(up->port.iobase + offset, size);
2613 static void serial8250_release_port(struct uart_port *port)
2615 struct uart_8250_port *up =
2616 container_of(port, struct uart_8250_port, port);
2618 serial8250_release_std_resource(up);
2619 if (up->port.type == PORT_RSA)
2620 serial8250_release_rsa_resource(up);
2623 static int serial8250_request_port(struct uart_port *port)
2625 struct uart_8250_port *up =
2626 container_of(port, struct uart_8250_port, port);
2629 ret = serial8250_request_std_resource(up);
2630 if (ret == 0 && up->port.type == PORT_RSA) {
2631 ret = serial8250_request_rsa_resource(up);
2633 serial8250_release_std_resource(up);
2639 static void serial8250_config_port(struct uart_port *port, int flags)
2641 struct uart_8250_port *up =
2642 container_of(port, struct uart_8250_port, port);
2643 int probeflags = PROBE_ANY;
2647 * Find the region that we can probe for. This in turn
2648 * tells us whether we can probe for the type of port.
2650 ret = serial8250_request_std_resource(up);
2654 ret = serial8250_request_rsa_resource(up);
2656 probeflags &= ~PROBE_RSA;
2658 if (up->port.iotype != up->cur_iotype)
2659 set_io_from_upio(port);
2661 if (flags & UART_CONFIG_TYPE)
2662 autoconfig(up, probeflags);
2664 /* if access method is AU, it is a 16550 with a quirk */
2665 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2666 up->bugs |= UART_BUG_NOMSR;
2668 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2671 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2672 serial8250_release_rsa_resource(up);
2673 if (up->port.type == PORT_UNKNOWN)
2674 serial8250_release_std_resource(up);
2678 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2680 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2681 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2682 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2683 ser->type == PORT_STARTECH)
2689 serial8250_type(struct uart_port *port)
2691 int type = port->type;
2693 if (type >= ARRAY_SIZE(uart_config))
2695 return uart_config[type].name;
2698 static struct uart_ops serial8250_pops = {
2699 .tx_empty = serial8250_tx_empty,
2700 .set_mctrl = serial8250_set_mctrl,
2701 .get_mctrl = serial8250_get_mctrl,
2702 .stop_tx = serial8250_stop_tx,
2703 .start_tx = serial8250_start_tx,
2704 .stop_rx = serial8250_stop_rx,
2705 .enable_ms = serial8250_enable_ms,
2706 .break_ctl = serial8250_break_ctl,
2707 .startup = serial8250_startup,
2708 .shutdown = serial8250_shutdown,
2709 .set_termios = serial8250_set_termios,
2710 .set_ldisc = serial8250_set_ldisc,
2711 .pm = serial8250_pm,
2712 .type = serial8250_type,
2713 .release_port = serial8250_release_port,
2714 .request_port = serial8250_request_port,
2715 .config_port = serial8250_config_port,
2716 .verify_port = serial8250_verify_port,
2717 #ifdef CONFIG_CONSOLE_POLL
2718 .poll_get_char = serial8250_get_poll_char,
2719 .poll_put_char = serial8250_put_poll_char,
2723 static struct uart_8250_port serial8250_ports[UART_NR];
2725 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2726 unsigned short *capabilities);
2728 void serial8250_set_isa_configurator(
2729 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2731 serial8250_isa_config = v;
2733 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2735 static void __init serial8250_isa_init_ports(void)
2737 struct uart_8250_port *up;
2738 static int first = 1;
2745 for (i = 0; i < nr_uarts; i++) {
2746 struct uart_8250_port *up = &serial8250_ports[i];
2749 spin_lock_init(&up->port.lock);
2751 init_timer(&up->timer);
2752 up->timer.function = serial8250_timeout;
2755 * ALPHA_KLUDGE_MCR needs to be killed.
2757 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2758 up->mcr_force = ALPHA_KLUDGE_MCR;
2760 up->port.ops = &serial8250_pops;
2764 irqflag = IRQF_SHARED;
2766 for (i = 0, up = serial8250_ports;
2767 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2769 up->port.iobase = old_serial_port[i].port;
2770 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2771 up->port.irqflags = old_serial_port[i].irqflags;
2772 up->port.uartclk = old_serial_port[i].baud_base * 16;
2773 up->port.flags = old_serial_port[i].flags;
2774 up->port.hub6 = old_serial_port[i].hub6;
2775 up->port.membase = old_serial_port[i].iomem_base;
2776 up->port.iotype = old_serial_port[i].io_type;
2777 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2778 set_io_from_upio(&up->port);
2779 up->port.irqflags |= irqflag;
2780 if (serial8250_isa_config != NULL)
2781 serial8250_isa_config(i, &up->port, &up->capabilities);
2787 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2789 up->port.type = type;
2790 up->port.fifosize = uart_config[type].fifo_size;
2791 up->capabilities = uart_config[type].flags;
2792 up->tx_loadsz = uart_config[type].tx_loadsz;
2796 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2800 for (i = 0; i < nr_uarts; i++) {
2801 struct uart_8250_port *up = &serial8250_ports[i];
2802 up->cur_iotype = 0xFF;
2805 serial8250_isa_init_ports();
2807 for (i = 0; i < nr_uarts; i++) {
2808 struct uart_8250_port *up = &serial8250_ports[i];
2812 if (up->port.flags & UPF_FIXED_TYPE)
2813 serial8250_init_fixed_type_port(up, up->port.type);
2815 uart_add_one_port(drv, &up->port);
2819 #ifdef CONFIG_SERIAL_8250_CONSOLE
2821 static void serial8250_console_putchar(struct uart_port *port, int ch)
2823 struct uart_8250_port *up =
2824 container_of(port, struct uart_8250_port, port);
2826 wait_for_xmitr(up, UART_LSR_THRE);
2827 serial_out(up, UART_TX, ch);
2831 * Print a string to the serial port trying not to disturb
2832 * any possible real use of the port...
2834 * The console_lock must be held when we get here.
2837 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2839 struct uart_8250_port *up = &serial8250_ports[co->index];
2840 unsigned long flags;
2844 touch_nmi_watchdog();
2846 local_irq_save(flags);
2847 if (up->port.sysrq) {
2848 /* serial8250_handle_port() already took the lock */
2850 } else if (oops_in_progress) {
2851 locked = spin_trylock(&up->port.lock);
2853 spin_lock(&up->port.lock);
2856 * First save the IER then disable the interrupts
2858 ier = serial_in(up, UART_IER);
2860 if (up->capabilities & UART_CAP_UUE)
2861 serial_out(up, UART_IER, UART_IER_UUE);
2863 serial_out(up, UART_IER, 0);
2865 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2868 * Finally, wait for transmitter to become empty
2869 * and restore the IER
2871 wait_for_xmitr(up, BOTH_EMPTY);
2872 serial_out(up, UART_IER, ier);
2875 * The receive handling will happen properly because the
2876 * receive ready bit will still be set; it is not cleared
2877 * on read. However, modem control will not, we must
2878 * call it if we have saved something in the saved flags
2879 * while processing with interrupts off.
2881 if (up->msr_saved_flags)
2882 check_modem_status(up);
2885 spin_unlock(&up->port.lock);
2886 local_irq_restore(flags);
2889 static int __init serial8250_console_setup(struct console *co, char *options)
2891 struct uart_port *port;
2898 * Check whether an invalid uart number has been specified, and
2899 * if so, search for the first available port that does have
2902 if (co->index >= nr_uarts)
2904 port = &serial8250_ports[co->index].port;
2905 if (!port->iobase && !port->membase)
2909 uart_parse_options(options, &baud, &parity, &bits, &flow);
2911 return uart_set_options(port, co, baud, parity, bits, flow);
2914 static int serial8250_console_early_setup(void)
2916 return serial8250_find_port_for_earlycon();
2919 static struct console serial8250_console = {
2921 .write = serial8250_console_write,
2922 .device = uart_console_device,
2923 .setup = serial8250_console_setup,
2924 .early_setup = serial8250_console_early_setup,
2925 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2927 .data = &serial8250_reg,
2930 static int __init serial8250_console_init(void)
2932 if (nr_uarts > UART_NR)
2935 serial8250_isa_init_ports();
2936 register_console(&serial8250_console);
2939 console_initcall(serial8250_console_init);
2941 int serial8250_find_port(struct uart_port *p)
2944 struct uart_port *port;
2946 for (line = 0; line < nr_uarts; line++) {
2947 port = &serial8250_ports[line].port;
2948 if (uart_match_port(p, port))
2954 #define SERIAL8250_CONSOLE &serial8250_console
2956 #define SERIAL8250_CONSOLE NULL
2959 static struct uart_driver serial8250_reg = {
2960 .owner = THIS_MODULE,
2961 .driver_name = "serial",
2965 .cons = SERIAL8250_CONSOLE,
2969 * early_serial_setup - early registration for 8250 ports
2971 * Setup an 8250 port structure prior to console initialisation. Use
2972 * after console initialisation will cause undefined behaviour.
2974 int __init early_serial_setup(struct uart_port *port)
2976 struct uart_port *p;
2978 if (port->line >= ARRAY_SIZE(serial8250_ports))
2981 serial8250_isa_init_ports();
2982 p = &serial8250_ports[port->line].port;
2983 p->iobase = port->iobase;
2984 p->membase = port->membase;
2986 p->irqflags = port->irqflags;
2987 p->uartclk = port->uartclk;
2988 p->fifosize = port->fifosize;
2989 p->regshift = port->regshift;
2990 p->iotype = port->iotype;
2991 p->flags = port->flags;
2992 p->mapbase = port->mapbase;
2993 p->private_data = port->private_data;
2994 p->type = port->type;
2995 p->line = port->line;
2997 set_io_from_upio(p);
2998 if (port->serial_in)
2999 p->serial_in = port->serial_in;
3000 if (port->serial_out)
3001 p->serial_out = port->serial_out;
3007 * serial8250_suspend_port - suspend one serial port
3008 * @line: serial line number
3010 * Suspend one serial port.
3012 void serial8250_suspend_port(int line)
3014 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3018 * serial8250_resume_port - resume one serial port
3019 * @line: serial line number
3021 * Resume one serial port.
3023 void serial8250_resume_port(int line)
3025 struct uart_8250_port *up = &serial8250_ports[line];
3027 if (up->capabilities & UART_NATSEMI) {
3030 /* Ensure it's still in high speed mode */
3031 serial_outp(up, UART_LCR, 0xE0);
3033 tmp = serial_in(up, 0x04); /* EXCR2 */
3034 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
3035 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
3036 serial_outp(up, 0x04, tmp);
3038 serial_outp(up, UART_LCR, 0);
3040 uart_resume_port(&serial8250_reg, &up->port);
3044 * Register a set of serial devices attached to a platform device. The
3045 * list is terminated with a zero flags entry, which means we expect
3046 * all entries to have at least UPF_BOOT_AUTOCONF set.
3048 static int __devinit serial8250_probe(struct platform_device *dev)
3050 struct plat_serial8250_port *p = dev->dev.platform_data;
3051 struct uart_port port;
3052 int ret, i, irqflag = 0;
3054 memset(&port, 0, sizeof(struct uart_port));
3057 irqflag = IRQF_SHARED;
3059 for (i = 0; p && p->flags != 0; p++, i++) {
3060 port.iobase = p->iobase;
3061 port.membase = p->membase;
3063 port.irqflags = p->irqflags;
3064 port.uartclk = p->uartclk;
3065 port.regshift = p->regshift;
3066 port.iotype = p->iotype;
3067 port.flags = p->flags;
3068 port.mapbase = p->mapbase;
3069 port.hub6 = p->hub6;
3070 port.private_data = p->private_data;
3071 port.type = p->type;
3072 port.serial_in = p->serial_in;
3073 port.serial_out = p->serial_out;
3074 port.set_termios = p->set_termios;
3076 port.dev = &dev->dev;
3077 port.irqflags |= irqflag;
3078 ret = serial8250_register_port(&port);
3080 dev_err(&dev->dev, "unable to register port at index %d "
3081 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3082 p->iobase, (unsigned long long)p->mapbase,
3090 * Remove serial ports registered against a platform device.
3092 static int __devexit serial8250_remove(struct platform_device *dev)
3096 for (i = 0; i < nr_uarts; i++) {
3097 struct uart_8250_port *up = &serial8250_ports[i];
3099 if (up->port.dev == &dev->dev)
3100 serial8250_unregister_port(i);
3105 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3109 for (i = 0; i < UART_NR; i++) {
3110 struct uart_8250_port *up = &serial8250_ports[i];
3112 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3113 uart_suspend_port(&serial8250_reg, &up->port);
3119 static int serial8250_resume(struct platform_device *dev)
3123 for (i = 0; i < UART_NR; i++) {
3124 struct uart_8250_port *up = &serial8250_ports[i];
3126 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3127 serial8250_resume_port(i);
3133 static struct platform_driver serial8250_isa_driver = {
3134 .probe = serial8250_probe,
3135 .remove = __devexit_p(serial8250_remove),
3136 .suspend = serial8250_suspend,
3137 .resume = serial8250_resume,
3139 .name = "serial8250",
3140 .owner = THIS_MODULE,
3145 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3146 * in the table in include/asm/serial.h
3148 static struct platform_device *serial8250_isa_devs;
3151 * serial8250_register_port and serial8250_unregister_port allows for
3152 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3153 * modems and PCI multiport cards.
3155 static DEFINE_MUTEX(serial_mutex);
3157 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3162 * First, find a port entry which matches.
3164 for (i = 0; i < nr_uarts; i++)
3165 if (uart_match_port(&serial8250_ports[i].port, port))
3166 return &serial8250_ports[i];
3169 * We didn't find a matching entry, so look for the first
3170 * free entry. We look for one which hasn't been previously
3171 * used (indicated by zero iobase).
3173 for (i = 0; i < nr_uarts; i++)
3174 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3175 serial8250_ports[i].port.iobase == 0)
3176 return &serial8250_ports[i];
3179 * That also failed. Last resort is to find any entry which
3180 * doesn't have a real port associated with it.
3182 for (i = 0; i < nr_uarts; i++)
3183 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3184 return &serial8250_ports[i];
3190 * serial8250_register_port - register a serial port
3191 * @port: serial port template
3193 * Configure the serial port specified by the request. If the
3194 * port exists and is in use, it is hung up and unregistered
3197 * The port is then probed and if necessary the IRQ is autodetected
3198 * If this fails an error is returned.
3200 * On success the port is ready to use and the line number is returned.
3202 int serial8250_register_port(struct uart_port *port)
3204 struct uart_8250_port *uart;
3207 if (port->uartclk == 0)
3210 mutex_lock(&serial_mutex);
3212 uart = serial8250_find_match_or_unused(port);
3214 uart_remove_one_port(&serial8250_reg, &uart->port);
3216 uart->port.iobase = port->iobase;
3217 uart->port.membase = port->membase;
3218 uart->port.irq = port->irq;
3219 uart->port.irqflags = port->irqflags;
3220 uart->port.uartclk = port->uartclk;
3221 uart->port.fifosize = port->fifosize;
3222 uart->port.regshift = port->regshift;
3223 uart->port.iotype = port->iotype;
3224 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3225 uart->port.mapbase = port->mapbase;
3226 uart->port.private_data = port->private_data;
3228 uart->port.dev = port->dev;
3230 if (port->flags & UPF_FIXED_TYPE)
3231 serial8250_init_fixed_type_port(uart, port->type);
3233 set_io_from_upio(&uart->port);
3234 /* Possibly override default I/O functions. */
3235 if (port->serial_in)
3236 uart->port.serial_in = port->serial_in;
3237 if (port->serial_out)
3238 uart->port.serial_out = port->serial_out;
3239 /* Possibly override set_termios call */
3240 if (port->set_termios)
3241 uart->port.set_termios = port->set_termios;
3243 uart->port.pm = port->pm;
3245 if (serial8250_isa_config != NULL)
3246 serial8250_isa_config(0, &uart->port,
3247 &uart->capabilities);
3249 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3251 ret = uart->port.line;
3253 mutex_unlock(&serial_mutex);
3257 EXPORT_SYMBOL(serial8250_register_port);
3260 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3261 * @line: serial line number
3263 * Remove one serial port. This may not be called from interrupt
3264 * context. We hand the port back to the our control.
3266 void serial8250_unregister_port(int line)
3268 struct uart_8250_port *uart = &serial8250_ports[line];
3270 mutex_lock(&serial_mutex);
3271 uart_remove_one_port(&serial8250_reg, &uart->port);
3272 if (serial8250_isa_devs) {
3273 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3274 uart->port.type = PORT_UNKNOWN;
3275 uart->port.dev = &serial8250_isa_devs->dev;
3276 uart_add_one_port(&serial8250_reg, &uart->port);
3278 uart->port.dev = NULL;
3280 mutex_unlock(&serial_mutex);
3282 EXPORT_SYMBOL(serial8250_unregister_port);
3284 static int __init serial8250_init(void)
3288 if (nr_uarts > UART_NR)
3291 printk(KERN_INFO "Serial: 8250/16550 driver, "
3292 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3293 share_irqs ? "en" : "dis");
3296 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3298 serial8250_reg.nr = UART_NR;
3299 ret = uart_register_driver(&serial8250_reg);
3304 serial8250_isa_devs = platform_device_alloc("serial8250",
3305 PLAT8250_DEV_LEGACY);
3306 if (!serial8250_isa_devs) {
3308 goto unreg_uart_drv;
3311 ret = platform_device_add(serial8250_isa_devs);
3315 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3317 ret = platform_driver_register(&serial8250_isa_driver);
3321 platform_device_del(serial8250_isa_devs);
3323 platform_device_put(serial8250_isa_devs);
3326 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3328 uart_unregister_driver(&serial8250_reg);
3334 static void __exit serial8250_exit(void)
3336 struct platform_device *isa_dev = serial8250_isa_devs;
3339 * This tells serial8250_unregister_port() not to re-register
3340 * the ports (thereby making serial8250_isa_driver permanently
3343 serial8250_isa_devs = NULL;
3345 platform_driver_unregister(&serial8250_isa_driver);
3346 platform_device_unregister(isa_dev);
3349 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3351 uart_unregister_driver(&serial8250_reg);
3355 module_init(serial8250_init);
3356 module_exit(serial8250_exit);
3358 EXPORT_SYMBOL(serial8250_suspend_port);
3359 EXPORT_SYMBOL(serial8250_resume_port);
3361 MODULE_LICENSE("GPL");
3362 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3364 module_param(share_irqs, uint, 0644);
3365 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3368 module_param(nr_uarts, uint, 0644);
3369 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3371 module_param(skip_txen_test, uint, 0644);
3372 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3374 #ifdef CONFIG_SERIAL_8250_RSA
3375 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3376 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3378 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);