drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*init)(struct pci_dev *dev);
  43         int     (*setup)(struct serial_private *,
  44                          const struct pciserial_board *,
  45                          struct uart_port *, int);
  46         void    (*exit)(struct pci_dev *dev);
  47 };
  48
  49 #define PCI_NUM_BAR_RESOURCES   6
  50
  51 struct serial_private {
  52         struct pci_dev          *dev;
  53         unsigned int            nr;
  54         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  55         struct pci_serial_quirk *quirk;
  56         int                     line[0];
  57 };
  58
  59 static int pci_default_setup(struct serial_private*,
  60           const struct pciserial_board*, struct uart_port*, int);
  61
  62 static void moan_device(const char *str, struct pci_dev *dev)
  63 {
  64         printk(KERN_WARNING
  65                "%s: %s\n"
  66                "Please send the output of lspci -vv, this\n"
  67                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                "manufacturer and name of serial board or\n"
  69                "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->iotype = UPIO_MEM;
  95                 port->iobase = 0;
  96                 port->mapbase = base + offset;
  97                 port->membase = priv->remapped_bar[bar] + offset;
  98                 port->regshift = regshift;
  99         } else {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = base + offset;
 102                 port->mapbase = 0;
 103                 port->membase = NULL;
 104                 port->regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 111  */
 112 static int addidata_apci7800_setup(struct serial_private *priv,
 113                                 const struct pciserial_board *board,
 114                                 struct uart_port *port, int idx)
 115 {
 116         unsigned int bar = 0, offset = board->first_offset;
 117         bar = FL_GET_BASE(board->flags);
 118
 119         if (idx < 2) {
 120                 offset += idx * board->uart_offset;
 121         } else if ((idx >= 2) && (idx < 4)) {
 122                 bar += 1;
 123                 offset += ((idx - 2) * board->uart_offset);
 124         } else if ((idx >= 4) && (idx < 6)) {
 125                 bar += 2;
 126                 offset += ((idx - 4) * board->uart_offset);
 127         } else if (idx >= 6) {
 128                 bar += 3;
 129                 offset += ((idx - 6) * board->uart_offset);
 130         }
 131
 132         return setup_port(priv, port, bar, offset, board->reg_shift);
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 141               struct uart_port *port, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(priv, port, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct serial_private *priv,
 195                 const struct pciserial_board *board,
 196                 struct uart_port *port, int idx)
 197 {
 198         unsigned int offset = board->first_offset;
 199         unsigned int bar = FL_GET_BASE(board->flags);
 200
 201         switch (priv->dev->subsystem_device) {
 202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 203                 if (idx == 3)
 204                         idx++;
 205                 break;
 206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 207                 if (idx > 0)
 208                         idx++;
 209                 if (idx > 2)
 210                         idx++;
 211                 break;
 212         }
 213         if (idx > 2)
 214                 offset = 0x18;
 215
 216         offset += idx * board->uart_offset;
 217
 218         return setup_port(priv, port, bar, offset, board->reg_shift);
 219 }
 220
 221 /*
 222  * Added for EKF Intel i960 serial boards
 223  */
 224 static int pci_inteli960ni_init(struct pci_dev *dev)
 225 {
 226         unsigned long oldval;
 227
 228         if (!(dev->subsystem_device & 0x1000))
 229                 return -ENODEV;
 230
 231         /* is firmware started? */
 232         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 233         if (oldval == 0x00001000L) { /* RESET value */
 234                 printk(KERN_DEBUG "Local i960 firmware missing");
 235                 return -ENODEV;
 236         }
 237         return 0;
 238 }
 239
 240 /*
 241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 242  * that the card interrupt be explicitly enabled or disabled.  This
 243  * seems to be mainly needed on card using the PLX which also use I/O
 244  * mapped memory.
 245  */
 246 static int pci_plx9050_init(struct pci_dev *dev)
 247 {
 248         u8 irq_config;
 249         void __iomem *p;
 250
 251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 252                 moan_device("no memory in bar 0", dev);
 253                 return 0;
 254         }
 255
 256         irq_config = 0x41;
 257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 259                 irq_config = 0x43;
 260
 261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 263                 /*
 264                  * As the megawolf cards have the int pins active
 265                  * high, and have 2 UART chips, both ints must be
 266                  * enabled on the 9050. Also, the UARTS are set in
 267                  * 16450 mode by default, so we have to enable the
 268                  * 16C950 'enhanced' mode so that we can use the
 269                  * deep FIFOs
 270                  */
 271                 irq_config = 0x5b;
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 #define NI8420_INT_ENABLE_REG   0x38
 312 #define NI8420_INT_ENABLE_BIT   0x2000
 313
 314 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 315 {
 316         void __iomem *p;
 317         unsigned long base, len;
 318         unsigned int bar = 0;
 319
 320         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 321                 moan_device("no memory in bar", dev);
 322                 return;
 323         }
 324
 325         base = pci_resource_start(dev, bar);
 326         len =  pci_resource_len(dev, bar);
 327         p = ioremap_nocache(base, len);
 328         if (p == NULL)
 329                 return;
 330
 331         /* Disable the CPU Interrupt */
 332         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 333                p + NI8420_INT_ENABLE_REG);
 334         iounmap(p);
 335 }
 336
 337
 338 /* MITE registers */
 339 #define MITE_IOWBSR1    0xc4
 340 #define MITE_IOWCR1     0xf4
 341 #define MITE_LCIMR1     0x08
 342 #define MITE_LCIMR2     0x10
 343
 344 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 345
 346 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 347 {
 348         void __iomem *p;
 349         unsigned long base, len;
 350         unsigned int bar = 0;
 351
 352         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 353                 moan_device("no memory in bar", dev);
 354                 return;
 355         }
 356
 357         base = pci_resource_start(dev, bar);
 358         len =  pci_resource_len(dev, bar);
 359         p = ioremap_nocache(base, len);
 360         if (p == NULL)
 361                 return;
 362
 363         /* Disable the CPU Interrupt */
 364         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 365         iounmap(p);
 366 }
 367
 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 369 static int
 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 371                 struct uart_port *port, int idx)
 372 {
 373         unsigned int bar, offset = board->first_offset;
 374
 375         bar = 0;
 376
 377         if (idx < 4) {
 378                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 379                 offset += idx * board->uart_offset;
 380         } else if (idx < 8) {
 381                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 382                 offset += idx * board->uart_offset + 0xC00;
 383         } else /* we have only 8 ports on PMC-OCTALPRO */
 384                 return 1;
 385
 386         return setup_port(priv, port, bar, offset, board->reg_shift);
 387 }
 388
 389 /*
 390 * This does initialization for PMC OCTALPRO cards:
 391 * maps the device memory, resets the UARTs (needed, bc
 392 * if the module is removed and inserted again, the card
 393 * is in the sleep mode) and enables global interrupt.
 394 */
 395
 396 /* global control register offset for SBS PMC-OctalPro */
 397 #define OCT_REG_CR_OFF          0x500
 398
 399 static int sbs_init(struct pci_dev *dev)
 400 {
 401         u8 __iomem *p;
 402
 403         p = pci_ioremap_bar(dev, 0);
 404
 405         if (p == NULL)
 406                 return -ENOMEM;
 407         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 408         writeb(0x10, p + OCT_REG_CR_OFF);
 409         udelay(50);
 410         writeb(0x0, p + OCT_REG_CR_OFF);
 411
 412         /* Set bit-2 (INTENABLE) of Control Register */
 413         writeb(0x4, p + OCT_REG_CR_OFF);
 414         iounmap(p);
 415
 416         return 0;
 417 }
 418
 419 /*
 420  * Disables the global interrupt of PMC-OctalPro
 421  */
 422
 423 static void __devexit sbs_exit(struct pci_dev *dev)
 424 {
 425         u8 __iomem *p;
 426
 427         p = pci_ioremap_bar(dev, 0);
 428         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 429         if (p != NULL)
 430                 writeb(0, p + OCT_REG_CR_OFF);
 431         iounmap(p);
 432 }
 433
 434 /*
 435  * SIIG serial cards have an PCI interface chip which also controls
 436  * the UART clocking frequency. Each UART can be clocked independently
 437  * (except cards equipped with 4 UARTs) and initial clocking settings
 438  * are stored in the EEPROM chip. It can cause problems because this
 439  * version of serial driver doesn't support differently clocked UART's
 440  * on single PCI card. To prevent this, initialization functions set
 441  * high frequency clocking for all UART's on given card. It is safe (I
 442  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 443  * with other OSes (like M$ DOS).
 444  *
 445  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 446  *
 447  * There is two family of SIIG serial cards with different PCI
 448  * interface chip and different configuration methods:
 449  *     - 10x cards have control registers in IO and/or memory space;
 450  *     - 20x cards have control registers in standard PCI configuration space.
 451  *
 452  * Note: all 10x cards have PCI device ids 0x10..
 453  *       all 20x cards have PCI device ids 0x20..
 454  *
 455  * There are also Quartet Serial cards which use Oxford Semiconductor
 456  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 457  *
 458  * Note: some SIIG cards are probed by the parport_serial object.
 459  */
 460
 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 463
 464 static int pci_siig10x_init(struct pci_dev *dev)
 465 {
 466         u16 data;
 467         void __iomem *p;
 468
 469         switch (dev->device & 0xfff8) {
 470         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 471                 data = 0xffdf;
 472                 break;
 473         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 474                 data = 0xf7ff;
 475                 break;
 476         default:                        /* 1S1P, 4S */
 477                 data = 0xfffb;
 478                 break;
 479         }
 480
 481         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 482         if (p == NULL)
 483                 return -ENOMEM;
 484
 485         writew(readw(p + 0x28) & data, p + 0x28);
 486         readw(p + 0x28);
 487         iounmap(p);
 488         return 0;
 489 }
 490
 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 493
 494 static int pci_siig20x_init(struct pci_dev *dev)
 495 {
 496         u8 data;
 497
 498         /* Change clock frequency for the first UART. */
 499         pci_read_config_byte(dev, 0x6f, &data);
 500         pci_write_config_byte(dev, 0x6f, data & 0xef);
 501
 502         /* If this card has 2 UART, we have to do the same with second UART. */
 503         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 504             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 505                 pci_read_config_byte(dev, 0x73, &data);
 506                 pci_write_config_byte(dev, 0x73, data & 0xef);
 507         }
 508         return 0;
 509 }
 510
 511 static int pci_siig_init(struct pci_dev *dev)
 512 {
 513         unsigned int type = dev->device & 0xff00;
 514
 515         if (type == 0x1000)
 516                 return pci_siig10x_init(dev);
 517         else if (type == 0x2000)
 518                 return pci_siig20x_init(dev);
 519
 520         moan_device("Unknown SIIG card", dev);
 521         return -ENODEV;
 522 }
 523
 524 static int pci_siig_setup(struct serial_private *priv,
 525                           const struct pciserial_board *board,
 526                           struct uart_port *port, int idx)
 527 {
 528         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 529
 530         if (idx > 3) {
 531                 bar = 4;
 532                 offset = (idx - 4) * 8;
 533         }
 534
 535         return setup_port(priv, port, bar, offset, 0);
 536 }
 537
 538 /*
 539  * Timedia has an explosion of boards, and to avoid the PCI table from
 540  * growing *huge*, we use this function to collapse some 70 entries
 541  * in the PCI table into one, for sanity's and compactness's sake.
 542  */
 543 static const unsigned short timedia_single_port[] = {
 544         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 545 };
 546
 547 static const unsigned short timedia_dual_port[] = {
 548         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 549         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 550         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 551         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 552         0xD079, 0
 553 };
 554
 555 static const unsigned short timedia_quad_port[] = {
 556         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 557         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 558         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 559         0xB157, 0
 560 };
 561
 562 static const unsigned short timedia_eight_port[] = {
 563         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 564         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 565 };
 566
 567 static const struct timedia_struct {
 568         int num;
 569         const unsigned short *ids;
 570 } timedia_data[] = {
 571         { 1, timedia_single_port },
 572         { 2, timedia_dual_port },
 573         { 4, timedia_quad_port },
 574         { 8, timedia_eight_port }
 575 };
 576
 577 static int pci_timedia_init(struct pci_dev *dev)
 578 {
 579         const unsigned short *ids;
 580         int i, j;
 581
 582         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 583                 ids = timedia_data[i].ids;
 584                 for (j = 0; ids[j]; j++)
 585                         if (dev->subsystem_device == ids[j])
 586                                 return timedia_data[i].num;
 587         }
 588         return 0;
 589 }
 590
 591 /*
 592  * Timedia/SUNIX uses a mixture of BARs and offsets
 593  * Ugh, this is ugly as all hell --- TYT
 594  */
 595 static int
 596 pci_timedia_setup(struct serial_private *priv,
 597                   const struct pciserial_board *board,
 598                   struct uart_port *port, int idx)
 599 {
 600         unsigned int bar = 0, offset = board->first_offset;
 601
 602         switch (idx) {
 603         case 0:
 604                 bar = 0;
 605                 break;
 606         case 1:
 607                 offset = board->uart_offset;
 608                 bar = 0;
 609                 break;
 610         case 2:
 611                 bar = 1;
 612                 break;
 613         case 3:
 614                 offset = board->uart_offset;
 615                 /* FALLTHROUGH */
 616         case 4: /* BAR 2 */
 617         case 5: /* BAR 3 */
 618         case 6: /* BAR 4 */
 619         case 7: /* BAR 5 */
 620                 bar = idx - 2;
 621         }
 622
 623         return setup_port(priv, port, bar, offset, board->reg_shift);
 624 }
 625
 626 /*
 627  * Some Titan cards are also a little weird
 628  */
 629 static int
 630 titan_400l_800l_setup(struct serial_private *priv,
 631                       const struct pciserial_board *board,
 632                       struct uart_port *port, int idx)
 633 {
 634         unsigned int bar, offset = board->first_offset;
 635
 636         switch (idx) {
 637         case 0:
 638                 bar = 1;
 639                 break;
 640         case 1:
 641                 bar = 2;
 642                 break;
 643         default:
 644                 bar = 4;
 645                 offset = (idx - 2) * board->uart_offset;
 646         }
 647
 648         return setup_port(priv, port, bar, offset, board->reg_shift);
 649 }
 650
 651 static int pci_xircom_init(struct pci_dev *dev)
 652 {
 653         msleep(100);
 654         return 0;
 655 }
 656
 657 static int pci_ni8420_init(struct pci_dev *dev)
 658 {
 659         void __iomem *p;
 660         unsigned long base, len;
 661         unsigned int bar = 0;
 662
 663         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 664                 moan_device("no memory in bar", dev);
 665                 return 0;
 666         }
 667
 668         base = pci_resource_start(dev, bar);
 669         len =  pci_resource_len(dev, bar);
 670         p = ioremap_nocache(base, len);
 671         if (p == NULL)
 672                 return -ENOMEM;
 673
 674         /* Enable CPU Interrupt */
 675         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 676                p + NI8420_INT_ENABLE_REG);
 677
 678         iounmap(p);
 679         return 0;
 680 }
 681
 682 #define MITE_IOWBSR1_WSIZE      0xa
 683 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 684 #define MITE_IOWBSR1_WENAB      (1 << 7)
 685 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 686 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 687 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 688
 689 static int pci_ni8430_init(struct pci_dev *dev)
 690 {
 691         void __iomem *p;
 692         unsigned long base, len;
 693         u32 device_window;
 694         unsigned int bar = 0;
 695
 696         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 697                 moan_device("no memory in bar", dev);
 698                 return 0;
 699         }
 700
 701         base = pci_resource_start(dev, bar);
 702         len =  pci_resource_len(dev, bar);
 703         p = ioremap_nocache(base, len);
 704         if (p == NULL)
 705                 return -ENOMEM;
 706
 707         /* Set device window address and size in BAR0 */
 708         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 709                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 710         writel(device_window, p + MITE_IOWBSR1);
 711
 712         /* Set window access to go to RAMSEL IO address space */
 713         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 714                p + MITE_IOWCR1);
 715
 716         /* Enable IO Bus Interrupt 0 */
 717         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 718
 719         /* Enable CPU Interrupt */
 720         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 721
 722         iounmap(p);
 723         return 0;
 724 }
 725
 726 /* UART Port Control Register */
 727 #define NI8430_PORTCON  0x0f
 728 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 729
 730 static int
 731 pci_ni8430_setup(struct serial_private *priv,
 732                  const struct pciserial_board *board,
 733                  struct uart_port *port, int idx)
 734 {
 735         void __iomem *p;
 736         unsigned long base, len;
 737         unsigned int bar, offset = board->first_offset;
 738
 739         if (idx >= board->num_ports)
 740                 return 1;
 741
 742         bar = FL_GET_BASE(board->flags);
 743         offset += idx * board->uart_offset;
 744
 745         base = pci_resource_start(priv->dev, bar);
 746         len =  pci_resource_len(priv->dev, bar);
 747         p = ioremap_nocache(base, len);
 748
 749         /* enable the transciever */
 750         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 751                p + offset + NI8430_PORTCON);
 752
 753         iounmap(p);
 754
 755         return setup_port(priv, port, bar, offset, board->reg_shift);
 756 }
 757
 758 static int pci_netmos_9900_setup(struct serial_private *priv,
 759                                 const struct pciserial_board *board,
 760                                 struct uart_port *port, int idx)
 761 {
 762         unsigned int bar;
 763
 764         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 765                 /* netmos apparently orders BARs by datasheet layout, so serial
 766                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 767                  */
 768                 bar = 3 * idx;
 769
 770                 return setup_port(priv, port, bar, 0, board->reg_shift);
 771         } else {
 772                 return pci_default_setup(priv, board, port, idx);
 773         }
 774 }
 775
 776 /* the 99xx series comes with a range of device IDs and a variety
 777  * of capabilities:
 778  *
 779  * 9900 has varying capabilities and can cascade to sub-controllers
 780  *   (cascading should be purely internal)
 781  * 9904 is hardwired with 4 serial ports
 782  * 9912 and 9922 are hardwired with 2 serial ports
 783  */
 784 static int pci_netmos_9900_numports(struct pci_dev *dev)
 785 {
 786         unsigned int c = dev->class;
 787         unsigned int pi;
 788         unsigned short sub_serports;
 789
 790         pi = (c & 0xff);
 791
 792         if (pi == 2) {
 793                 return 1;
 794         } else if ((pi == 0) &&
 795                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 796                 /* two possibilities: 0x30ps encodes number of parallel and
 797                  * serial ports, or 0x1000 indicates *something*. This is not
 798                  * immediately obvious, since the 2s1p+4s configuration seems
 799                  * to offer all functionality on functions 0..2, while still
 800                  * advertising the same function 3 as the 4s+2s1p config.
 801                  */
 802                 sub_serports = dev->subsystem_device & 0xf;
 803                 if (sub_serports > 0) {
 804                         return sub_serports;
 805                 } else {
 806                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 807                         return 0;
 808                 }
 809         }
 810
 811         moan_device("unknown NetMos/Mostech program interface", dev);
 812         return 0;
 813 }
 814
 815 static int pci_netmos_init(struct pci_dev *dev)
 816 {
 817         /* subdevice 0x00PS means <P> parallel, <S> serial */
 818         unsigned int num_serial = dev->subsystem_device & 0xf;
 819
 820         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 821                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 822                 return 0;
 823
 824         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 825                         dev->subsystem_device == 0x0299)
 826                 return 0;
 827
 828         switch (dev->device) { /* FALLTHROUGH on all */
 829                 case PCI_DEVICE_ID_NETMOS_9904:
 830                 case PCI_DEVICE_ID_NETMOS_9912:
 831                 case PCI_DEVICE_ID_NETMOS_9922:
 832                 case PCI_DEVICE_ID_NETMOS_9900:
 833                         num_serial = pci_netmos_9900_numports(dev);
 834                         break;
 835
 836                 default:
 837                         if (num_serial == 0 ) {
 838                                 moan_device("unknown NetMos/Mostech device", dev);
 839                         }
 840         }
 841
 842         if (num_serial == 0)
 843                 return -ENODEV;
 844
 845         return num_serial;
 846 }
 847
 848 /*
 849  * These chips are available with optionally one parallel port and up to
 850  * two serial ports. Unfortunately they all have the same product id.
 851  *
 852  * Basic configuration is done over a region of 32 I/O ports. The base
 853  * ioport is called INTA or INTC, depending on docs/other drivers.
 854  *
 855  * The region of the 32 I/O ports is configured in POSIO0R...
 856  */
 857
 858 /* registers */
 859 #define ITE_887x_MISCR          0x9c
 860 #define ITE_887x_INTCBAR        0x78
 861 #define ITE_887x_UARTBAR        0x7c
 862 #define ITE_887x_PS0BAR         0x10
 863 #define ITE_887x_POSIO0         0x60
 864
 865 /* I/O space size */
 866 #define ITE_887x_IOSIZE         32
 867 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 868 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 869 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 870 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 871 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 872 #define ITE_887x_POSIO_SPEED            (3 << 29)
 873 /* enable IO_Space bit */
 874 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 875
 876 static int pci_ite887x_init(struct pci_dev *dev)
 877 {
 878         /* inta_addr are the configuration addresses of the ITE */
 879         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 880                                                         0x200, 0x280, 0 };
 881         int ret, i, type;
 882         struct resource *iobase = NULL;
 883         u32 miscr, uartbar, ioport;
 884
 885         /* search for the base-ioport */
 886         i = 0;
 887         while (inta_addr[i] && iobase == NULL) {
 888                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 889                                                                 "ite887x");
 890                 if (iobase != NULL) {
 891                         /* write POSIO0R - speed | size | ioport */
 892                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 893                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 894                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 895                         /* write INTCBAR - ioport */
 896                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 897                                                                 inta_addr[i]);
 898                         ret = inb(inta_addr[i]);
 899                         if (ret != 0xff) {
 900                                 /* ioport connected */
 901                                 break;
 902                         }
 903                         release_region(iobase->start, ITE_887x_IOSIZE);
 904                         iobase = NULL;
 905                 }
 906                 i++;
 907         }
 908
 909         if (!inta_addr[i]) {
 910                 printk(KERN_ERR "ite887x: could not find iobase\n");
 911                 return -ENODEV;
 912         }
 913
 914         /* start of undocumented type checking (see parport_pc.c) */
 915         type = inb(iobase->start + 0x18) & 0x0f;
 916
 917         switch (type) {
 918         case 0x2:       /* ITE8871 (1P) */
 919         case 0xa:       /* ITE8875 (1P) */
 920                 ret = 0;
 921                 break;
 922         case 0xe:       /* ITE8872 (2S1P) */
 923                 ret = 2;
 924                 break;
 925         case 0x6:       /* ITE8873 (1S) */
 926                 ret = 1;
 927                 break;
 928         case 0x8:       /* ITE8874 (2S) */
 929                 ret = 2;
 930                 break;
 931         default:
 932                 moan_device("Unknown ITE887x", dev);
 933                 ret = -ENODEV;
 934         }
 935
 936         /* configure all serial ports */
 937         for (i = 0; i < ret; i++) {
 938                 /* read the I/O port from the device */
 939                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 940                                                                 &ioport);
 941                 ioport &= 0x0000FF00;   /* the actual base address */
 942                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 943                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 944                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 945
 946                 /* write the ioport to the UARTBAR */
 947                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 948                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 949                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 950                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 951
 952                 /* get current config */
 953                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 954                 /* disable interrupts (UARTx_Routing[3:0]) */
 955                 miscr &= ~(0xf << (12 - 4 * i));
 956                 /* activate the UART (UARTx_En) */
 957                 miscr |= 1 << (23 - i);
 958                 /* write new config with activated UART */
 959                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 960         }
 961
 962         if (ret <= 0) {
 963                 /* the device has no UARTs if we get here */
 964                 release_region(iobase->start, ITE_887x_IOSIZE);
 965         }
 966
 967         return ret;
 968 }
 969
 970 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 971 {
 972         u32 ioport;
 973         /* the ioport is bit 0-15 in POSIO0R */
 974         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 975         ioport &= 0xffff;
 976         release_region(ioport, ITE_887x_IOSIZE);
 977 }
 978
 979 /*
 980  * Oxford Semiconductor Inc.
 981  * Check that device is part of the Tornado range of devices, then determine
 982  * the number of ports available on the device.
 983  */
 984 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
 985 {
 986         u8 __iomem *p;
 987         unsigned long deviceID;
 988         unsigned int  number_uarts = 0;
 989
 990         /* OxSemi Tornado devices are all 0xCxxx */
 991         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
 992             (dev->device & 0xF000) != 0xC000)
 993                 return 0;
 994
 995         p = pci_iomap(dev, 0, 5);
 996         if (p == NULL)
 997                 return -ENOMEM;
 998
 999         deviceID = ioread32(p);
1000         /* Tornado device */
1001         if (deviceID == 0x07000200) {
1002                 number_uarts = ioread8(p + 4);
1003                 printk(KERN_DEBUG
1004                         "%d ports detected on Oxford PCI Express device\n",
1005                                                                 number_uarts);
1006         }
1007         pci_iounmap(dev, p);
1008         return number_uarts;
1009 }
1010
1011 static int
1012 pci_default_setup(struct serial_private *priv,
1013                   const struct pciserial_board *board,
1014                   struct uart_port *port, int idx)
1015 {
1016         unsigned int bar, offset = board->first_offset, maxnr;
1017
1018         bar = FL_GET_BASE(board->flags);
1019         if (board->flags & FL_BASE_BARS)
1020                 bar += idx;
1021         else
1022                 offset += idx * board->uart_offset;
1023
1024         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1025                 (board->reg_shift + 3);
1026
1027         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1028                 return 1;
1029
1030         return setup_port(priv, port, bar, offset, board->reg_shift);
1031 }
1032
1033 static int
1034 ce4100_serial_setup(struct serial_private *priv,
1035                   const struct pciserial_board *board,
1036                   struct uart_port *port, int idx)
1037 {
1038         int ret;
1039
1040         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1041         port->iotype = UPIO_MEM32;
1042         port->type = PORT_XSCALE;
1043         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1044         port->regshift = 2;
1045
1046         return ret;
1047 }
1048
1049 static int
1050 pci_omegapci_setup(struct serial_private *priv,
1051                       struct pciserial_board *board,
1052                       struct uart_port *port, int idx)
1053 {
1054         return setup_port(priv, port, 2, idx * 8, 0);
1055 }
1056
1057 static int skip_tx_en_setup(struct serial_private *priv,
1058                         const struct pciserial_board *board,
1059                         struct uart_port *port, int idx)
1060 {
1061         port->flags |= UPF_NO_TXEN_TEST;
1062         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1063                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1064                           priv->dev->vendor,
1065                           priv->dev->device,
1066                           priv->dev->subsystem_vendor,
1067                           priv->dev->subsystem_device);
1068
1069         return pci_default_setup(priv, board, port, idx);
1070 }
1071
1072 /* This should be in linux/pci_ids.h */
1073 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1074 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1075 #define PCI_DEVICE_ID_OCTPRO            0x0001
1076 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1077 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1078 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1079 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1080 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1081 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1082 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1083 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1084 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1085 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1086 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1087 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1088 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1089 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1090 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1091 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1092 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1093 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1094 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1095 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1096 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1097 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1098
1099 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1100 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1101
1102 /*
1103  * Master list of serial port init/setup/exit quirks.
1104  * This does not describe the general nature of the port.
1105  * (ie, baud base, number and location of ports, etc)
1106  *
1107  * This list is ordered alphabetically by vendor then device.
1108  * Specific entries must come before more generic entries.
1109  */
1110 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1111         /*
1112         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1113         */
1114         {
1115                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1116                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1117                 .subvendor      = PCI_ANY_ID,
1118                 .subdevice      = PCI_ANY_ID,
1119                 .setup          = addidata_apci7800_setup,
1120         },
1121         /*
1122          * AFAVLAB cards - these may be called via parport_serial
1123          *  It is not clear whether this applies to all products.
1124          */
1125         {
1126                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1127                 .device         = PCI_ANY_ID,
1128                 .subvendor      = PCI_ANY_ID,
1129                 .subdevice      = PCI_ANY_ID,
1130                 .setup          = afavlab_setup,
1131         },
1132         /*
1133          * HP Diva
1134          */
1135         {
1136                 .vendor         = PCI_VENDOR_ID_HP,
1137                 .device         = PCI_DEVICE_ID_HP_DIVA,
1138                 .subvendor      = PCI_ANY_ID,
1139                 .subdevice      = PCI_ANY_ID,
1140                 .init           = pci_hp_diva_init,
1141                 .setup          = pci_hp_diva_setup,
1142         },
1143         /*
1144          * Intel
1145          */
1146         {
1147                 .vendor         = PCI_VENDOR_ID_INTEL,
1148                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1149                 .subvendor      = 0xe4bf,
1150                 .subdevice      = PCI_ANY_ID,
1151                 .init           = pci_inteli960ni_init,
1152                 .setup          = pci_default_setup,
1153         },
1154         {
1155                 .vendor         = PCI_VENDOR_ID_INTEL,
1156                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1157                 .subvendor      = PCI_ANY_ID,
1158                 .subdevice      = PCI_ANY_ID,
1159                 .setup          = skip_tx_en_setup,
1160         },
1161         {
1162                 .vendor         = PCI_VENDOR_ID_INTEL,
1163                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1164                 .subvendor      = PCI_ANY_ID,
1165                 .subdevice      = PCI_ANY_ID,
1166                 .setup          = skip_tx_en_setup,
1167         },
1168         {
1169                 .vendor         = PCI_VENDOR_ID_INTEL,
1170                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1171                 .subvendor      = PCI_ANY_ID,
1172                 .subdevice      = PCI_ANY_ID,
1173                 .setup          = skip_tx_en_setup,
1174         },
1175         {
1176                 .vendor         = PCI_VENDOR_ID_INTEL,
1177                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1178                 .subvendor      = PCI_ANY_ID,
1179                 .subdevice      = PCI_ANY_ID,
1180                 .setup          = ce4100_serial_setup,
1181         },
1182         /*
1183          * ITE
1184          */
1185         {
1186                 .vendor         = PCI_VENDOR_ID_ITE,
1187                 .device         = PCI_DEVICE_ID_ITE_8872,
1188                 .subvendor      = PCI_ANY_ID,
1189                 .subdevice      = PCI_ANY_ID,
1190                 .init           = pci_ite887x_init,
1191                 .setup          = pci_default_setup,
1192                 .exit           = __devexit_p(pci_ite887x_exit),
1193         },
1194         /*
1195          * National Instruments
1196          */
1197         {
1198                 .vendor         = PCI_VENDOR_ID_NI,
1199                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1200                 .subvendor      = PCI_ANY_ID,
1201                 .subdevice      = PCI_ANY_ID,
1202                 .init           = pci_ni8420_init,
1203                 .setup          = pci_default_setup,
1204                 .exit           = __devexit_p(pci_ni8420_exit),
1205         },
1206         {
1207                 .vendor         = PCI_VENDOR_ID_NI,
1208                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1209                 .subvendor      = PCI_ANY_ID,
1210                 .subdevice      = PCI_ANY_ID,
1211                 .init           = pci_ni8420_init,
1212                 .setup          = pci_default_setup,
1213                 .exit           = __devexit_p(pci_ni8420_exit),
1214         },
1215         {
1216                 .vendor         = PCI_VENDOR_ID_NI,
1217                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1218                 .subvendor      = PCI_ANY_ID,
1219                 .subdevice      = PCI_ANY_ID,
1220                 .init           = pci_ni8420_init,
1221                 .setup          = pci_default_setup,
1222                 .exit           = __devexit_p(pci_ni8420_exit),
1223         },
1224         {
1225                 .vendor         = PCI_VENDOR_ID_NI,
1226                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1227                 .subvendor      = PCI_ANY_ID,
1228                 .subdevice      = PCI_ANY_ID,
1229                 .init           = pci_ni8420_init,
1230                 .setup          = pci_default_setup,
1231                 .exit           = __devexit_p(pci_ni8420_exit),
1232         },
1233         {
1234                 .vendor         = PCI_VENDOR_ID_NI,
1235                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1236                 .subvendor      = PCI_ANY_ID,
1237                 .subdevice      = PCI_ANY_ID,
1238                 .init           = pci_ni8420_init,
1239                 .setup          = pci_default_setup,
1240                 .exit           = __devexit_p(pci_ni8420_exit),
1241         },
1242         {
1243                 .vendor         = PCI_VENDOR_ID_NI,
1244                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1245                 .subvendor      = PCI_ANY_ID,
1246                 .subdevice      = PCI_ANY_ID,
1247                 .init           = pci_ni8420_init,
1248                 .setup          = pci_default_setup,
1249                 .exit           = __devexit_p(pci_ni8420_exit),
1250         },
1251         {
1252                 .vendor         = PCI_VENDOR_ID_NI,
1253                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1254                 .subvendor      = PCI_ANY_ID,
1255                 .subdevice      = PCI_ANY_ID,
1256                 .init           = pci_ni8420_init,
1257                 .setup          = pci_default_setup,
1258                 .exit           = __devexit_p(pci_ni8420_exit),
1259         },
1260         {
1261                 .vendor         = PCI_VENDOR_ID_NI,
1262                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1263                 .subvendor      = PCI_ANY_ID,
1264                 .subdevice      = PCI_ANY_ID,
1265                 .init           = pci_ni8420_init,
1266                 .setup          = pci_default_setup,
1267                 .exit           = __devexit_p(pci_ni8420_exit),
1268         },
1269         {
1270                 .vendor         = PCI_VENDOR_ID_NI,
1271                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1272                 .subvendor      = PCI_ANY_ID,
1273                 .subdevice      = PCI_ANY_ID,
1274                 .init           = pci_ni8420_init,
1275                 .setup          = pci_default_setup,
1276                 .exit           = __devexit_p(pci_ni8420_exit),
1277         },
1278         {
1279                 .vendor         = PCI_VENDOR_ID_NI,
1280                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1281                 .subvendor      = PCI_ANY_ID,
1282                 .subdevice      = PCI_ANY_ID,
1283                 .init           = pci_ni8420_init,
1284                 .setup          = pci_default_setup,
1285                 .exit           = __devexit_p(pci_ni8420_exit),
1286         },
1287         {
1288                 .vendor         = PCI_VENDOR_ID_NI,
1289                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1290                 .subvendor      = PCI_ANY_ID,
1291                 .subdevice      = PCI_ANY_ID,
1292                 .init           = pci_ni8420_init,
1293                 .setup          = pci_default_setup,
1294                 .exit           = __devexit_p(pci_ni8420_exit),
1295         },
1296         {
1297                 .vendor         = PCI_VENDOR_ID_NI,
1298                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1299                 .subvendor      = PCI_ANY_ID,
1300                 .subdevice      = PCI_ANY_ID,
1301                 .init           = pci_ni8420_init,
1302                 .setup          = pci_default_setup,
1303                 .exit           = __devexit_p(pci_ni8420_exit),
1304         },
1305         {
1306                 .vendor         = PCI_VENDOR_ID_NI,
1307                 .device         = PCI_ANY_ID,
1308                 .subvendor      = PCI_ANY_ID,
1309                 .subdevice      = PCI_ANY_ID,
1310                 .init           = pci_ni8430_init,
1311                 .setup          = pci_ni8430_setup,
1312                 .exit           = __devexit_p(pci_ni8430_exit),
1313         },
1314         /*
1315          * Panacom
1316          */
1317         {
1318                 .vendor         = PCI_VENDOR_ID_PANACOM,
1319                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1320                 .subvendor      = PCI_ANY_ID,
1321                 .subdevice      = PCI_ANY_ID,
1322                 .init           = pci_plx9050_init,
1323                 .setup          = pci_default_setup,
1324                 .exit           = __devexit_p(pci_plx9050_exit),
1325         },
1326         {
1327                 .vendor         = PCI_VENDOR_ID_PANACOM,
1328                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1329                 .subvendor      = PCI_ANY_ID,
1330                 .subdevice      = PCI_ANY_ID,
1331                 .init           = pci_plx9050_init,
1332                 .setup          = pci_default_setup,
1333                 .exit           = __devexit_p(pci_plx9050_exit),
1334         },
1335         /*
1336          * PLX
1337          */
1338         {
1339                 .vendor         = PCI_VENDOR_ID_PLX,
1340                 .device         = PCI_DEVICE_ID_PLX_9030,
1341                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1342                 .subdevice      = PCI_ANY_ID,
1343                 .setup          = pci_default_setup,
1344         },
1345         {
1346                 .vendor         = PCI_VENDOR_ID_PLX,
1347                 .device         = PCI_DEVICE_ID_PLX_9050,
1348                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1349                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1350                 .init           = pci_plx9050_init,
1351                 .setup          = pci_default_setup,
1352                 .exit           = __devexit_p(pci_plx9050_exit),
1353         },
1354         {
1355                 .vendor         = PCI_VENDOR_ID_PLX,
1356                 .device         = PCI_DEVICE_ID_PLX_9050,
1357                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1358                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1359                 .init           = pci_plx9050_init,
1360                 .setup          = pci_default_setup,
1361                 .exit           = __devexit_p(pci_plx9050_exit),
1362         },
1363         {
1364                 .vendor         = PCI_VENDOR_ID_PLX,
1365                 .device         = PCI_DEVICE_ID_PLX_9050,
1366                 .subvendor      = PCI_VENDOR_ID_PLX,
1367                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1368                 .init           = pci_plx9050_init,
1369                 .setup          = pci_default_setup,
1370                 .exit           = __devexit_p(pci_plx9050_exit),
1371         },
1372         {
1373                 .vendor         = PCI_VENDOR_ID_PLX,
1374                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1375                 .subvendor      = PCI_VENDOR_ID_PLX,
1376                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1377                 .init           = pci_plx9050_init,
1378                 .setup          = pci_default_setup,
1379                 .exit           = __devexit_p(pci_plx9050_exit),
1380         },
1381         /*
1382          * SBS Technologies, Inc., PMC-OCTALPRO 232
1383          */
1384         {
1385                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1386                 .device         = PCI_DEVICE_ID_OCTPRO,
1387                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1388                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1389                 .init           = sbs_init,
1390                 .setup          = sbs_setup,
1391                 .exit           = __devexit_p(sbs_exit),
1392         },
1393         /*
1394          * SBS Technologies, Inc., PMC-OCTALPRO 422
1395          */
1396         {
1397                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1398                 .device         = PCI_DEVICE_ID_OCTPRO,
1399                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1400                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1401                 .init           = sbs_init,
1402                 .setup          = sbs_setup,
1403                 .exit           = __devexit_p(sbs_exit),
1404         },
1405         /*
1406          * SBS Technologies, Inc., P-Octal 232
1407          */
1408         {
1409                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1410                 .device         = PCI_DEVICE_ID_OCTPRO,
1411                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1412                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1413                 .init           = sbs_init,
1414                 .setup          = sbs_setup,
1415                 .exit           = __devexit_p(sbs_exit),
1416         },
1417         /*
1418          * SBS Technologies, Inc., P-Octal 422
1419          */
1420         {
1421                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1422                 .device         = PCI_DEVICE_ID_OCTPRO,
1423                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1424                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1425                 .init           = sbs_init,
1426                 .setup          = sbs_setup,
1427                 .exit           = __devexit_p(sbs_exit),
1428         },
1429         /*
1430          * SIIG cards - these may be called via parport_serial
1431          */
1432         {
1433                 .vendor         = PCI_VENDOR_ID_SIIG,
1434                 .device         = PCI_ANY_ID,
1435                 .subvendor      = PCI_ANY_ID,
1436                 .subdevice      = PCI_ANY_ID,
1437                 .init           = pci_siig_init,
1438                 .setup          = pci_siig_setup,
1439         },
1440         /*
1441          * Titan cards
1442          */
1443         {
1444                 .vendor         = PCI_VENDOR_ID_TITAN,
1445                 .device         = PCI_DEVICE_ID_TITAN_400L,
1446                 .subvendor      = PCI_ANY_ID,
1447                 .subdevice      = PCI_ANY_ID,
1448                 .setup          = titan_400l_800l_setup,
1449         },
1450         {
1451                 .vendor         = PCI_VENDOR_ID_TITAN,
1452                 .device         = PCI_DEVICE_ID_TITAN_800L,
1453                 .subvendor      = PCI_ANY_ID,
1454                 .subdevice      = PCI_ANY_ID,
1455                 .setup          = titan_400l_800l_setup,
1456         },
1457         /*
1458          * Timedia cards
1459          */
1460         {
1461                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1462                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1463                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1464                 .subdevice      = PCI_ANY_ID,
1465                 .init           = pci_timedia_init,
1466                 .setup          = pci_timedia_setup,
1467         },
1468         {
1469                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1470                 .device         = PCI_ANY_ID,
1471                 .subvendor      = PCI_ANY_ID,
1472                 .subdevice      = PCI_ANY_ID,
1473                 .setup          = pci_timedia_setup,
1474         },
1475         /*
1476          * Xircom cards
1477          */
1478         {
1479                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1480                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1481                 .subvendor      = PCI_ANY_ID,
1482                 .subdevice      = PCI_ANY_ID,
1483                 .init           = pci_xircom_init,
1484                 .setup          = pci_default_setup,
1485         },
1486         /*
1487          * Netmos cards - these may be called via parport_serial
1488          */
1489         {
1490                 .vendor         = PCI_VENDOR_ID_NETMOS,
1491                 .device         = PCI_ANY_ID,
1492                 .subvendor      = PCI_ANY_ID,
1493                 .subdevice      = PCI_ANY_ID,
1494                 .init           = pci_netmos_init,
1495                 .setup          = pci_netmos_9900_setup,
1496         },
1497         /*
1498          * For Oxford Semiconductor Tornado based devices
1499          */
1500         {
1501                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1502                 .device         = PCI_ANY_ID,
1503                 .subvendor      = PCI_ANY_ID,
1504                 .subdevice      = PCI_ANY_ID,
1505                 .init           = pci_oxsemi_tornado_init,
1506                 .setup          = pci_default_setup,
1507         },
1508         {
1509                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1510                 .device         = PCI_ANY_ID,
1511                 .subvendor      = PCI_ANY_ID,
1512                 .subdevice      = PCI_ANY_ID,
1513                 .init           = pci_oxsemi_tornado_init,
1514                 .setup          = pci_default_setup,
1515         },
1516         {
1517                 .vendor         = PCI_VENDOR_ID_DIGI,
1518                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1519                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1520                 .subdevice              = PCI_ANY_ID,
1521                 .init                   = pci_oxsemi_tornado_init,
1522                 .setup          = pci_default_setup,
1523         },
1524         /*
1525          * Cronyx Omega PCI (PLX-chip based)
1526          */
1527         {
1528                 .vendor         = PCI_VENDOR_ID_PLX,
1529                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1530                 .subvendor      = PCI_ANY_ID,
1531                 .subdevice      = PCI_ANY_ID,
1532                 .setup          = pci_omegapci_setup,
1533          },
1534         /*
1535          * Default "match everything" terminator entry
1536          */
1537         {
1538                 .vendor         = PCI_ANY_ID,
1539                 .device         = PCI_ANY_ID,
1540                 .subvendor      = PCI_ANY_ID,
1541                 .subdevice      = PCI_ANY_ID,
1542                 .setup          = pci_default_setup,
1543         }
1544 };
1545
1546 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1547 {
1548         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1549 }
1550
1551 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1552 {
1553         struct pci_serial_quirk *quirk;
1554
1555         for (quirk = pci_serial_quirks; ; quirk++)
1556                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1557                     quirk_id_matches(quirk->device, dev->device) &&
1558                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1559                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1560                         break;
1561         return quirk;
1562 }
1563
1564 static inline int get_pci_irq(struct pci_dev *dev,
1565                                 const struct pciserial_board *board)
1566 {
1567         if (board->flags & FL_NOIRQ)
1568                 return 0;
1569         else
1570                 return dev->irq;
1571 }
1572
1573 /*
1574  * This is the configuration table for all of the PCI serial boards
1575  * which we support.  It is directly indexed by the pci_board_num_t enum
1576  * value, which is encoded in the pci_device_id PCI probe table's
1577  * driver_data member.
1578  *
1579  * The makeup of these names are:
1580  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1581  *
1582  *  bn          = PCI BAR number
1583  *  bt          = Index using PCI BARs
1584  *  n           = number of serial ports
1585  *  baud        = baud rate
1586  *  offsetinhex = offset for each sequential port (in hex)
1587  *
1588  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1589  *
1590  * Please note: in theory if n = 1, _bt infix should make no difference.
1591  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1592  */
1593 enum pci_board_num_t {
1594         pbn_default = 0,
1595
1596         pbn_b0_1_115200,
1597         pbn_b0_2_115200,
1598         pbn_b0_4_115200,
1599         pbn_b0_5_115200,
1600         pbn_b0_8_115200,
1601
1602         pbn_b0_1_921600,
1603         pbn_b0_2_921600,
1604         pbn_b0_4_921600,
1605
1606         pbn_b0_2_1130000,
1607
1608         pbn_b0_4_1152000,
1609
1610         pbn_b0_2_1843200,
1611         pbn_b0_4_1843200,
1612
1613         pbn_b0_2_1843200_200,
1614         pbn_b0_4_1843200_200,
1615         pbn_b0_8_1843200_200,
1616
1617         pbn_b0_1_4000000,
1618
1619         pbn_b0_bt_1_115200,
1620         pbn_b0_bt_2_115200,
1621         pbn_b0_bt_4_115200,
1622         pbn_b0_bt_8_115200,
1623
1624         pbn_b0_bt_1_460800,
1625         pbn_b0_bt_2_460800,
1626         pbn_b0_bt_4_460800,
1627
1628         pbn_b0_bt_1_921600,
1629         pbn_b0_bt_2_921600,
1630         pbn_b0_bt_4_921600,
1631         pbn_b0_bt_8_921600,
1632
1633         pbn_b1_1_115200,
1634         pbn_b1_2_115200,
1635         pbn_b1_4_115200,
1636         pbn_b1_8_115200,
1637         pbn_b1_16_115200,
1638
1639         pbn_b1_1_921600,
1640         pbn_b1_2_921600,
1641         pbn_b1_4_921600,
1642         pbn_b1_8_921600,
1643
1644         pbn_b1_2_1250000,
1645
1646         pbn_b1_bt_1_115200,
1647         pbn_b1_bt_2_115200,
1648         pbn_b1_bt_4_115200,
1649
1650         pbn_b1_bt_2_921600,
1651
1652         pbn_b1_1_1382400,
1653         pbn_b1_2_1382400,
1654         pbn_b1_4_1382400,
1655         pbn_b1_8_1382400,
1656
1657         pbn_b2_1_115200,
1658         pbn_b2_2_115200,
1659         pbn_b2_4_115200,
1660         pbn_b2_8_115200,
1661
1662         pbn_b2_1_460800,
1663         pbn_b2_4_460800,
1664         pbn_b2_8_460800,
1665         pbn_b2_16_460800,
1666
1667         pbn_b2_1_921600,
1668         pbn_b2_4_921600,
1669         pbn_b2_8_921600,
1670
1671         pbn_b2_8_1152000,
1672
1673         pbn_b2_bt_1_115200,
1674         pbn_b2_bt_2_115200,
1675         pbn_b2_bt_4_115200,
1676
1677         pbn_b2_bt_2_921600,
1678         pbn_b2_bt_4_921600,
1679
1680         pbn_b3_2_115200,
1681         pbn_b3_4_115200,
1682         pbn_b3_8_115200,
1683
1684         pbn_b4_bt_2_921600,
1685         pbn_b4_bt_4_921600,
1686         pbn_b4_bt_8_921600,
1687
1688         /*
1689          * Board-specific versions.
1690          */
1691         pbn_panacom,
1692         pbn_panacom2,
1693         pbn_panacom4,
1694         pbn_exsys_4055,
1695         pbn_plx_romulus,
1696         pbn_oxsemi,
1697         pbn_oxsemi_1_4000000,
1698         pbn_oxsemi_2_4000000,
1699         pbn_oxsemi_4_4000000,
1700         pbn_oxsemi_8_4000000,
1701         pbn_intel_i960,
1702         pbn_sgi_ioc3,
1703         pbn_computone_4,
1704         pbn_computone_6,
1705         pbn_computone_8,
1706         pbn_sbsxrsio,
1707         pbn_exar_XR17C152,
1708         pbn_exar_XR17C154,
1709         pbn_exar_XR17C158,
1710         pbn_exar_ibm_saturn,
1711         pbn_pasemi_1682M,
1712         pbn_ni8430_2,
1713         pbn_ni8430_4,
1714         pbn_ni8430_8,
1715         pbn_ni8430_16,
1716         pbn_ADDIDATA_PCIe_1_3906250,
1717         pbn_ADDIDATA_PCIe_2_3906250,
1718         pbn_ADDIDATA_PCIe_4_3906250,
1719         pbn_ADDIDATA_PCIe_8_3906250,
1720         pbn_ce4100_1_115200,
1721         pbn_omegapci,
1722         pbn_NETMOS9900_2s_115200,
1723 };
1724
1725 /*
1726  * uart_offset - the space between channels
1727  * reg_shift   - describes how the UART registers are mapped
1728  *               to PCI memory by the card.
1729  * For example IER register on SBS, Inc. PMC-OctPro is located at
1730  * offset 0x10 from the UART base, while UART_IER is defined as 1
1731  * in include/linux/serial_reg.h,
1732  * see first lines of serial_in() and serial_out() in 8250.c
1733 */
1734
1735 static struct pciserial_board pci_boards[] __devinitdata = {
1736         [pbn_default] = {
1737                 .flags          = FL_BASE0,
1738                 .num_ports      = 1,
1739                 .base_baud      = 115200,
1740                 .uart_offset    = 8,
1741         },
1742         [pbn_b0_1_115200] = {
1743                 .flags          = FL_BASE0,
1744                 .num_ports      = 1,
1745                 .base_baud      = 115200,
1746                 .uart_offset    = 8,
1747         },
1748         [pbn_b0_2_115200] = {
1749                 .flags          = FL_BASE0,
1750                 .num_ports      = 2,
1751                 .base_baud      = 115200,
1752                 .uart_offset    = 8,
1753         },
1754         [pbn_b0_4_115200] = {
1755                 .flags          = FL_BASE0,
1756                 .num_ports      = 4,
1757                 .base_baud      = 115200,
1758                 .uart_offset    = 8,
1759         },
1760         [pbn_b0_5_115200] = {
1761                 .flags          = FL_BASE0,
1762                 .num_ports      = 5,
1763                 .base_baud      = 115200,
1764                 .uart_offset    = 8,
1765         },
1766         [pbn_b0_8_115200] = {
1767                 .flags          = FL_BASE0,
1768                 .num_ports      = 8,
1769                 .base_baud      = 115200,
1770                 .uart_offset    = 8,
1771         },
1772         [pbn_b0_1_921600] = {
1773                 .flags          = FL_BASE0,
1774                 .num_ports      = 1,
1775                 .base_baud      = 921600,
1776                 .uart_offset    = 8,
1777         },
1778         [pbn_b0_2_921600] = {
1779                 .flags          = FL_BASE0,
1780                 .num_ports      = 2,
1781                 .base_baud      = 921600,
1782                 .uart_offset    = 8,
1783         },
1784         [pbn_b0_4_921600] = {
1785                 .flags          = FL_BASE0,
1786                 .num_ports      = 4,
1787                 .base_baud      = 921600,
1788                 .uart_offset    = 8,
1789         },
1790
1791         [pbn_b0_2_1130000] = {
1792                 .flags          = FL_BASE0,
1793                 .num_ports      = 2,
1794                 .base_baud      = 1130000,
1795                 .uart_offset    = 8,
1796         },
1797
1798         [pbn_b0_4_1152000] = {
1799                 .flags          = FL_BASE0,
1800                 .num_ports      = 4,
1801                 .base_baud      = 1152000,
1802                 .uart_offset    = 8,
1803         },
1804
1805         [pbn_b0_2_1843200] = {
1806                 .flags          = FL_BASE0,
1807                 .num_ports      = 2,
1808                 .base_baud      = 1843200,
1809                 .uart_offset    = 8,
1810         },
1811         [pbn_b0_4_1843200] = {
1812                 .flags          = FL_BASE0,
1813                 .num_ports      = 4,
1814                 .base_baud      = 1843200,
1815                 .uart_offset    = 8,
1816         },
1817
1818         [pbn_b0_2_1843200_200] = {
1819                 .flags          = FL_BASE0,
1820                 .num_ports      = 2,
1821                 .base_baud      = 1843200,
1822                 .uart_offset    = 0x200,
1823         },
1824         [pbn_b0_4_1843200_200] = {
1825                 .flags          = FL_BASE0,
1826                 .num_ports      = 4,
1827                 .base_baud      = 1843200,
1828                 .uart_offset    = 0x200,
1829         },
1830         [pbn_b0_8_1843200_200] = {
1831                 .flags          = FL_BASE0,
1832                 .num_ports      = 8,
1833                 .base_baud      = 1843200,
1834                 .uart_offset    = 0x200,
1835         },
1836         [pbn_b0_1_4000000] = {
1837                 .flags          = FL_BASE0,
1838                 .num_ports      = 1,
1839                 .base_baud      = 4000000,
1840                 .uart_offset    = 8,
1841         },
1842
1843         [pbn_b0_bt_1_115200] = {
1844                 .flags          = FL_BASE0|FL_BASE_BARS,
1845                 .num_ports      = 1,
1846                 .base_baud      = 115200,
1847                 .uart_offset    = 8,
1848         },
1849         [pbn_b0_bt_2_115200] = {
1850                 .flags          = FL_BASE0|FL_BASE_BARS,
1851                 .num_ports      = 2,
1852                 .base_baud      = 115200,
1853                 .uart_offset    = 8,
1854         },
1855         [pbn_b0_bt_4_115200] = {
1856                 .flags          = FL_BASE0|FL_BASE_BARS,
1857                 .num_ports      = 4,
1858                 .base_baud      = 115200,
1859                 .uart_offset    = 8,
1860         },
1861         [pbn_b0_bt_8_115200] = {
1862                 .flags          = FL_BASE0|FL_BASE_BARS,
1863                 .num_ports      = 8,
1864                 .base_baud      = 115200,
1865                 .uart_offset    = 8,
1866         },
1867
1868         [pbn_b0_bt_1_460800] = {
1869                 .flags          = FL_BASE0|FL_BASE_BARS,
1870                 .num_ports      = 1,
1871                 .base_baud      = 460800,
1872                 .uart_offset    = 8,
1873         },
1874         [pbn_b0_bt_2_460800] = {
1875                 .flags          = FL_BASE0|FL_BASE_BARS,
1876                 .num_ports      = 2,
1877                 .base_baud      = 460800,
1878                 .uart_offset    = 8,
1879         },
1880         [pbn_b0_bt_4_460800] = {
1881                 .flags          = FL_BASE0|FL_BASE_BARS,
1882                 .num_ports      = 4,
1883                 .base_baud      = 460800,
1884                 .uart_offset    = 8,
1885         },
1886
1887         [pbn_b0_bt_1_921600] = {
1888                 .flags          = FL_BASE0|FL_BASE_BARS,
1889                 .num_ports      = 1,
1890                 .base_baud      = 921600,
1891                 .uart_offset    = 8,
1892         },
1893         [pbn_b0_bt_2_921600] = {
1894                 .flags          = FL_BASE0|FL_BASE_BARS,
1895                 .num_ports      = 2,
1896                 .base_baud      = 921600,
1897                 .uart_offset    = 8,
1898         },
1899         [pbn_b0_bt_4_921600] = {
1900                 .flags          = FL_BASE0|FL_BASE_BARS,
1901                 .num_ports      = 4,
1902                 .base_baud      = 921600,
1903                 .uart_offset    = 8,
1904         },
1905         [pbn_b0_bt_8_921600] = {
1906                 .flags          = FL_BASE0|FL_BASE_BARS,
1907                 .num_ports      = 8,
1908                 .base_baud      = 921600,
1909                 .uart_offset    = 8,
1910         },
1911
1912         [pbn_b1_1_115200] = {
1913                 .flags          = FL_BASE1,
1914                 .num_ports      = 1,
1915                 .base_baud      = 115200,
1916                 .uart_offset    = 8,
1917         },
1918         [pbn_b1_2_115200] = {
1919                 .flags          = FL_BASE1,
1920                 .num_ports      = 2,
1921                 .base_baud      = 115200,
1922                 .uart_offset    = 8,
1923         },
1924         [pbn_b1_4_115200] = {
1925                 .flags          = FL_BASE1,
1926                 .num_ports      = 4,
1927                 .base_baud      = 115200,
1928                 .uart_offset    = 8,
1929         },
1930         [pbn_b1_8_115200] = {
1931                 .flags          = FL_BASE1,
1932                 .num_ports      = 8,
1933                 .base_baud      = 115200,
1934                 .uart_offset    = 8,
1935         },
1936         [pbn_b1_16_115200] = {
1937                 .flags          = FL_BASE1,
1938                 .num_ports      = 16,
1939                 .base_baud      = 115200,
1940                 .uart_offset    = 8,
1941         },
1942
1943         [pbn_b1_1_921600] = {
1944                 .flags          = FL_BASE1,
1945                 .num_ports      = 1,
1946                 .base_baud      = 921600,
1947                 .uart_offset    = 8,
1948         },
1949         [pbn_b1_2_921600] = {
1950                 .flags          = FL_BASE1,
1951                 .num_ports      = 2,
1952                 .base_baud      = 921600,
1953                 .uart_offset    = 8,
1954         },
1955         [pbn_b1_4_921600] = {
1956                 .flags          = FL_BASE1,
1957                 .num_ports      = 4,
1958                 .base_baud      = 921600,
1959                 .uart_offset    = 8,
1960         },
1961         [pbn_b1_8_921600] = {
1962                 .flags          = FL_BASE1,
1963                 .num_ports      = 8,
1964                 .base_baud      = 921600,
1965                 .uart_offset    = 8,
1966         },
1967         [pbn_b1_2_1250000] = {
1968                 .flags          = FL_BASE1,
1969                 .num_ports      = 2,
1970                 .base_baud      = 1250000,
1971                 .uart_offset    = 8,
1972         },
1973
1974         [pbn_b1_bt_1_115200] = {
1975                 .flags          = FL_BASE1|FL_BASE_BARS,
1976                 .num_ports      = 1,
1977                 .base_baud      = 115200,
1978                 .uart_offset    = 8,
1979         },
1980         [pbn_b1_bt_2_115200] = {
1981                 .flags          = FL_BASE1|FL_BASE_BARS,
1982                 .num_ports      = 2,
1983                 .base_baud      = 115200,
1984                 .uart_offset    = 8,
1985         },
1986         [pbn_b1_bt_4_115200] = {
1987                 .flags          = FL_BASE1|FL_BASE_BARS,
1988                 .num_ports      = 4,
1989                 .base_baud      = 115200,
1990                 .uart_offset    = 8,
1991         },
1992
1993         [pbn_b1_bt_2_921600] = {
1994                 .flags          = FL_BASE1|FL_BASE_BARS,
1995                 .num_ports      = 2,
1996                 .base_baud      = 921600,
1997                 .uart_offset    = 8,
1998         },
1999
2000         [pbn_b1_1_1382400] = {
2001                 .flags          = FL_BASE1,
2002                 .num_ports      = 1,
2003                 .base_baud      = 1382400,
2004                 .uart_offset    = 8,
2005         },
2006         [pbn_b1_2_1382400] = {
2007                 .flags          = FL_BASE1,
2008                 .num_ports      = 2,
2009                 .base_baud      = 1382400,
2010                 .uart_offset    = 8,
2011         },
2012         [pbn_b1_4_1382400] = {
2013                 .flags          = FL_BASE1,
2014                 .num_ports      = 4,
2015                 .base_baud      = 1382400,
2016                 .uart_offset    = 8,
2017         },
2018         [pbn_b1_8_1382400] = {
2019                 .flags          = FL_BASE1,
2020                 .num_ports      = 8,
2021                 .base_baud      = 1382400,
2022                 .uart_offset    = 8,
2023         },
2024
2025         [pbn_b2_1_115200] = {
2026                 .flags          = FL_BASE2,
2027                 .num_ports      = 1,
2028                 .base_baud      = 115200,
2029                 .uart_offset    = 8,
2030         },
2031         [pbn_b2_2_115200] = {
2032                 .flags          = FL_BASE2,
2033                 .num_ports      = 2,
2034                 .base_baud      = 115200,
2035                 .uart_offset    = 8,
2036         },
2037         [pbn_b2_4_115200] = {
2038                 .flags          = FL_BASE2,
2039                 .num_ports      = 4,
2040                 .base_baud      = 115200,
2041                 .uart_offset    = 8,
2042         },
2043         [pbn_b2_8_115200] = {
2044                 .flags          = FL_BASE2,
2045                 .num_ports      = 8,
2046                 .base_baud      = 115200,
2047                 .uart_offset    = 8,
2048         },
2049
2050         [pbn_b2_1_460800] = {
2051                 .flags          = FL_BASE2,
2052                 .num_ports      = 1,
2053                 .base_baud      = 460800,
2054                 .uart_offset    = 8,
2055         },
2056         [pbn_b2_4_460800] = {
2057                 .flags          = FL_BASE2,
2058                 .num_ports      = 4,
2059                 .base_baud      = 460800,
2060                 .uart_offset    = 8,
2061         },
2062         [pbn_b2_8_460800] = {
2063                 .flags          = FL_BASE2,
2064                 .num_ports      = 8,
2065                 .base_baud      = 460800,
2066                 .uart_offset    = 8,
2067         },
2068         [pbn_b2_16_460800] = {
2069                 .flags          = FL_BASE2,
2070                 .num_ports      = 16,
2071                 .base_baud      = 460800,
2072                 .uart_offset    = 8,
2073          },
2074
2075         [pbn_b2_1_921600] = {
2076                 .flags          = FL_BASE2,
2077                 .num_ports      = 1,
2078                 .base_baud      = 921600,
2079                 .uart_offset    = 8,
2080         },
2081         [pbn_b2_4_921600] = {
2082                 .flags          = FL_BASE2,
2083                 .num_ports      = 4,
2084                 .base_baud      = 921600,
2085                 .uart_offset    = 8,
2086         },
2087         [pbn_b2_8_921600] = {
2088                 .flags          = FL_BASE2,
2089                 .num_ports      = 8,
2090                 .base_baud      = 921600,
2091                 .uart_offset    = 8,
2092         },
2093
2094         [pbn_b2_8_1152000] = {
2095                 .flags          = FL_BASE2,
2096                 .num_ports      = 8,
2097                 .base_baud      = 1152000,
2098                 .uart_offset    = 8,
2099         },
2100
2101         [pbn_b2_bt_1_115200] = {
2102                 .flags          = FL_BASE2|FL_BASE_BARS,
2103                 .num_ports      = 1,
2104                 .base_baud      = 115200,
2105                 .uart_offset    = 8,
2106         },
2107         [pbn_b2_bt_2_115200] = {
2108                 .flags          = FL_BASE2|FL_BASE_BARS,
2109                 .num_ports      = 2,
2110                 .base_baud      = 115200,
2111                 .uart_offset    = 8,
2112         },
2113         [pbn_b2_bt_4_115200] = {
2114                 .flags          = FL_BASE2|FL_BASE_BARS,
2115                 .num_ports      = 4,
2116                 .base_baud      = 115200,
2117                 .uart_offset    = 8,
2118         },
2119
2120         [pbn_b2_bt_2_921600] = {
2121                 .flags          = FL_BASE2|FL_BASE_BARS,
2122                 .num_ports      = 2,
2123                 .base_baud      = 921600,
2124                 .uart_offset    = 8,
2125         },
2126         [pbn_b2_bt_4_921600] = {
2127                 .flags          = FL_BASE2|FL_BASE_BARS,
2128                 .num_ports      = 4,
2129                 .base_baud      = 921600,
2130                 .uart_offset    = 8,
2131         },
2132
2133         [pbn_b3_2_115200] = {
2134                 .flags          = FL_BASE3,
2135                 .num_ports      = 2,
2136                 .base_baud      = 115200,
2137                 .uart_offset    = 8,
2138         },
2139         [pbn_b3_4_115200] = {
2140                 .flags          = FL_BASE3,
2141                 .num_ports      = 4,
2142                 .base_baud      = 115200,
2143                 .uart_offset    = 8,
2144         },
2145         [pbn_b3_8_115200] = {
2146                 .flags          = FL_BASE3,
2147                 .num_ports      = 8,
2148                 .base_baud      = 115200,
2149                 .uart_offset    = 8,
2150         },
2151
2152         [pbn_b4_bt_2_921600] = {
2153                 .flags          = FL_BASE4,
2154                 .num_ports      = 2,
2155                 .base_baud      = 921600,
2156                 .uart_offset    = 8,
2157         },
2158         [pbn_b4_bt_4_921600] = {
2159                 .flags          = FL_BASE4,
2160                 .num_ports      = 4,
2161                 .base_baud      = 921600,
2162                 .uart_offset    = 8,
2163         },
2164         [pbn_b4_bt_8_921600] = {
2165                 .flags          = FL_BASE4,
2166                 .num_ports      = 8,
2167                 .base_baud      = 921600,
2168                 .uart_offset    = 8,
2169         },
2170
2171         /*
2172          * Entries following this are board-specific.
2173          */
2174
2175         /*
2176          * Panacom - IOMEM
2177          */
2178         [pbn_panacom] = {
2179                 .flags          = FL_BASE2,
2180                 .num_ports      = 2,
2181                 .base_baud      = 921600,
2182                 .uart_offset    = 0x400,
2183                 .reg_shift      = 7,
2184         },
2185         [pbn_panacom2] = {
2186                 .flags          = FL_BASE2|FL_BASE_BARS,
2187                 .num_ports      = 2,
2188                 .base_baud      = 921600,
2189                 .uart_offset    = 0x400,
2190                 .reg_shift      = 7,
2191         },
2192         [pbn_panacom4] = {
2193                 .flags          = FL_BASE2|FL_BASE_BARS,
2194                 .num_ports      = 4,
2195                 .base_baud      = 921600,
2196                 .uart_offset    = 0x400,
2197                 .reg_shift      = 7,
2198         },
2199
2200         [pbn_exsys_4055] = {
2201                 .flags          = FL_BASE2,
2202                 .num_ports      = 4,
2203                 .base_baud      = 115200,
2204                 .uart_offset    = 8,
2205         },
2206
2207         /* I think this entry is broken - the first_offset looks wrong --rmk */
2208         [pbn_plx_romulus] = {
2209                 .flags          = FL_BASE2,
2210                 .num_ports      = 4,
2211                 .base_baud      = 921600,
2212                 .uart_offset    = 8 << 2,
2213                 .reg_shift      = 2,
2214                 .first_offset   = 0x03,
2215         },
2216
2217         /*
2218          * This board uses the size of PCI Base region 0 to
2219          * signal now many ports are available
2220          */
2221         [pbn_oxsemi] = {
2222                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2223                 .num_ports      = 32,
2224                 .base_baud      = 115200,
2225                 .uart_offset    = 8,
2226         },
2227         [pbn_oxsemi_1_4000000] = {
2228                 .flags          = FL_BASE0,
2229                 .num_ports      = 1,
2230                 .base_baud      = 4000000,
2231                 .uart_offset    = 0x200,
2232                 .first_offset   = 0x1000,
2233         },
2234         [pbn_oxsemi_2_4000000] = {
2235                 .flags          = FL_BASE0,
2236                 .num_ports      = 2,
2237                 .base_baud      = 4000000,
2238                 .uart_offset    = 0x200,
2239                 .first_offset   = 0x1000,
2240         },
2241         [pbn_oxsemi_4_4000000] = {
2242                 .flags          = FL_BASE0,
2243                 .num_ports      = 4,
2244                 .base_baud      = 4000000,
2245                 .uart_offset    = 0x200,
2246                 .first_offset   = 0x1000,
2247         },
2248         [pbn_oxsemi_8_4000000] = {
2249                 .flags          = FL_BASE0,
2250                 .num_ports      = 8,
2251                 .base_baud      = 4000000,
2252                 .uart_offset    = 0x200,
2253                 .first_offset   = 0x1000,
2254         },
2255
2256
2257         /*
2258          * EKF addition for i960 Boards form EKF with serial port.
2259          * Max 256 ports.
2260          */
2261         [pbn_intel_i960] = {
2262                 .flags          = FL_BASE0,
2263                 .num_ports      = 32,
2264                 .base_baud      = 921600,
2265                 .uart_offset    = 8 << 2,
2266                 .reg_shift      = 2,
2267                 .first_offset   = 0x10000,
2268         },
2269         [pbn_sgi_ioc3] = {
2270                 .flags          = FL_BASE0|FL_NOIRQ,
2271                 .num_ports      = 1,
2272                 .base_baud      = 458333,
2273                 .uart_offset    = 8,
2274                 .reg_shift      = 0,
2275                 .first_offset   = 0x20178,
2276         },
2277
2278         /*
2279          * Computone - uses IOMEM.
2280          */
2281         [pbn_computone_4] = {
2282                 .flags          = FL_BASE0,
2283                 .num_ports      = 4,
2284                 .base_baud      = 921600,
2285                 .uart_offset    = 0x40,
2286                 .reg_shift      = 2,
2287                 .first_offset   = 0x200,
2288         },
2289         [pbn_computone_6] = {
2290                 .flags          = FL_BASE0,
2291                 .num_ports      = 6,
2292                 .base_baud      = 921600,
2293                 .uart_offset    = 0x40,
2294                 .reg_shift      = 2,
2295                 .first_offset   = 0x200,
2296         },
2297         [pbn_computone_8] = {
2298                 .flags          = FL_BASE0,
2299                 .num_ports      = 8,
2300                 .base_baud      = 921600,
2301                 .uart_offset    = 0x40,
2302                 .reg_shift      = 2,
2303                 .first_offset   = 0x200,
2304         },
2305         [pbn_sbsxrsio] = {
2306                 .flags          = FL_BASE0,
2307                 .num_ports      = 8,
2308                 .base_baud      = 460800,
2309                 .uart_offset    = 256,
2310                 .reg_shift      = 4,
2311         },
2312         /*
2313          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2314          *  Only basic 16550A support.
2315          *  XR17C15[24] are not tested, but they should work.
2316          */
2317         [pbn_exar_XR17C152] = {
2318                 .flags          = FL_BASE0,
2319                 .num_ports      = 2,
2320                 .base_baud      = 921600,
2321                 .uart_offset    = 0x200,
2322         },
2323         [pbn_exar_XR17C154] = {
2324                 .flags          = FL_BASE0,
2325                 .num_ports      = 4,
2326                 .base_baud      = 921600,
2327                 .uart_offset    = 0x200,
2328         },
2329         [pbn_exar_XR17C158] = {
2330                 .flags          = FL_BASE0,
2331                 .num_ports      = 8,
2332                 .base_baud      = 921600,
2333                 .uart_offset    = 0x200,
2334         },
2335         [pbn_exar_ibm_saturn] = {
2336                 .flags          = FL_BASE0,
2337                 .num_ports      = 1,
2338                 .base_baud      = 921600,
2339                 .uart_offset    = 0x200,
2340         },
2341
2342         /*
2343          * PA Semi PWRficient PA6T-1682M on-chip UART
2344          */
2345         [pbn_pasemi_1682M] = {
2346                 .flags          = FL_BASE0,
2347                 .num_ports      = 1,
2348                 .base_baud      = 8333333,
2349         },
2350         /*
2351          * National Instruments 843x
2352          */
2353         [pbn_ni8430_16] = {
2354                 .flags          = FL_BASE0,
2355                 .num_ports      = 16,
2356                 .base_baud      = 3686400,
2357                 .uart_offset    = 0x10,
2358                 .first_offset   = 0x800,
2359         },
2360         [pbn_ni8430_8] = {
2361                 .flags          = FL_BASE0,
2362                 .num_ports      = 8,
2363                 .base_baud      = 3686400,
2364                 .uart_offset    = 0x10,
2365                 .first_offset   = 0x800,
2366         },
2367         [pbn_ni8430_4] = {
2368                 .flags          = FL_BASE0,
2369                 .num_ports      = 4,
2370                 .base_baud      = 3686400,
2371                 .uart_offset    = 0x10,
2372                 .first_offset   = 0x800,
2373         },
2374         [pbn_ni8430_2] = {
2375                 .flags          = FL_BASE0,
2376                 .num_ports      = 2,
2377                 .base_baud      = 3686400,
2378                 .uart_offset    = 0x10,
2379                 .first_offset   = 0x800,
2380         },
2381         /*
2382          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2383          */
2384         [pbn_ADDIDATA_PCIe_1_3906250] = {
2385                 .flags          = FL_BASE0,
2386                 .num_ports      = 1,
2387                 .base_baud      = 3906250,
2388                 .uart_offset    = 0x200,
2389                 .first_offset   = 0x1000,
2390         },
2391         [pbn_ADDIDATA_PCIe_2_3906250] = {
2392                 .flags          = FL_BASE0,
2393                 .num_ports      = 2,
2394                 .base_baud      = 3906250,
2395                 .uart_offset    = 0x200,
2396                 .first_offset   = 0x1000,
2397         },
2398         [pbn_ADDIDATA_PCIe_4_3906250] = {
2399                 .flags          = FL_BASE0,
2400                 .num_ports      = 4,
2401                 .base_baud      = 3906250,
2402                 .uart_offset    = 0x200,
2403                 .first_offset   = 0x1000,
2404         },
2405         [pbn_ADDIDATA_PCIe_8_3906250] = {
2406                 .flags          = FL_BASE0,
2407                 .num_ports      = 8,
2408                 .base_baud      = 3906250,
2409                 .uart_offset    = 0x200,
2410                 .first_offset   = 0x1000,
2411         },
2412         [pbn_ce4100_1_115200] = {
2413                 .flags          = FL_BASE0,
2414                 .num_ports      = 1,
2415                 .base_baud      = 921600,
2416                 .reg_shift      = 2,
2417         },
2418         [pbn_omegapci] = {
2419                 .flags          = FL_BASE0,
2420                 .num_ports      = 8,
2421                 .base_baud      = 115200,
2422                 .uart_offset    = 0x200,
2423         },
2424         [pbn_NETMOS9900_2s_115200] = {
2425                 .flags          = FL_BASE0,
2426                 .num_ports      = 2,
2427                 .base_baud      = 115200,
2428         },
2429 };
2430
2431 static const struct pci_device_id softmodem_blacklist[] = {
2432         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2433         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2434         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2435 };
2436
2437 /*
2438  * Given a complete unknown PCI device, try to use some heuristics to
2439  * guess what the configuration might be, based on the pitiful PCI
2440  * serial specs.  Returns 0 on success, 1 on failure.
2441  */
2442 static int __devinit
2443 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2444 {
2445         const struct pci_device_id *blacklist;
2446         int num_iomem, num_port, first_port = -1, i;
2447
2448         /*
2449          * If it is not a communications device or the programming
2450          * interface is greater than 6, give up.
2451          *
2452          * (Should we try to make guesses for multiport serial devices
2453          * later?)
2454          */
2455         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2456              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2457             (dev->class & 0xff) > 6)
2458                 return -ENODEV;
2459
2460         /*
2461          * Do not access blacklisted devices that are known not to
2462          * feature serial ports.
2463          */
2464         for (blacklist = softmodem_blacklist;
2465              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2466              blacklist++) {
2467                 if (dev->vendor == blacklist->vendor &&
2468                     dev->device == blacklist->device)
2469                         return -ENODEV;
2470         }
2471
2472         num_iomem = num_port = 0;
2473         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2474                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2475                         num_port++;
2476                         if (first_port == -1)
2477                                 first_port = i;
2478                 }
2479                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2480                         num_iomem++;
2481         }
2482
2483         /*
2484          * If there is 1 or 0 iomem regions, and exactly one port,
2485          * use it.  We guess the number of ports based on the IO
2486          * region size.
2487          */
2488         if (num_iomem <= 1 && num_port == 1) {
2489                 board->flags = first_port;
2490                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2491                 return 0;
2492         }
2493
2494         /*
2495          * Now guess if we've got a board which indexes by BARs.
2496          * Each IO BAR should be 8 bytes, and they should follow
2497          * consecutively.
2498          */
2499         first_port = -1;
2500         num_port = 0;
2501         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2502                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2503                     pci_resource_len(dev, i) == 8 &&
2504                     (first_port == -1 || (first_port + num_port) == i)) {
2505                         num_port++;
2506                         if (first_port == -1)
2507                                 first_port = i;
2508                 }
2509         }
2510
2511         if (num_port > 1) {
2512                 board->flags = first_port | FL_BASE_BARS;
2513                 board->num_ports = num_port;
2514                 return 0;
2515         }
2516
2517         return -ENODEV;
2518 }
2519
2520 static inline int
2521 serial_pci_matches(const struct pciserial_board *board,
2522                    const struct pciserial_board *guessed)
2523 {
2524         return
2525             board->num_ports == guessed->num_ports &&
2526             board->base_baud == guessed->base_baud &&
2527             board->uart_offset == guessed->uart_offset &&
2528             board->reg_shift == guessed->reg_shift &&
2529             board->first_offset == guessed->first_offset;
2530 }
2531
2532 struct serial_private *
2533 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2534 {
2535         struct uart_port serial_port;
2536         struct serial_private *priv;
2537         struct pci_serial_quirk *quirk;
2538         int rc, nr_ports, i;
2539
2540         nr_ports = board->num_ports;
2541
2542         /*
2543          * Find an init and setup quirks.
2544          */
2545         quirk = find_quirk(dev);
2546
2547         /*
2548          * Run the new-style initialization function.
2549          * The initialization function returns:
2550          *  <0  - error
2551          *   0  - use board->num_ports
2552          *  >0  - number of ports
2553          */
2554         if (quirk->init) {
2555                 rc = quirk->init(dev);
2556                 if (rc < 0) {
2557                         priv = ERR_PTR(rc);
2558                         goto err_out;
2559                 }
2560                 if (rc)
2561                         nr_ports = rc;
2562         }
2563
2564         priv = kzalloc(sizeof(struct serial_private) +
2565                        sizeof(unsigned int) * nr_ports,
2566                        GFP_KERNEL);
2567         if (!priv) {
2568                 priv = ERR_PTR(-ENOMEM);
2569                 goto err_deinit;
2570         }
2571
2572         priv->dev = dev;
2573         priv->quirk = quirk;
2574
2575         memset(&serial_port, 0, sizeof(struct uart_port));
2576         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2577         serial_port.uartclk = board->base_baud * 16;
2578         serial_port.irq = get_pci_irq(dev, board);
2579         serial_port.dev = &dev->dev;
2580
2581         for (i = 0; i < nr_ports; i++) {
2582                 if (quirk->setup(priv, board, &serial_port, i))
2583                         break;
2584
2585 #ifdef SERIAL_DEBUG_PCI
2586                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2587                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2588 #endif
2589
2590                 priv->line[i] = serial8250_register_port(&serial_port);
2591                 if (priv->line[i] < 0) {
2592                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2593                         break;
2594                 }
2595         }
2596         priv->nr = i;
2597         return priv;
2598
2599 err_deinit:
2600         if (quirk->exit)
2601                 quirk->exit(dev);
2602 err_out:
2603         return priv;
2604 }
2605 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2606
2607 void pciserial_remove_ports(struct serial_private *priv)
2608 {
2609         struct pci_serial_quirk *quirk;
2610         int i;
2611
2612         for (i = 0; i < priv->nr; i++)
2613                 serial8250_unregister_port(priv->line[i]);
2614
2615         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2616                 if (priv->remapped_bar[i])
2617                         iounmap(priv->remapped_bar[i]);
2618                 priv->remapped_bar[i] = NULL;
2619         }
2620
2621         /*
2622          * Find the exit quirks.
2623          */
2624         quirk = find_quirk(priv->dev);
2625         if (quirk->exit)
2626                 quirk->exit(priv->dev);
2627
2628         kfree(priv);
2629 }
2630 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2631
2632 void pciserial_suspend_ports(struct serial_private *priv)
2633 {
2634         int i;
2635
2636         for (i = 0; i < priv->nr; i++)
2637                 if (priv->line[i] >= 0)
2638                         serial8250_suspend_port(priv->line[i]);
2639 }
2640 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2641
2642 void pciserial_resume_ports(struct serial_private *priv)
2643 {
2644         int i;
2645
2646         /*
2647          * Ensure that the board is correctly configured.
2648          */
2649         if (priv->quirk->init)
2650                 priv->quirk->init(priv->dev);
2651
2652         for (i = 0; i < priv->nr; i++)
2653                 if (priv->line[i] >= 0)
2654                         serial8250_resume_port(priv->line[i]);
2655 }
2656 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2657
2658 /*
2659  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2660  * to the arrangement of serial ports on a PCI card.
2661  */
2662 static int __devinit
2663 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2664 {
2665         struct serial_private *priv;
2666         const struct pciserial_board *board;
2667         struct pciserial_board tmp;
2668         int rc;
2669
2670         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2671                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2672                         ent->driver_data);
2673                 return -EINVAL;
2674         }
2675
2676         board = &pci_boards[ent->driver_data];
2677
2678         rc = pci_enable_device(dev);
2679         if (rc)
2680                 return rc;
2681
2682         if (ent->driver_data == pbn_default) {
2683                 /*
2684                  * Use a copy of the pci_board entry for this;
2685                  * avoid changing entries in the table.
2686                  */
2687                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2688                 board = &tmp;
2689
2690                 /*
2691                  * We matched one of our class entries.  Try to
2692                  * determine the parameters of this board.
2693                  */
2694                 rc = serial_pci_guess_board(dev, &tmp);
2695                 if (rc)
2696                         goto disable;
2697         } else {
2698                 /*
2699                  * We matched an explicit entry.  If we are able to
2700                  * detect this boards settings with our heuristic,
2701                  * then we no longer need this entry.
2702                  */
2703                 memcpy(&tmp, &pci_boards[pbn_default],
2704                        sizeof(struct pciserial_board));
2705                 rc = serial_pci_guess_board(dev, &tmp);
2706                 if (rc == 0 && serial_pci_matches(board, &tmp))
2707                         moan_device("Redundant entry in serial pci_table.",
2708                                     dev);
2709         }
2710
2711         priv = pciserial_init_ports(dev, board);
2712         if (!IS_ERR(priv)) {
2713                 pci_set_drvdata(dev, priv);
2714                 return 0;
2715         }
2716
2717         rc = PTR_ERR(priv);
2718
2719  disable:
2720         pci_disable_device(dev);
2721         return rc;
2722 }
2723
2724 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2725 {
2726         struct serial_private *priv = pci_get_drvdata(dev);
2727
2728         pci_set_drvdata(dev, NULL);
2729
2730         pciserial_remove_ports(priv);
2731
2732         pci_disable_device(dev);
2733 }
2734
2735 #ifdef CONFIG_PM
2736 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2737 {
2738         struct serial_private *priv = pci_get_drvdata(dev);
2739
2740         if (priv)
2741                 pciserial_suspend_ports(priv);
2742
2743         pci_save_state(dev);
2744         pci_set_power_state(dev, pci_choose_state(dev, state));
2745         return 0;
2746 }
2747
2748 static int pciserial_resume_one(struct pci_dev *dev)
2749 {
2750         int err;
2751         struct serial_private *priv = pci_get_drvdata(dev);
2752
2753         pci_set_power_state(dev, PCI_D0);
2754         pci_restore_state(dev);
2755
2756         if (priv) {
2757                 /*
2758                  * The device may have been disabled.  Re-enable it.
2759                  */
2760                 err = pci_enable_device(dev);
2761                 /* FIXME: We cannot simply error out here */
2762                 if (err)
2763                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2764                 pciserial_resume_ports(priv);
2765         }
2766         return 0;
2767 }
2768 #endif
2769
2770 static struct pci_device_id serial_pci_tbl[] = {
2771         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2772         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2773                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2774                 pbn_b2_8_921600 },
2775         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2776                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2777                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2778                 pbn_b1_8_1382400 },
2779         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2780                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2781                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2782                 pbn_b1_4_1382400 },
2783         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2784                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2785                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2786                 pbn_b1_2_1382400 },
2787         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2788                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2789                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2790                 pbn_b1_8_1382400 },
2791         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2792                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2793                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2794                 pbn_b1_4_1382400 },
2795         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2796                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2797                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2798                 pbn_b1_2_1382400 },
2799         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2800                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2801                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2802                 pbn_b1_8_921600 },
2803         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2804                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2805                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2806                 pbn_b1_8_921600 },
2807         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2808                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2809                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2810                 pbn_b1_4_921600 },
2811         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2812                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2813                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2814                 pbn_b1_4_921600 },
2815         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2816                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2817                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2818                 pbn_b1_2_921600 },
2819         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2820                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2821                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2822                 pbn_b1_8_921600 },
2823         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2824                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2825                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2826                 pbn_b1_8_921600 },
2827         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2828                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2829                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2830                 pbn_b1_4_921600 },
2831         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2832                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2833                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2834                 pbn_b1_2_1250000 },
2835         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2836                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2837                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2838                 pbn_b0_2_1843200 },
2839         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2840                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2841                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2842                 pbn_b0_4_1843200 },
2843         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2844                 PCI_VENDOR_ID_AFAVLAB,
2845                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2846                 pbn_b0_4_1152000 },
2847         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2848                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2849                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2850                 pbn_b0_2_1843200_200 },
2851         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2852                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2853                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2854                 pbn_b0_4_1843200_200 },
2855         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2856                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2857                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2858                 pbn_b0_8_1843200_200 },
2859         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2860                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2861                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2862                 pbn_b0_2_1843200_200 },
2863         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2864                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2865                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2866                 pbn_b0_4_1843200_200 },
2867         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2868                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2869                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2870                 pbn_b0_8_1843200_200 },
2871         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2872                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2873                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2874                 pbn_b0_2_1843200_200 },
2875         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2876                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2877                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2878                 pbn_b0_4_1843200_200 },
2879         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2880                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2881                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2882                 pbn_b0_8_1843200_200 },
2883         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2884                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2885                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2886                 pbn_b0_2_1843200_200 },
2887         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2888                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2889                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2890                 pbn_b0_4_1843200_200 },
2891         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2892                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2893                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2894                 pbn_b0_8_1843200_200 },
2895         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2896                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2897                 0, 0, pbn_exar_ibm_saturn },
2898
2899         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2900                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2901                 pbn_b2_bt_1_115200 },
2902         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2903                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904                 pbn_b2_bt_2_115200 },
2905         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2906                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907                 pbn_b2_bt_4_115200 },
2908         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910                 pbn_b2_bt_2_115200 },
2911         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913                 pbn_b2_bt_4_115200 },
2914         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916                 pbn_b2_8_115200 },
2917         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2918                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919                 pbn_b2_8_460800 },
2920         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922                 pbn_b2_8_115200 },
2923
2924         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2925                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2926                 pbn_b2_bt_2_115200 },
2927         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2929                 pbn_b2_bt_2_921600 },
2930         /*
2931          * VScom SPCOM800, from sl@s.pl
2932          */
2933         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2935                 pbn_b2_8_921600 },
2936         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2938                 pbn_b2_4_921600 },
2939         /* Unknown card - subdevice 0x1584 */
2940         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2941                 PCI_VENDOR_ID_PLX,
2942                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2943                 pbn_b0_4_115200 },
2944         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2945                 PCI_SUBVENDOR_ID_KEYSPAN,
2946                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2947                 pbn_panacom },
2948         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2950                 pbn_panacom4 },
2951         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2953                 pbn_panacom2 },
2954         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2955                 PCI_VENDOR_ID_ESDGMBH,
2956                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2957                 pbn_b2_4_115200 },
2958         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2959                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2960                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2961                 pbn_b2_4_460800 },
2962         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2963                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2964                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2965                 pbn_b2_8_460800 },
2966         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2967                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2968                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2969                 pbn_b2_16_460800 },
2970         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2971                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2972                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2973                 pbn_b2_16_460800 },
2974         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2975                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2976                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2977                 pbn_b2_4_460800 },
2978         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2979                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2980                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2981                 pbn_b2_8_460800 },
2982         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2983                 PCI_SUBVENDOR_ID_EXSYS,
2984                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2985                 pbn_exsys_4055 },
2986         /*
2987          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2988          * (Exoray@isys.ca)
2989          */
2990         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2991                 0x10b5, 0x106a, 0, 0,
2992                 pbn_plx_romulus },
2993         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2995                 pbn_b1_4_115200 },
2996         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2998                 pbn_b1_2_115200 },
2999         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3001                 pbn_b1_8_115200 },
3002         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3004                 pbn_b1_8_115200 },
3005         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3006                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3007                 0, 0,
3008                 pbn_b0_4_921600 },
3009         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3010                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3011                 0, 0,
3012                 pbn_b0_4_1152000 },
3013         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3015                 pbn_b0_bt_2_921600 },
3016
3017                 /*
3018                  * The below card is a little controversial since it is the
3019                  * subject of a PCI vendor/device ID clash.  (See
3020                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3021                  * For now just used the hex ID 0x950a.
3022                  */
3023         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3024                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3025                 pbn_b0_2_115200 },
3026         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3028                 pbn_b0_2_1130000 },
3029         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3030                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3031                 pbn_b0_1_921600 },
3032         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3034                 pbn_b0_4_115200 },
3035         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037                 pbn_b0_bt_2_921600 },
3038         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3039                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3040                 pbn_b2_8_1152000 },
3041
3042         /*
3043          * Oxford Semiconductor Inc. Tornado PCI express device range.
3044          */
3045         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3047                 pbn_b0_1_4000000 },
3048         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3050                 pbn_b0_1_4000000 },
3051         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3052                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3053                 pbn_oxsemi_1_4000000 },
3054         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3055                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3056                 pbn_oxsemi_1_4000000 },
3057         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059                 pbn_b0_1_4000000 },
3060         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062                 pbn_b0_1_4000000 },
3063         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3065                 pbn_oxsemi_1_4000000 },
3066         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3068                 pbn_oxsemi_1_4000000 },
3069         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3071                 pbn_b0_1_4000000 },
3072         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3074                 pbn_b0_1_4000000 },
3075         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077                 pbn_b0_1_4000000 },
3078         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080                 pbn_b0_1_4000000 },
3081         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083                 pbn_oxsemi_2_4000000 },
3084         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086                 pbn_oxsemi_2_4000000 },
3087         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089                 pbn_oxsemi_4_4000000 },
3090         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092                 pbn_oxsemi_4_4000000 },
3093         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095                 pbn_oxsemi_8_4000000 },
3096         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098                 pbn_oxsemi_8_4000000 },
3099         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101                 pbn_oxsemi_1_4000000 },
3102         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3104                 pbn_oxsemi_1_4000000 },
3105         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_oxsemi_1_4000000 },
3108         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3110                 pbn_oxsemi_1_4000000 },
3111         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3113                 pbn_oxsemi_1_4000000 },
3114         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3116                 pbn_oxsemi_1_4000000 },
3117         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3119                 pbn_oxsemi_1_4000000 },
3120         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3121                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3122                 pbn_oxsemi_1_4000000 },
3123         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3125                 pbn_oxsemi_1_4000000 },
3126         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3128                 pbn_oxsemi_1_4000000 },
3129         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3131                 pbn_oxsemi_1_4000000 },
3132         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3134                 pbn_oxsemi_1_4000000 },
3135         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3137                 pbn_oxsemi_1_4000000 },
3138         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3139                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140                 pbn_oxsemi_1_4000000 },
3141         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143                 pbn_oxsemi_1_4000000 },
3144         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146                 pbn_oxsemi_1_4000000 },
3147         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149                 pbn_oxsemi_1_4000000 },
3150         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152                 pbn_oxsemi_1_4000000 },
3153         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155                 pbn_oxsemi_1_4000000 },
3156         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158                 pbn_oxsemi_1_4000000 },
3159         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161                 pbn_oxsemi_1_4000000 },
3162         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164                 pbn_oxsemi_1_4000000 },
3165         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167                 pbn_oxsemi_1_4000000 },
3168         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170                 pbn_oxsemi_1_4000000 },
3171         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3172                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173                 pbn_oxsemi_1_4000000 },
3174         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176                 pbn_oxsemi_1_4000000 },
3177         /*
3178          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3179          */
3180         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3181                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3182                 pbn_oxsemi_1_4000000 },
3183         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3184                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3185                 pbn_oxsemi_2_4000000 },
3186         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3187                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3188                 pbn_oxsemi_4_4000000 },
3189         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3190                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3191                 pbn_oxsemi_8_4000000 },
3192
3193         /*
3194          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3195          */
3196         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3197                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3198                 pbn_oxsemi_2_4000000 },
3199
3200         /*
3201          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3202          * from skokodyn@yahoo.com
3203          */
3204         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3205                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3206                 pbn_sbsxrsio },
3207         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3208                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3209                 pbn_sbsxrsio },
3210         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3211                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3212                 pbn_sbsxrsio },
3213         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3214                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3215                 pbn_sbsxrsio },
3216
3217         /*
3218          * Digitan DS560-558, from jimd@esoft.com
3219          */
3220         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222                 pbn_b1_1_115200 },
3223
3224         /*
3225          * Titan Electronic cards
3226          *  The 400L and 800L have a custom setup quirk.
3227          */
3228         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230                 pbn_b0_1_921600 },
3231         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233                 pbn_b0_2_921600 },
3234         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236                 pbn_b0_4_921600 },
3237         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_b0_4_921600 },
3240         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b1_1_921600 },
3243         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_b1_bt_2_921600 },
3246         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_b0_bt_4_921600 },
3249         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_b0_bt_8_921600 },
3252         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_b4_bt_2_921600 },
3255         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_b4_bt_4_921600 },
3258         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b4_bt_8_921600 },
3261         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_b0_4_921600 },
3264         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_b0_4_921600 },
3267         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_b0_4_921600 },
3270         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272                 pbn_oxsemi_1_4000000 },
3273         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275                 pbn_oxsemi_2_4000000 },
3276         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278                 pbn_oxsemi_4_4000000 },
3279         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281                 pbn_oxsemi_8_4000000 },
3282         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284                 pbn_oxsemi_2_4000000 },
3285         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi_2_4000000 },
3288
3289         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3291                 pbn_b2_1_460800 },
3292         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294                 pbn_b2_1_460800 },
3295         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3297                 pbn_b2_1_460800 },
3298         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300                 pbn_b2_bt_2_921600 },
3301         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3303                 pbn_b2_bt_2_921600 },
3304         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3306                 pbn_b2_bt_2_921600 },
3307         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309                 pbn_b2_bt_4_921600 },
3310         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312                 pbn_b2_bt_4_921600 },
3313         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315                 pbn_b2_bt_4_921600 },
3316         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3318                 pbn_b0_1_921600 },
3319         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321                 pbn_b0_1_921600 },
3322         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3324                 pbn_b0_1_921600 },
3325         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3327                 pbn_b0_bt_2_921600 },
3328         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3330                 pbn_b0_bt_2_921600 },
3331         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3333                 pbn_b0_bt_2_921600 },
3334         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3336                 pbn_b0_bt_4_921600 },
3337         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3339                 pbn_b0_bt_4_921600 },
3340         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3342                 pbn_b0_bt_4_921600 },
3343         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3345                 pbn_b0_bt_8_921600 },
3346         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3348                 pbn_b0_bt_8_921600 },
3349         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351                 pbn_b0_bt_8_921600 },
3352
3353         /*
3354          * Computone devices submitted by Doug McNash dmcnash@computone.com
3355          */
3356         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3357                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3358                 0, 0, pbn_computone_4 },
3359         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3360                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3361                 0, 0, pbn_computone_8 },
3362         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3363                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3364                 0, 0, pbn_computone_6 },
3365
3366         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3367                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3368                 pbn_oxsemi },
3369         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3370                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3371                 pbn_b0_bt_1_921600 },
3372
3373         /*
3374          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3375          */
3376         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3377                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378                 pbn_b0_bt_8_115200 },
3379         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3380                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381                 pbn_b0_bt_8_115200 },
3382
3383         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3384                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3385                 pbn_b0_bt_2_115200 },
3386         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3387                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3388                 pbn_b0_bt_2_115200 },
3389         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3391                 pbn_b0_bt_2_115200 },
3392         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3394                 pbn_b0_bt_2_115200 },
3395         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397                 pbn_b0_bt_2_115200 },
3398         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400                 pbn_b0_bt_4_460800 },
3401         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403                 pbn_b0_bt_4_460800 },
3404         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406                 pbn_b0_bt_2_460800 },
3407         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409                 pbn_b0_bt_2_460800 },
3410         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412                 pbn_b0_bt_2_460800 },
3413         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415                 pbn_b0_bt_1_115200 },
3416         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418                 pbn_b0_bt_1_460800 },
3419
3420         /*
3421          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3422          * Cards are identified by their subsystem vendor IDs, which
3423          * (in hex) match the model number.
3424          *
3425          * Note that JC140x are RS422/485 cards which require ox950
3426          * ACR = 0x10, and as such are not currently fully supported.
3427          */
3428         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3429                 0x1204, 0x0004, 0, 0,
3430                 pbn_b0_4_921600 },
3431         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3432                 0x1208, 0x0004, 0, 0,
3433                 pbn_b0_4_921600 },
3434 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3435                 0x1402, 0x0002, 0, 0,
3436                 pbn_b0_2_921600 }, */
3437 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3438                 0x1404, 0x0004, 0, 0,
3439                 pbn_b0_4_921600 }, */
3440         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3441                 0x1208, 0x0004, 0, 0,
3442                 pbn_b0_4_921600 },
3443
3444         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3445                 0x1204, 0x0004, 0, 0,
3446                 pbn_b0_4_921600 },
3447         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3448                 0x1208, 0x0004, 0, 0,
3449                 pbn_b0_4_921600 },
3450         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3451                 0x1208, 0x0004, 0, 0,
3452                 pbn_b0_4_921600 },
3453         /*
3454          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3455          */
3456         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458                 pbn_b1_1_1382400 },
3459
3460         /*
3461          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3462          */
3463         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3464                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465                 pbn_b1_1_1382400 },
3466
3467         /*
3468          * RAStel 2 port modem, gerg@moreton.com.au
3469          */
3470         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472                 pbn_b2_bt_2_115200 },
3473
3474         /*
3475          * EKF addition for i960 Boards form EKF with serial port
3476          */
3477         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3478                 0xE4BF, PCI_ANY_ID, 0, 0,
3479                 pbn_intel_i960 },
3480
3481         /*
3482          * Xircom Cardbus/Ethernet combos
3483          */
3484         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_b0_1_115200 },
3487         /*
3488          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3489          */
3490         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492                 pbn_b0_1_115200 },
3493
3494         /*
3495          * Untested PCI modems, sent in from various folks...
3496          */
3497
3498         /*
3499          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3500          */
3501         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3502                 0x1048, 0x1500, 0, 0,
3503                 pbn_b1_1_115200 },
3504
3505         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3506                 0xFF00, 0, 0, 0,
3507                 pbn_sgi_ioc3 },
3508
3509         /*
3510          * HP Diva card
3511          */
3512         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3513                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3514                 pbn_b1_1_115200 },
3515         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3517                 pbn_b0_5_115200 },
3518         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3520                 pbn_b2_1_115200 },
3521
3522         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3524                 pbn_b3_2_115200 },
3525         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3526                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3527                 pbn_b3_4_115200 },
3528         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3529                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530                 pbn_b3_8_115200 },
3531
3532         /*
3533          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3534          */
3535         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3536                 PCI_ANY_ID, PCI_ANY_ID,
3537                 0,
3538                 0, pbn_exar_XR17C152 },
3539         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3540                 PCI_ANY_ID, PCI_ANY_ID,
3541                 0,
3542                 0, pbn_exar_XR17C154 },
3543         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3544                 PCI_ANY_ID, PCI_ANY_ID,
3545                 0,
3546                 0, pbn_exar_XR17C158 },
3547
3548         /*
3549          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3550          */
3551         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3553                 pbn_b0_1_115200 },
3554         /*
3555          * ITE
3556          */
3557         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3558                 PCI_ANY_ID, PCI_ANY_ID,
3559                 0, 0,
3560                 pbn_b1_bt_1_115200 },
3561
3562         /*
3563          * IntaShield IS-200
3564          */
3565         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3567                 pbn_b2_2_115200 },
3568         /*
3569          * IntaShield IS-400
3570          */
3571         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3573                 pbn_b2_4_115200 },
3574         /*
3575          * Perle PCI-RAS cards
3576          */
3577         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3578                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3579                 0, 0, pbn_b2_4_921600 },
3580         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3581                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3582                 0, 0, pbn_b2_8_921600 },
3583
3584         /*
3585          * Mainpine series cards: Fairly standard layout but fools
3586          * parts of the autodetect in some cases and uses otherwise
3587          * unmatched communications subclasses in the PCI Express case
3588          */
3589
3590         {       /* RockForceDUO */
3591                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3592                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3593                 0, 0, pbn_b0_2_115200 },
3594         {       /* RockForceQUATRO */
3595                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3596                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3597                 0, 0, pbn_b0_4_115200 },
3598         {       /* RockForceDUO+ */
3599                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3600                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3601                 0, 0, pbn_b0_2_115200 },
3602         {       /* RockForceQUATRO+ */
3603                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3604                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3605                 0, 0, pbn_b0_4_115200 },
3606         {       /* RockForce+ */
3607                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3608                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3609                 0, 0, pbn_b0_2_115200 },
3610         {       /* RockForce+ */
3611                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3612                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3613                 0, 0, pbn_b0_4_115200 },
3614         {       /* RockForceOCTO+ */
3615                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3616                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3617                 0, 0, pbn_b0_8_115200 },
3618         {       /* RockForceDUO+ */
3619                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3620                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3621                 0, 0, pbn_b0_2_115200 },
3622         {       /* RockForceQUARTRO+ */
3623                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3624                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3625                 0, 0, pbn_b0_4_115200 },
3626         {       /* RockForceOCTO+ */
3627                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3628                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3629                 0, 0, pbn_b0_8_115200 },
3630         {       /* RockForceD1 */
3631                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3632                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3633                 0, 0, pbn_b0_1_115200 },
3634         {       /* RockForceF1 */
3635                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3636                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3637                 0, 0, pbn_b0_1_115200 },
3638         {       /* RockForceD2 */
3639                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3640                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3641                 0, 0, pbn_b0_2_115200 },
3642         {       /* RockForceF2 */
3643                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3644                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3645                 0, 0, pbn_b0_2_115200 },
3646         {       /* RockForceD4 */
3647                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3648                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3649                 0, 0, pbn_b0_4_115200 },
3650         {       /* RockForceF4 */
3651                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3652                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3653                 0, 0, pbn_b0_4_115200 },
3654         {       /* RockForceD8 */
3655                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3656                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3657                 0, 0, pbn_b0_8_115200 },
3658         {       /* RockForceF8 */
3659                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3660                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3661                 0, 0, pbn_b0_8_115200 },
3662         {       /* IQ Express D1 */
3663                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3664                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3665                 0, 0, pbn_b0_1_115200 },
3666         {       /* IQ Express F1 */
3667                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3668                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3669                 0, 0, pbn_b0_1_115200 },
3670         {       /* IQ Express D2 */
3671                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3672                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3673                 0, 0, pbn_b0_2_115200 },
3674         {       /* IQ Express F2 */
3675                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3676                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3677                 0, 0, pbn_b0_2_115200 },
3678         {       /* IQ Express D4 */
3679                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3680                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3681                 0, 0, pbn_b0_4_115200 },
3682         {       /* IQ Express F4 */
3683                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3684                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3685                 0, 0, pbn_b0_4_115200 },
3686         {       /* IQ Express D8 */
3687                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3688                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3689                 0, 0, pbn_b0_8_115200 },
3690         {       /* IQ Express F8 */
3691                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3692                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3693                 0, 0, pbn_b0_8_115200 },
3694
3695
3696         /*
3697          * PA Semi PA6T-1682M on-chip UART
3698          */
3699         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701                 pbn_pasemi_1682M },
3702
3703         /*
3704          * National Instruments
3705          */
3706         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3707                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3708                 pbn_b1_16_115200 },
3709         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3711                 pbn_b1_8_115200 },
3712         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3713                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3714                 pbn_b1_bt_4_115200 },
3715         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3716                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3717                 pbn_b1_bt_2_115200 },
3718         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3719                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3720                 pbn_b1_bt_4_115200 },
3721         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3722                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723                 pbn_b1_bt_2_115200 },
3724         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3726                 pbn_b1_16_115200 },
3727         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3729                 pbn_b1_8_115200 },
3730         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3732                 pbn_b1_bt_4_115200 },
3733         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3735                 pbn_b1_bt_2_115200 },
3736         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3738                 pbn_b1_bt_4_115200 },
3739         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3741                 pbn_b1_bt_2_115200 },
3742         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3743                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3744                 pbn_ni8430_2 },
3745         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3747                 pbn_ni8430_2 },
3748         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3750                 pbn_ni8430_4 },
3751         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3753                 pbn_ni8430_4 },
3754         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3756                 pbn_ni8430_8 },
3757         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3759                 pbn_ni8430_8 },
3760         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3762                 pbn_ni8430_16 },
3763         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3765                 pbn_ni8430_16 },
3766         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3768                 pbn_ni8430_2 },
3769         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3771                 pbn_ni8430_2 },
3772         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3774                 pbn_ni8430_4 },
3775         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3777                 pbn_ni8430_4 },
3778
3779         /*
3780         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3781         */
3782         {       PCI_VENDOR_ID_ADDIDATA,
3783                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3784                 PCI_ANY_ID,
3785                 PCI_ANY_ID,
3786                 0,
3787                 0,
3788                 pbn_b0_4_115200 },
3789
3790         {       PCI_VENDOR_ID_ADDIDATA,
3791                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3792                 PCI_ANY_ID,
3793                 PCI_ANY_ID,
3794                 0,
3795                 0,
3796                 pbn_b0_2_115200 },
3797
3798         {       PCI_VENDOR_ID_ADDIDATA,
3799                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3800                 PCI_ANY_ID,
3801                 PCI_ANY_ID,
3802                 0,
3803                 0,
3804                 pbn_b0_1_115200 },
3805
3806         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3807                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3808                 PCI_ANY_ID,
3809                 PCI_ANY_ID,
3810                 0,
3811                 0,
3812                 pbn_b1_8_115200 },
3813
3814         {       PCI_VENDOR_ID_ADDIDATA,
3815                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3816                 PCI_ANY_ID,
3817                 PCI_ANY_ID,
3818                 0,
3819                 0,
3820                 pbn_b0_4_115200 },
3821
3822         {       PCI_VENDOR_ID_ADDIDATA,
3823                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3824                 PCI_ANY_ID,
3825                 PCI_ANY_ID,
3826                 0,
3827                 0,
3828                 pbn_b0_2_115200 },
3829
3830         {       PCI_VENDOR_ID_ADDIDATA,
3831                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3832                 PCI_ANY_ID,
3833                 PCI_ANY_ID,
3834                 0,
3835                 0,
3836                 pbn_b0_1_115200 },
3837
3838         {       PCI_VENDOR_ID_ADDIDATA,
3839                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3840                 PCI_ANY_ID,
3841                 PCI_ANY_ID,
3842                 0,
3843                 0,
3844                 pbn_b0_4_115200 },
3845
3846         {       PCI_VENDOR_ID_ADDIDATA,
3847                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3848                 PCI_ANY_ID,
3849                 PCI_ANY_ID,
3850                 0,
3851                 0,
3852                 pbn_b0_2_115200 },
3853
3854         {       PCI_VENDOR_ID_ADDIDATA,
3855                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3856                 PCI_ANY_ID,
3857                 PCI_ANY_ID,
3858                 0,
3859                 0,
3860                 pbn_b0_1_115200 },
3861
3862         {       PCI_VENDOR_ID_ADDIDATA,
3863                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3864                 PCI_ANY_ID,
3865                 PCI_ANY_ID,
3866                 0,
3867                 0,
3868                 pbn_b0_8_115200 },
3869
3870         {       PCI_VENDOR_ID_ADDIDATA,
3871                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3872                 PCI_ANY_ID,
3873                 PCI_ANY_ID,
3874                 0,
3875                 0,
3876                 pbn_ADDIDATA_PCIe_4_3906250 },
3877
3878         {       PCI_VENDOR_ID_ADDIDATA,
3879                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3880                 PCI_ANY_ID,
3881                 PCI_ANY_ID,
3882                 0,
3883                 0,
3884                 pbn_ADDIDATA_PCIe_2_3906250 },
3885
3886         {       PCI_VENDOR_ID_ADDIDATA,
3887                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3888                 PCI_ANY_ID,
3889                 PCI_ANY_ID,
3890                 0,
3891                 0,
3892                 pbn_ADDIDATA_PCIe_1_3906250 },
3893
3894         {       PCI_VENDOR_ID_ADDIDATA,
3895                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3896                 PCI_ANY_ID,
3897                 PCI_ANY_ID,
3898                 0,
3899                 0,
3900                 pbn_ADDIDATA_PCIe_8_3906250 },
3901
3902         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3903                 PCI_VENDOR_ID_IBM, 0x0299,
3904                 0, 0, pbn_b0_bt_2_115200 },
3905
3906         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3907                 0xA000, 0x1000,
3908                 0, 0, pbn_b0_1_115200 },
3909
3910         /* the 9901 is a rebranded 9912 */
3911         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
3912                 0xA000, 0x1000,
3913                 0, 0, pbn_b0_1_115200 },
3914
3915         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
3916                 0xA000, 0x1000,
3917                 0, 0, pbn_b0_1_115200 },
3918
3919         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
3920                 0xA000, 0x1000,
3921                 0, 0, pbn_b0_1_115200 },
3922
3923         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
3924                 0xA000, 0x1000,
3925                 0, 0, pbn_b0_1_115200 },
3926
3927         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
3928                 0xA000, 0x3002,
3929                 0, 0, pbn_NETMOS9900_2s_115200 },
3930
3931         /*
3932          * Best Connectivity PCI Multi I/O cards
3933          */
3934
3935         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3936                 0xA000, 0x1000,
3937                 0, 0, pbn_b0_1_115200 },
3938
3939         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3940                 0xA000, 0x3004,
3941                 0, 0, pbn_b0_bt_4_115200 },
3942         /* Intel CE4100 */
3943         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3944                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
3945                 pbn_ce4100_1_115200 },
3946
3947         /*
3948          * Cronyx Omega PCI
3949          */
3950         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
3951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952                 pbn_omegapci },
3953
3954         /*
3955          * These entries match devices with class COMMUNICATION_SERIAL,
3956          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3957          */
3958         {       PCI_ANY_ID, PCI_ANY_ID,
3959                 PCI_ANY_ID, PCI_ANY_ID,
3960                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3961                 0xffff00, pbn_default },
3962         {       PCI_ANY_ID, PCI_ANY_ID,
3963                 PCI_ANY_ID, PCI_ANY_ID,
3964                 PCI_CLASS_COMMUNICATION_MODEM << 8,
3965                 0xffff00, pbn_default },
3966         {       PCI_ANY_ID, PCI_ANY_ID,
3967                 PCI_ANY_ID, PCI_ANY_ID,
3968                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3969                 0xffff00, pbn_default },
3970         { 0, }
3971 };
3972
3973 static struct pci_driver serial_pci_driver = {
3974         .name           = "serial",
3975         .probe          = pciserial_init_one,
3976         .remove         = __devexit_p(pciserial_remove_one),
3977 #ifdef CONFIG_PM
3978         .suspend        = pciserial_suspend_one,
3979         .resume         = pciserial_resume_one,
3980 #endif
3981         .id_table       = serial_pci_tbl,
3982 };
3983
3984 static int __init serial8250_pci_init(void)
3985 {
3986         return pci_register_driver(&serial_pci_driver);
3987 }
3988
3989 static void __exit serial8250_pci_exit(void)
3990 {
3991         pci_unregister_driver(&serial_pci_driver);
3992 }
3993
3994 module_init(serial8250_pci_init);
3995 module_exit(serial8250_pci_exit);
3996
3997 MODULE_LICENSE("GPL");
3998 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3999 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);