drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 static int pci_timedia_init(struct pci_dev *dev)
 579 {
 580         const unsigned short *ids;
 581         int i, j;
 582
 583         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 584                 ids = timedia_data[i].ids;
 585                 for (j = 0; ids[j]; j++)
 586                         if (dev->subsystem_device == ids[j])
 587                                 return timedia_data[i].num;
 588         }
 589         return 0;
 590 }
 591
 592 /*
 593  * Timedia/SUNIX uses a mixture of BARs and offsets
 594  * Ugh, this is ugly as all hell --- TYT
 595  */
 596 static int
 597 pci_timedia_setup(struct serial_private *priv,
 598                   const struct pciserial_board *board,
 599                   struct uart_port *port, int idx)
 600 {
 601         unsigned int bar = 0, offset = board->first_offset;
 602
 603         switch (idx) {
 604         case 0:
 605                 bar = 0;
 606                 break;
 607         case 1:
 608                 offset = board->uart_offset;
 609                 bar = 0;
 610                 break;
 611         case 2:
 612                 bar = 1;
 613                 break;
 614         case 3:
 615                 offset = board->uart_offset;
 616                 /* FALLTHROUGH */
 617         case 4: /* BAR 2 */
 618         case 5: /* BAR 3 */
 619         case 6: /* BAR 4 */
 620         case 7: /* BAR 5 */
 621                 bar = idx - 2;
 622         }
 623
 624         return setup_port(priv, port, bar, offset, board->reg_shift);
 625 }
 626
 627 /*
 628  * Some Titan cards are also a little weird
 629  */
 630 static int
 631 titan_400l_800l_setup(struct serial_private *priv,
 632                       const struct pciserial_board *board,
 633                       struct uart_port *port, int idx)
 634 {
 635         unsigned int bar, offset = board->first_offset;
 636
 637         switch (idx) {
 638         case 0:
 639                 bar = 1;
 640                 break;
 641         case 1:
 642                 bar = 2;
 643                 break;
 644         default:
 645                 bar = 4;
 646                 offset = (idx - 2) * board->uart_offset;
 647         }
 648
 649         return setup_port(priv, port, bar, offset, board->reg_shift);
 650 }
 651
 652 static int pci_xircom_init(struct pci_dev *dev)
 653 {
 654         msleep(100);
 655         return 0;
 656 }
 657
 658 static int pci_ni8420_init(struct pci_dev *dev)
 659 {
 660         void __iomem *p;
 661         unsigned long base, len;
 662         unsigned int bar = 0;
 663
 664         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 665                 moan_device("no memory in bar", dev);
 666                 return 0;
 667         }
 668
 669         base = pci_resource_start(dev, bar);
 670         len =  pci_resource_len(dev, bar);
 671         p = ioremap_nocache(base, len);
 672         if (p == NULL)
 673                 return -ENOMEM;
 674
 675         /* Enable CPU Interrupt */
 676         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 677                p + NI8420_INT_ENABLE_REG);
 678
 679         iounmap(p);
 680         return 0;
 681 }
 682
 683 #define MITE_IOWBSR1_WSIZE      0xa
 684 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 685 #define MITE_IOWBSR1_WENAB      (1 << 7)
 686 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 687 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 688 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 689
 690 static int pci_ni8430_init(struct pci_dev *dev)
 691 {
 692         void __iomem *p;
 693         unsigned long base, len;
 694         u32 device_window;
 695         unsigned int bar = 0;
 696
 697         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 698                 moan_device("no memory in bar", dev);
 699                 return 0;
 700         }
 701
 702         base = pci_resource_start(dev, bar);
 703         len =  pci_resource_len(dev, bar);
 704         p = ioremap_nocache(base, len);
 705         if (p == NULL)
 706                 return -ENOMEM;
 707
 708         /* Set device window address and size in BAR0 */
 709         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 710                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 711         writel(device_window, p + MITE_IOWBSR1);
 712
 713         /* Set window access to go to RAMSEL IO address space */
 714         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 715                p + MITE_IOWCR1);
 716
 717         /* Enable IO Bus Interrupt 0 */
 718         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 719
 720         /* Enable CPU Interrupt */
 721         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 722
 723         iounmap(p);
 724         return 0;
 725 }
 726
 727 /* UART Port Control Register */
 728 #define NI8430_PORTCON  0x0f
 729 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 730
 731 static int
 732 pci_ni8430_setup(struct serial_private *priv,
 733                  const struct pciserial_board *board,
 734                  struct uart_port *port, int idx)
 735 {
 736         void __iomem *p;
 737         unsigned long base, len;
 738         unsigned int bar, offset = board->first_offset;
 739
 740         if (idx >= board->num_ports)
 741                 return 1;
 742
 743         bar = FL_GET_BASE(board->flags);
 744         offset += idx * board->uart_offset;
 745
 746         base = pci_resource_start(priv->dev, bar);
 747         len =  pci_resource_len(priv->dev, bar);
 748         p = ioremap_nocache(base, len);
 749
 750         /* enable the transciever */
 751         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 752                p + offset + NI8430_PORTCON);
 753
 754         iounmap(p);
 755
 756         return setup_port(priv, port, bar, offset, board->reg_shift);
 757 }
 758
 759 static int pci_netmos_9900_setup(struct serial_private *priv,
 760                                 const struct pciserial_board *board,
 761                                 struct uart_port *port, int idx)
 762 {
 763         unsigned int bar;
 764
 765         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 766                 /* netmos apparently orders BARs by datasheet layout, so serial
 767                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 768                  */
 769                 bar = 3 * idx;
 770
 771                 return setup_port(priv, port, bar, 0, board->reg_shift);
 772         } else {
 773                 return pci_default_setup(priv, board, port, idx);
 774         }
 775 }
 776
 777 /* the 99xx series comes with a range of device IDs and a variety
 778  * of capabilities:
 779  *
 780  * 9900 has varying capabilities and can cascade to sub-controllers
 781  *   (cascading should be purely internal)
 782  * 9904 is hardwired with 4 serial ports
 783  * 9912 and 9922 are hardwired with 2 serial ports
 784  */
 785 static int pci_netmos_9900_numports(struct pci_dev *dev)
 786 {
 787         unsigned int c = dev->class;
 788         unsigned int pi;
 789         unsigned short sub_serports;
 790
 791         pi = (c & 0xff);
 792
 793         if (pi == 2) {
 794                 return 1;
 795         } else if ((pi == 0) &&
 796                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 797                 /* two possibilities: 0x30ps encodes number of parallel and
 798                  * serial ports, or 0x1000 indicates *something*. This is not
 799                  * immediately obvious, since the 2s1p+4s configuration seems
 800                  * to offer all functionality on functions 0..2, while still
 801                  * advertising the same function 3 as the 4s+2s1p config.
 802                  */
 803                 sub_serports = dev->subsystem_device & 0xf;
 804                 if (sub_serports > 0) {
 805                         return sub_serports;
 806                 } else {
 807                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 808                         return 0;
 809                 }
 810         }
 811
 812         moan_device("unknown NetMos/Mostech program interface", dev);
 813         return 0;
 814 }
 815
 816 static int pci_netmos_init(struct pci_dev *dev)
 817 {
 818         /* subdevice 0x00PS means <P> parallel, <S> serial */
 819         unsigned int num_serial = dev->subsystem_device & 0xf;
 820
 821         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 822                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 823                 return 0;
 824
 825         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 826                         dev->subsystem_device == 0x0299)
 827                 return 0;
 828
 829         switch (dev->device) { /* FALLTHROUGH on all */
 830                 case PCI_DEVICE_ID_NETMOS_9904:
 831                 case PCI_DEVICE_ID_NETMOS_9912:
 832                 case PCI_DEVICE_ID_NETMOS_9922:
 833                 case PCI_DEVICE_ID_NETMOS_9900:
 834                         num_serial = pci_netmos_9900_numports(dev);
 835                         break;
 836
 837                 default:
 838                         if (num_serial == 0 ) {
 839                                 moan_device("unknown NetMos/Mostech device", dev);
 840                         }
 841         }
 842
 843         if (num_serial == 0)
 844                 return -ENODEV;
 845
 846         return num_serial;
 847 }
 848
 849 /*
 850  * These chips are available with optionally one parallel port and up to
 851  * two serial ports. Unfortunately they all have the same product id.
 852  *
 853  * Basic configuration is done over a region of 32 I/O ports. The base
 854  * ioport is called INTA or INTC, depending on docs/other drivers.
 855  *
 856  * The region of the 32 I/O ports is configured in POSIO0R...
 857  */
 858
 859 /* registers */
 860 #define ITE_887x_MISCR          0x9c
 861 #define ITE_887x_INTCBAR        0x78
 862 #define ITE_887x_UARTBAR        0x7c
 863 #define ITE_887x_PS0BAR         0x10
 864 #define ITE_887x_POSIO0         0x60
 865
 866 /* I/O space size */
 867 #define ITE_887x_IOSIZE         32
 868 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 869 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 870 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 871 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 872 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 873 #define ITE_887x_POSIO_SPEED            (3 << 29)
 874 /* enable IO_Space bit */
 875 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 876
 877 static int pci_ite887x_init(struct pci_dev *dev)
 878 {
 879         /* inta_addr are the configuration addresses of the ITE */
 880         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 881                                                         0x200, 0x280, 0 };
 882         int ret, i, type;
 883         struct resource *iobase = NULL;
 884         u32 miscr, uartbar, ioport;
 885
 886         /* search for the base-ioport */
 887         i = 0;
 888         while (inta_addr[i] && iobase == NULL) {
 889                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 890                                                                 "ite887x");
 891                 if (iobase != NULL) {
 892                         /* write POSIO0R - speed | size | ioport */
 893                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 894                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 895                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 896                         /* write INTCBAR - ioport */
 897                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 898                                                                 inta_addr[i]);
 899                         ret = inb(inta_addr[i]);
 900                         if (ret != 0xff) {
 901                                 /* ioport connected */
 902                                 break;
 903                         }
 904                         release_region(iobase->start, ITE_887x_IOSIZE);
 905                         iobase = NULL;
 906                 }
 907                 i++;
 908         }
 909
 910         if (!inta_addr[i]) {
 911                 printk(KERN_ERR "ite887x: could not find iobase\n");
 912                 return -ENODEV;
 913         }
 914
 915         /* start of undocumented type checking (see parport_pc.c) */
 916         type = inb(iobase->start + 0x18) & 0x0f;
 917
 918         switch (type) {
 919         case 0x2:       /* ITE8871 (1P) */
 920         case 0xa:       /* ITE8875 (1P) */
 921                 ret = 0;
 922                 break;
 923         case 0xe:       /* ITE8872 (2S1P) */
 924                 ret = 2;
 925                 break;
 926         case 0x6:       /* ITE8873 (1S) */
 927                 ret = 1;
 928                 break;
 929         case 0x8:       /* ITE8874 (2S) */
 930                 ret = 2;
 931                 break;
 932         default:
 933                 moan_device("Unknown ITE887x", dev);
 934                 ret = -ENODEV;
 935         }
 936
 937         /* configure all serial ports */
 938         for (i = 0; i < ret; i++) {
 939                 /* read the I/O port from the device */
 940                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 941                                                                 &ioport);
 942                 ioport &= 0x0000FF00;   /* the actual base address */
 943                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 944                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 945                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 946
 947                 /* write the ioport to the UARTBAR */
 948                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 949                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 950                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 951                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 952
 953                 /* get current config */
 954                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 955                 /* disable interrupts (UARTx_Routing[3:0]) */
 956                 miscr &= ~(0xf << (12 - 4 * i));
 957                 /* activate the UART (UARTx_En) */
 958                 miscr |= 1 << (23 - i);
 959                 /* write new config with activated UART */
 960                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 961         }
 962
 963         if (ret <= 0) {
 964                 /* the device has no UARTs if we get here */
 965                 release_region(iobase->start, ITE_887x_IOSIZE);
 966         }
 967
 968         return ret;
 969 }
 970
 971 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 972 {
 973         u32 ioport;
 974         /* the ioport is bit 0-15 in POSIO0R */
 975         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 976         ioport &= 0xffff;
 977         release_region(ioport, ITE_887x_IOSIZE);
 978 }
 979
 980 /*
 981  * Oxford Semiconductor Inc.
 982  * Check that device is part of the Tornado range of devices, then determine
 983  * the number of ports available on the device.
 984  */
 985 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
 986 {
 987         u8 __iomem *p;
 988         unsigned long deviceID;
 989         unsigned int  number_uarts = 0;
 990
 991         /* OxSemi Tornado devices are all 0xCxxx */
 992         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
 993             (dev->device & 0xF000) != 0xC000)
 994                 return 0;
 995
 996         p = pci_iomap(dev, 0, 5);
 997         if (p == NULL)
 998                 return -ENOMEM;
 999
1000         deviceID = ioread32(p);
1001         /* Tornado device */
1002         if (deviceID == 0x07000200) {
1003                 number_uarts = ioread8(p + 4);
1004                 printk(KERN_DEBUG
1005                         "%d ports detected on Oxford PCI Express device\n",
1006                                                                 number_uarts);
1007         }
1008         pci_iounmap(dev, p);
1009         return number_uarts;
1010 }
1011
1012 static int
1013 pci_default_setup(struct serial_private *priv,
1014                   const struct pciserial_board *board,
1015                   struct uart_port *port, int idx)
1016 {
1017         unsigned int bar, offset = board->first_offset, maxnr;
1018
1019         bar = FL_GET_BASE(board->flags);
1020         if (board->flags & FL_BASE_BARS)
1021                 bar += idx;
1022         else
1023                 offset += idx * board->uart_offset;
1024
1025         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1026                 (board->reg_shift + 3);
1027
1028         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1029                 return 1;
1030
1031         return setup_port(priv, port, bar, offset, board->reg_shift);
1032 }
1033
1034 static int
1035 ce4100_serial_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         int ret;
1040
1041         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1042         port->iotype = UPIO_MEM32;
1043         port->type = PORT_XSCALE;
1044         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1045         port->regshift = 2;
1046
1047         return ret;
1048 }
1049
1050 static int
1051 pci_omegapci_setup(struct serial_private *priv,
1052                       struct pciserial_board *board,
1053                       struct uart_port *port, int idx)
1054 {
1055         return setup_port(priv, port, 2, idx * 8, 0);
1056 }
1057
1058 static int skip_tx_en_setup(struct serial_private *priv,
1059                         const struct pciserial_board *board,
1060                         struct uart_port *port, int idx)
1061 {
1062         port->flags |= UPF_NO_TXEN_TEST;
1063         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1064                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1065                           priv->dev->vendor,
1066                           priv->dev->device,
1067                           priv->dev->subsystem_vendor,
1068                           priv->dev->subsystem_device);
1069
1070         return pci_default_setup(priv, board, port, idx);
1071 }
1072
1073 /* This should be in linux/pci_ids.h */
1074 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1075 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1076 #define PCI_DEVICE_ID_OCTPRO            0x0001
1077 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1078 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1079 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1080 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1081 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1082 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1083 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1084 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1085 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1086 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1087 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1088 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1089 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1090 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1091 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1092 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1093 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1094 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1095 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1096 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1097 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1098 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1099
1100 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1101 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1102
1103 /*
1104  * Master list of serial port init/setup/exit quirks.
1105  * This does not describe the general nature of the port.
1106  * (ie, baud base, number and location of ports, etc)
1107  *
1108  * This list is ordered alphabetically by vendor then device.
1109  * Specific entries must come before more generic entries.
1110  */
1111 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1112         /*
1113         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1114         */
1115         {
1116                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1117                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1118                 .subvendor      = PCI_ANY_ID,
1119                 .subdevice      = PCI_ANY_ID,
1120                 .setup          = addidata_apci7800_setup,
1121         },
1122         /*
1123          * AFAVLAB cards - these may be called via parport_serial
1124          *  It is not clear whether this applies to all products.
1125          */
1126         {
1127                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1128                 .device         = PCI_ANY_ID,
1129                 .subvendor      = PCI_ANY_ID,
1130                 .subdevice      = PCI_ANY_ID,
1131                 .setup          = afavlab_setup,
1132         },
1133         /*
1134          * HP Diva
1135          */
1136         {
1137                 .vendor         = PCI_VENDOR_ID_HP,
1138                 .device         = PCI_DEVICE_ID_HP_DIVA,
1139                 .subvendor      = PCI_ANY_ID,
1140                 .subdevice      = PCI_ANY_ID,
1141                 .init           = pci_hp_diva_init,
1142                 .setup          = pci_hp_diva_setup,
1143         },
1144         /*
1145          * Intel
1146          */
1147         {
1148                 .vendor         = PCI_VENDOR_ID_INTEL,
1149                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1150                 .subvendor      = 0xe4bf,
1151                 .subdevice      = PCI_ANY_ID,
1152                 .init           = pci_inteli960ni_init,
1153                 .setup          = pci_default_setup,
1154         },
1155         {
1156                 .vendor         = PCI_VENDOR_ID_INTEL,
1157                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1158                 .subvendor      = PCI_ANY_ID,
1159                 .subdevice      = PCI_ANY_ID,
1160                 .setup          = skip_tx_en_setup,
1161         },
1162         {
1163                 .vendor         = PCI_VENDOR_ID_INTEL,
1164                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1165                 .subvendor      = PCI_ANY_ID,
1166                 .subdevice      = PCI_ANY_ID,
1167                 .setup          = skip_tx_en_setup,
1168         },
1169         {
1170                 .vendor         = PCI_VENDOR_ID_INTEL,
1171                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1172                 .subvendor      = PCI_ANY_ID,
1173                 .subdevice      = PCI_ANY_ID,
1174                 .setup          = skip_tx_en_setup,
1175         },
1176         {
1177                 .vendor         = PCI_VENDOR_ID_INTEL,
1178                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1179                 .subvendor      = PCI_ANY_ID,
1180                 .subdevice      = PCI_ANY_ID,
1181                 .setup          = ce4100_serial_setup,
1182         },
1183         /*
1184          * ITE
1185          */
1186         {
1187                 .vendor         = PCI_VENDOR_ID_ITE,
1188                 .device         = PCI_DEVICE_ID_ITE_8872,
1189                 .subvendor      = PCI_ANY_ID,
1190                 .subdevice      = PCI_ANY_ID,
1191                 .init           = pci_ite887x_init,
1192                 .setup          = pci_default_setup,
1193                 .exit           = __devexit_p(pci_ite887x_exit),
1194         },
1195         /*
1196          * National Instruments
1197          */
1198         {
1199                 .vendor         = PCI_VENDOR_ID_NI,
1200                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1201                 .subvendor      = PCI_ANY_ID,
1202                 .subdevice      = PCI_ANY_ID,
1203                 .init           = pci_ni8420_init,
1204                 .setup          = pci_default_setup,
1205                 .exit           = __devexit_p(pci_ni8420_exit),
1206         },
1207         {
1208                 .vendor         = PCI_VENDOR_ID_NI,
1209                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1210                 .subvendor      = PCI_ANY_ID,
1211                 .subdevice      = PCI_ANY_ID,
1212                 .init           = pci_ni8420_init,
1213                 .setup          = pci_default_setup,
1214                 .exit           = __devexit_p(pci_ni8420_exit),
1215         },
1216         {
1217                 .vendor         = PCI_VENDOR_ID_NI,
1218                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1219                 .subvendor      = PCI_ANY_ID,
1220                 .subdevice      = PCI_ANY_ID,
1221                 .init           = pci_ni8420_init,
1222                 .setup          = pci_default_setup,
1223                 .exit           = __devexit_p(pci_ni8420_exit),
1224         },
1225         {
1226                 .vendor         = PCI_VENDOR_ID_NI,
1227                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1228                 .subvendor      = PCI_ANY_ID,
1229                 .subdevice      = PCI_ANY_ID,
1230                 .init           = pci_ni8420_init,
1231                 .setup          = pci_default_setup,
1232                 .exit           = __devexit_p(pci_ni8420_exit),
1233         },
1234         {
1235                 .vendor         = PCI_VENDOR_ID_NI,
1236                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1237                 .subvendor      = PCI_ANY_ID,
1238                 .subdevice      = PCI_ANY_ID,
1239                 .init           = pci_ni8420_init,
1240                 .setup          = pci_default_setup,
1241                 .exit           = __devexit_p(pci_ni8420_exit),
1242         },
1243         {
1244                 .vendor         = PCI_VENDOR_ID_NI,
1245                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1246                 .subvendor      = PCI_ANY_ID,
1247                 .subdevice      = PCI_ANY_ID,
1248                 .init           = pci_ni8420_init,
1249                 .setup          = pci_default_setup,
1250                 .exit           = __devexit_p(pci_ni8420_exit),
1251         },
1252         {
1253                 .vendor         = PCI_VENDOR_ID_NI,
1254                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1255                 .subvendor      = PCI_ANY_ID,
1256                 .subdevice      = PCI_ANY_ID,
1257                 .init           = pci_ni8420_init,
1258                 .setup          = pci_default_setup,
1259                 .exit           = __devexit_p(pci_ni8420_exit),
1260         },
1261         {
1262                 .vendor         = PCI_VENDOR_ID_NI,
1263                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1264                 .subvendor      = PCI_ANY_ID,
1265                 .subdevice      = PCI_ANY_ID,
1266                 .init           = pci_ni8420_init,
1267                 .setup          = pci_default_setup,
1268                 .exit           = __devexit_p(pci_ni8420_exit),
1269         },
1270         {
1271                 .vendor         = PCI_VENDOR_ID_NI,
1272                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1273                 .subvendor      = PCI_ANY_ID,
1274                 .subdevice      = PCI_ANY_ID,
1275                 .init           = pci_ni8420_init,
1276                 .setup          = pci_default_setup,
1277                 .exit           = __devexit_p(pci_ni8420_exit),
1278         },
1279         {
1280                 .vendor         = PCI_VENDOR_ID_NI,
1281                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1282                 .subvendor      = PCI_ANY_ID,
1283                 .subdevice      = PCI_ANY_ID,
1284                 .init           = pci_ni8420_init,
1285                 .setup          = pci_default_setup,
1286                 .exit           = __devexit_p(pci_ni8420_exit),
1287         },
1288         {
1289                 .vendor         = PCI_VENDOR_ID_NI,
1290                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1291                 .subvendor      = PCI_ANY_ID,
1292                 .subdevice      = PCI_ANY_ID,
1293                 .init           = pci_ni8420_init,
1294                 .setup          = pci_default_setup,
1295                 .exit           = __devexit_p(pci_ni8420_exit),
1296         },
1297         {
1298                 .vendor         = PCI_VENDOR_ID_NI,
1299                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1300                 .subvendor      = PCI_ANY_ID,
1301                 .subdevice      = PCI_ANY_ID,
1302                 .init           = pci_ni8420_init,
1303                 .setup          = pci_default_setup,
1304                 .exit           = __devexit_p(pci_ni8420_exit),
1305         },
1306         {
1307                 .vendor         = PCI_VENDOR_ID_NI,
1308                 .device         = PCI_ANY_ID,
1309                 .subvendor      = PCI_ANY_ID,
1310                 .subdevice      = PCI_ANY_ID,
1311                 .init           = pci_ni8430_init,
1312                 .setup          = pci_ni8430_setup,
1313                 .exit           = __devexit_p(pci_ni8430_exit),
1314         },
1315         /*
1316          * Panacom
1317          */
1318         {
1319                 .vendor         = PCI_VENDOR_ID_PANACOM,
1320                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1321                 .subvendor      = PCI_ANY_ID,
1322                 .subdevice      = PCI_ANY_ID,
1323                 .init           = pci_plx9050_init,
1324                 .setup          = pci_default_setup,
1325                 .exit           = __devexit_p(pci_plx9050_exit),
1326         },
1327         {
1328                 .vendor         = PCI_VENDOR_ID_PANACOM,
1329                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1330                 .subvendor      = PCI_ANY_ID,
1331                 .subdevice      = PCI_ANY_ID,
1332                 .init           = pci_plx9050_init,
1333                 .setup          = pci_default_setup,
1334                 .exit           = __devexit_p(pci_plx9050_exit),
1335         },
1336         /*
1337          * PLX
1338          */
1339         {
1340                 .vendor         = PCI_VENDOR_ID_PLX,
1341                 .device         = PCI_DEVICE_ID_PLX_9030,
1342                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1343                 .subdevice      = PCI_ANY_ID,
1344                 .setup          = pci_default_setup,
1345         },
1346         {
1347                 .vendor         = PCI_VENDOR_ID_PLX,
1348                 .device         = PCI_DEVICE_ID_PLX_9050,
1349                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1350                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1351                 .init           = pci_plx9050_init,
1352                 .setup          = pci_default_setup,
1353                 .exit           = __devexit_p(pci_plx9050_exit),
1354         },
1355         {
1356                 .vendor         = PCI_VENDOR_ID_PLX,
1357                 .device         = PCI_DEVICE_ID_PLX_9050,
1358                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1359                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1360                 .init           = pci_plx9050_init,
1361                 .setup          = pci_default_setup,
1362                 .exit           = __devexit_p(pci_plx9050_exit),
1363         },
1364         {
1365                 .vendor         = PCI_VENDOR_ID_PLX,
1366                 .device         = PCI_DEVICE_ID_PLX_9050,
1367                 .subvendor      = PCI_VENDOR_ID_PLX,
1368                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1369                 .init           = pci_plx9050_init,
1370                 .setup          = pci_default_setup,
1371                 .exit           = __devexit_p(pci_plx9050_exit),
1372         },
1373         {
1374                 .vendor         = PCI_VENDOR_ID_PLX,
1375                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1376                 .subvendor      = PCI_VENDOR_ID_PLX,
1377                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1378                 .init           = pci_plx9050_init,
1379                 .setup          = pci_default_setup,
1380                 .exit           = __devexit_p(pci_plx9050_exit),
1381         },
1382         /*
1383          * SBS Technologies, Inc., PMC-OCTALPRO 232
1384          */
1385         {
1386                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1387                 .device         = PCI_DEVICE_ID_OCTPRO,
1388                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1389                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1390                 .init           = sbs_init,
1391                 .setup          = sbs_setup,
1392                 .exit           = __devexit_p(sbs_exit),
1393         },
1394         /*
1395          * SBS Technologies, Inc., PMC-OCTALPRO 422
1396          */
1397         {
1398                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1399                 .device         = PCI_DEVICE_ID_OCTPRO,
1400                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1401                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1402                 .init           = sbs_init,
1403                 .setup          = sbs_setup,
1404                 .exit           = __devexit_p(sbs_exit),
1405         },
1406         /*
1407          * SBS Technologies, Inc., P-Octal 232
1408          */
1409         {
1410                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1411                 .device         = PCI_DEVICE_ID_OCTPRO,
1412                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1413                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1414                 .init           = sbs_init,
1415                 .setup          = sbs_setup,
1416                 .exit           = __devexit_p(sbs_exit),
1417         },
1418         /*
1419          * SBS Technologies, Inc., P-Octal 422
1420          */
1421         {
1422                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1423                 .device         = PCI_DEVICE_ID_OCTPRO,
1424                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1425                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1426                 .init           = sbs_init,
1427                 .setup          = sbs_setup,
1428                 .exit           = __devexit_p(sbs_exit),
1429         },
1430         /*
1431          * SIIG cards - these may be called via parport_serial
1432          */
1433         {
1434                 .vendor         = PCI_VENDOR_ID_SIIG,
1435                 .device         = PCI_ANY_ID,
1436                 .subvendor      = PCI_ANY_ID,
1437                 .subdevice      = PCI_ANY_ID,
1438                 .init           = pci_siig_init,
1439                 .setup          = pci_siig_setup,
1440         },
1441         /*
1442          * Titan cards
1443          */
1444         {
1445                 .vendor         = PCI_VENDOR_ID_TITAN,
1446                 .device         = PCI_DEVICE_ID_TITAN_400L,
1447                 .subvendor      = PCI_ANY_ID,
1448                 .subdevice      = PCI_ANY_ID,
1449                 .setup          = titan_400l_800l_setup,
1450         },
1451         {
1452                 .vendor         = PCI_VENDOR_ID_TITAN,
1453                 .device         = PCI_DEVICE_ID_TITAN_800L,
1454                 .subvendor      = PCI_ANY_ID,
1455                 .subdevice      = PCI_ANY_ID,
1456                 .setup          = titan_400l_800l_setup,
1457         },
1458         /*
1459          * Timedia cards
1460          */
1461         {
1462                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1463                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1464                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1465                 .subdevice      = PCI_ANY_ID,
1466                 .init           = pci_timedia_init,
1467                 .setup          = pci_timedia_setup,
1468         },
1469         {
1470                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1471                 .device         = PCI_ANY_ID,
1472                 .subvendor      = PCI_ANY_ID,
1473                 .subdevice      = PCI_ANY_ID,
1474                 .setup          = pci_timedia_setup,
1475         },
1476         /*
1477          * Xircom cards
1478          */
1479         {
1480                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1481                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1482                 .subvendor      = PCI_ANY_ID,
1483                 .subdevice      = PCI_ANY_ID,
1484                 .init           = pci_xircom_init,
1485                 .setup          = pci_default_setup,
1486         },
1487         /*
1488          * Netmos cards - these may be called via parport_serial
1489          */
1490         {
1491                 .vendor         = PCI_VENDOR_ID_NETMOS,
1492                 .device         = PCI_ANY_ID,
1493                 .subvendor      = PCI_ANY_ID,
1494                 .subdevice      = PCI_ANY_ID,
1495                 .init           = pci_netmos_init,
1496                 .setup          = pci_netmos_9900_setup,
1497         },
1498         /*
1499          * For Oxford Semiconductor Tornado based devices
1500          */
1501         {
1502                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1503                 .device         = PCI_ANY_ID,
1504                 .subvendor      = PCI_ANY_ID,
1505                 .subdevice      = PCI_ANY_ID,
1506                 .init           = pci_oxsemi_tornado_init,
1507                 .setup          = pci_default_setup,
1508         },
1509         {
1510                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1511                 .device         = PCI_ANY_ID,
1512                 .subvendor      = PCI_ANY_ID,
1513                 .subdevice      = PCI_ANY_ID,
1514                 .init           = pci_oxsemi_tornado_init,
1515                 .setup          = pci_default_setup,
1516         },
1517         {
1518                 .vendor         = PCI_VENDOR_ID_DIGI,
1519                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1520                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1521                 .subdevice              = PCI_ANY_ID,
1522                 .init                   = pci_oxsemi_tornado_init,
1523                 .setup          = pci_default_setup,
1524         },
1525         /*
1526          * Cronyx Omega PCI (PLX-chip based)
1527          */
1528         {
1529                 .vendor         = PCI_VENDOR_ID_PLX,
1530                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1531                 .subvendor      = PCI_ANY_ID,
1532                 .subdevice      = PCI_ANY_ID,
1533                 .setup          = pci_omegapci_setup,
1534          },
1535         /*
1536          * Default "match everything" terminator entry
1537          */
1538         {
1539                 .vendor         = PCI_ANY_ID,
1540                 .device         = PCI_ANY_ID,
1541                 .subvendor      = PCI_ANY_ID,
1542                 .subdevice      = PCI_ANY_ID,
1543                 .setup          = pci_default_setup,
1544         }
1545 };
1546
1547 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1548 {
1549         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1550 }
1551
1552 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1553 {
1554         struct pci_serial_quirk *quirk;
1555
1556         for (quirk = pci_serial_quirks; ; quirk++)
1557                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1558                     quirk_id_matches(quirk->device, dev->device) &&
1559                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1560                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1561                         break;
1562         return quirk;
1563 }
1564
1565 static inline int get_pci_irq(struct pci_dev *dev,
1566                                 const struct pciserial_board *board)
1567 {
1568         if (board->flags & FL_NOIRQ)
1569                 return 0;
1570         else
1571                 return dev->irq;
1572 }
1573
1574 /*
1575  * This is the configuration table for all of the PCI serial boards
1576  * which we support.  It is directly indexed by the pci_board_num_t enum
1577  * value, which is encoded in the pci_device_id PCI probe table's
1578  * driver_data member.
1579  *
1580  * The makeup of these names are:
1581  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1582  *
1583  *  bn          = PCI BAR number
1584  *  bt          = Index using PCI BARs
1585  *  n           = number of serial ports
1586  *  baud        = baud rate
1587  *  offsetinhex = offset for each sequential port (in hex)
1588  *
1589  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1590  *
1591  * Please note: in theory if n = 1, _bt infix should make no difference.
1592  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1593  */
1594 enum pci_board_num_t {
1595         pbn_default = 0,
1596
1597         pbn_b0_1_115200,
1598         pbn_b0_2_115200,
1599         pbn_b0_4_115200,
1600         pbn_b0_5_115200,
1601         pbn_b0_8_115200,
1602
1603         pbn_b0_1_921600,
1604         pbn_b0_2_921600,
1605         pbn_b0_4_921600,
1606
1607         pbn_b0_2_1130000,
1608
1609         pbn_b0_4_1152000,
1610
1611         pbn_b0_2_1843200,
1612         pbn_b0_4_1843200,
1613
1614         pbn_b0_2_1843200_200,
1615         pbn_b0_4_1843200_200,
1616         pbn_b0_8_1843200_200,
1617
1618         pbn_b0_1_4000000,
1619
1620         pbn_b0_bt_1_115200,
1621         pbn_b0_bt_2_115200,
1622         pbn_b0_bt_4_115200,
1623         pbn_b0_bt_8_115200,
1624
1625         pbn_b0_bt_1_460800,
1626         pbn_b0_bt_2_460800,
1627         pbn_b0_bt_4_460800,
1628
1629         pbn_b0_bt_1_921600,
1630         pbn_b0_bt_2_921600,
1631         pbn_b0_bt_4_921600,
1632         pbn_b0_bt_8_921600,
1633
1634         pbn_b1_1_115200,
1635         pbn_b1_2_115200,
1636         pbn_b1_4_115200,
1637         pbn_b1_8_115200,
1638         pbn_b1_16_115200,
1639
1640         pbn_b1_1_921600,
1641         pbn_b1_2_921600,
1642         pbn_b1_4_921600,
1643         pbn_b1_8_921600,
1644
1645         pbn_b1_2_1250000,
1646
1647         pbn_b1_bt_1_115200,
1648         pbn_b1_bt_2_115200,
1649         pbn_b1_bt_4_115200,
1650
1651         pbn_b1_bt_2_921600,
1652
1653         pbn_b1_1_1382400,
1654         pbn_b1_2_1382400,
1655         pbn_b1_4_1382400,
1656         pbn_b1_8_1382400,
1657
1658         pbn_b2_1_115200,
1659         pbn_b2_2_115200,
1660         pbn_b2_4_115200,
1661         pbn_b2_8_115200,
1662
1663         pbn_b2_1_460800,
1664         pbn_b2_4_460800,
1665         pbn_b2_8_460800,
1666         pbn_b2_16_460800,
1667
1668         pbn_b2_1_921600,
1669         pbn_b2_4_921600,
1670         pbn_b2_8_921600,
1671
1672         pbn_b2_8_1152000,
1673
1674         pbn_b2_bt_1_115200,
1675         pbn_b2_bt_2_115200,
1676         pbn_b2_bt_4_115200,
1677
1678         pbn_b2_bt_2_921600,
1679         pbn_b2_bt_4_921600,
1680
1681         pbn_b3_2_115200,
1682         pbn_b3_4_115200,
1683         pbn_b3_8_115200,
1684
1685         pbn_b4_bt_2_921600,
1686         pbn_b4_bt_4_921600,
1687         pbn_b4_bt_8_921600,
1688
1689         /*
1690          * Board-specific versions.
1691          */
1692         pbn_panacom,
1693         pbn_panacom2,
1694         pbn_panacom4,
1695         pbn_exsys_4055,
1696         pbn_plx_romulus,
1697         pbn_oxsemi,
1698         pbn_oxsemi_1_4000000,
1699         pbn_oxsemi_2_4000000,
1700         pbn_oxsemi_4_4000000,
1701         pbn_oxsemi_8_4000000,
1702         pbn_intel_i960,
1703         pbn_sgi_ioc3,
1704         pbn_computone_4,
1705         pbn_computone_6,
1706         pbn_computone_8,
1707         pbn_sbsxrsio,
1708         pbn_exar_XR17C152,
1709         pbn_exar_XR17C154,
1710         pbn_exar_XR17C158,
1711         pbn_exar_ibm_saturn,
1712         pbn_pasemi_1682M,
1713         pbn_ni8430_2,
1714         pbn_ni8430_4,
1715         pbn_ni8430_8,
1716         pbn_ni8430_16,
1717         pbn_ADDIDATA_PCIe_1_3906250,
1718         pbn_ADDIDATA_PCIe_2_3906250,
1719         pbn_ADDIDATA_PCIe_4_3906250,
1720         pbn_ADDIDATA_PCIe_8_3906250,
1721         pbn_ce4100_1_115200,
1722         pbn_omegapci,
1723         pbn_NETMOS9900_2s_115200,
1724 };
1725
1726 /*
1727  * uart_offset - the space between channels
1728  * reg_shift   - describes how the UART registers are mapped
1729  *               to PCI memory by the card.
1730  * For example IER register on SBS, Inc. PMC-OctPro is located at
1731  * offset 0x10 from the UART base, while UART_IER is defined as 1
1732  * in include/linux/serial_reg.h,
1733  * see first lines of serial_in() and serial_out() in 8250.c
1734 */
1735
1736 static struct pciserial_board pci_boards[] __devinitdata = {
1737         [pbn_default] = {
1738                 .flags          = FL_BASE0,
1739                 .num_ports      = 1,
1740                 .base_baud      = 115200,
1741                 .uart_offset    = 8,
1742         },
1743         [pbn_b0_1_115200] = {
1744                 .flags          = FL_BASE0,
1745                 .num_ports      = 1,
1746                 .base_baud      = 115200,
1747                 .uart_offset    = 8,
1748         },
1749         [pbn_b0_2_115200] = {
1750                 .flags          = FL_BASE0,
1751                 .num_ports      = 2,
1752                 .base_baud      = 115200,
1753                 .uart_offset    = 8,
1754         },
1755         [pbn_b0_4_115200] = {
1756                 .flags          = FL_BASE0,
1757                 .num_ports      = 4,
1758                 .base_baud      = 115200,
1759                 .uart_offset    = 8,
1760         },
1761         [pbn_b0_5_115200] = {
1762                 .flags          = FL_BASE0,
1763                 .num_ports      = 5,
1764                 .base_baud      = 115200,
1765                 .uart_offset    = 8,
1766         },
1767         [pbn_b0_8_115200] = {
1768                 .flags          = FL_BASE0,
1769                 .num_ports      = 8,
1770                 .base_baud      = 115200,
1771                 .uart_offset    = 8,
1772         },
1773         [pbn_b0_1_921600] = {
1774                 .flags          = FL_BASE0,
1775                 .num_ports      = 1,
1776                 .base_baud      = 921600,
1777                 .uart_offset    = 8,
1778         },
1779         [pbn_b0_2_921600] = {
1780                 .flags          = FL_BASE0,
1781                 .num_ports      = 2,
1782                 .base_baud      = 921600,
1783                 .uart_offset    = 8,
1784         },
1785         [pbn_b0_4_921600] = {
1786                 .flags          = FL_BASE0,
1787                 .num_ports      = 4,
1788                 .base_baud      = 921600,
1789                 .uart_offset    = 8,
1790         },
1791
1792         [pbn_b0_2_1130000] = {
1793                 .flags          = FL_BASE0,
1794                 .num_ports      = 2,
1795                 .base_baud      = 1130000,
1796                 .uart_offset    = 8,
1797         },
1798
1799         [pbn_b0_4_1152000] = {
1800                 .flags          = FL_BASE0,
1801                 .num_ports      = 4,
1802                 .base_baud      = 1152000,
1803                 .uart_offset    = 8,
1804         },
1805
1806         [pbn_b0_2_1843200] = {
1807                 .flags          = FL_BASE0,
1808                 .num_ports      = 2,
1809                 .base_baud      = 1843200,
1810                 .uart_offset    = 8,
1811         },
1812         [pbn_b0_4_1843200] = {
1813                 .flags          = FL_BASE0,
1814                 .num_ports      = 4,
1815                 .base_baud      = 1843200,
1816                 .uart_offset    = 8,
1817         },
1818
1819         [pbn_b0_2_1843200_200] = {
1820                 .flags          = FL_BASE0,
1821                 .num_ports      = 2,
1822                 .base_baud      = 1843200,
1823                 .uart_offset    = 0x200,
1824         },
1825         [pbn_b0_4_1843200_200] = {
1826                 .flags          = FL_BASE0,
1827                 .num_ports      = 4,
1828                 .base_baud      = 1843200,
1829                 .uart_offset    = 0x200,
1830         },
1831         [pbn_b0_8_1843200_200] = {
1832                 .flags          = FL_BASE0,
1833                 .num_ports      = 8,
1834                 .base_baud      = 1843200,
1835                 .uart_offset    = 0x200,
1836         },
1837         [pbn_b0_1_4000000] = {
1838                 .flags          = FL_BASE0,
1839                 .num_ports      = 1,
1840                 .base_baud      = 4000000,
1841                 .uart_offset    = 8,
1842         },
1843
1844         [pbn_b0_bt_1_115200] = {
1845                 .flags          = FL_BASE0|FL_BASE_BARS,
1846                 .num_ports      = 1,
1847                 .base_baud      = 115200,
1848                 .uart_offset    = 8,
1849         },
1850         [pbn_b0_bt_2_115200] = {
1851                 .flags          = FL_BASE0|FL_BASE_BARS,
1852                 .num_ports      = 2,
1853                 .base_baud      = 115200,
1854                 .uart_offset    = 8,
1855         },
1856         [pbn_b0_bt_4_115200] = {
1857                 .flags          = FL_BASE0|FL_BASE_BARS,
1858                 .num_ports      = 4,
1859                 .base_baud      = 115200,
1860                 .uart_offset    = 8,
1861         },
1862         [pbn_b0_bt_8_115200] = {
1863                 .flags          = FL_BASE0|FL_BASE_BARS,
1864                 .num_ports      = 8,
1865                 .base_baud      = 115200,
1866                 .uart_offset    = 8,
1867         },
1868
1869         [pbn_b0_bt_1_460800] = {
1870                 .flags          = FL_BASE0|FL_BASE_BARS,
1871                 .num_ports      = 1,
1872                 .base_baud      = 460800,
1873                 .uart_offset    = 8,
1874         },
1875         [pbn_b0_bt_2_460800] = {
1876                 .flags          = FL_BASE0|FL_BASE_BARS,
1877                 .num_ports      = 2,
1878                 .base_baud      = 460800,
1879                 .uart_offset    = 8,
1880         },
1881         [pbn_b0_bt_4_460800] = {
1882                 .flags          = FL_BASE0|FL_BASE_BARS,
1883                 .num_ports      = 4,
1884                 .base_baud      = 460800,
1885                 .uart_offset    = 8,
1886         },
1887
1888         [pbn_b0_bt_1_921600] = {
1889                 .flags          = FL_BASE0|FL_BASE_BARS,
1890                 .num_ports      = 1,
1891                 .base_baud      = 921600,
1892                 .uart_offset    = 8,
1893         },
1894         [pbn_b0_bt_2_921600] = {
1895                 .flags          = FL_BASE0|FL_BASE_BARS,
1896                 .num_ports      = 2,
1897                 .base_baud      = 921600,
1898                 .uart_offset    = 8,
1899         },
1900         [pbn_b0_bt_4_921600] = {
1901                 .flags          = FL_BASE0|FL_BASE_BARS,
1902                 .num_ports      = 4,
1903                 .base_baud      = 921600,
1904                 .uart_offset    = 8,
1905         },
1906         [pbn_b0_bt_8_921600] = {
1907                 .flags          = FL_BASE0|FL_BASE_BARS,
1908                 .num_ports      = 8,
1909                 .base_baud      = 921600,
1910                 .uart_offset    = 8,
1911         },
1912
1913         [pbn_b1_1_115200] = {
1914                 .flags          = FL_BASE1,
1915                 .num_ports      = 1,
1916                 .base_baud      = 115200,
1917                 .uart_offset    = 8,
1918         },
1919         [pbn_b1_2_115200] = {
1920                 .flags          = FL_BASE1,
1921                 .num_ports      = 2,
1922                 .base_baud      = 115200,
1923                 .uart_offset    = 8,
1924         },
1925         [pbn_b1_4_115200] = {
1926                 .flags          = FL_BASE1,
1927                 .num_ports      = 4,
1928                 .base_baud      = 115200,
1929                 .uart_offset    = 8,
1930         },
1931         [pbn_b1_8_115200] = {
1932                 .flags          = FL_BASE1,
1933                 .num_ports      = 8,
1934                 .base_baud      = 115200,
1935                 .uart_offset    = 8,
1936         },
1937         [pbn_b1_16_115200] = {
1938                 .flags          = FL_BASE1,
1939                 .num_ports      = 16,
1940                 .base_baud      = 115200,
1941                 .uart_offset    = 8,
1942         },
1943
1944         [pbn_b1_1_921600] = {
1945                 .flags          = FL_BASE1,
1946                 .num_ports      = 1,
1947                 .base_baud      = 921600,
1948                 .uart_offset    = 8,
1949         },
1950         [pbn_b1_2_921600] = {
1951                 .flags          = FL_BASE1,
1952                 .num_ports      = 2,
1953                 .base_baud      = 921600,
1954                 .uart_offset    = 8,
1955         },
1956         [pbn_b1_4_921600] = {
1957                 .flags          = FL_BASE1,
1958                 .num_ports      = 4,
1959                 .base_baud      = 921600,
1960                 .uart_offset    = 8,
1961         },
1962         [pbn_b1_8_921600] = {
1963                 .flags          = FL_BASE1,
1964                 .num_ports      = 8,
1965                 .base_baud      = 921600,
1966                 .uart_offset    = 8,
1967         },
1968         [pbn_b1_2_1250000] = {
1969                 .flags          = FL_BASE1,
1970                 .num_ports      = 2,
1971                 .base_baud      = 1250000,
1972                 .uart_offset    = 8,
1973         },
1974
1975         [pbn_b1_bt_1_115200] = {
1976                 .flags          = FL_BASE1|FL_BASE_BARS,
1977                 .num_ports      = 1,
1978                 .base_baud      = 115200,
1979                 .uart_offset    = 8,
1980         },
1981         [pbn_b1_bt_2_115200] = {
1982                 .flags          = FL_BASE1|FL_BASE_BARS,
1983                 .num_ports      = 2,
1984                 .base_baud      = 115200,
1985                 .uart_offset    = 8,
1986         },
1987         [pbn_b1_bt_4_115200] = {
1988                 .flags          = FL_BASE1|FL_BASE_BARS,
1989                 .num_ports      = 4,
1990                 .base_baud      = 115200,
1991                 .uart_offset    = 8,
1992         },
1993
1994         [pbn_b1_bt_2_921600] = {
1995                 .flags          = FL_BASE1|FL_BASE_BARS,
1996                 .num_ports      = 2,
1997                 .base_baud      = 921600,
1998                 .uart_offset    = 8,
1999         },
2000
2001         [pbn_b1_1_1382400] = {
2002                 .flags          = FL_BASE1,
2003                 .num_ports      = 1,
2004                 .base_baud      = 1382400,
2005                 .uart_offset    = 8,
2006         },
2007         [pbn_b1_2_1382400] = {
2008                 .flags          = FL_BASE1,
2009                 .num_ports      = 2,
2010                 .base_baud      = 1382400,
2011                 .uart_offset    = 8,
2012         },
2013         [pbn_b1_4_1382400] = {
2014                 .flags          = FL_BASE1,
2015                 .num_ports      = 4,
2016                 .base_baud      = 1382400,
2017                 .uart_offset    = 8,
2018         },
2019         [pbn_b1_8_1382400] = {
2020                 .flags          = FL_BASE1,
2021                 .num_ports      = 8,
2022                 .base_baud      = 1382400,
2023                 .uart_offset    = 8,
2024         },
2025
2026         [pbn_b2_1_115200] = {
2027                 .flags          = FL_BASE2,
2028                 .num_ports      = 1,
2029                 .base_baud      = 115200,
2030                 .uart_offset    = 8,
2031         },
2032         [pbn_b2_2_115200] = {
2033                 .flags          = FL_BASE2,
2034                 .num_ports      = 2,
2035                 .base_baud      = 115200,
2036                 .uart_offset    = 8,
2037         },
2038         [pbn_b2_4_115200] = {
2039                 .flags          = FL_BASE2,
2040                 .num_ports      = 4,
2041                 .base_baud      = 115200,
2042                 .uart_offset    = 8,
2043         },
2044         [pbn_b2_8_115200] = {
2045                 .flags          = FL_BASE2,
2046                 .num_ports      = 8,
2047                 .base_baud      = 115200,
2048                 .uart_offset    = 8,
2049         },
2050
2051         [pbn_b2_1_460800] = {
2052                 .flags          = FL_BASE2,
2053                 .num_ports      = 1,
2054                 .base_baud      = 460800,
2055                 .uart_offset    = 8,
2056         },
2057         [pbn_b2_4_460800] = {
2058                 .flags          = FL_BASE2,
2059                 .num_ports      = 4,
2060                 .base_baud      = 460800,
2061                 .uart_offset    = 8,
2062         },
2063         [pbn_b2_8_460800] = {
2064                 .flags          = FL_BASE2,
2065                 .num_ports      = 8,
2066                 .base_baud      = 460800,
2067                 .uart_offset    = 8,
2068         },
2069         [pbn_b2_16_460800] = {
2070                 .flags          = FL_BASE2,
2071                 .num_ports      = 16,
2072                 .base_baud      = 460800,
2073                 .uart_offset    = 8,
2074          },
2075
2076         [pbn_b2_1_921600] = {
2077                 .flags          = FL_BASE2,
2078                 .num_ports      = 1,
2079                 .base_baud      = 921600,
2080                 .uart_offset    = 8,
2081         },
2082         [pbn_b2_4_921600] = {
2083                 .flags          = FL_BASE2,
2084                 .num_ports      = 4,
2085                 .base_baud      = 921600,
2086                 .uart_offset    = 8,
2087         },
2088         [pbn_b2_8_921600] = {
2089                 .flags          = FL_BASE2,
2090                 .num_ports      = 8,
2091                 .base_baud      = 921600,
2092                 .uart_offset    = 8,
2093         },
2094
2095         [pbn_b2_8_1152000] = {
2096                 .flags          = FL_BASE2,
2097                 .num_ports      = 8,
2098                 .base_baud      = 1152000,
2099                 .uart_offset    = 8,
2100         },
2101
2102         [pbn_b2_bt_1_115200] = {
2103                 .flags          = FL_BASE2|FL_BASE_BARS,
2104                 .num_ports      = 1,
2105                 .base_baud      = 115200,
2106                 .uart_offset    = 8,
2107         },
2108         [pbn_b2_bt_2_115200] = {
2109                 .flags          = FL_BASE2|FL_BASE_BARS,
2110                 .num_ports      = 2,
2111                 .base_baud      = 115200,
2112                 .uart_offset    = 8,
2113         },
2114         [pbn_b2_bt_4_115200] = {
2115                 .flags          = FL_BASE2|FL_BASE_BARS,
2116                 .num_ports      = 4,
2117                 .base_baud      = 115200,
2118                 .uart_offset    = 8,
2119         },
2120
2121         [pbn_b2_bt_2_921600] = {
2122                 .flags          = FL_BASE2|FL_BASE_BARS,
2123                 .num_ports      = 2,
2124                 .base_baud      = 921600,
2125                 .uart_offset    = 8,
2126         },
2127         [pbn_b2_bt_4_921600] = {
2128                 .flags          = FL_BASE2|FL_BASE_BARS,
2129                 .num_ports      = 4,
2130                 .base_baud      = 921600,
2131                 .uart_offset    = 8,
2132         },
2133
2134         [pbn_b3_2_115200] = {
2135                 .flags          = FL_BASE3,
2136                 .num_ports      = 2,
2137                 .base_baud      = 115200,
2138                 .uart_offset    = 8,
2139         },
2140         [pbn_b3_4_115200] = {
2141                 .flags          = FL_BASE3,
2142                 .num_ports      = 4,
2143                 .base_baud      = 115200,
2144                 .uart_offset    = 8,
2145         },
2146         [pbn_b3_8_115200] = {
2147                 .flags          = FL_BASE3,
2148                 .num_ports      = 8,
2149                 .base_baud      = 115200,
2150                 .uart_offset    = 8,
2151         },
2152
2153         [pbn_b4_bt_2_921600] = {
2154                 .flags          = FL_BASE4,
2155                 .num_ports      = 2,
2156                 .base_baud      = 921600,
2157                 .uart_offset    = 8,
2158         },
2159         [pbn_b4_bt_4_921600] = {
2160                 .flags          = FL_BASE4,
2161                 .num_ports      = 4,
2162                 .base_baud      = 921600,
2163                 .uart_offset    = 8,
2164         },
2165         [pbn_b4_bt_8_921600] = {
2166                 .flags          = FL_BASE4,
2167                 .num_ports      = 8,
2168                 .base_baud      = 921600,
2169                 .uart_offset    = 8,
2170         },
2171
2172         /*
2173          * Entries following this are board-specific.
2174          */
2175
2176         /*
2177          * Panacom - IOMEM
2178          */
2179         [pbn_panacom] = {
2180                 .flags          = FL_BASE2,
2181                 .num_ports      = 2,
2182                 .base_baud      = 921600,
2183                 .uart_offset    = 0x400,
2184                 .reg_shift      = 7,
2185         },
2186         [pbn_panacom2] = {
2187                 .flags          = FL_BASE2|FL_BASE_BARS,
2188                 .num_ports      = 2,
2189                 .base_baud      = 921600,
2190                 .uart_offset    = 0x400,
2191                 .reg_shift      = 7,
2192         },
2193         [pbn_panacom4] = {
2194                 .flags          = FL_BASE2|FL_BASE_BARS,
2195                 .num_ports      = 4,
2196                 .base_baud      = 921600,
2197                 .uart_offset    = 0x400,
2198                 .reg_shift      = 7,
2199         },
2200
2201         [pbn_exsys_4055] = {
2202                 .flags          = FL_BASE2,
2203                 .num_ports      = 4,
2204                 .base_baud      = 115200,
2205                 .uart_offset    = 8,
2206         },
2207
2208         /* I think this entry is broken - the first_offset looks wrong --rmk */
2209         [pbn_plx_romulus] = {
2210                 .flags          = FL_BASE2,
2211                 .num_ports      = 4,
2212                 .base_baud      = 921600,
2213                 .uart_offset    = 8 << 2,
2214                 .reg_shift      = 2,
2215                 .first_offset   = 0x03,
2216         },
2217
2218         /*
2219          * This board uses the size of PCI Base region 0 to
2220          * signal now many ports are available
2221          */
2222         [pbn_oxsemi] = {
2223                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2224                 .num_ports      = 32,
2225                 .base_baud      = 115200,
2226                 .uart_offset    = 8,
2227         },
2228         [pbn_oxsemi_1_4000000] = {
2229                 .flags          = FL_BASE0,
2230                 .num_ports      = 1,
2231                 .base_baud      = 4000000,
2232                 .uart_offset    = 0x200,
2233                 .first_offset   = 0x1000,
2234         },
2235         [pbn_oxsemi_2_4000000] = {
2236                 .flags          = FL_BASE0,
2237                 .num_ports      = 2,
2238                 .base_baud      = 4000000,
2239                 .uart_offset    = 0x200,
2240                 .first_offset   = 0x1000,
2241         },
2242         [pbn_oxsemi_4_4000000] = {
2243                 .flags          = FL_BASE0,
2244                 .num_ports      = 4,
2245                 .base_baud      = 4000000,
2246                 .uart_offset    = 0x200,
2247                 .first_offset   = 0x1000,
2248         },
2249         [pbn_oxsemi_8_4000000] = {
2250                 .flags          = FL_BASE0,
2251                 .num_ports      = 8,
2252                 .base_baud      = 4000000,
2253                 .uart_offset    = 0x200,
2254                 .first_offset   = 0x1000,
2255         },
2256
2257
2258         /*
2259          * EKF addition for i960 Boards form EKF with serial port.
2260          * Max 256 ports.
2261          */
2262         [pbn_intel_i960] = {
2263                 .flags          = FL_BASE0,
2264                 .num_ports      = 32,
2265                 .base_baud      = 921600,
2266                 .uart_offset    = 8 << 2,
2267                 .reg_shift      = 2,
2268                 .first_offset   = 0x10000,
2269         },
2270         [pbn_sgi_ioc3] = {
2271                 .flags          = FL_BASE0|FL_NOIRQ,
2272                 .num_ports      = 1,
2273                 .base_baud      = 458333,
2274                 .uart_offset    = 8,
2275                 .reg_shift      = 0,
2276                 .first_offset   = 0x20178,
2277         },
2278
2279         /*
2280          * Computone - uses IOMEM.
2281          */
2282         [pbn_computone_4] = {
2283                 .flags          = FL_BASE0,
2284                 .num_ports      = 4,
2285                 .base_baud      = 921600,
2286                 .uart_offset    = 0x40,
2287                 .reg_shift      = 2,
2288                 .first_offset   = 0x200,
2289         },
2290         [pbn_computone_6] = {
2291                 .flags          = FL_BASE0,
2292                 .num_ports      = 6,
2293                 .base_baud      = 921600,
2294                 .uart_offset    = 0x40,
2295                 .reg_shift      = 2,
2296                 .first_offset   = 0x200,
2297         },
2298         [pbn_computone_8] = {
2299                 .flags          = FL_BASE0,
2300                 .num_ports      = 8,
2301                 .base_baud      = 921600,
2302                 .uart_offset    = 0x40,
2303                 .reg_shift      = 2,
2304                 .first_offset   = 0x200,
2305         },
2306         [pbn_sbsxrsio] = {
2307                 .flags          = FL_BASE0,
2308                 .num_ports      = 8,
2309                 .base_baud      = 460800,
2310                 .uart_offset    = 256,
2311                 .reg_shift      = 4,
2312         },
2313         /*
2314          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2315          *  Only basic 16550A support.
2316          *  XR17C15[24] are not tested, but they should work.
2317          */
2318         [pbn_exar_XR17C152] = {
2319                 .flags          = FL_BASE0,
2320                 .num_ports      = 2,
2321                 .base_baud      = 921600,
2322                 .uart_offset    = 0x200,
2323         },
2324         [pbn_exar_XR17C154] = {
2325                 .flags          = FL_BASE0,
2326                 .num_ports      = 4,
2327                 .base_baud      = 921600,
2328                 .uart_offset    = 0x200,
2329         },
2330         [pbn_exar_XR17C158] = {
2331                 .flags          = FL_BASE0,
2332                 .num_ports      = 8,
2333                 .base_baud      = 921600,
2334                 .uart_offset    = 0x200,
2335         },
2336         [pbn_exar_ibm_saturn] = {
2337                 .flags          = FL_BASE0,
2338                 .num_ports      = 1,
2339                 .base_baud      = 921600,
2340                 .uart_offset    = 0x200,
2341         },
2342
2343         /*
2344          * PA Semi PWRficient PA6T-1682M on-chip UART
2345          */
2346         [pbn_pasemi_1682M] = {
2347                 .flags          = FL_BASE0,
2348                 .num_ports      = 1,
2349                 .base_baud      = 8333333,
2350         },
2351         /*
2352          * National Instruments 843x
2353          */
2354         [pbn_ni8430_16] = {
2355                 .flags          = FL_BASE0,
2356                 .num_ports      = 16,
2357                 .base_baud      = 3686400,
2358                 .uart_offset    = 0x10,
2359                 .first_offset   = 0x800,
2360         },
2361         [pbn_ni8430_8] = {
2362                 .flags          = FL_BASE0,
2363                 .num_ports      = 8,
2364                 .base_baud      = 3686400,
2365                 .uart_offset    = 0x10,
2366                 .first_offset   = 0x800,
2367         },
2368         [pbn_ni8430_4] = {
2369                 .flags          = FL_BASE0,
2370                 .num_ports      = 4,
2371                 .base_baud      = 3686400,
2372                 .uart_offset    = 0x10,
2373                 .first_offset   = 0x800,
2374         },
2375         [pbn_ni8430_2] = {
2376                 .flags          = FL_BASE0,
2377                 .num_ports      = 2,
2378                 .base_baud      = 3686400,
2379                 .uart_offset    = 0x10,
2380                 .first_offset   = 0x800,
2381         },
2382         /*
2383          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2384          */
2385         [pbn_ADDIDATA_PCIe_1_3906250] = {
2386                 .flags          = FL_BASE0,
2387                 .num_ports      = 1,
2388                 .base_baud      = 3906250,
2389                 .uart_offset    = 0x200,
2390                 .first_offset   = 0x1000,
2391         },
2392         [pbn_ADDIDATA_PCIe_2_3906250] = {
2393                 .flags          = FL_BASE0,
2394                 .num_ports      = 2,
2395                 .base_baud      = 3906250,
2396                 .uart_offset    = 0x200,
2397                 .first_offset   = 0x1000,
2398         },
2399         [pbn_ADDIDATA_PCIe_4_3906250] = {
2400                 .flags          = FL_BASE0,
2401                 .num_ports      = 4,
2402                 .base_baud      = 3906250,
2403                 .uart_offset    = 0x200,
2404                 .first_offset   = 0x1000,
2405         },
2406         [pbn_ADDIDATA_PCIe_8_3906250] = {
2407                 .flags          = FL_BASE0,
2408                 .num_ports      = 8,
2409                 .base_baud      = 3906250,
2410                 .uart_offset    = 0x200,
2411                 .first_offset   = 0x1000,
2412         },
2413         [pbn_ce4100_1_115200] = {
2414                 .flags          = FL_BASE0,
2415                 .num_ports      = 1,
2416                 .base_baud      = 921600,
2417                 .reg_shift      = 2,
2418         },
2419         [pbn_omegapci] = {
2420                 .flags          = FL_BASE0,
2421                 .num_ports      = 8,
2422                 .base_baud      = 115200,
2423                 .uart_offset    = 0x200,
2424         },
2425         [pbn_NETMOS9900_2s_115200] = {
2426                 .flags          = FL_BASE0,
2427                 .num_ports      = 2,
2428                 .base_baud      = 115200,
2429         },
2430 };
2431
2432 static const struct pci_device_id softmodem_blacklist[] = {
2433         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2434         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2435         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2436 };
2437
2438 /*
2439  * Given a complete unknown PCI device, try to use some heuristics to
2440  * guess what the configuration might be, based on the pitiful PCI
2441  * serial specs.  Returns 0 on success, 1 on failure.
2442  */
2443 static int __devinit
2444 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2445 {
2446         const struct pci_device_id *blacklist;
2447         int num_iomem, num_port, first_port = -1, i;
2448
2449         /*
2450          * If it is not a communications device or the programming
2451          * interface is greater than 6, give up.
2452          *
2453          * (Should we try to make guesses for multiport serial devices
2454          * later?)
2455          */
2456         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2457              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2458             (dev->class & 0xff) > 6)
2459                 return -ENODEV;
2460
2461         /*
2462          * Do not access blacklisted devices that are known not to
2463          * feature serial ports.
2464          */
2465         for (blacklist = softmodem_blacklist;
2466              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2467              blacklist++) {
2468                 if (dev->vendor == blacklist->vendor &&
2469                     dev->device == blacklist->device)
2470                         return -ENODEV;
2471         }
2472
2473         num_iomem = num_port = 0;
2474         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2475                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2476                         num_port++;
2477                         if (first_port == -1)
2478                                 first_port = i;
2479                 }
2480                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2481                         num_iomem++;
2482         }
2483
2484         /*
2485          * If there is 1 or 0 iomem regions, and exactly one port,
2486          * use it.  We guess the number of ports based on the IO
2487          * region size.
2488          */
2489         if (num_iomem <= 1 && num_port == 1) {
2490                 board->flags = first_port;
2491                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2492                 return 0;
2493         }
2494
2495         /*
2496          * Now guess if we've got a board which indexes by BARs.
2497          * Each IO BAR should be 8 bytes, and they should follow
2498          * consecutively.
2499          */
2500         first_port = -1;
2501         num_port = 0;
2502         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2503                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2504                     pci_resource_len(dev, i) == 8 &&
2505                     (first_port == -1 || (first_port + num_port) == i)) {
2506                         num_port++;
2507                         if (first_port == -1)
2508                                 first_port = i;
2509                 }
2510         }
2511
2512         if (num_port > 1) {
2513                 board->flags = first_port | FL_BASE_BARS;
2514                 board->num_ports = num_port;
2515                 return 0;
2516         }
2517
2518         return -ENODEV;
2519 }
2520
2521 static inline int
2522 serial_pci_matches(const struct pciserial_board *board,
2523                    const struct pciserial_board *guessed)
2524 {
2525         return
2526             board->num_ports == guessed->num_ports &&
2527             board->base_baud == guessed->base_baud &&
2528             board->uart_offset == guessed->uart_offset &&
2529             board->reg_shift == guessed->reg_shift &&
2530             board->first_offset == guessed->first_offset;
2531 }
2532
2533 struct serial_private *
2534 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2535 {
2536         struct uart_port serial_port;
2537         struct serial_private *priv;
2538         struct pci_serial_quirk *quirk;
2539         int rc, nr_ports, i;
2540
2541         nr_ports = board->num_ports;
2542
2543         /*
2544          * Find an init and setup quirks.
2545          */
2546         quirk = find_quirk(dev);
2547
2548         /*
2549          * Run the new-style initialization function.
2550          * The initialization function returns:
2551          *  <0  - error
2552          *   0  - use board->num_ports
2553          *  >0  - number of ports
2554          */
2555         if (quirk->init) {
2556                 rc = quirk->init(dev);
2557                 if (rc < 0) {
2558                         priv = ERR_PTR(rc);
2559                         goto err_out;
2560                 }
2561                 if (rc)
2562                         nr_ports = rc;
2563         }
2564
2565         priv = kzalloc(sizeof(struct serial_private) +
2566                        sizeof(unsigned int) * nr_ports,
2567                        GFP_KERNEL);
2568         if (!priv) {
2569                 priv = ERR_PTR(-ENOMEM);
2570                 goto err_deinit;
2571         }
2572
2573         priv->dev = dev;
2574         priv->quirk = quirk;
2575
2576         memset(&serial_port, 0, sizeof(struct uart_port));
2577         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2578         serial_port.uartclk = board->base_baud * 16;
2579         serial_port.irq = get_pci_irq(dev, board);
2580         serial_port.dev = &dev->dev;
2581
2582         for (i = 0; i < nr_ports; i++) {
2583                 if (quirk->setup(priv, board, &serial_port, i))
2584                         break;
2585
2586 #ifdef SERIAL_DEBUG_PCI
2587                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2588                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2589 #endif
2590
2591                 priv->line[i] = serial8250_register_port(&serial_port);
2592                 if (priv->line[i] < 0) {
2593                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2594                         break;
2595                 }
2596         }
2597         priv->nr = i;
2598         return priv;
2599
2600 err_deinit:
2601         if (quirk->exit)
2602                 quirk->exit(dev);
2603 err_out:
2604         return priv;
2605 }
2606 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2607
2608 void pciserial_remove_ports(struct serial_private *priv)
2609 {
2610         struct pci_serial_quirk *quirk;
2611         int i;
2612
2613         for (i = 0; i < priv->nr; i++)
2614                 serial8250_unregister_port(priv->line[i]);
2615
2616         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2617                 if (priv->remapped_bar[i])
2618                         iounmap(priv->remapped_bar[i]);
2619                 priv->remapped_bar[i] = NULL;
2620         }
2621
2622         /*
2623          * Find the exit quirks.
2624          */
2625         quirk = find_quirk(priv->dev);
2626         if (quirk->exit)
2627                 quirk->exit(priv->dev);
2628
2629         kfree(priv);
2630 }
2631 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2632
2633 void pciserial_suspend_ports(struct serial_private *priv)
2634 {
2635         int i;
2636
2637         for (i = 0; i < priv->nr; i++)
2638                 if (priv->line[i] >= 0)
2639                         serial8250_suspend_port(priv->line[i]);
2640 }
2641 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2642
2643 void pciserial_resume_ports(struct serial_private *priv)
2644 {
2645         int i;
2646
2647         /*
2648          * Ensure that the board is correctly configured.
2649          */
2650         if (priv->quirk->init)
2651                 priv->quirk->init(priv->dev);
2652
2653         for (i = 0; i < priv->nr; i++)
2654                 if (priv->line[i] >= 0)
2655                         serial8250_resume_port(priv->line[i]);
2656 }
2657 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2658
2659 /*
2660  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2661  * to the arrangement of serial ports on a PCI card.
2662  */
2663 static int __devinit
2664 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2665 {
2666         struct pci_serial_quirk *quirk;
2667         struct serial_private *priv;
2668         const struct pciserial_board *board;
2669         struct pciserial_board tmp;
2670         int rc;
2671
2672         quirk = find_quirk(dev);
2673         if (quirk->probe) {
2674                 rc = quirk->probe(dev);
2675                 if (rc)
2676                         return rc;
2677         }
2678
2679         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2680                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2681                         ent->driver_data);
2682                 return -EINVAL;
2683         }
2684
2685         board = &pci_boards[ent->driver_data];
2686
2687         rc = pci_enable_device(dev);
2688         if (rc)
2689                 return rc;
2690
2691         if (ent->driver_data == pbn_default) {
2692                 /*
2693                  * Use a copy of the pci_board entry for this;
2694                  * avoid changing entries in the table.
2695                  */
2696                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2697                 board = &tmp;
2698
2699                 /*
2700                  * We matched one of our class entries.  Try to
2701                  * determine the parameters of this board.
2702                  */
2703                 rc = serial_pci_guess_board(dev, &tmp);
2704                 if (rc)
2705                         goto disable;
2706         } else {
2707                 /*
2708                  * We matched an explicit entry.  If we are able to
2709                  * detect this boards settings with our heuristic,
2710                  * then we no longer need this entry.
2711                  */
2712                 memcpy(&tmp, &pci_boards[pbn_default],
2713                        sizeof(struct pciserial_board));
2714                 rc = serial_pci_guess_board(dev, &tmp);
2715                 if (rc == 0 && serial_pci_matches(board, &tmp))
2716                         moan_device("Redundant entry in serial pci_table.",
2717                                     dev);
2718         }
2719
2720         priv = pciserial_init_ports(dev, board);
2721         if (!IS_ERR(priv)) {
2722                 pci_set_drvdata(dev, priv);
2723                 return 0;
2724         }
2725
2726         rc = PTR_ERR(priv);
2727
2728  disable:
2729         pci_disable_device(dev);
2730         return rc;
2731 }
2732
2733 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2734 {
2735         struct serial_private *priv = pci_get_drvdata(dev);
2736
2737         pci_set_drvdata(dev, NULL);
2738
2739         pciserial_remove_ports(priv);
2740
2741         pci_disable_device(dev);
2742 }
2743
2744 #ifdef CONFIG_PM
2745 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2746 {
2747         struct serial_private *priv = pci_get_drvdata(dev);
2748
2749         if (priv)
2750                 pciserial_suspend_ports(priv);
2751
2752         pci_save_state(dev);
2753         pci_set_power_state(dev, pci_choose_state(dev, state));
2754         return 0;
2755 }
2756
2757 static int pciserial_resume_one(struct pci_dev *dev)
2758 {
2759         int err;
2760         struct serial_private *priv = pci_get_drvdata(dev);
2761
2762         pci_set_power_state(dev, PCI_D0);
2763         pci_restore_state(dev);
2764
2765         if (priv) {
2766                 /*
2767                  * The device may have been disabled.  Re-enable it.
2768                  */
2769                 err = pci_enable_device(dev);
2770                 /* FIXME: We cannot simply error out here */
2771                 if (err)
2772                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2773                 pciserial_resume_ports(priv);
2774         }
2775         return 0;
2776 }
2777 #endif
2778
2779 static struct pci_device_id serial_pci_tbl[] = {
2780         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2781         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2782                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2783                 pbn_b2_8_921600 },
2784         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2785                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2786                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2787                 pbn_b1_8_1382400 },
2788         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2789                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2790                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2791                 pbn_b1_4_1382400 },
2792         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2793                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2794                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2795                 pbn_b1_2_1382400 },
2796         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2797                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2798                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2799                 pbn_b1_8_1382400 },
2800         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2801                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2802                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2803                 pbn_b1_4_1382400 },
2804         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2805                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2806                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2807                 pbn_b1_2_1382400 },
2808         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2809                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2810                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2811                 pbn_b1_8_921600 },
2812         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2813                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2814                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2815                 pbn_b1_8_921600 },
2816         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2817                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2818                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2819                 pbn_b1_4_921600 },
2820         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2821                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2822                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2823                 pbn_b1_4_921600 },
2824         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2825                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2826                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2827                 pbn_b1_2_921600 },
2828         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2829                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2830                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2831                 pbn_b1_8_921600 },
2832         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2833                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2834                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2835                 pbn_b1_8_921600 },
2836         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2837                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2838                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2839                 pbn_b1_4_921600 },
2840         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2841                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2842                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2843                 pbn_b1_2_1250000 },
2844         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2845                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2846                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2847                 pbn_b0_2_1843200 },
2848         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2849                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2850                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2851                 pbn_b0_4_1843200 },
2852         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2853                 PCI_VENDOR_ID_AFAVLAB,
2854                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2855                 pbn_b0_4_1152000 },
2856         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2857                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2858                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2859                 pbn_b0_2_1843200_200 },
2860         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2861                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2862                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2863                 pbn_b0_4_1843200_200 },
2864         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2865                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2866                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2867                 pbn_b0_8_1843200_200 },
2868         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2869                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2870                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2871                 pbn_b0_2_1843200_200 },
2872         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2873                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2874                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2875                 pbn_b0_4_1843200_200 },
2876         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2877                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2878                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2879                 pbn_b0_8_1843200_200 },
2880         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2881                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2882                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2883                 pbn_b0_2_1843200_200 },
2884         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2885                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2886                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2887                 pbn_b0_4_1843200_200 },
2888         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2889                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2890                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2891                 pbn_b0_8_1843200_200 },
2892         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2893                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2894                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2895                 pbn_b0_2_1843200_200 },
2896         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2897                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2898                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2899                 pbn_b0_4_1843200_200 },
2900         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2901                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2902                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2903                 pbn_b0_8_1843200_200 },
2904         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2905                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2906                 0, 0, pbn_exar_ibm_saturn },
2907
2908         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910                 pbn_b2_bt_1_115200 },
2911         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913                 pbn_b2_bt_2_115200 },
2914         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916                 pbn_b2_bt_4_115200 },
2917         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2918                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919                 pbn_b2_bt_2_115200 },
2920         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922                 pbn_b2_bt_4_115200 },
2923         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2925                 pbn_b2_8_115200 },
2926         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2927                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2928                 pbn_b2_8_460800 },
2929         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931                 pbn_b2_8_115200 },
2932
2933         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2935                 pbn_b2_bt_2_115200 },
2936         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2938                 pbn_b2_bt_2_921600 },
2939         /*
2940          * VScom SPCOM800, from sl@s.pl
2941          */
2942         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2944                 pbn_b2_8_921600 },
2945         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2947                 pbn_b2_4_921600 },
2948         /* Unknown card - subdevice 0x1584 */
2949         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2950                 PCI_VENDOR_ID_PLX,
2951                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2952                 pbn_b0_4_115200 },
2953         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2954                 PCI_SUBVENDOR_ID_KEYSPAN,
2955                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2956                 pbn_panacom },
2957         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2959                 pbn_panacom4 },
2960         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2962                 pbn_panacom2 },
2963         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2964                 PCI_VENDOR_ID_ESDGMBH,
2965                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2966                 pbn_b2_4_115200 },
2967         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2968                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2969                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2970                 pbn_b2_4_460800 },
2971         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2972                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2973                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2974                 pbn_b2_8_460800 },
2975         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2976                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2977                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2978                 pbn_b2_16_460800 },
2979         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2980                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2981                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2982                 pbn_b2_16_460800 },
2983         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2984                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2985                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2986                 pbn_b2_4_460800 },
2987         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2988                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2989                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2990                 pbn_b2_8_460800 },
2991         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2992                 PCI_SUBVENDOR_ID_EXSYS,
2993                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2994                 pbn_exsys_4055 },
2995         /*
2996          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2997          * (Exoray@isys.ca)
2998          */
2999         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3000                 0x10b5, 0x106a, 0, 0,
3001                 pbn_plx_romulus },
3002         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3004                 pbn_b1_4_115200 },
3005         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3007                 pbn_b1_2_115200 },
3008         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3010                 pbn_b1_8_115200 },
3011         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3013                 pbn_b1_8_115200 },
3014         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3015                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3016                 0, 0,
3017                 pbn_b0_4_921600 },
3018         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3019                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3020                 0, 0,
3021                 pbn_b0_4_1152000 },
3022         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3023                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3024                 pbn_b0_bt_2_921600 },
3025
3026                 /*
3027                  * The below card is a little controversial since it is the
3028                  * subject of a PCI vendor/device ID clash.  (See
3029                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3030                  * For now just used the hex ID 0x950a.
3031                  */
3032         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3033                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3034                 pbn_b0_2_115200 },
3035         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037                 pbn_b0_2_1130000 },
3038         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3039                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3040                 pbn_b0_1_921600 },
3041         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3043                 pbn_b0_4_115200 },
3044         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3046                 pbn_b0_bt_2_921600 },
3047         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3048                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3049                 pbn_b2_8_1152000 },
3050
3051         /*
3052          * Oxford Semiconductor Inc. Tornado PCI express device range.
3053          */
3054         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3055                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3056                 pbn_b0_1_4000000 },
3057         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059                 pbn_b0_1_4000000 },
3060         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062                 pbn_oxsemi_1_4000000 },
3063         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3065                 pbn_oxsemi_1_4000000 },
3066         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3068                 pbn_b0_1_4000000 },
3069         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3071                 pbn_b0_1_4000000 },
3072         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3074                 pbn_oxsemi_1_4000000 },
3075         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077                 pbn_oxsemi_1_4000000 },
3078         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080                 pbn_b0_1_4000000 },
3081         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083                 pbn_b0_1_4000000 },
3084         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086                 pbn_b0_1_4000000 },
3087         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089                 pbn_b0_1_4000000 },
3090         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092                 pbn_oxsemi_2_4000000 },
3093         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095                 pbn_oxsemi_2_4000000 },
3096         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098                 pbn_oxsemi_4_4000000 },
3099         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101                 pbn_oxsemi_4_4000000 },
3102         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3104                 pbn_oxsemi_8_4000000 },
3105         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_oxsemi_8_4000000 },
3108         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3110                 pbn_oxsemi_1_4000000 },
3111         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3113                 pbn_oxsemi_1_4000000 },
3114         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3116                 pbn_oxsemi_1_4000000 },
3117         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3119                 pbn_oxsemi_1_4000000 },
3120         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3121                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3122                 pbn_oxsemi_1_4000000 },
3123         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3125                 pbn_oxsemi_1_4000000 },
3126         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3128                 pbn_oxsemi_1_4000000 },
3129         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3131                 pbn_oxsemi_1_4000000 },
3132         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3134                 pbn_oxsemi_1_4000000 },
3135         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3137                 pbn_oxsemi_1_4000000 },
3138         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3139                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140                 pbn_oxsemi_1_4000000 },
3141         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143                 pbn_oxsemi_1_4000000 },
3144         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146                 pbn_oxsemi_1_4000000 },
3147         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149                 pbn_oxsemi_1_4000000 },
3150         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152                 pbn_oxsemi_1_4000000 },
3153         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155                 pbn_oxsemi_1_4000000 },
3156         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158                 pbn_oxsemi_1_4000000 },
3159         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161                 pbn_oxsemi_1_4000000 },
3162         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164                 pbn_oxsemi_1_4000000 },
3165         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167                 pbn_oxsemi_1_4000000 },
3168         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170                 pbn_oxsemi_1_4000000 },
3171         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3172                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173                 pbn_oxsemi_1_4000000 },
3174         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176                 pbn_oxsemi_1_4000000 },
3177         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179                 pbn_oxsemi_1_4000000 },
3180         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182                 pbn_oxsemi_1_4000000 },
3183         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185                 pbn_oxsemi_1_4000000 },
3186         /*
3187          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3188          */
3189         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3190                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3191                 pbn_oxsemi_1_4000000 },
3192         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3193                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3194                 pbn_oxsemi_2_4000000 },
3195         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3196                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3197                 pbn_oxsemi_4_4000000 },
3198         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3199                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3200                 pbn_oxsemi_8_4000000 },
3201
3202         /*
3203          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3204          */
3205         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3206                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3207                 pbn_oxsemi_2_4000000 },
3208
3209         /*
3210          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3211          * from skokodyn@yahoo.com
3212          */
3213         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3214                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3215                 pbn_sbsxrsio },
3216         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3217                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3218                 pbn_sbsxrsio },
3219         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3220                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3221                 pbn_sbsxrsio },
3222         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3223                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3224                 pbn_sbsxrsio },
3225
3226         /*
3227          * Digitan DS560-558, from jimd@esoft.com
3228          */
3229         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3230                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231                 pbn_b1_1_115200 },
3232
3233         /*
3234          * Titan Electronic cards
3235          *  The 400L and 800L have a custom setup quirk.
3236          */
3237         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_b0_1_921600 },
3240         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b0_2_921600 },
3243         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_b0_4_921600 },
3246         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_b0_4_921600 },
3249         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_b1_1_921600 },
3252         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_b1_bt_2_921600 },
3255         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_b0_bt_4_921600 },
3258         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b0_bt_8_921600 },
3261         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_b4_bt_2_921600 },
3264         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_b4_bt_4_921600 },
3267         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_b4_bt_8_921600 },
3270         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272                 pbn_b0_4_921600 },
3273         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275                 pbn_b0_4_921600 },
3276         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278                 pbn_b0_4_921600 },
3279         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281                 pbn_oxsemi_1_4000000 },
3282         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284                 pbn_oxsemi_2_4000000 },
3285         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi_4_4000000 },
3288         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290                 pbn_oxsemi_8_4000000 },
3291         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293                 pbn_oxsemi_2_4000000 },
3294         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296                 pbn_oxsemi_2_4000000 },
3297
3298         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300                 pbn_b2_1_460800 },
3301         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3303                 pbn_b2_1_460800 },
3304         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3306                 pbn_b2_1_460800 },
3307         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309                 pbn_b2_bt_2_921600 },
3310         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312                 pbn_b2_bt_2_921600 },
3313         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315                 pbn_b2_bt_2_921600 },
3316         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3318                 pbn_b2_bt_4_921600 },
3319         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321                 pbn_b2_bt_4_921600 },
3322         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3324                 pbn_b2_bt_4_921600 },
3325         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3327                 pbn_b0_1_921600 },
3328         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3330                 pbn_b0_1_921600 },
3331         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3333                 pbn_b0_1_921600 },
3334         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3336                 pbn_b0_bt_2_921600 },
3337         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3339                 pbn_b0_bt_2_921600 },
3340         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3342                 pbn_b0_bt_2_921600 },
3343         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3345                 pbn_b0_bt_4_921600 },
3346         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3348                 pbn_b0_bt_4_921600 },
3349         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351                 pbn_b0_bt_4_921600 },
3352         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3354                 pbn_b0_bt_8_921600 },
3355         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3356                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3357                 pbn_b0_bt_8_921600 },
3358         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3359                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3360                 pbn_b0_bt_8_921600 },
3361
3362         /*
3363          * Computone devices submitted by Doug McNash dmcnash@computone.com
3364          */
3365         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3366                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3367                 0, 0, pbn_computone_4 },
3368         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3369                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3370                 0, 0, pbn_computone_8 },
3371         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3372                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3373                 0, 0, pbn_computone_6 },
3374
3375         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3376                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3377                 pbn_oxsemi },
3378         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3379                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3380                 pbn_b0_bt_1_921600 },
3381
3382         /*
3383          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3384          */
3385         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387                 pbn_b0_bt_8_115200 },
3388         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390                 pbn_b0_bt_8_115200 },
3391
3392         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3394                 pbn_b0_bt_2_115200 },
3395         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397                 pbn_b0_bt_2_115200 },
3398         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400                 pbn_b0_bt_2_115200 },
3401         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403                 pbn_b0_bt_2_115200 },
3404         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406                 pbn_b0_bt_2_115200 },
3407         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409                 pbn_b0_bt_4_460800 },
3410         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412                 pbn_b0_bt_4_460800 },
3413         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415                 pbn_b0_bt_2_460800 },
3416         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418                 pbn_b0_bt_2_460800 },
3419         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421                 pbn_b0_bt_2_460800 },
3422         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424                 pbn_b0_bt_1_115200 },
3425         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427                 pbn_b0_bt_1_460800 },
3428
3429         /*
3430          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3431          * Cards are identified by their subsystem vendor IDs, which
3432          * (in hex) match the model number.
3433          *
3434          * Note that JC140x are RS422/485 cards which require ox950
3435          * ACR = 0x10, and as such are not currently fully supported.
3436          */
3437         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3438                 0x1204, 0x0004, 0, 0,
3439                 pbn_b0_4_921600 },
3440         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3441                 0x1208, 0x0004, 0, 0,
3442                 pbn_b0_4_921600 },
3443 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3444                 0x1402, 0x0002, 0, 0,
3445                 pbn_b0_2_921600 }, */
3446 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3447                 0x1404, 0x0004, 0, 0,
3448                 pbn_b0_4_921600 }, */
3449         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3450                 0x1208, 0x0004, 0, 0,
3451                 pbn_b0_4_921600 },
3452
3453         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3454                 0x1204, 0x0004, 0, 0,
3455                 pbn_b0_4_921600 },
3456         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3457                 0x1208, 0x0004, 0, 0,
3458                 pbn_b0_4_921600 },
3459         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3460                 0x1208, 0x0004, 0, 0,
3461                 pbn_b0_4_921600 },
3462         /*
3463          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3464          */
3465         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467                 pbn_b1_1_1382400 },
3468
3469         /*
3470          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3471          */
3472         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474                 pbn_b1_1_1382400 },
3475
3476         /*
3477          * RAStel 2 port modem, gerg@moreton.com.au
3478          */
3479         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481                 pbn_b2_bt_2_115200 },
3482
3483         /*
3484          * EKF addition for i960 Boards form EKF with serial port
3485          */
3486         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3487                 0xE4BF, PCI_ANY_ID, 0, 0,
3488                 pbn_intel_i960 },
3489
3490         /*
3491          * Xircom Cardbus/Ethernet combos
3492          */
3493         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_b0_1_115200 },
3496         /*
3497          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3498          */
3499         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_b0_1_115200 },
3502
3503         /*
3504          * Untested PCI modems, sent in from various folks...
3505          */
3506
3507         /*
3508          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3509          */
3510         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3511                 0x1048, 0x1500, 0, 0,
3512                 pbn_b1_1_115200 },
3513
3514         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3515                 0xFF00, 0, 0, 0,
3516                 pbn_sgi_ioc3 },
3517
3518         /*
3519          * HP Diva card
3520          */
3521         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3522                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3523                 pbn_b1_1_115200 },
3524         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526                 pbn_b0_5_115200 },
3527         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3529                 pbn_b2_1_115200 },
3530
3531         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3532                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533                 pbn_b3_2_115200 },
3534         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3535                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536                 pbn_b3_4_115200 },
3537         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3538                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539                 pbn_b3_8_115200 },
3540
3541         /*
3542          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3543          */
3544         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3545                 PCI_ANY_ID, PCI_ANY_ID,
3546                 0,
3547                 0, pbn_exar_XR17C152 },
3548         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3549                 PCI_ANY_ID, PCI_ANY_ID,
3550                 0,
3551                 0, pbn_exar_XR17C154 },
3552         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3553                 PCI_ANY_ID, PCI_ANY_ID,
3554                 0,
3555                 0, pbn_exar_XR17C158 },
3556
3557         /*
3558          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3559          */
3560         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562                 pbn_b0_1_115200 },
3563         /*
3564          * ITE
3565          */
3566         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3567                 PCI_ANY_ID, PCI_ANY_ID,
3568                 0, 0,
3569                 pbn_b1_bt_1_115200 },
3570
3571         /*
3572          * IntaShield IS-200
3573          */
3574         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3576                 pbn_b2_2_115200 },
3577         /*
3578          * IntaShield IS-400
3579          */
3580         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3582                 pbn_b2_4_115200 },
3583         /*
3584          * Perle PCI-RAS cards
3585          */
3586         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3587                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3588                 0, 0, pbn_b2_4_921600 },
3589         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3590                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3591                 0, 0, pbn_b2_8_921600 },
3592
3593         /*
3594          * Mainpine series cards: Fairly standard layout but fools
3595          * parts of the autodetect in some cases and uses otherwise
3596          * unmatched communications subclasses in the PCI Express case
3597          */
3598
3599         {       /* RockForceDUO */
3600                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3601                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3602                 0, 0, pbn_b0_2_115200 },
3603         {       /* RockForceQUATRO */
3604                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3605                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3606                 0, 0, pbn_b0_4_115200 },
3607         {       /* RockForceDUO+ */
3608                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3609                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3610                 0, 0, pbn_b0_2_115200 },
3611         {       /* RockForceQUATRO+ */
3612                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3613                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3614                 0, 0, pbn_b0_4_115200 },
3615         {       /* RockForce+ */
3616                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3617                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3618                 0, 0, pbn_b0_2_115200 },
3619         {       /* RockForce+ */
3620                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3621                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3622                 0, 0, pbn_b0_4_115200 },
3623         {       /* RockForceOCTO+ */
3624                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3625                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3626                 0, 0, pbn_b0_8_115200 },
3627         {       /* RockForceDUO+ */
3628                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3629                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3630                 0, 0, pbn_b0_2_115200 },
3631         {       /* RockForceQUARTRO+ */
3632                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3633                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3634                 0, 0, pbn_b0_4_115200 },
3635         {       /* RockForceOCTO+ */
3636                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3637                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3638                 0, 0, pbn_b0_8_115200 },
3639         {       /* RockForceD1 */
3640                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3641                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3642                 0, 0, pbn_b0_1_115200 },
3643         {       /* RockForceF1 */
3644                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3645                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3646                 0, 0, pbn_b0_1_115200 },
3647         {       /* RockForceD2 */
3648                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3649                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3650                 0, 0, pbn_b0_2_115200 },
3651         {       /* RockForceF2 */
3652                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3653                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3654                 0, 0, pbn_b0_2_115200 },
3655         {       /* RockForceD4 */
3656                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3657                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3658                 0, 0, pbn_b0_4_115200 },
3659         {       /* RockForceF4 */
3660                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3661                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3662                 0, 0, pbn_b0_4_115200 },
3663         {       /* RockForceD8 */
3664                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3665                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3666                 0, 0, pbn_b0_8_115200 },
3667         {       /* RockForceF8 */
3668                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3669                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3670                 0, 0, pbn_b0_8_115200 },
3671         {       /* IQ Express D1 */
3672                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3673                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3674                 0, 0, pbn_b0_1_115200 },
3675         {       /* IQ Express F1 */
3676                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3677                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3678                 0, 0, pbn_b0_1_115200 },
3679         {       /* IQ Express D2 */
3680                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3681                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3682                 0, 0, pbn_b0_2_115200 },
3683         {       /* IQ Express F2 */
3684                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3685                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3686                 0, 0, pbn_b0_2_115200 },
3687         {       /* IQ Express D4 */
3688                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3689                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3690                 0, 0, pbn_b0_4_115200 },
3691         {       /* IQ Express F4 */
3692                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3693                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3694                 0, 0, pbn_b0_4_115200 },
3695         {       /* IQ Express D8 */
3696                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3697                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3698                 0, 0, pbn_b0_8_115200 },
3699         {       /* IQ Express F8 */
3700                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3701                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3702                 0, 0, pbn_b0_8_115200 },
3703
3704
3705         /*
3706          * PA Semi PA6T-1682M on-chip UART
3707          */
3708         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3710                 pbn_pasemi_1682M },
3711
3712         /*
3713          * National Instruments
3714          */
3715         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3716                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3717                 pbn_b1_16_115200 },
3718         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3719                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3720                 pbn_b1_8_115200 },
3721         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3722                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723                 pbn_b1_bt_4_115200 },
3724         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3725                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3726                 pbn_b1_bt_2_115200 },
3727         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3729                 pbn_b1_bt_4_115200 },
3730         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3732                 pbn_b1_bt_2_115200 },
3733         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3735                 pbn_b1_16_115200 },
3736         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3738                 pbn_b1_8_115200 },
3739         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3741                 pbn_b1_bt_4_115200 },
3742         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3743                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3744                 pbn_b1_bt_2_115200 },
3745         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3746                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3747                 pbn_b1_bt_4_115200 },
3748         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3750                 pbn_b1_bt_2_115200 },
3751         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3753                 pbn_ni8430_2 },
3754         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3756                 pbn_ni8430_2 },
3757         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3758                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3759                 pbn_ni8430_4 },
3760         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3761                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3762                 pbn_ni8430_4 },
3763         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3764                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3765                 pbn_ni8430_8 },
3766         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3767                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3768                 pbn_ni8430_8 },
3769         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3770                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3771                 pbn_ni8430_16 },
3772         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3773                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3774                 pbn_ni8430_16 },
3775         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3777                 pbn_ni8430_2 },
3778         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3780                 pbn_ni8430_2 },
3781         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3783                 pbn_ni8430_4 },
3784         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3785                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3786                 pbn_ni8430_4 },
3787
3788         /*
3789         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3790         */
3791         {       PCI_VENDOR_ID_ADDIDATA,
3792                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3793                 PCI_ANY_ID,
3794                 PCI_ANY_ID,
3795                 0,
3796                 0,
3797                 pbn_b0_4_115200 },
3798
3799         {       PCI_VENDOR_ID_ADDIDATA,
3800                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3801                 PCI_ANY_ID,
3802                 PCI_ANY_ID,
3803                 0,
3804                 0,
3805                 pbn_b0_2_115200 },
3806
3807         {       PCI_VENDOR_ID_ADDIDATA,
3808                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3809                 PCI_ANY_ID,
3810                 PCI_ANY_ID,
3811                 0,
3812                 0,
3813                 pbn_b0_1_115200 },
3814
3815         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3816                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3817                 PCI_ANY_ID,
3818                 PCI_ANY_ID,
3819                 0,
3820                 0,
3821                 pbn_b1_8_115200 },
3822
3823         {       PCI_VENDOR_ID_ADDIDATA,
3824                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3825                 PCI_ANY_ID,
3826                 PCI_ANY_ID,
3827                 0,
3828                 0,
3829                 pbn_b0_4_115200 },
3830
3831         {       PCI_VENDOR_ID_ADDIDATA,
3832                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3833                 PCI_ANY_ID,
3834                 PCI_ANY_ID,
3835                 0,
3836                 0,
3837                 pbn_b0_2_115200 },
3838
3839         {       PCI_VENDOR_ID_ADDIDATA,
3840                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3841                 PCI_ANY_ID,
3842                 PCI_ANY_ID,
3843                 0,
3844                 0,
3845                 pbn_b0_1_115200 },
3846
3847         {       PCI_VENDOR_ID_ADDIDATA,
3848                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3849                 PCI_ANY_ID,
3850                 PCI_ANY_ID,
3851                 0,
3852                 0,
3853                 pbn_b0_4_115200 },
3854
3855         {       PCI_VENDOR_ID_ADDIDATA,
3856                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3857                 PCI_ANY_ID,
3858                 PCI_ANY_ID,
3859                 0,
3860                 0,
3861                 pbn_b0_2_115200 },
3862
3863         {       PCI_VENDOR_ID_ADDIDATA,
3864                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3865                 PCI_ANY_ID,
3866                 PCI_ANY_ID,
3867                 0,
3868                 0,
3869                 pbn_b0_1_115200 },
3870
3871         {       PCI_VENDOR_ID_ADDIDATA,
3872                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3873                 PCI_ANY_ID,
3874                 PCI_ANY_ID,
3875                 0,
3876                 0,
3877                 pbn_b0_8_115200 },
3878
3879         {       PCI_VENDOR_ID_ADDIDATA,
3880                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3881                 PCI_ANY_ID,
3882                 PCI_ANY_ID,
3883                 0,
3884                 0,
3885                 pbn_ADDIDATA_PCIe_4_3906250 },
3886
3887         {       PCI_VENDOR_ID_ADDIDATA,
3888                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3889                 PCI_ANY_ID,
3890                 PCI_ANY_ID,
3891                 0,
3892                 0,
3893                 pbn_ADDIDATA_PCIe_2_3906250 },
3894
3895         {       PCI_VENDOR_ID_ADDIDATA,
3896                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3897                 PCI_ANY_ID,
3898                 PCI_ANY_ID,
3899                 0,
3900                 0,
3901                 pbn_ADDIDATA_PCIe_1_3906250 },
3902
3903         {       PCI_VENDOR_ID_ADDIDATA,
3904                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3905                 PCI_ANY_ID,
3906                 PCI_ANY_ID,
3907                 0,
3908                 0,
3909                 pbn_ADDIDATA_PCIe_8_3906250 },
3910
3911         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3912                 PCI_VENDOR_ID_IBM, 0x0299,
3913                 0, 0, pbn_b0_bt_2_115200 },
3914
3915         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3916                 0xA000, 0x1000,
3917                 0, 0, pbn_b0_1_115200 },
3918
3919         /* the 9901 is a rebranded 9912 */
3920         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
3921                 0xA000, 0x1000,
3922                 0, 0, pbn_b0_1_115200 },
3923
3924         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
3925                 0xA000, 0x1000,
3926                 0, 0, pbn_b0_1_115200 },
3927
3928         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
3929                 0xA000, 0x1000,
3930                 0, 0, pbn_b0_1_115200 },
3931
3932         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
3933                 0xA000, 0x1000,
3934                 0, 0, pbn_b0_1_115200 },
3935
3936         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
3937                 0xA000, 0x3002,
3938                 0, 0, pbn_NETMOS9900_2s_115200 },
3939
3940         /*
3941          * Best Connectivity PCI Multi I/O cards
3942          */
3943
3944         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3945                 0xA000, 0x1000,
3946                 0, 0, pbn_b0_1_115200 },
3947
3948         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3949                 0xA000, 0x3004,
3950                 0, 0, pbn_b0_bt_4_115200 },
3951         /* Intel CE4100 */
3952         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3953                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
3954                 pbn_ce4100_1_115200 },
3955
3956         /*
3957          * Cronyx Omega PCI
3958          */
3959         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
3960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961                 pbn_omegapci },
3962
3963         /*
3964          * These entries match devices with class COMMUNICATION_SERIAL,
3965          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3966          */
3967         {       PCI_ANY_ID, PCI_ANY_ID,
3968                 PCI_ANY_ID, PCI_ANY_ID,
3969                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3970                 0xffff00, pbn_default },
3971         {       PCI_ANY_ID, PCI_ANY_ID,
3972                 PCI_ANY_ID, PCI_ANY_ID,
3973                 PCI_CLASS_COMMUNICATION_MODEM << 8,
3974                 0xffff00, pbn_default },
3975         {       PCI_ANY_ID, PCI_ANY_ID,
3976                 PCI_ANY_ID, PCI_ANY_ID,
3977                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3978                 0xffff00, pbn_default },
3979         { 0, }
3980 };
3981
3982 static struct pci_driver serial_pci_driver = {
3983         .name           = "serial",
3984         .probe          = pciserial_init_one,
3985         .remove         = __devexit_p(pciserial_remove_one),
3986 #ifdef CONFIG_PM
3987         .suspend        = pciserial_suspend_one,
3988         .resume         = pciserial_resume_one,
3989 #endif
3990         .id_table       = serial_pci_tbl,
3991 };
3992
3993 static int __init serial8250_pci_init(void)
3994 {
3995         return pci_register_driver(&serial_pci_driver);
3996 }
3997
3998 static void __exit serial8250_pci_exit(void)
3999 {
4000         pci_unregister_driver(&serial_pci_driver);
4001 }
4002
4003 module_init(serial8250_pci_init);
4004 module_exit(serial8250_pci_exit);
4005
4006 MODULE_LICENSE("GPL");
4007 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4008 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);