2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
111 #define ATMEL_SERIAL_RINGSIZE 1024
114 * at91: 6 USARTs and one DBGU port (SAM9260)
117 #define ATMEL_MAX_UART 7
120 * We wrap our port structure around the generic uart_port.
122 struct atmel_uart_port {
123 struct uart_port uart; /* uart */
124 struct clk *clk; /* uart clock */
125 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
126 u32 backup_imr; /* IMR saved during suspend */
127 int break_active; /* break being received */
129 bool use_dma_rx; /* enable DMA receiver */
130 bool use_pdc_rx; /* enable PDC receiver */
131 short pdc_rx_idx; /* current PDC RX buffer */
132 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
134 bool use_dma_tx; /* enable DMA transmitter */
135 bool use_pdc_tx; /* enable PDC transmitter */
136 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
138 spinlock_t lock_tx; /* port lock */
139 spinlock_t lock_rx; /* port lock */
140 struct dma_chan *chan_tx;
141 struct dma_chan *chan_rx;
142 struct dma_async_tx_descriptor *desc_tx;
143 struct dma_async_tx_descriptor *desc_rx;
144 dma_cookie_t cookie_tx;
145 dma_cookie_t cookie_rx;
146 struct scatterlist sg_tx;
147 struct scatterlist sg_rx;
148 struct tasklet_struct tasklet;
149 unsigned int irq_status;
150 unsigned int irq_status_prev;
151 unsigned int status_change;
154 struct circ_buf rx_ring;
156 struct mctrl_gpios *gpios;
157 unsigned int tx_done_mask;
163 struct timer_list uart_timer;
166 unsigned int pending;
167 unsigned int pending_status;
168 spinlock_t lock_suspended;
170 int (*prepare_rx)(struct uart_port *port);
171 int (*prepare_tx)(struct uart_port *port);
172 void (*schedule_rx)(struct uart_port *port);
173 void (*schedule_tx)(struct uart_port *port);
174 void (*release_rx)(struct uart_port *port);
175 void (*release_tx)(struct uart_port *port);
178 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
179 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
182 static struct console atmel_console;
185 #if defined(CONFIG_OF)
186 static const struct of_device_id atmel_serial_dt_ids[] = {
187 { .compatible = "atmel,at91rm9200-usart" },
188 { .compatible = "atmel,at91sam9260-usart" },
193 static inline struct atmel_uart_port *
194 to_atmel_uart_port(struct uart_port *uart)
196 return container_of(uart, struct atmel_uart_port, uart);
199 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
201 return __raw_readl(port->membase + reg);
204 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
206 __raw_writel(value, port->membase + reg);
211 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
212 static inline u8 atmel_uart_read_char(struct uart_port *port)
214 return __raw_readl(port->membase + ATMEL_US_RHR);
217 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
219 __raw_writel(value, port->membase + ATMEL_US_THR);
224 static inline u8 atmel_uart_read_char(struct uart_port *port)
226 return __raw_readb(port->membase + ATMEL_US_RHR);
229 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
231 __raw_writeb(value, port->membase + ATMEL_US_THR);
236 #ifdef CONFIG_SERIAL_ATMEL_PDC
237 static bool atmel_use_pdc_rx(struct uart_port *port)
239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
241 return atmel_port->use_pdc_rx;
244 static bool atmel_use_pdc_tx(struct uart_port *port)
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248 return atmel_port->use_pdc_tx;
251 static bool atmel_use_pdc_rx(struct uart_port *port)
256 static bool atmel_use_pdc_tx(struct uart_port *port)
262 static bool atmel_use_dma_tx(struct uart_port *port)
264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
266 return atmel_port->use_dma_tx;
269 static bool atmel_use_dma_rx(struct uart_port *port)
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
273 return atmel_port->use_dma_rx;
276 static unsigned int atmel_get_lines_status(struct uart_port *port)
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279 unsigned int status, ret = 0;
281 status = atmel_uart_readl(port, ATMEL_US_CSR);
283 mctrl_gpio_get(atmel_port->gpios, &ret);
285 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
288 status &= ~ATMEL_US_CTS;
290 status |= ATMEL_US_CTS;
293 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
296 status &= ~ATMEL_US_DSR;
298 status |= ATMEL_US_DSR;
301 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
304 status &= ~ATMEL_US_RI;
306 status |= ATMEL_US_RI;
309 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
312 status &= ~ATMEL_US_DCD;
314 status |= ATMEL_US_DCD;
320 /* Enable or disable the rs485 support */
321 static int atmel_config_rs485(struct uart_port *port,
322 struct serial_rs485 *rs485conf)
324 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
327 /* Disable interrupts */
328 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
330 mode = atmel_uart_readl(port, ATMEL_US_MR);
332 /* Resetting serial mode to RS232 (0x0) */
333 mode &= ~ATMEL_US_USMODE;
335 port->rs485 = *rs485conf;
337 if (rs485conf->flags & SER_RS485_ENABLED) {
338 dev_dbg(port->dev, "Setting UART to RS485\n");
339 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
340 atmel_uart_writel(port, ATMEL_US_TTGR,
341 rs485conf->delay_rts_after_send);
342 mode |= ATMEL_US_USMODE_RS485;
344 dev_dbg(port->dev, "Setting UART to RS232\n");
345 if (atmel_use_pdc_tx(port))
346 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
349 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
351 atmel_uart_writel(port, ATMEL_US_MR, mode);
353 /* Enable interrupts */
354 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
360 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
362 static u_int atmel_tx_empty(struct uart_port *port)
364 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
370 * Set state of the modem control output lines
372 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
374 unsigned int control = 0;
375 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
376 unsigned int rts_paused, rts_ready;
377 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
379 /* override mode to RS485 if needed, otherwise keep the current mode */
380 if (port->rs485.flags & SER_RS485_ENABLED) {
381 atmel_uart_writel(port, ATMEL_US_TTGR,
382 port->rs485.delay_rts_after_send);
383 mode &= ~ATMEL_US_USMODE;
384 mode |= ATMEL_US_USMODE_RS485;
387 /* set the RTS line state according to the mode */
388 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
389 /* force RTS line to high level */
390 rts_paused = ATMEL_US_RTSEN;
392 /* give the control of the RTS line back to the hardware */
393 rts_ready = ATMEL_US_RTSDIS;
395 /* force RTS line to high level */
396 rts_paused = ATMEL_US_RTSDIS;
398 /* force RTS line to low level */
399 rts_ready = ATMEL_US_RTSEN;
402 if (mctrl & TIOCM_RTS)
403 control |= rts_ready;
405 control |= rts_paused;
407 if (mctrl & TIOCM_DTR)
408 control |= ATMEL_US_DTREN;
410 control |= ATMEL_US_DTRDIS;
412 atmel_uart_writel(port, ATMEL_US_CR, control);
414 mctrl_gpio_set(atmel_port->gpios, mctrl);
416 /* Local loopback mode? */
417 mode &= ~ATMEL_US_CHMODE;
418 if (mctrl & TIOCM_LOOP)
419 mode |= ATMEL_US_CHMODE_LOC_LOOP;
421 mode |= ATMEL_US_CHMODE_NORMAL;
423 atmel_uart_writel(port, ATMEL_US_MR, mode);
427 * Get state of the modem control input lines
429 static u_int atmel_get_mctrl(struct uart_port *port)
431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
432 unsigned int ret = 0, status;
434 status = atmel_uart_readl(port, ATMEL_US_CSR);
437 * The control signals are active low.
439 if (!(status & ATMEL_US_DCD))
441 if (!(status & ATMEL_US_CTS))
443 if (!(status & ATMEL_US_DSR))
445 if (!(status & ATMEL_US_RI))
448 return mctrl_gpio_get(atmel_port->gpios, &ret);
454 static void atmel_stop_tx(struct uart_port *port)
456 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
458 if (atmel_use_pdc_tx(port)) {
459 /* disable PDC transmit */
460 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
462 /* Disable interrupts */
463 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
465 if ((port->rs485.flags & SER_RS485_ENABLED) &&
466 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
467 atmel_start_rx(port);
471 * Start transmitting.
473 static void atmel_start_tx(struct uart_port *port)
475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
477 if (atmel_use_pdc_tx(port)) {
478 if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN)
479 /* The transmitter is already running. Yes, we
483 if ((port->rs485.flags & SER_RS485_ENABLED) &&
484 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
487 /* re-enable PDC transmit */
488 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
490 /* Enable interrupts */
491 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
495 * start receiving - port is in process of being opened.
497 static void atmel_start_rx(struct uart_port *port)
499 /* reset status and receiver */
500 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
502 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
504 if (atmel_use_pdc_rx(port)) {
505 /* enable PDC controller */
506 atmel_uart_writel(port, ATMEL_US_IER,
507 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
508 port->read_status_mask);
509 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
511 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
516 * Stop receiving - port is in process of being closed.
518 static void atmel_stop_rx(struct uart_port *port)
520 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
522 if (atmel_use_pdc_rx(port)) {
523 /* disable PDC receive */
524 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
525 atmel_uart_writel(port, ATMEL_US_IDR,
526 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
527 port->read_status_mask);
529 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
534 * Enable modem status interrupts
536 static void atmel_enable_ms(struct uart_port *port)
538 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
542 * Interrupt should not be enabled twice
544 if (atmel_port->ms_irq_enabled)
547 atmel_port->ms_irq_enabled = true;
549 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
550 ier |= ATMEL_US_CTSIC;
552 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
553 ier |= ATMEL_US_DSRIC;
555 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
556 ier |= ATMEL_US_RIIC;
558 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
559 ier |= ATMEL_US_DCDIC;
561 atmel_uart_writel(port, ATMEL_US_IER, ier);
563 mctrl_gpio_enable_ms(atmel_port->gpios);
567 * Disable modem status interrupts
569 static void atmel_disable_ms(struct uart_port *port)
571 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
575 * Interrupt should not be disabled twice
577 if (!atmel_port->ms_irq_enabled)
580 atmel_port->ms_irq_enabled = false;
582 mctrl_gpio_disable_ms(atmel_port->gpios);
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
585 idr |= ATMEL_US_CTSIC;
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
588 idr |= ATMEL_US_DSRIC;
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
591 idr |= ATMEL_US_RIIC;
593 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
594 idr |= ATMEL_US_DCDIC;
596 atmel_uart_writel(port, ATMEL_US_IDR, idr);
600 * Control the transmission of a break signal
602 static void atmel_break_ctl(struct uart_port *port, int break_state)
604 if (break_state != 0)
606 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
609 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
613 * Stores the incoming character in the ring buffer
616 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
619 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
620 struct circ_buf *ring = &atmel_port->rx_ring;
621 struct atmel_uart_char *c;
623 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
624 /* Buffer overflow, ignore char */
627 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
631 /* Make sure the character is stored before we update head. */
634 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
638 * Deal with parity, framing and overrun errors.
640 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
643 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
645 if (status & ATMEL_US_RXBRK) {
646 /* ignore side-effect */
647 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
650 if (status & ATMEL_US_PARE)
651 port->icount.parity++;
652 if (status & ATMEL_US_FRAME)
653 port->icount.frame++;
654 if (status & ATMEL_US_OVRE)
655 port->icount.overrun++;
659 * Characters received (called from interrupt handler)
661 static void atmel_rx_chars(struct uart_port *port)
663 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
664 unsigned int status, ch;
666 status = atmel_uart_readl(port, ATMEL_US_CSR);
667 while (status & ATMEL_US_RXRDY) {
668 ch = atmel_uart_read_char(port);
671 * note that the error handling code is
672 * out of the main execution path
674 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
675 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
676 || atmel_port->break_active)) {
679 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
681 if (status & ATMEL_US_RXBRK
682 && !atmel_port->break_active) {
683 atmel_port->break_active = 1;
684 atmel_uart_writel(port, ATMEL_US_IER,
688 * This is either the end-of-break
689 * condition or we've received at
690 * least one character without RXBRK
691 * being set. In both cases, the next
692 * RXBRK will indicate start-of-break.
694 atmel_uart_writel(port, ATMEL_US_IDR,
696 status &= ~ATMEL_US_RXBRK;
697 atmel_port->break_active = 0;
701 atmel_buffer_rx_char(port, status, ch);
702 status = atmel_uart_readl(port, ATMEL_US_CSR);
705 tasklet_schedule(&atmel_port->tasklet);
709 * Transmit characters (called from tasklet with TXRDY interrupt
712 static void atmel_tx_chars(struct uart_port *port)
714 struct circ_buf *xmit = &port->state->xmit;
715 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
718 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
719 atmel_uart_write_char(port, port->x_char);
723 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
726 while (atmel_uart_readl(port, ATMEL_US_CSR) &
727 atmel_port->tx_done_mask) {
728 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
729 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
731 if (uart_circ_empty(xmit))
735 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
736 uart_write_wakeup(port);
738 if (!uart_circ_empty(xmit))
739 /* Enable interrupts */
740 atmel_uart_writel(port, ATMEL_US_IER,
741 atmel_port->tx_done_mask);
744 static void atmel_complete_tx_dma(void *arg)
746 struct atmel_uart_port *atmel_port = arg;
747 struct uart_port *port = &atmel_port->uart;
748 struct circ_buf *xmit = &port->state->xmit;
749 struct dma_chan *chan = atmel_port->chan_tx;
752 spin_lock_irqsave(&port->lock, flags);
755 dmaengine_terminate_all(chan);
756 xmit->tail += atmel_port->tx_len;
757 xmit->tail &= UART_XMIT_SIZE - 1;
759 port->icount.tx += atmel_port->tx_len;
761 spin_lock_irq(&atmel_port->lock_tx);
762 async_tx_ack(atmel_port->desc_tx);
763 atmel_port->cookie_tx = -EINVAL;
764 atmel_port->desc_tx = NULL;
765 spin_unlock_irq(&atmel_port->lock_tx);
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
768 uart_write_wakeup(port);
771 * xmit is a circular buffer so, if we have just send data from
772 * xmit->tail to the end of xmit->buf, now we have to transmit the
773 * remaining data from the beginning of xmit->buf to xmit->head.
775 if (!uart_circ_empty(xmit))
776 tasklet_schedule(&atmel_port->tasklet);
778 spin_unlock_irqrestore(&port->lock, flags);
781 static void atmel_release_tx_dma(struct uart_port *port)
783 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
784 struct dma_chan *chan = atmel_port->chan_tx;
787 dmaengine_terminate_all(chan);
788 dma_release_channel(chan);
789 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
793 atmel_port->desc_tx = NULL;
794 atmel_port->chan_tx = NULL;
795 atmel_port->cookie_tx = -EINVAL;
799 * Called from tasklet with TXRDY interrupt is disabled.
801 static void atmel_tx_dma(struct uart_port *port)
803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
804 struct circ_buf *xmit = &port->state->xmit;
805 struct dma_chan *chan = atmel_port->chan_tx;
806 struct dma_async_tx_descriptor *desc;
807 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
808 unsigned int tx_len, part1_len, part2_len, sg_len;
809 dma_addr_t phys_addr;
811 /* Make sure we have an idle channel */
812 if (atmel_port->desc_tx != NULL)
815 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
818 * Port xmit buffer is already mapped,
819 * and it is one page... Just adjust
820 * offsets and lengths. Since it is a circular buffer,
821 * we have to transmit till the end, and then the rest.
822 * Take the port lock to get a
823 * consistent xmit buffer state.
825 tx_len = CIRC_CNT_TO_END(xmit->head,
829 if (atmel_port->fifo_size) {
830 /* multi data mode */
831 part1_len = (tx_len & ~0x3); /* DWORD access */
832 part2_len = (tx_len & 0x3); /* BYTE access */
834 /* single data (legacy) mode */
836 part2_len = tx_len; /* BYTE access only */
839 sg_init_table(sgl, 2);
841 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
844 sg_dma_address(sg) = phys_addr;
845 sg_dma_len(sg) = part1_len;
847 phys_addr += part1_len;
852 sg_dma_address(sg) = phys_addr;
853 sg_dma_len(sg) = part2_len;
857 * save tx_len so atmel_complete_tx_dma() will increase
858 * xmit->tail correctly
860 atmel_port->tx_len = tx_len;
862 desc = dmaengine_prep_slave_sg(chan,
869 dev_err(port->dev, "Failed to send via dma!\n");
873 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
875 atmel_port->desc_tx = desc;
876 desc->callback = atmel_complete_tx_dma;
877 desc->callback_param = atmel_port;
878 atmel_port->cookie_tx = dmaengine_submit(desc);
881 if (port->rs485.flags & SER_RS485_ENABLED) {
882 /* DMA done, stop TX, start RX for RS485 */
883 atmel_start_rx(port);
887 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
888 uart_write_wakeup(port);
891 static int atmel_prepare_tx_dma(struct uart_port *port)
893 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
895 struct dma_slave_config config;
899 dma_cap_set(DMA_SLAVE, mask);
901 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
902 if (atmel_port->chan_tx == NULL)
904 dev_info(port->dev, "using %s for tx DMA transfers\n",
905 dma_chan_name(atmel_port->chan_tx));
907 spin_lock_init(&atmel_port->lock_tx);
908 sg_init_table(&atmel_port->sg_tx, 1);
909 /* UART circular tx buffer is an aligned page. */
910 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
911 sg_set_page(&atmel_port->sg_tx,
912 virt_to_page(port->state->xmit.buf),
914 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
915 nent = dma_map_sg(port->dev,
921 dev_dbg(port->dev, "need to release resource of dma\n");
924 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
925 sg_dma_len(&atmel_port->sg_tx),
926 port->state->xmit.buf,
927 &sg_dma_address(&atmel_port->sg_tx));
930 /* Configure the slave DMA */
931 memset(&config, 0, sizeof(config));
932 config.direction = DMA_MEM_TO_DEV;
933 config.dst_addr_width = (atmel_port->fifo_size) ?
934 DMA_SLAVE_BUSWIDTH_4_BYTES :
935 DMA_SLAVE_BUSWIDTH_1_BYTE;
936 config.dst_addr = port->mapbase + ATMEL_US_THR;
937 config.dst_maxburst = 1;
939 ret = dmaengine_slave_config(atmel_port->chan_tx,
942 dev_err(port->dev, "DMA tx slave configuration failed\n");
949 dev_err(port->dev, "TX channel not available, switch to pio\n");
950 atmel_port->use_dma_tx = 0;
951 if (atmel_port->chan_tx)
952 atmel_release_tx_dma(port);
956 static void atmel_complete_rx_dma(void *arg)
958 struct uart_port *port = arg;
959 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
961 tasklet_schedule(&atmel_port->tasklet);
964 static void atmel_release_rx_dma(struct uart_port *port)
966 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
967 struct dma_chan *chan = atmel_port->chan_rx;
970 dmaengine_terminate_all(chan);
971 dma_release_channel(chan);
972 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
976 atmel_port->desc_rx = NULL;
977 atmel_port->chan_rx = NULL;
978 atmel_port->cookie_rx = -EINVAL;
981 static void atmel_rx_from_dma(struct uart_port *port)
983 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
984 struct tty_port *tport = &port->state->port;
985 struct circ_buf *ring = &atmel_port->rx_ring;
986 struct dma_chan *chan = atmel_port->chan_rx;
987 struct dma_tx_state state;
988 enum dma_status dmastat;
992 /* Reset the UART timeout early so that we don't miss one */
993 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
994 dmastat = dmaengine_tx_status(chan,
995 atmel_port->cookie_rx,
997 /* Restart a new tasklet if DMA status is error */
998 if (dmastat == DMA_ERROR) {
999 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1000 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1001 tasklet_schedule(&atmel_port->tasklet);
1005 /* CPU claims ownership of RX DMA buffer */
1006 dma_sync_sg_for_cpu(port->dev,
1012 * ring->head points to the end of data already written by the DMA.
1013 * ring->tail points to the beginning of data to be read by the
1015 * The current transfer size should not be larger than the dma buffer
1018 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1019 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1021 * At this point ring->head may point to the first byte right after the
1022 * last byte of the dma buffer:
1023 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1025 * However ring->tail must always points inside the dma buffer:
1026 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1028 * Since we use a ring buffer, we have to handle the case
1029 * where head is lower than tail. In such a case, we first read from
1030 * tail to the end of the buffer then reset tail.
1032 if (ring->head < ring->tail) {
1033 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1035 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1037 port->icount.rx += count;
1040 /* Finally we read data from tail to head */
1041 if (ring->tail < ring->head) {
1042 count = ring->head - ring->tail;
1044 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1045 /* Wrap ring->head if needed */
1046 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1048 ring->tail = ring->head;
1049 port->icount.rx += count;
1052 /* USART retreives ownership of RX DMA buffer */
1053 dma_sync_sg_for_device(port->dev,
1059 * Drop the lock here since it might end up calling
1060 * uart_start(), which takes the lock.
1062 spin_unlock(&port->lock);
1063 tty_flip_buffer_push(tport);
1064 spin_lock(&port->lock);
1066 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1069 static int atmel_prepare_rx_dma(struct uart_port *port)
1071 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1072 struct dma_async_tx_descriptor *desc;
1073 dma_cap_mask_t mask;
1074 struct dma_slave_config config;
1075 struct circ_buf *ring;
1078 ring = &atmel_port->rx_ring;
1081 dma_cap_set(DMA_CYCLIC, mask);
1083 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1084 if (atmel_port->chan_rx == NULL)
1086 dev_info(port->dev, "using %s for rx DMA transfers\n",
1087 dma_chan_name(atmel_port->chan_rx));
1089 spin_lock_init(&atmel_port->lock_rx);
1090 sg_init_table(&atmel_port->sg_rx, 1);
1091 /* UART circular rx buffer is an aligned page. */
1092 BUG_ON(!PAGE_ALIGNED(ring->buf));
1093 sg_set_page(&atmel_port->sg_rx,
1094 virt_to_page(ring->buf),
1095 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1096 (unsigned long)ring->buf & ~PAGE_MASK);
1097 nent = dma_map_sg(port->dev,
1103 dev_dbg(port->dev, "need to release resource of dma\n");
1106 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1107 sg_dma_len(&atmel_port->sg_rx),
1109 &sg_dma_address(&atmel_port->sg_rx));
1112 /* Configure the slave DMA */
1113 memset(&config, 0, sizeof(config));
1114 config.direction = DMA_DEV_TO_MEM;
1115 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1116 config.src_addr = port->mapbase + ATMEL_US_RHR;
1117 config.src_maxburst = 1;
1119 ret = dmaengine_slave_config(atmel_port->chan_rx,
1122 dev_err(port->dev, "DMA rx slave configuration failed\n");
1126 * Prepare a cyclic dma transfer, assign 2 descriptors,
1127 * each one is half ring buffer size
1129 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1130 sg_dma_address(&atmel_port->sg_rx),
1131 sg_dma_len(&atmel_port->sg_rx),
1132 sg_dma_len(&atmel_port->sg_rx)/2,
1134 DMA_PREP_INTERRUPT);
1135 desc->callback = atmel_complete_rx_dma;
1136 desc->callback_param = port;
1137 atmel_port->desc_rx = desc;
1138 atmel_port->cookie_rx = dmaengine_submit(desc);
1143 dev_err(port->dev, "RX channel not available, switch to pio\n");
1144 atmel_port->use_dma_rx = 0;
1145 if (atmel_port->chan_rx)
1146 atmel_release_rx_dma(port);
1150 static void atmel_uart_timer_callback(unsigned long data)
1152 struct uart_port *port = (void *)data;
1153 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1155 tasklet_schedule(&atmel_port->tasklet);
1156 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1160 * receive interrupt handler.
1163 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1165 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1167 if (atmel_use_pdc_rx(port)) {
1169 * PDC receive. Just schedule the tasklet and let it
1170 * figure out the details.
1172 * TODO: We're not handling error flags correctly at
1175 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1176 atmel_uart_writel(port, ATMEL_US_IDR,
1177 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1178 tasklet_schedule(&atmel_port->tasklet);
1181 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1182 ATMEL_US_FRAME | ATMEL_US_PARE))
1183 atmel_pdc_rxerr(port, pending);
1186 if (atmel_use_dma_rx(port)) {
1187 if (pending & ATMEL_US_TIMEOUT) {
1188 atmel_uart_writel(port, ATMEL_US_IDR,
1190 tasklet_schedule(&atmel_port->tasklet);
1194 /* Interrupt receive */
1195 if (pending & ATMEL_US_RXRDY)
1196 atmel_rx_chars(port);
1197 else if (pending & ATMEL_US_RXBRK) {
1199 * End of break detected. If it came along with a
1200 * character, atmel_rx_chars will handle it.
1202 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1203 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1204 atmel_port->break_active = 0;
1209 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1212 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1214 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1216 if (pending & atmel_port->tx_done_mask) {
1217 /* Either PDC or interrupt transmission */
1218 atmel_uart_writel(port, ATMEL_US_IDR,
1219 atmel_port->tx_done_mask);
1220 tasklet_schedule(&atmel_port->tasklet);
1225 * status flags interrupt handler.
1228 atmel_handle_status(struct uart_port *port, unsigned int pending,
1229 unsigned int status)
1231 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1233 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1234 | ATMEL_US_CTSIC)) {
1235 atmel_port->irq_status = status;
1236 atmel_port->status_change = atmel_port->irq_status ^
1237 atmel_port->irq_status_prev;
1238 atmel_port->irq_status_prev = status;
1239 tasklet_schedule(&atmel_port->tasklet);
1246 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1248 struct uart_port *port = dev_id;
1249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1250 unsigned int status, pending, mask, pass_counter = 0;
1252 spin_lock(&atmel_port->lock_suspended);
1255 status = atmel_get_lines_status(port);
1256 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1257 pending = status & mask;
1261 if (atmel_port->suspended) {
1262 atmel_port->pending |= pending;
1263 atmel_port->pending_status = status;
1264 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1269 atmel_handle_receive(port, pending);
1270 atmel_handle_status(port, pending, status);
1271 atmel_handle_transmit(port, pending);
1272 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1274 spin_unlock(&atmel_port->lock_suspended);
1276 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1279 static void atmel_release_tx_pdc(struct uart_port *port)
1281 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1282 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1284 dma_unmap_single(port->dev,
1291 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1293 static void atmel_tx_pdc(struct uart_port *port)
1295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1296 struct circ_buf *xmit = &port->state->xmit;
1297 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1300 /* nothing left to transmit? */
1301 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1304 xmit->tail += pdc->ofs;
1305 xmit->tail &= UART_XMIT_SIZE - 1;
1307 port->icount.tx += pdc->ofs;
1310 /* more to transmit - setup next transfer */
1312 /* disable PDC transmit */
1313 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1315 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1316 dma_sync_single_for_device(port->dev,
1321 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1324 atmel_uart_writel(port, ATMEL_PDC_TPR,
1325 pdc->dma_addr + xmit->tail);
1326 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1327 /* re-enable PDC transmit */
1328 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1329 /* Enable interrupts */
1330 atmel_uart_writel(port, ATMEL_US_IER,
1331 atmel_port->tx_done_mask);
1333 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1334 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1335 /* DMA done, stop TX, start RX for RS485 */
1336 atmel_start_rx(port);
1340 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1341 uart_write_wakeup(port);
1344 static int atmel_prepare_tx_pdc(struct uart_port *port)
1346 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1347 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1348 struct circ_buf *xmit = &port->state->xmit;
1350 pdc->buf = xmit->buf;
1351 pdc->dma_addr = dma_map_single(port->dev,
1355 pdc->dma_size = UART_XMIT_SIZE;
1361 static void atmel_rx_from_ring(struct uart_port *port)
1363 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1364 struct circ_buf *ring = &atmel_port->rx_ring;
1366 unsigned int status;
1368 while (ring->head != ring->tail) {
1369 struct atmel_uart_char c;
1371 /* Make sure c is loaded after head. */
1374 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1376 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1383 * note that the error handling code is
1384 * out of the main execution path
1386 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1387 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1388 if (status & ATMEL_US_RXBRK) {
1389 /* ignore side-effect */
1390 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1393 if (uart_handle_break(port))
1396 if (status & ATMEL_US_PARE)
1397 port->icount.parity++;
1398 if (status & ATMEL_US_FRAME)
1399 port->icount.frame++;
1400 if (status & ATMEL_US_OVRE)
1401 port->icount.overrun++;
1403 status &= port->read_status_mask;
1405 if (status & ATMEL_US_RXBRK)
1407 else if (status & ATMEL_US_PARE)
1409 else if (status & ATMEL_US_FRAME)
1414 if (uart_handle_sysrq_char(port, c.ch))
1417 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1421 * Drop the lock here since it might end up calling
1422 * uart_start(), which takes the lock.
1424 spin_unlock(&port->lock);
1425 tty_flip_buffer_push(&port->state->port);
1426 spin_lock(&port->lock);
1429 static void atmel_release_rx_pdc(struct uart_port *port)
1431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1434 for (i = 0; i < 2; i++) {
1435 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1437 dma_unmap_single(port->dev,
1445 static void atmel_rx_from_pdc(struct uart_port *port)
1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1448 struct tty_port *tport = &port->state->port;
1449 struct atmel_dma_buffer *pdc;
1450 int rx_idx = atmel_port->pdc_rx_idx;
1456 /* Reset the UART timeout early so that we don't miss one */
1457 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1459 pdc = &atmel_port->pdc_rx[rx_idx];
1460 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1463 /* If the PDC has switched buffers, RPR won't contain
1464 * any address within the current buffer. Since head
1465 * is unsigned, we just need a one-way comparison to
1468 * In this case, we just need to consume the entire
1469 * buffer and resubmit it for DMA. This will clear the
1470 * ENDRX bit as well, so that we can safely re-enable
1471 * all interrupts below.
1473 head = min(head, pdc->dma_size);
1475 if (likely(head != tail)) {
1476 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1477 pdc->dma_size, DMA_FROM_DEVICE);
1480 * head will only wrap around when we recycle
1481 * the DMA buffer, and when that happens, we
1482 * explicitly set tail to 0. So head will
1483 * always be greater than tail.
1485 count = head - tail;
1487 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1490 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1491 pdc->dma_size, DMA_FROM_DEVICE);
1493 port->icount.rx += count;
1498 * If the current buffer is full, we need to check if
1499 * the next one contains any additional data.
1501 if (head >= pdc->dma_size) {
1503 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1504 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1507 atmel_port->pdc_rx_idx = rx_idx;
1509 } while (head >= pdc->dma_size);
1512 * Drop the lock here since it might end up calling
1513 * uart_start(), which takes the lock.
1515 spin_unlock(&port->lock);
1516 tty_flip_buffer_push(tport);
1517 spin_lock(&port->lock);
1519 atmel_uart_writel(port, ATMEL_US_IER,
1520 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1523 static int atmel_prepare_rx_pdc(struct uart_port *port)
1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1528 for (i = 0; i < 2; i++) {
1529 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1531 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1532 if (pdc->buf == NULL) {
1534 dma_unmap_single(port->dev,
1535 atmel_port->pdc_rx[0].dma_addr,
1538 kfree(atmel_port->pdc_rx[0].buf);
1540 atmel_port->use_pdc_rx = 0;
1543 pdc->dma_addr = dma_map_single(port->dev,
1547 pdc->dma_size = PDC_BUFFER_SIZE;
1551 atmel_port->pdc_rx_idx = 0;
1553 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1554 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1556 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1557 atmel_port->pdc_rx[1].dma_addr);
1558 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1564 * tasklet handling tty stuff outside the interrupt handler.
1566 static void atmel_tasklet_func(unsigned long data)
1568 struct uart_port *port = (struct uart_port *)data;
1569 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1570 unsigned int status = atmel_port->irq_status;
1571 unsigned int status_change = atmel_port->status_change;
1573 /* The interrupt handler does not take the lock */
1574 spin_lock(&port->lock);
1576 atmel_port->schedule_tx(port);
1578 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1579 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1580 /* TODO: All reads to CSR will clear these interrupts! */
1581 if (status_change & ATMEL_US_RI)
1583 if (status_change & ATMEL_US_DSR)
1585 if (status_change & ATMEL_US_DCD)
1586 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1587 if (status_change & ATMEL_US_CTS)
1588 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1590 wake_up_interruptible(&port->state->port.delta_msr_wait);
1592 atmel_port->status_change = 0;
1595 atmel_port->schedule_rx(port);
1597 spin_unlock(&port->lock);
1600 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1601 struct platform_device *pdev)
1603 struct device_node *np = pdev->dev.of_node;
1604 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1607 /* DMA/PDC usage specification */
1608 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1609 if (of_get_property(np, "dmas", NULL)) {
1610 atmel_port->use_dma_rx = true;
1611 atmel_port->use_pdc_rx = false;
1613 atmel_port->use_dma_rx = false;
1614 atmel_port->use_pdc_rx = true;
1617 atmel_port->use_dma_rx = false;
1618 atmel_port->use_pdc_rx = false;
1621 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1622 if (of_get_property(np, "dmas", NULL)) {
1623 atmel_port->use_dma_tx = true;
1624 atmel_port->use_pdc_tx = false;
1626 atmel_port->use_dma_tx = false;
1627 atmel_port->use_pdc_tx = true;
1630 atmel_port->use_dma_tx = false;
1631 atmel_port->use_pdc_tx = false;
1635 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1636 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1637 atmel_port->use_dma_rx = false;
1638 atmel_port->use_dma_tx = false;
1643 static void atmel_init_rs485(struct uart_port *port,
1644 struct platform_device *pdev)
1646 struct device_node *np = pdev->dev.of_node;
1647 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1650 struct serial_rs485 *rs485conf = &port->rs485;
1652 /* rs485 properties */
1653 if (of_property_read_u32_array(np, "rs485-rts-delay",
1654 rs485_delay, 2) == 0) {
1655 rs485conf->delay_rts_before_send = rs485_delay[0];
1656 rs485conf->delay_rts_after_send = rs485_delay[1];
1657 rs485conf->flags = 0;
1660 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1661 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1663 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1665 rs485conf->flags |= SER_RS485_ENABLED;
1667 port->rs485 = pdata->rs485;
1672 static void atmel_set_ops(struct uart_port *port)
1674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1676 if (atmel_use_dma_rx(port)) {
1677 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1678 atmel_port->schedule_rx = &atmel_rx_from_dma;
1679 atmel_port->release_rx = &atmel_release_rx_dma;
1680 } else if (atmel_use_pdc_rx(port)) {
1681 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1682 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1683 atmel_port->release_rx = &atmel_release_rx_pdc;
1685 atmel_port->prepare_rx = NULL;
1686 atmel_port->schedule_rx = &atmel_rx_from_ring;
1687 atmel_port->release_rx = NULL;
1690 if (atmel_use_dma_tx(port)) {
1691 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1692 atmel_port->schedule_tx = &atmel_tx_dma;
1693 atmel_port->release_tx = &atmel_release_tx_dma;
1694 } else if (atmel_use_pdc_tx(port)) {
1695 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1696 atmel_port->schedule_tx = &atmel_tx_pdc;
1697 atmel_port->release_tx = &atmel_release_tx_pdc;
1699 atmel_port->prepare_tx = NULL;
1700 atmel_port->schedule_tx = &atmel_tx_chars;
1701 atmel_port->release_tx = NULL;
1706 * Get ip name usart or uart
1708 static void atmel_get_ip_name(struct uart_port *port)
1710 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1711 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1713 u32 usart, dbgu_uart, new_uart;
1714 /* ASCII decoding for IP version */
1715 usart = 0x55534152; /* USAR(T) */
1716 dbgu_uart = 0x44424755; /* DBGU */
1717 new_uart = 0x55415254; /* UART */
1719 atmel_port->has_hw_timer = false;
1721 if (name == usart || name == new_uart) {
1722 dev_dbg(port->dev, "Usart or uart with hw timer\n");
1723 atmel_port->has_hw_timer = true;
1724 } else if (name == dbgu_uart) {
1725 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1726 atmel_port->has_hw_timer = false;
1728 /* fallback for older SoCs: use version field */
1729 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1733 dev_dbg(port->dev, "This version is usart\n");
1734 atmel_port->has_hw_timer = true;
1738 dev_dbg(port->dev, "This version is uart\n");
1739 atmel_port->has_hw_timer = false;
1742 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1748 * Perform initialization and enable port for reception
1750 static int atmel_startup(struct uart_port *port)
1752 struct platform_device *pdev = to_platform_device(port->dev);
1753 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1754 struct tty_struct *tty = port->state->port.tty;
1758 * Ensure that no interrupts are enabled otherwise when
1759 * request_irq() is called we could get stuck trying to
1760 * handle an unexpected interrupt
1762 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1763 atmel_port->ms_irq_enabled = false;
1768 retval = request_irq(port->irq, atmel_interrupt,
1769 IRQF_SHARED | IRQF_COND_SUSPEND,
1770 tty ? tty->name : "atmel_serial", port);
1772 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1776 tasklet_enable(&atmel_port->tasklet);
1779 * Initialize DMA (if necessary)
1781 atmel_init_property(atmel_port, pdev);
1782 atmel_set_ops(port);
1784 if (atmel_port->prepare_rx) {
1785 retval = atmel_port->prepare_rx(port);
1787 atmel_set_ops(port);
1790 if (atmel_port->prepare_tx) {
1791 retval = atmel_port->prepare_tx(port);
1793 atmel_set_ops(port);
1797 * Enable FIFO when available
1799 if (atmel_port->fifo_size) {
1800 unsigned int txrdym = ATMEL_US_ONE_DATA;
1801 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1804 atmel_uart_writel(port, ATMEL_US_CR,
1809 if (atmel_use_dma_tx(port))
1810 txrdym = ATMEL_US_FOUR_DATA;
1812 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1813 if (atmel_port->rts_high &&
1814 atmel_port->rts_low)
1815 fmr |= ATMEL_US_FRTSC |
1816 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1817 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1819 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1822 /* Save current CSR for comparison in atmel_tasklet_func() */
1823 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1824 atmel_port->irq_status = atmel_port->irq_status_prev;
1827 * Finally, enable the serial port
1829 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1830 /* enable xmit & rcvr */
1831 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1833 setup_timer(&atmel_port->uart_timer,
1834 atmel_uart_timer_callback,
1835 (unsigned long)port);
1837 if (atmel_use_pdc_rx(port)) {
1838 /* set UART timeout */
1839 if (!atmel_port->has_hw_timer) {
1840 mod_timer(&atmel_port->uart_timer,
1841 jiffies + uart_poll_timeout(port));
1842 /* set USART timeout */
1844 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1845 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1847 atmel_uart_writel(port, ATMEL_US_IER,
1848 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1850 /* enable PDC controller */
1851 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1852 } else if (atmel_use_dma_rx(port)) {
1853 /* set UART timeout */
1854 if (!atmel_port->has_hw_timer) {
1855 mod_timer(&atmel_port->uart_timer,
1856 jiffies + uart_poll_timeout(port));
1857 /* set USART timeout */
1859 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1860 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1862 atmel_uart_writel(port, ATMEL_US_IER,
1866 /* enable receive only */
1867 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1874 * Flush any TX data submitted for DMA. Called when the TX circular
1877 static void atmel_flush_buffer(struct uart_port *port)
1879 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1881 if (atmel_use_pdc_tx(port)) {
1882 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1883 atmel_port->pdc_tx.ofs = 0;
1890 static void atmel_shutdown(struct uart_port *port)
1892 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1895 * Prevent any tasklets being scheduled during
1898 del_timer_sync(&atmel_port->uart_timer);
1901 * Clear out any scheduled tasklets before
1902 * we destroy the buffers
1904 tasklet_disable(&atmel_port->tasklet);
1905 tasklet_kill(&atmel_port->tasklet);
1908 * Ensure everything is stopped and
1909 * disable all interrupts, port and break condition.
1911 atmel_stop_rx(port);
1912 atmel_stop_tx(port);
1914 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1915 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1919 * Shut-down the DMA.
1921 if (atmel_port->release_rx)
1922 atmel_port->release_rx(port);
1923 if (atmel_port->release_tx)
1924 atmel_port->release_tx(port);
1927 * Reset ring buffer pointers
1929 atmel_port->rx_ring.head = 0;
1930 atmel_port->rx_ring.tail = 0;
1933 * Free the interrupts
1935 free_irq(port->irq, port);
1937 atmel_port->ms_irq_enabled = false;
1939 atmel_flush_buffer(port);
1943 * Power / Clock management.
1945 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1946 unsigned int oldstate)
1948 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1953 * Enable the peripheral clock for this serial port.
1954 * This is called on uart_open() or a resume event.
1956 clk_prepare_enable(atmel_port->clk);
1958 /* re-enable interrupts if we disabled some on suspend */
1959 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
1962 /* Back up the interrupt mask and disable all interrupts */
1963 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
1964 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1967 * Disable the peripheral clock for this serial port.
1968 * This is called on uart_close() or a suspend event.
1970 clk_disable_unprepare(atmel_port->clk);
1973 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1978 * Change the port parameters
1980 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1981 struct ktermios *old)
1983 unsigned long flags;
1984 unsigned int old_mode, mode, imr, quot, baud;
1986 /* save the current mode register */
1987 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1989 /* reset the mode, clock divisor, parity, stop bits and data size */
1990 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
1991 ATMEL_US_PAR | ATMEL_US_USMODE);
1993 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1994 quot = uart_get_divisor(port, baud);
1996 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1998 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2002 switch (termios->c_cflag & CSIZE) {
2004 mode |= ATMEL_US_CHRL_5;
2007 mode |= ATMEL_US_CHRL_6;
2010 mode |= ATMEL_US_CHRL_7;
2013 mode |= ATMEL_US_CHRL_8;
2018 if (termios->c_cflag & CSTOPB)
2019 mode |= ATMEL_US_NBSTOP_2;
2022 if (termios->c_cflag & PARENB) {
2023 /* Mark or Space parity */
2024 if (termios->c_cflag & CMSPAR) {
2025 if (termios->c_cflag & PARODD)
2026 mode |= ATMEL_US_PAR_MARK;
2028 mode |= ATMEL_US_PAR_SPACE;
2029 } else if (termios->c_cflag & PARODD)
2030 mode |= ATMEL_US_PAR_ODD;
2032 mode |= ATMEL_US_PAR_EVEN;
2034 mode |= ATMEL_US_PAR_NONE;
2036 spin_lock_irqsave(&port->lock, flags);
2038 port->read_status_mask = ATMEL_US_OVRE;
2039 if (termios->c_iflag & INPCK)
2040 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2041 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2042 port->read_status_mask |= ATMEL_US_RXBRK;
2044 if (atmel_use_pdc_rx(port))
2045 /* need to enable error interrupts */
2046 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2049 * Characters to ignore
2051 port->ignore_status_mask = 0;
2052 if (termios->c_iflag & IGNPAR)
2053 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2054 if (termios->c_iflag & IGNBRK) {
2055 port->ignore_status_mask |= ATMEL_US_RXBRK;
2057 * If we're ignoring parity and break indicators,
2058 * ignore overruns too (for real raw support).
2060 if (termios->c_iflag & IGNPAR)
2061 port->ignore_status_mask |= ATMEL_US_OVRE;
2063 /* TODO: Ignore all characters if CREAD is set.*/
2065 /* update the per-port timeout */
2066 uart_update_timeout(port, termios->c_cflag, baud);
2069 * save/disable interrupts. The tty layer will ensure that the
2070 * transmitter is empty if requested by the caller, so there's
2071 * no need to wait for it here.
2073 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2074 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2076 /* disable receiver and transmitter */
2077 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2080 if (port->rs485.flags & SER_RS485_ENABLED) {
2081 atmel_uart_writel(port, ATMEL_US_TTGR,
2082 port->rs485.delay_rts_after_send);
2083 mode |= ATMEL_US_USMODE_RS485;
2084 } else if (termios->c_cflag & CRTSCTS) {
2085 /* RS232 with hardware handshake (RTS/CTS) */
2086 mode |= ATMEL_US_USMODE_HWHS;
2088 /* RS232 without hadware handshake */
2089 mode |= ATMEL_US_USMODE_NORMAL;
2092 /* set the mode, clock divisor, parity, stop bits and data size */
2093 atmel_uart_writel(port, ATMEL_US_MR, mode);
2096 * when switching the mode, set the RTS line state according to the
2097 * new mode, otherwise keep the former state
2099 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2100 unsigned int rts_state;
2102 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2103 /* let the hardware control the RTS line */
2104 rts_state = ATMEL_US_RTSDIS;
2106 /* force RTS line to low level */
2107 rts_state = ATMEL_US_RTSEN;
2110 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2113 /* set the baud rate */
2114 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2115 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2116 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2118 /* restore interrupts */
2119 atmel_uart_writel(port, ATMEL_US_IER, imr);
2121 /* CTS flow-control and modem-status interrupts */
2122 if (UART_ENABLE_MS(port, termios->c_cflag))
2123 atmel_enable_ms(port);
2125 atmel_disable_ms(port);
2127 spin_unlock_irqrestore(&port->lock, flags);
2130 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2132 if (termios->c_line == N_PPS) {
2133 port->flags |= UPF_HARDPPS_CD;
2134 spin_lock_irq(&port->lock);
2135 atmel_enable_ms(port);
2136 spin_unlock_irq(&port->lock);
2138 port->flags &= ~UPF_HARDPPS_CD;
2139 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2140 spin_lock_irq(&port->lock);
2141 atmel_disable_ms(port);
2142 spin_unlock_irq(&port->lock);
2148 * Return string describing the specified port
2150 static const char *atmel_type(struct uart_port *port)
2152 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2156 * Release the memory region(s) being used by 'port'.
2158 static void atmel_release_port(struct uart_port *port)
2160 struct platform_device *pdev = to_platform_device(port->dev);
2161 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2163 release_mem_region(port->mapbase, size);
2165 if (port->flags & UPF_IOREMAP) {
2166 iounmap(port->membase);
2167 port->membase = NULL;
2172 * Request the memory region(s) being used by 'port'.
2174 static int atmel_request_port(struct uart_port *port)
2176 struct platform_device *pdev = to_platform_device(port->dev);
2177 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2179 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2182 if (port->flags & UPF_IOREMAP) {
2183 port->membase = ioremap(port->mapbase, size);
2184 if (port->membase == NULL) {
2185 release_mem_region(port->mapbase, size);
2194 * Configure/autoconfigure the port.
2196 static void atmel_config_port(struct uart_port *port, int flags)
2198 if (flags & UART_CONFIG_TYPE) {
2199 port->type = PORT_ATMEL;
2200 atmel_request_port(port);
2205 * Verify the new serial_struct (for TIOCSSERIAL).
2207 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2210 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2212 if (port->irq != ser->irq)
2214 if (ser->io_type != SERIAL_IO_MEM)
2216 if (port->uartclk / 16 != ser->baud_base)
2218 if (port->mapbase != (unsigned long)ser->iomem_base)
2220 if (port->iobase != ser->port)
2227 #ifdef CONFIG_CONSOLE_POLL
2228 static int atmel_poll_get_char(struct uart_port *port)
2230 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2233 return atmel_uart_read_char(port);
2236 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2238 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2241 atmel_uart_write_char(port, ch);
2245 static struct uart_ops atmel_pops = {
2246 .tx_empty = atmel_tx_empty,
2247 .set_mctrl = atmel_set_mctrl,
2248 .get_mctrl = atmel_get_mctrl,
2249 .stop_tx = atmel_stop_tx,
2250 .start_tx = atmel_start_tx,
2251 .stop_rx = atmel_stop_rx,
2252 .enable_ms = atmel_enable_ms,
2253 .break_ctl = atmel_break_ctl,
2254 .startup = atmel_startup,
2255 .shutdown = atmel_shutdown,
2256 .flush_buffer = atmel_flush_buffer,
2257 .set_termios = atmel_set_termios,
2258 .set_ldisc = atmel_set_ldisc,
2260 .release_port = atmel_release_port,
2261 .request_port = atmel_request_port,
2262 .config_port = atmel_config_port,
2263 .verify_port = atmel_verify_port,
2264 .pm = atmel_serial_pm,
2265 #ifdef CONFIG_CONSOLE_POLL
2266 .poll_get_char = atmel_poll_get_char,
2267 .poll_put_char = atmel_poll_put_char,
2272 * Configure the port from the platform device resource info.
2274 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2275 struct platform_device *pdev)
2278 struct uart_port *port = &atmel_port->uart;
2279 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2281 atmel_init_property(atmel_port, pdev);
2282 atmel_set_ops(port);
2284 atmel_init_rs485(port, pdev);
2286 port->iotype = UPIO_MEM;
2287 port->flags = UPF_BOOT_AUTOCONF;
2288 port->ops = &atmel_pops;
2290 port->dev = &pdev->dev;
2291 port->mapbase = pdev->resource[0].start;
2292 port->irq = pdev->resource[1].start;
2293 port->rs485_config = atmel_config_rs485;
2295 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2296 (unsigned long)port);
2297 tasklet_disable(&atmel_port->tasklet);
2299 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2301 if (pdata && pdata->regs) {
2302 /* Already mapped by setup code */
2303 port->membase = pdata->regs;
2305 port->flags |= UPF_IOREMAP;
2306 port->membase = NULL;
2309 /* for console, the clock could already be configured */
2310 if (!atmel_port->clk) {
2311 atmel_port->clk = clk_get(&pdev->dev, "usart");
2312 if (IS_ERR(atmel_port->clk)) {
2313 ret = PTR_ERR(atmel_port->clk);
2314 atmel_port->clk = NULL;
2317 ret = clk_prepare_enable(atmel_port->clk);
2319 clk_put(atmel_port->clk);
2320 atmel_port->clk = NULL;
2323 port->uartclk = clk_get_rate(atmel_port->clk);
2324 clk_disable_unprepare(atmel_port->clk);
2325 /* only enable clock when USART is in use */
2328 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2329 if (port->rs485.flags & SER_RS485_ENABLED)
2330 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2331 else if (atmel_use_pdc_tx(port)) {
2332 port->fifosize = PDC_BUFFER_SIZE;
2333 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2335 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2341 struct platform_device *atmel_default_console_device; /* the serial console device */
2343 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2344 static void atmel_console_putchar(struct uart_port *port, int ch)
2346 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2348 atmel_uart_write_char(port, ch);
2352 * Interrupts are disabled on entering
2354 static void atmel_console_write(struct console *co, const char *s, u_int count)
2356 struct uart_port *port = &atmel_ports[co->index].uart;
2357 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2358 unsigned int status, imr;
2359 unsigned int pdc_tx;
2362 * First, save IMR and then disable interrupts
2364 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2365 atmel_uart_writel(port, ATMEL_US_IDR,
2366 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2368 /* Store PDC transmit status and disable it */
2369 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2370 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2372 uart_console_write(port, s, count, atmel_console_putchar);
2375 * Finally, wait for transmitter to become empty
2379 status = atmel_uart_readl(port, ATMEL_US_CSR);
2380 } while (!(status & ATMEL_US_TXRDY));
2382 /* Restore PDC transmit status */
2384 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2386 /* set interrupts back the way they were */
2387 atmel_uart_writel(port, ATMEL_US_IER, imr);
2391 * If the port was already initialised (eg, by a boot loader),
2392 * try to determine the current setup.
2394 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2395 int *parity, int *bits)
2397 unsigned int mr, quot;
2400 * If the baud rate generator isn't running, the port wasn't
2401 * initialized by the boot loader.
2403 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2407 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2408 if (mr == ATMEL_US_CHRL_8)
2413 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2414 if (mr == ATMEL_US_PAR_EVEN)
2416 else if (mr == ATMEL_US_PAR_ODD)
2420 * The serial core only rounds down when matching this to a
2421 * supported baud rate. Make sure we don't end up slightly
2422 * lower than one of those, as it would make us fall through
2423 * to a much lower baud rate than we really want.
2425 *baud = port->uartclk / (16 * (quot - 1));
2428 static int __init atmel_console_setup(struct console *co, char *options)
2431 struct uart_port *port = &atmel_ports[co->index].uart;
2437 if (port->membase == NULL) {
2438 /* Port not initialized yet - delay setup */
2442 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2446 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2447 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2448 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2451 uart_parse_options(options, &baud, &parity, &bits, &flow);
2453 atmel_console_get_options(port, &baud, &parity, &bits);
2455 return uart_set_options(port, co, baud, parity, bits, flow);
2458 static struct uart_driver atmel_uart;
2460 static struct console atmel_console = {
2461 .name = ATMEL_DEVICENAME,
2462 .write = atmel_console_write,
2463 .device = uart_console_device,
2464 .setup = atmel_console_setup,
2465 .flags = CON_PRINTBUFFER,
2467 .data = &atmel_uart,
2470 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2473 * Early console initialization (before VM subsystem initialized).
2475 static int __init atmel_console_init(void)
2478 if (atmel_default_console_device) {
2479 struct atmel_uart_data *pdata =
2480 dev_get_platdata(&atmel_default_console_device->dev);
2481 int id = pdata->num;
2482 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2484 atmel_port->backup_imr = 0;
2485 atmel_port->uart.line = id;
2487 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2488 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2491 register_console(&atmel_console);
2497 console_initcall(atmel_console_init);
2500 * Late console initialization.
2502 static int __init atmel_late_console_init(void)
2504 if (atmel_default_console_device
2505 && !(atmel_console.flags & CON_ENABLED))
2506 register_console(&atmel_console);
2511 core_initcall(atmel_late_console_init);
2513 static inline bool atmel_is_console_port(struct uart_port *port)
2515 return port->cons && port->cons->index == port->line;
2519 #define ATMEL_CONSOLE_DEVICE NULL
2521 static inline bool atmel_is_console_port(struct uart_port *port)
2527 static struct uart_driver atmel_uart = {
2528 .owner = THIS_MODULE,
2529 .driver_name = "atmel_serial",
2530 .dev_name = ATMEL_DEVICENAME,
2531 .major = SERIAL_ATMEL_MAJOR,
2532 .minor = MINOR_START,
2533 .nr = ATMEL_MAX_UART,
2534 .cons = ATMEL_CONSOLE_DEVICE,
2538 static bool atmel_serial_clk_will_stop(void)
2540 #ifdef CONFIG_ARCH_AT91
2541 return at91_suspend_entering_slow_clock();
2547 static int atmel_serial_suspend(struct platform_device *pdev,
2550 struct uart_port *port = platform_get_drvdata(pdev);
2551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2553 if (atmel_is_console_port(port) && console_suspend_enabled) {
2554 /* Drain the TX shifter */
2555 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2560 /* we can not wake up if we're running on slow clock */
2561 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2562 if (atmel_serial_clk_will_stop()) {
2563 unsigned long flags;
2565 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2566 atmel_port->suspended = true;
2567 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2568 device_set_wakeup_enable(&pdev->dev, 0);
2571 uart_suspend_port(&atmel_uart, port);
2576 static int atmel_serial_resume(struct platform_device *pdev)
2578 struct uart_port *port = platform_get_drvdata(pdev);
2579 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2580 unsigned long flags;
2582 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2583 if (atmel_port->pending) {
2584 atmel_handle_receive(port, atmel_port->pending);
2585 atmel_handle_status(port, atmel_port->pending,
2586 atmel_port->pending_status);
2587 atmel_handle_transmit(port, atmel_port->pending);
2588 atmel_port->pending = 0;
2590 atmel_port->suspended = false;
2591 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2593 uart_resume_port(&atmel_uart, port);
2594 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2599 #define atmel_serial_suspend NULL
2600 #define atmel_serial_resume NULL
2603 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2604 struct platform_device *pdev)
2606 atmel_port->fifo_size = 0;
2607 atmel_port->rts_low = 0;
2608 atmel_port->rts_high = 0;
2610 if (of_property_read_u32(pdev->dev.of_node,
2612 &atmel_port->fifo_size))
2615 if (!atmel_port->fifo_size)
2618 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2619 atmel_port->fifo_size = 0;
2620 dev_err(&pdev->dev, "Invalid FIFO size\n");
2625 * 0 <= rts_low <= rts_high <= fifo_size
2626 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2627 * to flush their internal TX FIFO, commonly up to 16 data, before
2628 * actually stopping to send new data. So we try to set the RTS High
2629 * Threshold to a reasonably high value respecting this 16 data
2630 * empirical rule when possible.
2632 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2633 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2634 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2635 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2637 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2638 atmel_port->fifo_size);
2639 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2640 atmel_port->rts_high);
2641 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2642 atmel_port->rts_low);
2645 static int atmel_serial_probe(struct platform_device *pdev)
2647 struct atmel_uart_port *atmel_port;
2648 struct device_node *np = pdev->dev.of_node;
2649 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2654 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2657 ret = of_alias_get_id(np, "serial");
2663 /* port id not found in platform data nor device-tree aliases:
2664 * auto-enumerate it */
2665 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2667 if (ret >= ATMEL_MAX_UART) {
2672 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2673 /* port already in use */
2678 atmel_port = &atmel_ports[ret];
2679 atmel_port->backup_imr = 0;
2680 atmel_port->uart.line = ret;
2681 atmel_serial_probe_fifos(atmel_port, pdev);
2683 spin_lock_init(&atmel_port->lock_suspended);
2685 ret = atmel_init_port(atmel_port, pdev);
2689 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2690 if (IS_ERR(atmel_port->gpios)) {
2691 ret = PTR_ERR(atmel_port->gpios);
2695 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2697 data = kmalloc(sizeof(struct atmel_uart_char)
2698 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2700 goto err_alloc_ring;
2701 atmel_port->rx_ring.buf = data;
2704 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2706 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2710 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2711 if (atmel_is_console_port(&atmel_port->uart)
2712 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2714 * The serial core enabled the clock for us, so undo
2715 * the clk_prepare_enable() in atmel_console_setup()
2717 clk_disable_unprepare(atmel_port->clk);
2721 device_init_wakeup(&pdev->dev, 1);
2722 platform_set_drvdata(pdev, atmel_port);
2725 * The peripheral clock has been disabled by atmel_init_port():
2726 * enable it before accessing I/O registers
2728 clk_prepare_enable(atmel_port->clk);
2730 if (rs485_enabled) {
2731 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2732 ATMEL_US_USMODE_NORMAL);
2733 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2738 * Get port name of usart or uart
2740 atmel_get_ip_name(&atmel_port->uart);
2743 * The peripheral clock can now safely be disabled till the port
2746 clk_disable_unprepare(atmel_port->clk);
2751 kfree(atmel_port->rx_ring.buf);
2752 atmel_port->rx_ring.buf = NULL;
2754 if (!atmel_is_console_port(&atmel_port->uart)) {
2755 clk_put(atmel_port->clk);
2756 atmel_port->clk = NULL;
2759 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2764 static struct platform_driver atmel_serial_driver = {
2765 .probe = atmel_serial_probe,
2766 .suspend = atmel_serial_suspend,
2767 .resume = atmel_serial_resume,
2769 .name = "atmel_usart",
2770 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2771 .suppress_bind_attrs = true,
2775 static int __init atmel_serial_init(void)
2779 ret = uart_register_driver(&atmel_uart);
2783 ret = platform_driver_register(&atmel_serial_driver);
2785 uart_unregister_driver(&atmel_uart);
2789 device_initcall(atmel_serial_init);