2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/uaccess.h>
42 #include <linux/platform_data/atmel.h>
43 #include <linux/timer.h>
44 #include <linux/gpio.h>
45 #include <linux/gpio/consumer.h>
46 #include <linux/err.h>
47 #include <linux/irq.h>
48 #include <linux/suspend.h>
51 #include <asm/ioctls.h>
53 #define PDC_BUFFER_SIZE 512
54 /* Revisit: We should calculate this based on the actual port settings */
55 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57 /* The minium number of data FIFOs should be able to contain */
58 #define ATMEL_MIN_FIFO_SIZE 8
60 * These two offsets are substracted from the RX FIFO size to define the RTS
61 * high and low thresholds
63 #define ATMEL_RTS_HIGH_OFFSET 16
64 #define ATMEL_RTS_LOW_OFFSET 20
66 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
70 #include <linux/serial_core.h>
72 #include "serial_mctrl_gpio.h"
73 #include "atmel_serial.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
117 #define ATMEL_SERIAL_RINGSIZE 1024
120 * at91: 6 USARTs and one DBGU port (SAM9260)
122 * samx7: 3 USARTs and 5 UARTs
124 #define ATMEL_MAX_UART 8
127 * We wrap our port structure around the generic uart_port.
129 struct atmel_uart_port {
130 struct uart_port uart; /* uart */
131 struct clk *clk; /* uart clock */
132 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
133 u32 backup_imr; /* IMR saved during suspend */
134 int break_active; /* break being received */
136 bool use_dma_rx; /* enable DMA receiver */
137 bool use_pdc_rx; /* enable PDC receiver */
138 short pdc_rx_idx; /* current PDC RX buffer */
139 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
141 bool use_dma_tx; /* enable DMA transmitter */
142 bool use_pdc_tx; /* enable PDC transmitter */
143 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
145 spinlock_t lock_tx; /* port lock */
146 spinlock_t lock_rx; /* port lock */
147 struct dma_chan *chan_tx;
148 struct dma_chan *chan_rx;
149 struct dma_async_tx_descriptor *desc_tx;
150 struct dma_async_tx_descriptor *desc_rx;
151 dma_cookie_t cookie_tx;
152 dma_cookie_t cookie_rx;
153 struct scatterlist sg_tx;
154 struct scatterlist sg_rx;
155 struct tasklet_struct tasklet_rx;
156 struct tasklet_struct tasklet_tx;
157 atomic_t tasklet_shutdown;
158 unsigned int irq_status_prev;
161 struct circ_buf rx_ring;
163 struct mctrl_gpios *gpios;
164 unsigned int tx_done_mask;
169 u32 rtor; /* address of receiver timeout register if it exists */
170 bool has_frac_baudrate;
172 struct timer_list uart_timer;
175 unsigned int pending;
176 unsigned int pending_status;
177 spinlock_t lock_suspended;
192 int (*prepare_rx)(struct uart_port *port);
193 int (*prepare_tx)(struct uart_port *port);
194 void (*schedule_rx)(struct uart_port *port);
195 void (*schedule_tx)(struct uart_port *port);
196 void (*release_rx)(struct uart_port *port);
197 void (*release_tx)(struct uart_port *port);
200 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
201 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
204 static struct console atmel_console;
207 #if defined(CONFIG_OF)
208 static const struct of_device_id atmel_serial_dt_ids[] = {
209 { .compatible = "atmel,at91rm9200-usart" },
210 { .compatible = "atmel,at91sam9260-usart" },
215 static inline struct atmel_uart_port *
216 to_atmel_uart_port(struct uart_port *uart)
218 return container_of(uart, struct atmel_uart_port, uart);
221 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
223 return __raw_readl(port->membase + reg);
226 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
228 __raw_writel(value, port->membase + reg);
233 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
234 static inline u8 atmel_uart_read_char(struct uart_port *port)
236 return __raw_readl(port->membase + ATMEL_US_RHR);
239 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
241 __raw_writel(value, port->membase + ATMEL_US_THR);
246 static inline u8 atmel_uart_read_char(struct uart_port *port)
248 return __raw_readb(port->membase + ATMEL_US_RHR);
251 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
253 __raw_writeb(value, port->membase + ATMEL_US_THR);
258 #ifdef CONFIG_SERIAL_ATMEL_PDC
259 static bool atmel_use_pdc_rx(struct uart_port *port)
261 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
263 return atmel_port->use_pdc_rx;
266 static bool atmel_use_pdc_tx(struct uart_port *port)
268 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
270 return atmel_port->use_pdc_tx;
273 static bool atmel_use_pdc_rx(struct uart_port *port)
278 static bool atmel_use_pdc_tx(struct uart_port *port)
284 static bool atmel_use_dma_tx(struct uart_port *port)
286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
288 return atmel_port->use_dma_tx;
291 static bool atmel_use_dma_rx(struct uart_port *port)
293 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
295 return atmel_port->use_dma_rx;
298 static bool atmel_use_fifo(struct uart_port *port)
300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
302 return atmel_port->fifo_size;
305 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
306 struct tasklet_struct *t)
308 if (!atomic_read(&atmel_port->tasklet_shutdown))
312 static unsigned int atmel_get_lines_status(struct uart_port *port)
314 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
315 unsigned int status, ret = 0;
317 status = atmel_uart_readl(port, ATMEL_US_CSR);
319 mctrl_gpio_get(atmel_port->gpios, &ret);
321 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
324 status &= ~ATMEL_US_CTS;
326 status |= ATMEL_US_CTS;
329 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
332 status &= ~ATMEL_US_DSR;
334 status |= ATMEL_US_DSR;
337 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
340 status &= ~ATMEL_US_RI;
342 status |= ATMEL_US_RI;
345 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
348 status &= ~ATMEL_US_DCD;
350 status |= ATMEL_US_DCD;
356 /* Enable or disable the rs485 support */
357 static int atmel_config_rs485(struct uart_port *port,
358 struct serial_rs485 *rs485conf)
360 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
363 /* Disable interrupts */
364 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
366 mode = atmel_uart_readl(port, ATMEL_US_MR);
368 /* Resetting serial mode to RS232 (0x0) */
369 mode &= ~ATMEL_US_USMODE;
371 port->rs485 = *rs485conf;
373 if (rs485conf->flags & SER_RS485_ENABLED) {
374 dev_dbg(port->dev, "Setting UART to RS485\n");
375 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
376 atmel_uart_writel(port, ATMEL_US_TTGR,
377 rs485conf->delay_rts_after_send);
378 mode |= ATMEL_US_USMODE_RS485;
380 dev_dbg(port->dev, "Setting UART to RS232\n");
381 if (atmel_use_pdc_tx(port))
382 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
385 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
387 atmel_uart_writel(port, ATMEL_US_MR, mode);
389 /* Enable interrupts */
390 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
396 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
398 static u_int atmel_tx_empty(struct uart_port *port)
400 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
406 * Set state of the modem control output lines
408 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
410 unsigned int control = 0;
411 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
412 unsigned int rts_paused, rts_ready;
413 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
415 /* override mode to RS485 if needed, otherwise keep the current mode */
416 if (port->rs485.flags & SER_RS485_ENABLED) {
417 atmel_uart_writel(port, ATMEL_US_TTGR,
418 port->rs485.delay_rts_after_send);
419 mode &= ~ATMEL_US_USMODE;
420 mode |= ATMEL_US_USMODE_RS485;
423 /* set the RTS line state according to the mode */
424 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
425 /* force RTS line to high level */
426 rts_paused = ATMEL_US_RTSEN;
428 /* give the control of the RTS line back to the hardware */
429 rts_ready = ATMEL_US_RTSDIS;
431 /* force RTS line to high level */
432 rts_paused = ATMEL_US_RTSDIS;
434 /* force RTS line to low level */
435 rts_ready = ATMEL_US_RTSEN;
438 if (mctrl & TIOCM_RTS)
439 control |= rts_ready;
441 control |= rts_paused;
443 if (mctrl & TIOCM_DTR)
444 control |= ATMEL_US_DTREN;
446 control |= ATMEL_US_DTRDIS;
448 atmel_uart_writel(port, ATMEL_US_CR, control);
450 mctrl_gpio_set(atmel_port->gpios, mctrl);
452 /* Local loopback mode? */
453 mode &= ~ATMEL_US_CHMODE;
454 if (mctrl & TIOCM_LOOP)
455 mode |= ATMEL_US_CHMODE_LOC_LOOP;
457 mode |= ATMEL_US_CHMODE_NORMAL;
459 atmel_uart_writel(port, ATMEL_US_MR, mode);
463 * Get state of the modem control input lines
465 static u_int atmel_get_mctrl(struct uart_port *port)
467 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
468 unsigned int ret = 0, status;
470 status = atmel_uart_readl(port, ATMEL_US_CSR);
473 * The control signals are active low.
475 if (!(status & ATMEL_US_DCD))
477 if (!(status & ATMEL_US_CTS))
479 if (!(status & ATMEL_US_DSR))
481 if (!(status & ATMEL_US_RI))
484 return mctrl_gpio_get(atmel_port->gpios, &ret);
490 static void atmel_stop_tx(struct uart_port *port)
492 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
494 if (atmel_use_pdc_tx(port)) {
495 /* disable PDC transmit */
496 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
500 * Disable the transmitter.
501 * This is mandatory when DMA is used, otherwise the DMA buffer
502 * is fully transmitted.
504 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
506 /* Disable interrupts */
507 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
509 if ((port->rs485.flags & SER_RS485_ENABLED) &&
510 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
511 atmel_start_rx(port);
515 * Start transmitting.
517 static void atmel_start_tx(struct uart_port *port)
519 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
521 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
523 /* The transmitter is already running. Yes, we
527 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
528 if ((port->rs485.flags & SER_RS485_ENABLED) &&
529 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
532 if (atmel_use_pdc_tx(port))
533 /* re-enable PDC transmit */
534 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
536 /* Enable interrupts */
537 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
539 /* re-enable the transmitter */
540 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
544 * start receiving - port is in process of being opened.
546 static void atmel_start_rx(struct uart_port *port)
548 /* reset status and receiver */
549 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
551 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
553 if (atmel_use_pdc_rx(port)) {
554 /* enable PDC controller */
555 atmel_uart_writel(port, ATMEL_US_IER,
556 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
557 port->read_status_mask);
558 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
560 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
565 * Stop receiving - port is in process of being closed.
567 static void atmel_stop_rx(struct uart_port *port)
569 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
571 if (atmel_use_pdc_rx(port)) {
572 /* disable PDC receive */
573 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
574 atmel_uart_writel(port, ATMEL_US_IDR,
575 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
576 port->read_status_mask);
578 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
583 * Enable modem status interrupts
585 static void atmel_enable_ms(struct uart_port *port)
587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
591 * Interrupt should not be enabled twice
593 if (atmel_port->ms_irq_enabled)
596 atmel_port->ms_irq_enabled = true;
598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
599 ier |= ATMEL_US_CTSIC;
601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
602 ier |= ATMEL_US_DSRIC;
604 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
605 ier |= ATMEL_US_RIIC;
607 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
608 ier |= ATMEL_US_DCDIC;
610 atmel_uart_writel(port, ATMEL_US_IER, ier);
612 mctrl_gpio_enable_ms(atmel_port->gpios);
616 * Disable modem status interrupts
618 static void atmel_disable_ms(struct uart_port *port)
620 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
624 * Interrupt should not be disabled twice
626 if (!atmel_port->ms_irq_enabled)
629 atmel_port->ms_irq_enabled = false;
631 mctrl_gpio_disable_ms(atmel_port->gpios);
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
634 idr |= ATMEL_US_CTSIC;
636 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
637 idr |= ATMEL_US_DSRIC;
639 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
640 idr |= ATMEL_US_RIIC;
642 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
643 idr |= ATMEL_US_DCDIC;
645 atmel_uart_writel(port, ATMEL_US_IDR, idr);
649 * Control the transmission of a break signal
651 static void atmel_break_ctl(struct uart_port *port, int break_state)
653 if (break_state != 0)
655 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
658 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
662 * Stores the incoming character in the ring buffer
665 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
668 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
669 struct circ_buf *ring = &atmel_port->rx_ring;
670 struct atmel_uart_char *c;
672 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
673 /* Buffer overflow, ignore char */
676 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
680 /* Make sure the character is stored before we update head. */
683 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
687 * Deal with parity, framing and overrun errors.
689 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
692 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
694 if (status & ATMEL_US_RXBRK) {
695 /* ignore side-effect */
696 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
699 if (status & ATMEL_US_PARE)
700 port->icount.parity++;
701 if (status & ATMEL_US_FRAME)
702 port->icount.frame++;
703 if (status & ATMEL_US_OVRE)
704 port->icount.overrun++;
708 * Characters received (called from interrupt handler)
710 static void atmel_rx_chars(struct uart_port *port)
712 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
713 unsigned int status, ch;
715 status = atmel_uart_readl(port, ATMEL_US_CSR);
716 while (status & ATMEL_US_RXRDY) {
717 ch = atmel_uart_read_char(port);
720 * note that the error handling code is
721 * out of the main execution path
723 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
724 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
725 || atmel_port->break_active)) {
728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
730 if (status & ATMEL_US_RXBRK
731 && !atmel_port->break_active) {
732 atmel_port->break_active = 1;
733 atmel_uart_writel(port, ATMEL_US_IER,
737 * This is either the end-of-break
738 * condition or we've received at
739 * least one character without RXBRK
740 * being set. In both cases, the next
741 * RXBRK will indicate start-of-break.
743 atmel_uart_writel(port, ATMEL_US_IDR,
745 status &= ~ATMEL_US_RXBRK;
746 atmel_port->break_active = 0;
750 atmel_buffer_rx_char(port, status, ch);
751 status = atmel_uart_readl(port, ATMEL_US_CSR);
754 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
758 * Transmit characters (called from tasklet with TXRDY interrupt
761 static void atmel_tx_chars(struct uart_port *port)
763 struct circ_buf *xmit = &port->state->xmit;
764 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
767 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
768 atmel_uart_write_char(port, port->x_char);
772 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
775 while (atmel_uart_readl(port, ATMEL_US_CSR) &
776 atmel_port->tx_done_mask) {
777 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
778 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
780 if (uart_circ_empty(xmit))
784 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
785 uart_write_wakeup(port);
787 if (!uart_circ_empty(xmit))
788 /* Enable interrupts */
789 atmel_uart_writel(port, ATMEL_US_IER,
790 atmel_port->tx_done_mask);
793 static void atmel_complete_tx_dma(void *arg)
795 struct atmel_uart_port *atmel_port = arg;
796 struct uart_port *port = &atmel_port->uart;
797 struct circ_buf *xmit = &port->state->xmit;
798 struct dma_chan *chan = atmel_port->chan_tx;
801 spin_lock_irqsave(&port->lock, flags);
804 dmaengine_terminate_all(chan);
805 xmit->tail += atmel_port->tx_len;
806 xmit->tail &= UART_XMIT_SIZE - 1;
808 port->icount.tx += atmel_port->tx_len;
810 spin_lock_irq(&atmel_port->lock_tx);
811 async_tx_ack(atmel_port->desc_tx);
812 atmel_port->cookie_tx = -EINVAL;
813 atmel_port->desc_tx = NULL;
814 spin_unlock_irq(&atmel_port->lock_tx);
816 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
817 uart_write_wakeup(port);
820 * xmit is a circular buffer so, if we have just send data from
821 * xmit->tail to the end of xmit->buf, now we have to transmit the
822 * remaining data from the beginning of xmit->buf to xmit->head.
824 if (!uart_circ_empty(xmit))
825 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
826 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
827 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
828 /* DMA done, stop TX, start RX for RS485 */
829 atmel_start_rx(port);
832 spin_unlock_irqrestore(&port->lock, flags);
835 static void atmel_release_tx_dma(struct uart_port *port)
837 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
838 struct dma_chan *chan = atmel_port->chan_tx;
841 dmaengine_terminate_all(chan);
842 dma_release_channel(chan);
843 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
847 atmel_port->desc_tx = NULL;
848 atmel_port->chan_tx = NULL;
849 atmel_port->cookie_tx = -EINVAL;
853 * Called from tasklet with TXRDY interrupt is disabled.
855 static void atmel_tx_dma(struct uart_port *port)
857 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
858 struct circ_buf *xmit = &port->state->xmit;
859 struct dma_chan *chan = atmel_port->chan_tx;
860 struct dma_async_tx_descriptor *desc;
861 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
862 unsigned int tx_len, part1_len, part2_len, sg_len;
863 dma_addr_t phys_addr;
865 /* Make sure we have an idle channel */
866 if (atmel_port->desc_tx != NULL)
869 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
872 * Port xmit buffer is already mapped,
873 * and it is one page... Just adjust
874 * offsets and lengths. Since it is a circular buffer,
875 * we have to transmit till the end, and then the rest.
876 * Take the port lock to get a
877 * consistent xmit buffer state.
879 tx_len = CIRC_CNT_TO_END(xmit->head,
883 if (atmel_port->fifo_size) {
884 /* multi data mode */
885 part1_len = (tx_len & ~0x3); /* DWORD access */
886 part2_len = (tx_len & 0x3); /* BYTE access */
888 /* single data (legacy) mode */
890 part2_len = tx_len; /* BYTE access only */
893 sg_init_table(sgl, 2);
895 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
898 sg_dma_address(sg) = phys_addr;
899 sg_dma_len(sg) = part1_len;
901 phys_addr += part1_len;
906 sg_dma_address(sg) = phys_addr;
907 sg_dma_len(sg) = part2_len;
911 * save tx_len so atmel_complete_tx_dma() will increase
912 * xmit->tail correctly
914 atmel_port->tx_len = tx_len;
916 desc = dmaengine_prep_slave_sg(chan,
923 dev_err(port->dev, "Failed to send via dma!\n");
927 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
929 atmel_port->desc_tx = desc;
930 desc->callback = atmel_complete_tx_dma;
931 desc->callback_param = atmel_port;
932 atmel_port->cookie_tx = dmaengine_submit(desc);
935 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
936 uart_write_wakeup(port);
939 static int atmel_prepare_tx_dma(struct uart_port *port)
941 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
943 struct dma_slave_config config;
947 dma_cap_set(DMA_SLAVE, mask);
949 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
950 if (atmel_port->chan_tx == NULL)
952 dev_info(port->dev, "using %s for tx DMA transfers\n",
953 dma_chan_name(atmel_port->chan_tx));
955 spin_lock_init(&atmel_port->lock_tx);
956 sg_init_table(&atmel_port->sg_tx, 1);
957 /* UART circular tx buffer is an aligned page. */
958 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
959 sg_set_page(&atmel_port->sg_tx,
960 virt_to_page(port->state->xmit.buf),
962 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
963 nent = dma_map_sg(port->dev,
969 dev_dbg(port->dev, "need to release resource of dma\n");
972 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
973 sg_dma_len(&atmel_port->sg_tx),
974 port->state->xmit.buf,
975 &sg_dma_address(&atmel_port->sg_tx));
978 /* Configure the slave DMA */
979 memset(&config, 0, sizeof(config));
980 config.direction = DMA_MEM_TO_DEV;
981 config.dst_addr_width = (atmel_port->fifo_size) ?
982 DMA_SLAVE_BUSWIDTH_4_BYTES :
983 DMA_SLAVE_BUSWIDTH_1_BYTE;
984 config.dst_addr = port->mapbase + ATMEL_US_THR;
985 config.dst_maxburst = 1;
987 ret = dmaengine_slave_config(atmel_port->chan_tx,
990 dev_err(port->dev, "DMA tx slave configuration failed\n");
997 dev_err(port->dev, "TX channel not available, switch to pio\n");
998 atmel_port->use_dma_tx = 0;
999 if (atmel_port->chan_tx)
1000 atmel_release_tx_dma(port);
1004 static void atmel_complete_rx_dma(void *arg)
1006 struct uart_port *port = arg;
1007 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1009 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1012 static void atmel_release_rx_dma(struct uart_port *port)
1014 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1015 struct dma_chan *chan = atmel_port->chan_rx;
1018 dmaengine_terminate_all(chan);
1019 dma_release_channel(chan);
1020 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1024 atmel_port->desc_rx = NULL;
1025 atmel_port->chan_rx = NULL;
1026 atmel_port->cookie_rx = -EINVAL;
1029 static void atmel_rx_from_dma(struct uart_port *port)
1031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1032 struct tty_port *tport = &port->state->port;
1033 struct circ_buf *ring = &atmel_port->rx_ring;
1034 struct dma_chan *chan = atmel_port->chan_rx;
1035 struct dma_tx_state state;
1036 enum dma_status dmastat;
1040 /* Reset the UART timeout early so that we don't miss one */
1041 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1042 dmastat = dmaengine_tx_status(chan,
1043 atmel_port->cookie_rx,
1045 /* Restart a new tasklet if DMA status is error */
1046 if (dmastat == DMA_ERROR) {
1047 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1048 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1049 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1053 /* CPU claims ownership of RX DMA buffer */
1054 dma_sync_sg_for_cpu(port->dev,
1060 * ring->head points to the end of data already written by the DMA.
1061 * ring->tail points to the beginning of data to be read by the
1063 * The current transfer size should not be larger than the dma buffer
1066 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1067 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1069 * At this point ring->head may point to the first byte right after the
1070 * last byte of the dma buffer:
1071 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1073 * However ring->tail must always points inside the dma buffer:
1074 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1076 * Since we use a ring buffer, we have to handle the case
1077 * where head is lower than tail. In such a case, we first read from
1078 * tail to the end of the buffer then reset tail.
1080 if (ring->head < ring->tail) {
1081 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1083 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1085 port->icount.rx += count;
1088 /* Finally we read data from tail to head */
1089 if (ring->tail < ring->head) {
1090 count = ring->head - ring->tail;
1092 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1093 /* Wrap ring->head if needed */
1094 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1096 ring->tail = ring->head;
1097 port->icount.rx += count;
1100 /* USART retreives ownership of RX DMA buffer */
1101 dma_sync_sg_for_device(port->dev,
1107 * Drop the lock here since it might end up calling
1108 * uart_start(), which takes the lock.
1110 spin_unlock(&port->lock);
1111 tty_flip_buffer_push(tport);
1112 spin_lock(&port->lock);
1114 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1117 static int atmel_prepare_rx_dma(struct uart_port *port)
1119 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1120 struct dma_async_tx_descriptor *desc;
1121 dma_cap_mask_t mask;
1122 struct dma_slave_config config;
1123 struct circ_buf *ring;
1126 ring = &atmel_port->rx_ring;
1129 dma_cap_set(DMA_CYCLIC, mask);
1131 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1132 if (atmel_port->chan_rx == NULL)
1134 dev_info(port->dev, "using %s for rx DMA transfers\n",
1135 dma_chan_name(atmel_port->chan_rx));
1137 spin_lock_init(&atmel_port->lock_rx);
1138 sg_init_table(&atmel_port->sg_rx, 1);
1139 /* UART circular rx buffer is an aligned page. */
1140 BUG_ON(!PAGE_ALIGNED(ring->buf));
1141 sg_set_page(&atmel_port->sg_rx,
1142 virt_to_page(ring->buf),
1143 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1144 (unsigned long)ring->buf & ~PAGE_MASK);
1145 nent = dma_map_sg(port->dev,
1151 dev_dbg(port->dev, "need to release resource of dma\n");
1154 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1155 sg_dma_len(&atmel_port->sg_rx),
1157 &sg_dma_address(&atmel_port->sg_rx));
1160 /* Configure the slave DMA */
1161 memset(&config, 0, sizeof(config));
1162 config.direction = DMA_DEV_TO_MEM;
1163 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1164 config.src_addr = port->mapbase + ATMEL_US_RHR;
1165 config.src_maxburst = 1;
1167 ret = dmaengine_slave_config(atmel_port->chan_rx,
1170 dev_err(port->dev, "DMA rx slave configuration failed\n");
1174 * Prepare a cyclic dma transfer, assign 2 descriptors,
1175 * each one is half ring buffer size
1177 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1178 sg_dma_address(&atmel_port->sg_rx),
1179 sg_dma_len(&atmel_port->sg_rx),
1180 sg_dma_len(&atmel_port->sg_rx)/2,
1182 DMA_PREP_INTERRUPT);
1183 desc->callback = atmel_complete_rx_dma;
1184 desc->callback_param = port;
1185 atmel_port->desc_rx = desc;
1186 atmel_port->cookie_rx = dmaengine_submit(desc);
1191 dev_err(port->dev, "RX channel not available, switch to pio\n");
1192 atmel_port->use_dma_rx = 0;
1193 if (atmel_port->chan_rx)
1194 atmel_release_rx_dma(port);
1198 static void atmel_uart_timer_callback(unsigned long data)
1200 struct uart_port *port = (void *)data;
1201 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1203 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1204 tasklet_schedule(&atmel_port->tasklet_rx);
1205 mod_timer(&atmel_port->uart_timer,
1206 jiffies + uart_poll_timeout(port));
1211 * receive interrupt handler.
1214 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1216 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1218 if (atmel_use_pdc_rx(port)) {
1220 * PDC receive. Just schedule the tasklet and let it
1221 * figure out the details.
1223 * TODO: We're not handling error flags correctly at
1226 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1227 atmel_uart_writel(port, ATMEL_US_IDR,
1228 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1229 atmel_tasklet_schedule(atmel_port,
1230 &atmel_port->tasklet_rx);
1233 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1234 ATMEL_US_FRAME | ATMEL_US_PARE))
1235 atmel_pdc_rxerr(port, pending);
1238 if (atmel_use_dma_rx(port)) {
1239 if (pending & ATMEL_US_TIMEOUT) {
1240 atmel_uart_writel(port, ATMEL_US_IDR,
1242 atmel_tasklet_schedule(atmel_port,
1243 &atmel_port->tasklet_rx);
1247 /* Interrupt receive */
1248 if (pending & ATMEL_US_RXRDY)
1249 atmel_rx_chars(port);
1250 else if (pending & ATMEL_US_RXBRK) {
1252 * End of break detected. If it came along with a
1253 * character, atmel_rx_chars will handle it.
1255 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1256 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1257 atmel_port->break_active = 0;
1262 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1265 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1269 if (pending & atmel_port->tx_done_mask) {
1270 /* Either PDC or interrupt transmission */
1271 atmel_uart_writel(port, ATMEL_US_IDR,
1272 atmel_port->tx_done_mask);
1273 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1278 * status flags interrupt handler.
1281 atmel_handle_status(struct uart_port *port, unsigned int pending,
1282 unsigned int status)
1284 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1285 unsigned int status_change;
1287 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1288 | ATMEL_US_CTSIC)) {
1289 status_change = status ^ atmel_port->irq_status_prev;
1290 atmel_port->irq_status_prev = status;
1292 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1293 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1294 /* TODO: All reads to CSR will clear these interrupts! */
1295 if (status_change & ATMEL_US_RI)
1297 if (status_change & ATMEL_US_DSR)
1299 if (status_change & ATMEL_US_DCD)
1300 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1301 if (status_change & ATMEL_US_CTS)
1302 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1304 wake_up_interruptible(&port->state->port.delta_msr_wait);
1312 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1314 struct uart_port *port = dev_id;
1315 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1316 unsigned int status, pending, mask, pass_counter = 0;
1318 spin_lock(&atmel_port->lock_suspended);
1321 status = atmel_get_lines_status(port);
1322 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1323 pending = status & mask;
1327 if (atmel_port->suspended) {
1328 atmel_port->pending |= pending;
1329 atmel_port->pending_status = status;
1330 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1335 atmel_handle_receive(port, pending);
1336 atmel_handle_status(port, pending, status);
1337 atmel_handle_transmit(port, pending);
1338 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1340 spin_unlock(&atmel_port->lock_suspended);
1342 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1345 static void atmel_release_tx_pdc(struct uart_port *port)
1347 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1348 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1350 dma_unmap_single(port->dev,
1357 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1359 static void atmel_tx_pdc(struct uart_port *port)
1361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1362 struct circ_buf *xmit = &port->state->xmit;
1363 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1366 /* nothing left to transmit? */
1367 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1370 xmit->tail += pdc->ofs;
1371 xmit->tail &= UART_XMIT_SIZE - 1;
1373 port->icount.tx += pdc->ofs;
1376 /* more to transmit - setup next transfer */
1378 /* disable PDC transmit */
1379 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1381 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1382 dma_sync_single_for_device(port->dev,
1387 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1390 atmel_uart_writel(port, ATMEL_PDC_TPR,
1391 pdc->dma_addr + xmit->tail);
1392 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1393 /* re-enable PDC transmit */
1394 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1395 /* Enable interrupts */
1396 atmel_uart_writel(port, ATMEL_US_IER,
1397 atmel_port->tx_done_mask);
1399 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1400 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1401 /* DMA done, stop TX, start RX for RS485 */
1402 atmel_start_rx(port);
1406 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1407 uart_write_wakeup(port);
1410 static int atmel_prepare_tx_pdc(struct uart_port *port)
1412 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1413 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1414 struct circ_buf *xmit = &port->state->xmit;
1416 pdc->buf = xmit->buf;
1417 pdc->dma_addr = dma_map_single(port->dev,
1421 pdc->dma_size = UART_XMIT_SIZE;
1427 static void atmel_rx_from_ring(struct uart_port *port)
1429 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1430 struct circ_buf *ring = &atmel_port->rx_ring;
1432 unsigned int status;
1434 while (ring->head != ring->tail) {
1435 struct atmel_uart_char c;
1437 /* Make sure c is loaded after head. */
1440 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1442 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1449 * note that the error handling code is
1450 * out of the main execution path
1452 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1453 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1454 if (status & ATMEL_US_RXBRK) {
1455 /* ignore side-effect */
1456 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1459 if (uart_handle_break(port))
1462 if (status & ATMEL_US_PARE)
1463 port->icount.parity++;
1464 if (status & ATMEL_US_FRAME)
1465 port->icount.frame++;
1466 if (status & ATMEL_US_OVRE)
1467 port->icount.overrun++;
1469 status &= port->read_status_mask;
1471 if (status & ATMEL_US_RXBRK)
1473 else if (status & ATMEL_US_PARE)
1475 else if (status & ATMEL_US_FRAME)
1480 if (uart_handle_sysrq_char(port, c.ch))
1483 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1487 * Drop the lock here since it might end up calling
1488 * uart_start(), which takes the lock.
1490 spin_unlock(&port->lock);
1491 tty_flip_buffer_push(&port->state->port);
1492 spin_lock(&port->lock);
1495 static void atmel_release_rx_pdc(struct uart_port *port)
1497 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1500 for (i = 0; i < 2; i++) {
1501 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1503 dma_unmap_single(port->dev,
1511 static void atmel_rx_from_pdc(struct uart_port *port)
1513 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1514 struct tty_port *tport = &port->state->port;
1515 struct atmel_dma_buffer *pdc;
1516 int rx_idx = atmel_port->pdc_rx_idx;
1522 /* Reset the UART timeout early so that we don't miss one */
1523 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1525 pdc = &atmel_port->pdc_rx[rx_idx];
1526 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1529 /* If the PDC has switched buffers, RPR won't contain
1530 * any address within the current buffer. Since head
1531 * is unsigned, we just need a one-way comparison to
1534 * In this case, we just need to consume the entire
1535 * buffer and resubmit it for DMA. This will clear the
1536 * ENDRX bit as well, so that we can safely re-enable
1537 * all interrupts below.
1539 head = min(head, pdc->dma_size);
1541 if (likely(head != tail)) {
1542 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1543 pdc->dma_size, DMA_FROM_DEVICE);
1546 * head will only wrap around when we recycle
1547 * the DMA buffer, and when that happens, we
1548 * explicitly set tail to 0. So head will
1549 * always be greater than tail.
1551 count = head - tail;
1553 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1556 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1557 pdc->dma_size, DMA_FROM_DEVICE);
1559 port->icount.rx += count;
1564 * If the current buffer is full, we need to check if
1565 * the next one contains any additional data.
1567 if (head >= pdc->dma_size) {
1569 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1570 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1573 atmel_port->pdc_rx_idx = rx_idx;
1575 } while (head >= pdc->dma_size);
1578 * Drop the lock here since it might end up calling
1579 * uart_start(), which takes the lock.
1581 spin_unlock(&port->lock);
1582 tty_flip_buffer_push(tport);
1583 spin_lock(&port->lock);
1585 atmel_uart_writel(port, ATMEL_US_IER,
1586 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1589 static int atmel_prepare_rx_pdc(struct uart_port *port)
1591 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1594 for (i = 0; i < 2; i++) {
1595 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1597 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1598 if (pdc->buf == NULL) {
1600 dma_unmap_single(port->dev,
1601 atmel_port->pdc_rx[0].dma_addr,
1604 kfree(atmel_port->pdc_rx[0].buf);
1606 atmel_port->use_pdc_rx = 0;
1609 pdc->dma_addr = dma_map_single(port->dev,
1613 pdc->dma_size = PDC_BUFFER_SIZE;
1617 atmel_port->pdc_rx_idx = 0;
1619 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1620 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1622 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1623 atmel_port->pdc_rx[1].dma_addr);
1624 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1630 * tasklet handling tty stuff outside the interrupt handler.
1632 static void atmel_tasklet_rx_func(unsigned long data)
1634 struct uart_port *port = (struct uart_port *)data;
1635 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1637 /* The interrupt handler does not take the lock */
1638 spin_lock(&port->lock);
1639 atmel_port->schedule_rx(port);
1640 spin_unlock(&port->lock);
1643 static void atmel_tasklet_tx_func(unsigned long data)
1645 struct uart_port *port = (struct uart_port *)data;
1646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1648 /* The interrupt handler does not take the lock */
1649 spin_lock(&port->lock);
1650 atmel_port->schedule_tx(port);
1651 spin_unlock(&port->lock);
1654 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1655 struct platform_device *pdev)
1657 struct device_node *np = pdev->dev.of_node;
1658 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1661 /* DMA/PDC usage specification */
1662 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1663 if (of_property_read_bool(np, "dmas")) {
1664 atmel_port->use_dma_rx = true;
1665 atmel_port->use_pdc_rx = false;
1667 atmel_port->use_dma_rx = false;
1668 atmel_port->use_pdc_rx = true;
1671 atmel_port->use_dma_rx = false;
1672 atmel_port->use_pdc_rx = false;
1675 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1676 if (of_property_read_bool(np, "dmas")) {
1677 atmel_port->use_dma_tx = true;
1678 atmel_port->use_pdc_tx = false;
1680 atmel_port->use_dma_tx = false;
1681 atmel_port->use_pdc_tx = true;
1684 atmel_port->use_dma_tx = false;
1685 atmel_port->use_pdc_tx = false;
1689 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1690 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1691 atmel_port->use_dma_rx = false;
1692 atmel_port->use_dma_tx = false;
1697 static void atmel_init_rs485(struct uart_port *port,
1698 struct platform_device *pdev)
1700 struct device_node *np = pdev->dev.of_node;
1701 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1704 struct serial_rs485 *rs485conf = &port->rs485;
1706 /* rs485 properties */
1707 if (of_property_read_u32_array(np, "rs485-rts-delay",
1708 rs485_delay, 2) == 0) {
1709 rs485conf->delay_rts_before_send = rs485_delay[0];
1710 rs485conf->delay_rts_after_send = rs485_delay[1];
1711 rs485conf->flags = 0;
1714 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1715 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1717 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1719 rs485conf->flags |= SER_RS485_ENABLED;
1721 port->rs485 = pdata->rs485;
1726 static void atmel_set_ops(struct uart_port *port)
1728 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1730 if (atmel_use_dma_rx(port)) {
1731 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1732 atmel_port->schedule_rx = &atmel_rx_from_dma;
1733 atmel_port->release_rx = &atmel_release_rx_dma;
1734 } else if (atmel_use_pdc_rx(port)) {
1735 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1736 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1737 atmel_port->release_rx = &atmel_release_rx_pdc;
1739 atmel_port->prepare_rx = NULL;
1740 atmel_port->schedule_rx = &atmel_rx_from_ring;
1741 atmel_port->release_rx = NULL;
1744 if (atmel_use_dma_tx(port)) {
1745 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1746 atmel_port->schedule_tx = &atmel_tx_dma;
1747 atmel_port->release_tx = &atmel_release_tx_dma;
1748 } else if (atmel_use_pdc_tx(port)) {
1749 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1750 atmel_port->schedule_tx = &atmel_tx_pdc;
1751 atmel_port->release_tx = &atmel_release_tx_pdc;
1753 atmel_port->prepare_tx = NULL;
1754 atmel_port->schedule_tx = &atmel_tx_chars;
1755 atmel_port->release_tx = NULL;
1760 * Get ip name usart or uart
1762 static void atmel_get_ip_name(struct uart_port *port)
1764 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1765 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1767 u32 usart, dbgu_uart, new_uart;
1768 /* ASCII decoding for IP version */
1769 usart = 0x55534152; /* USAR(T) */
1770 dbgu_uart = 0x44424755; /* DBGU */
1771 new_uart = 0x55415254; /* UART */
1774 * Only USART devices from at91sam9260 SOC implement fractional
1775 * baudrate. It is available for all asynchronous modes, with the
1776 * following restriction: the sampling clock's duty cycle is not
1779 atmel_port->has_frac_baudrate = false;
1780 atmel_port->has_hw_timer = false;
1782 if (name == new_uart) {
1783 dev_dbg(port->dev, "Uart with hw timer");
1784 atmel_port->has_hw_timer = true;
1785 atmel_port->rtor = ATMEL_UA_RTOR;
1786 } else if (name == usart) {
1787 dev_dbg(port->dev, "Usart\n");
1788 atmel_port->has_frac_baudrate = true;
1789 atmel_port->has_hw_timer = true;
1790 atmel_port->rtor = ATMEL_US_RTOR;
1791 } else if (name == dbgu_uart) {
1792 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1794 /* fallback for older SoCs: use version field */
1795 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1799 dev_dbg(port->dev, "This version is usart\n");
1800 atmel_port->has_frac_baudrate = true;
1801 atmel_port->has_hw_timer = true;
1802 atmel_port->rtor = ATMEL_US_RTOR;
1806 dev_dbg(port->dev, "This version is uart\n");
1809 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1815 * Perform initialization and enable port for reception
1817 static int atmel_startup(struct uart_port *port)
1819 struct platform_device *pdev = to_platform_device(port->dev);
1820 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1821 struct tty_struct *tty = port->state->port.tty;
1825 * Ensure that no interrupts are enabled otherwise when
1826 * request_irq() is called we could get stuck trying to
1827 * handle an unexpected interrupt
1829 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1830 atmel_port->ms_irq_enabled = false;
1835 retval = request_irq(port->irq, atmel_interrupt,
1836 IRQF_SHARED | IRQF_COND_SUSPEND,
1837 tty ? tty->name : "atmel_serial", port);
1839 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1843 atomic_set(&atmel_port->tasklet_shutdown, 0);
1844 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1845 (unsigned long)port);
1846 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1847 (unsigned long)port);
1850 * Initialize DMA (if necessary)
1852 atmel_init_property(atmel_port, pdev);
1853 atmel_set_ops(port);
1855 if (atmel_port->prepare_rx) {
1856 retval = atmel_port->prepare_rx(port);
1858 atmel_set_ops(port);
1861 if (atmel_port->prepare_tx) {
1862 retval = atmel_port->prepare_tx(port);
1864 atmel_set_ops(port);
1868 * Enable FIFO when available
1870 if (atmel_port->fifo_size) {
1871 unsigned int txrdym = ATMEL_US_ONE_DATA;
1872 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1875 atmel_uart_writel(port, ATMEL_US_CR,
1880 if (atmel_use_dma_tx(port))
1881 txrdym = ATMEL_US_FOUR_DATA;
1883 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1884 if (atmel_port->rts_high &&
1885 atmel_port->rts_low)
1886 fmr |= ATMEL_US_FRTSC |
1887 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1888 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1890 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1893 /* Save current CSR for comparison in atmel_tasklet_func() */
1894 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1897 * Finally, enable the serial port
1899 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1900 /* enable xmit & rcvr */
1901 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1903 setup_timer(&atmel_port->uart_timer,
1904 atmel_uart_timer_callback,
1905 (unsigned long)port);
1907 if (atmel_use_pdc_rx(port)) {
1908 /* set UART timeout */
1909 if (!atmel_port->has_hw_timer) {
1910 mod_timer(&atmel_port->uart_timer,
1911 jiffies + uart_poll_timeout(port));
1912 /* set USART timeout */
1914 atmel_uart_writel(port, atmel_port->rtor,
1916 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1918 atmel_uart_writel(port, ATMEL_US_IER,
1919 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1921 /* enable PDC controller */
1922 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1923 } else if (atmel_use_dma_rx(port)) {
1924 /* set UART timeout */
1925 if (!atmel_port->has_hw_timer) {
1926 mod_timer(&atmel_port->uart_timer,
1927 jiffies + uart_poll_timeout(port));
1928 /* set USART timeout */
1930 atmel_uart_writel(port, atmel_port->rtor,
1932 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1934 atmel_uart_writel(port, ATMEL_US_IER,
1938 /* enable receive only */
1939 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1946 * Flush any TX data submitted for DMA. Called when the TX circular
1949 static void atmel_flush_buffer(struct uart_port *port)
1951 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1953 if (atmel_use_pdc_tx(port)) {
1954 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1955 atmel_port->pdc_tx.ofs = 0;
1958 * in uart_flush_buffer(), the xmit circular buffer has just
1959 * been cleared, so we have to reset tx_len accordingly.
1961 atmel_port->tx_len = 0;
1967 static void atmel_shutdown(struct uart_port *port)
1969 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1971 /* Disable modem control lines interrupts */
1972 atmel_disable_ms(port);
1974 /* Disable interrupts at device level */
1975 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1977 /* Prevent spurious interrupts from scheduling the tasklet */
1978 atomic_inc(&atmel_port->tasklet_shutdown);
1981 * Prevent any tasklets being scheduled during
1984 del_timer_sync(&atmel_port->uart_timer);
1986 /* Make sure that no interrupt is on the fly */
1987 synchronize_irq(port->irq);
1990 * Clear out any scheduled tasklets before
1991 * we destroy the buffers
1993 tasklet_kill(&atmel_port->tasklet_rx);
1994 tasklet_kill(&atmel_port->tasklet_tx);
1997 * Ensure everything is stopped and
1998 * disable port and break condition.
2000 atmel_stop_rx(port);
2001 atmel_stop_tx(port);
2003 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2006 * Shut-down the DMA.
2008 if (atmel_port->release_rx)
2009 atmel_port->release_rx(port);
2010 if (atmel_port->release_tx)
2011 atmel_port->release_tx(port);
2014 * Reset ring buffer pointers
2016 atmel_port->rx_ring.head = 0;
2017 atmel_port->rx_ring.tail = 0;
2020 * Free the interrupts
2022 free_irq(port->irq, port);
2024 atmel_flush_buffer(port);
2028 * Power / Clock management.
2030 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2031 unsigned int oldstate)
2033 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2038 * Enable the peripheral clock for this serial port.
2039 * This is called on uart_open() or a resume event.
2041 clk_prepare_enable(atmel_port->clk);
2043 /* re-enable interrupts if we disabled some on suspend */
2044 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2047 /* Back up the interrupt mask and disable all interrupts */
2048 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2049 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2052 * Disable the peripheral clock for this serial port.
2053 * This is called on uart_close() or a suspend event.
2055 clk_disable_unprepare(atmel_port->clk);
2058 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2063 * Change the port parameters
2065 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2066 struct ktermios *old)
2068 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2069 unsigned long flags;
2070 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2072 /* save the current mode register */
2073 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2075 /* reset the mode, clock divisor, parity, stop bits and data size */
2076 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2077 ATMEL_US_PAR | ATMEL_US_USMODE);
2079 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2082 switch (termios->c_cflag & CSIZE) {
2084 mode |= ATMEL_US_CHRL_5;
2087 mode |= ATMEL_US_CHRL_6;
2090 mode |= ATMEL_US_CHRL_7;
2093 mode |= ATMEL_US_CHRL_8;
2098 if (termios->c_cflag & CSTOPB)
2099 mode |= ATMEL_US_NBSTOP_2;
2102 if (termios->c_cflag & PARENB) {
2103 /* Mark or Space parity */
2104 if (termios->c_cflag & CMSPAR) {
2105 if (termios->c_cflag & PARODD)
2106 mode |= ATMEL_US_PAR_MARK;
2108 mode |= ATMEL_US_PAR_SPACE;
2109 } else if (termios->c_cflag & PARODD)
2110 mode |= ATMEL_US_PAR_ODD;
2112 mode |= ATMEL_US_PAR_EVEN;
2114 mode |= ATMEL_US_PAR_NONE;
2116 spin_lock_irqsave(&port->lock, flags);
2118 port->read_status_mask = ATMEL_US_OVRE;
2119 if (termios->c_iflag & INPCK)
2120 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2121 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2122 port->read_status_mask |= ATMEL_US_RXBRK;
2124 if (atmel_use_pdc_rx(port))
2125 /* need to enable error interrupts */
2126 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2129 * Characters to ignore
2131 port->ignore_status_mask = 0;
2132 if (termios->c_iflag & IGNPAR)
2133 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2134 if (termios->c_iflag & IGNBRK) {
2135 port->ignore_status_mask |= ATMEL_US_RXBRK;
2137 * If we're ignoring parity and break indicators,
2138 * ignore overruns too (for real raw support).
2140 if (termios->c_iflag & IGNPAR)
2141 port->ignore_status_mask |= ATMEL_US_OVRE;
2143 /* TODO: Ignore all characters if CREAD is set.*/
2145 /* update the per-port timeout */
2146 uart_update_timeout(port, termios->c_cflag, baud);
2149 * save/disable interrupts. The tty layer will ensure that the
2150 * transmitter is empty if requested by the caller, so there's
2151 * no need to wait for it here.
2153 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2154 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2156 /* disable receiver and transmitter */
2157 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2160 if (port->rs485.flags & SER_RS485_ENABLED) {
2161 atmel_uart_writel(port, ATMEL_US_TTGR,
2162 port->rs485.delay_rts_after_send);
2163 mode |= ATMEL_US_USMODE_RS485;
2164 } else if (termios->c_cflag & CRTSCTS) {
2165 /* RS232 with hardware handshake (RTS/CTS) */
2166 if (atmel_use_fifo(port) &&
2167 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2169 * with ATMEL_US_USMODE_HWHS set, the controller will
2170 * be able to drive the RTS pin high/low when the RX
2171 * FIFO is above RXFTHRES/below RXFTHRES2.
2172 * It will also disable the transmitter when the CTS
2174 * This mode is not activated if CTS pin is a GPIO
2175 * because in this case, the transmitter is always
2176 * disabled (there must be an internal pull-up
2177 * responsible for this behaviour).
2178 * If the RTS pin is a GPIO, the controller won't be
2179 * able to drive it according to the FIFO thresholds,
2180 * but it will be handled by the driver.
2182 mode |= ATMEL_US_USMODE_HWHS;
2185 * For platforms without FIFO, the flow control is
2186 * handled by the driver.
2188 mode |= ATMEL_US_USMODE_NORMAL;
2191 /* RS232 without hadware handshake */
2192 mode |= ATMEL_US_USMODE_NORMAL;
2195 /* set the mode, clock divisor, parity, stop bits and data size */
2196 atmel_uart_writel(port, ATMEL_US_MR, mode);
2199 * when switching the mode, set the RTS line state according to the
2200 * new mode, otherwise keep the former state
2202 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2203 unsigned int rts_state;
2205 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2206 /* let the hardware control the RTS line */
2207 rts_state = ATMEL_US_RTSDIS;
2209 /* force RTS line to low level */
2210 rts_state = ATMEL_US_RTSEN;
2213 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2217 * Set the baud rate:
2218 * Fractional baudrate allows to setup output frequency more
2219 * accurately. This feature is enabled only when using normal mode.
2220 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2221 * Currently, OVER is always set to 0 so we get
2222 * baudrate = selected clock / (16 * (CD + FP / 8))
2224 * 8 CD + FP = selected clock / (2 * baudrate)
2226 if (atmel_port->has_frac_baudrate) {
2227 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2229 fp = div & ATMEL_US_FP_MASK;
2231 cd = uart_get_divisor(port, baud);
2234 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2236 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2238 quot = cd | fp << ATMEL_US_FP_OFFSET;
2240 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2241 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2242 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2244 /* restore interrupts */
2245 atmel_uart_writel(port, ATMEL_US_IER, imr);
2247 /* CTS flow-control and modem-status interrupts */
2248 if (UART_ENABLE_MS(port, termios->c_cflag))
2249 atmel_enable_ms(port);
2251 atmel_disable_ms(port);
2253 spin_unlock_irqrestore(&port->lock, flags);
2256 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2258 if (termios->c_line == N_PPS) {
2259 port->flags |= UPF_HARDPPS_CD;
2260 spin_lock_irq(&port->lock);
2261 atmel_enable_ms(port);
2262 spin_unlock_irq(&port->lock);
2264 port->flags &= ~UPF_HARDPPS_CD;
2265 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2266 spin_lock_irq(&port->lock);
2267 atmel_disable_ms(port);
2268 spin_unlock_irq(&port->lock);
2274 * Return string describing the specified port
2276 static const char *atmel_type(struct uart_port *port)
2278 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2282 * Release the memory region(s) being used by 'port'.
2284 static void atmel_release_port(struct uart_port *port)
2286 struct platform_device *pdev = to_platform_device(port->dev);
2287 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2289 release_mem_region(port->mapbase, size);
2291 if (port->flags & UPF_IOREMAP) {
2292 iounmap(port->membase);
2293 port->membase = NULL;
2298 * Request the memory region(s) being used by 'port'.
2300 static int atmel_request_port(struct uart_port *port)
2302 struct platform_device *pdev = to_platform_device(port->dev);
2303 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2305 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2308 if (port->flags & UPF_IOREMAP) {
2309 port->membase = ioremap(port->mapbase, size);
2310 if (port->membase == NULL) {
2311 release_mem_region(port->mapbase, size);
2320 * Configure/autoconfigure the port.
2322 static void atmel_config_port(struct uart_port *port, int flags)
2324 if (flags & UART_CONFIG_TYPE) {
2325 port->type = PORT_ATMEL;
2326 atmel_request_port(port);
2331 * Verify the new serial_struct (for TIOCSSERIAL).
2333 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2336 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2338 if (port->irq != ser->irq)
2340 if (ser->io_type != SERIAL_IO_MEM)
2342 if (port->uartclk / 16 != ser->baud_base)
2344 if (port->mapbase != (unsigned long)ser->iomem_base)
2346 if (port->iobase != ser->port)
2353 #ifdef CONFIG_CONSOLE_POLL
2354 static int atmel_poll_get_char(struct uart_port *port)
2356 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2359 return atmel_uart_read_char(port);
2362 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2364 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2367 atmel_uart_write_char(port, ch);
2371 static const struct uart_ops atmel_pops = {
2372 .tx_empty = atmel_tx_empty,
2373 .set_mctrl = atmel_set_mctrl,
2374 .get_mctrl = atmel_get_mctrl,
2375 .stop_tx = atmel_stop_tx,
2376 .start_tx = atmel_start_tx,
2377 .stop_rx = atmel_stop_rx,
2378 .enable_ms = atmel_enable_ms,
2379 .break_ctl = atmel_break_ctl,
2380 .startup = atmel_startup,
2381 .shutdown = atmel_shutdown,
2382 .flush_buffer = atmel_flush_buffer,
2383 .set_termios = atmel_set_termios,
2384 .set_ldisc = atmel_set_ldisc,
2386 .release_port = atmel_release_port,
2387 .request_port = atmel_request_port,
2388 .config_port = atmel_config_port,
2389 .verify_port = atmel_verify_port,
2390 .pm = atmel_serial_pm,
2391 #ifdef CONFIG_CONSOLE_POLL
2392 .poll_get_char = atmel_poll_get_char,
2393 .poll_put_char = atmel_poll_put_char,
2398 * Configure the port from the platform device resource info.
2400 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2401 struct platform_device *pdev)
2404 struct uart_port *port = &atmel_port->uart;
2405 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2407 atmel_init_property(atmel_port, pdev);
2408 atmel_set_ops(port);
2410 atmel_init_rs485(port, pdev);
2412 port->iotype = UPIO_MEM;
2413 port->flags = UPF_BOOT_AUTOCONF;
2414 port->ops = &atmel_pops;
2416 port->dev = &pdev->dev;
2417 port->mapbase = pdev->resource[0].start;
2418 port->irq = pdev->resource[1].start;
2419 port->rs485_config = atmel_config_rs485;
2421 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2423 if (pdata && pdata->regs) {
2424 /* Already mapped by setup code */
2425 port->membase = pdata->regs;
2427 port->flags |= UPF_IOREMAP;
2428 port->membase = NULL;
2431 /* for console, the clock could already be configured */
2432 if (!atmel_port->clk) {
2433 atmel_port->clk = clk_get(&pdev->dev, "usart");
2434 if (IS_ERR(atmel_port->clk)) {
2435 ret = PTR_ERR(atmel_port->clk);
2436 atmel_port->clk = NULL;
2439 ret = clk_prepare_enable(atmel_port->clk);
2441 clk_put(atmel_port->clk);
2442 atmel_port->clk = NULL;
2445 port->uartclk = clk_get_rate(atmel_port->clk);
2446 clk_disable_unprepare(atmel_port->clk);
2447 /* only enable clock when USART is in use */
2450 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2451 if (port->rs485.flags & SER_RS485_ENABLED)
2452 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2453 else if (atmel_use_pdc_tx(port)) {
2454 port->fifosize = PDC_BUFFER_SIZE;
2455 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2457 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2463 struct platform_device *atmel_default_console_device; /* the serial console device */
2465 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2466 static void atmel_console_putchar(struct uart_port *port, int ch)
2468 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2470 atmel_uart_write_char(port, ch);
2474 * Interrupts are disabled on entering
2476 static void atmel_console_write(struct console *co, const char *s, u_int count)
2478 struct uart_port *port = &atmel_ports[co->index].uart;
2479 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2480 unsigned int status, imr;
2481 unsigned int pdc_tx;
2484 * First, save IMR and then disable interrupts
2486 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2487 atmel_uart_writel(port, ATMEL_US_IDR,
2488 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2490 /* Store PDC transmit status and disable it */
2491 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2492 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2494 /* Make sure that tx path is actually able to send characters */
2495 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2497 uart_console_write(port, s, count, atmel_console_putchar);
2500 * Finally, wait for transmitter to become empty
2504 status = atmel_uart_readl(port, ATMEL_US_CSR);
2505 } while (!(status & ATMEL_US_TXRDY));
2507 /* Restore PDC transmit status */
2509 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2511 /* set interrupts back the way they were */
2512 atmel_uart_writel(port, ATMEL_US_IER, imr);
2516 * If the port was already initialised (eg, by a boot loader),
2517 * try to determine the current setup.
2519 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2520 int *parity, int *bits)
2522 unsigned int mr, quot;
2525 * If the baud rate generator isn't running, the port wasn't
2526 * initialized by the boot loader.
2528 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2532 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2533 if (mr == ATMEL_US_CHRL_8)
2538 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2539 if (mr == ATMEL_US_PAR_EVEN)
2541 else if (mr == ATMEL_US_PAR_ODD)
2545 * The serial core only rounds down when matching this to a
2546 * supported baud rate. Make sure we don't end up slightly
2547 * lower than one of those, as it would make us fall through
2548 * to a much lower baud rate than we really want.
2550 *baud = port->uartclk / (16 * (quot - 1));
2553 static int __init atmel_console_setup(struct console *co, char *options)
2556 struct uart_port *port = &atmel_ports[co->index].uart;
2562 if (port->membase == NULL) {
2563 /* Port not initialized yet - delay setup */
2567 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2571 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2572 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2573 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2576 uart_parse_options(options, &baud, &parity, &bits, &flow);
2578 atmel_console_get_options(port, &baud, &parity, &bits);
2580 return uart_set_options(port, co, baud, parity, bits, flow);
2583 static struct uart_driver atmel_uart;
2585 static struct console atmel_console = {
2586 .name = ATMEL_DEVICENAME,
2587 .write = atmel_console_write,
2588 .device = uart_console_device,
2589 .setup = atmel_console_setup,
2590 .flags = CON_PRINTBUFFER,
2592 .data = &atmel_uart,
2595 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2598 * Early console initialization (before VM subsystem initialized).
2600 static int __init atmel_console_init(void)
2603 if (atmel_default_console_device) {
2604 struct atmel_uart_data *pdata =
2605 dev_get_platdata(&atmel_default_console_device->dev);
2606 int id = pdata->num;
2607 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2609 atmel_port->backup_imr = 0;
2610 atmel_port->uart.line = id;
2612 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2613 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2616 register_console(&atmel_console);
2622 console_initcall(atmel_console_init);
2625 * Late console initialization.
2627 static int __init atmel_late_console_init(void)
2629 if (atmel_default_console_device
2630 && !(atmel_console.flags & CON_ENABLED))
2631 register_console(&atmel_console);
2636 core_initcall(atmel_late_console_init);
2638 static inline bool atmel_is_console_port(struct uart_port *port)
2640 return port->cons && port->cons->index == port->line;
2644 #define ATMEL_CONSOLE_DEVICE NULL
2646 static inline bool atmel_is_console_port(struct uart_port *port)
2652 static struct uart_driver atmel_uart = {
2653 .owner = THIS_MODULE,
2654 .driver_name = "atmel_serial",
2655 .dev_name = ATMEL_DEVICENAME,
2656 .major = SERIAL_ATMEL_MAJOR,
2657 .minor = MINOR_START,
2658 .nr = ATMEL_MAX_UART,
2659 .cons = ATMEL_CONSOLE_DEVICE,
2663 static bool atmel_serial_clk_will_stop(void)
2665 #ifdef CONFIG_ARCH_AT91
2666 return at91_suspend_entering_slow_clock();
2672 static int atmel_serial_suspend(struct platform_device *pdev,
2675 struct uart_port *port = platform_get_drvdata(pdev);
2676 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2678 if (atmel_is_console_port(port) && console_suspend_enabled) {
2679 /* Drain the TX shifter */
2680 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2685 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2686 /* Cache register values as we won't get a full shutdown/startup
2689 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2690 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2691 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2692 atmel_port->cache.rtor = atmel_uart_readl(port,
2694 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2695 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2696 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2699 /* we can not wake up if we're running on slow clock */
2700 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2701 if (atmel_serial_clk_will_stop()) {
2702 unsigned long flags;
2704 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2705 atmel_port->suspended = true;
2706 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2707 device_set_wakeup_enable(&pdev->dev, 0);
2710 uart_suspend_port(&atmel_uart, port);
2715 static int atmel_serial_resume(struct platform_device *pdev)
2717 struct uart_port *port = platform_get_drvdata(pdev);
2718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2719 unsigned long flags;
2721 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2722 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2723 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2724 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2725 atmel_uart_writel(port, atmel_port->rtor,
2726 atmel_port->cache.rtor);
2727 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2729 if (atmel_port->fifo_size) {
2730 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2731 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2732 atmel_uart_writel(port, ATMEL_US_FMR,
2733 atmel_port->cache.fmr);
2734 atmel_uart_writel(port, ATMEL_US_FIER,
2735 atmel_port->cache.fimr);
2737 atmel_start_rx(port);
2740 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2741 if (atmel_port->pending) {
2742 atmel_handle_receive(port, atmel_port->pending);
2743 atmel_handle_status(port, atmel_port->pending,
2744 atmel_port->pending_status);
2745 atmel_handle_transmit(port, atmel_port->pending);
2746 atmel_port->pending = 0;
2748 atmel_port->suspended = false;
2749 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2751 uart_resume_port(&atmel_uart, port);
2752 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2757 #define atmel_serial_suspend NULL
2758 #define atmel_serial_resume NULL
2761 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2762 struct platform_device *pdev)
2764 atmel_port->fifo_size = 0;
2765 atmel_port->rts_low = 0;
2766 atmel_port->rts_high = 0;
2768 if (of_property_read_u32(pdev->dev.of_node,
2770 &atmel_port->fifo_size))
2773 if (!atmel_port->fifo_size)
2776 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2777 atmel_port->fifo_size = 0;
2778 dev_err(&pdev->dev, "Invalid FIFO size\n");
2783 * 0 <= rts_low <= rts_high <= fifo_size
2784 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2785 * to flush their internal TX FIFO, commonly up to 16 data, before
2786 * actually stopping to send new data. So we try to set the RTS High
2787 * Threshold to a reasonably high value respecting this 16 data
2788 * empirical rule when possible.
2790 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2791 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2792 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2793 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2795 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2796 atmel_port->fifo_size);
2797 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2798 atmel_port->rts_high);
2799 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2800 atmel_port->rts_low);
2803 static int atmel_serial_probe(struct platform_device *pdev)
2805 struct atmel_uart_port *atmel_port;
2806 struct device_node *np = pdev->dev.of_node;
2807 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2812 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2815 ret = of_alias_get_id(np, "serial");
2821 /* port id not found in platform data nor device-tree aliases:
2822 * auto-enumerate it */
2823 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2825 if (ret >= ATMEL_MAX_UART) {
2830 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2831 /* port already in use */
2836 atmel_port = &atmel_ports[ret];
2837 atmel_port->backup_imr = 0;
2838 atmel_port->uart.line = ret;
2839 atmel_serial_probe_fifos(atmel_port, pdev);
2841 atomic_set(&atmel_port->tasklet_shutdown, 0);
2842 spin_lock_init(&atmel_port->lock_suspended);
2844 ret = atmel_init_port(atmel_port, pdev);
2848 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2849 if (IS_ERR(atmel_port->gpios)) {
2850 ret = PTR_ERR(atmel_port->gpios);
2854 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2856 data = kmalloc(sizeof(struct atmel_uart_char)
2857 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2859 goto err_alloc_ring;
2860 atmel_port->rx_ring.buf = data;
2863 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2865 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2869 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2870 if (atmel_is_console_port(&atmel_port->uart)
2871 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2873 * The serial core enabled the clock for us, so undo
2874 * the clk_prepare_enable() in atmel_console_setup()
2876 clk_disable_unprepare(atmel_port->clk);
2880 device_init_wakeup(&pdev->dev, 1);
2881 platform_set_drvdata(pdev, atmel_port);
2884 * The peripheral clock has been disabled by atmel_init_port():
2885 * enable it before accessing I/O registers
2887 clk_prepare_enable(atmel_port->clk);
2889 if (rs485_enabled) {
2890 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2891 ATMEL_US_USMODE_NORMAL);
2892 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2897 * Get port name of usart or uart
2899 atmel_get_ip_name(&atmel_port->uart);
2902 * The peripheral clock can now safely be disabled till the port
2905 clk_disable_unprepare(atmel_port->clk);
2910 kfree(atmel_port->rx_ring.buf);
2911 atmel_port->rx_ring.buf = NULL;
2913 if (!atmel_is_console_port(&atmel_port->uart)) {
2914 clk_put(atmel_port->clk);
2915 atmel_port->clk = NULL;
2918 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2924 * Even if the driver is not modular, it makes sense to be able to
2925 * unbind a device: there can be many bound devices, and there are
2926 * situations where dynamic binding and unbinding can be useful.
2928 * For example, a connected device can require a specific firmware update
2929 * protocol that needs bitbanging on IO lines, but use the regular serial
2930 * port in the normal case.
2932 static int atmel_serial_remove(struct platform_device *pdev)
2934 struct uart_port *port = platform_get_drvdata(pdev);
2935 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2938 tasklet_kill(&atmel_port->tasklet_rx);
2939 tasklet_kill(&atmel_port->tasklet_tx);
2941 device_init_wakeup(&pdev->dev, 0);
2943 ret = uart_remove_one_port(&atmel_uart, port);
2945 kfree(atmel_port->rx_ring.buf);
2947 /* "port" is allocated statically, so we shouldn't free it */
2949 clear_bit(port->line, atmel_ports_in_use);
2951 clk_put(atmel_port->clk);
2952 atmel_port->clk = NULL;
2957 static struct platform_driver atmel_serial_driver = {
2958 .probe = atmel_serial_probe,
2959 .remove = atmel_serial_remove,
2960 .suspend = atmel_serial_suspend,
2961 .resume = atmel_serial_resume,
2963 .name = "atmel_usart",
2964 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2968 static int __init atmel_serial_init(void)
2972 ret = uart_register_driver(&atmel_uart);
2976 ret = platform_driver_register(&atmel_serial_driver);
2978 uart_unregister_driver(&atmel_uart);
2982 device_initcall(atmel_serial_init);