2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
117 #define ATMEL_SERIAL_RINGSIZE 1024
120 * at91: 6 USARTs and one DBGU port (SAM9260)
123 #define ATMEL_MAX_UART 7
126 * We wrap our port structure around the generic uart_port.
128 struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 unsigned int irq_status_prev;
159 struct circ_buf rx_ring;
161 struct mctrl_gpios *gpios;
162 unsigned int tx_done_mask;
167 u32 rtor; /* address of receiver timeout register if it exists */
169 struct timer_list uart_timer;
172 unsigned int pending;
173 unsigned int pending_status;
174 spinlock_t lock_suspended;
176 int (*prepare_rx)(struct uart_port *port);
177 int (*prepare_tx)(struct uart_port *port);
178 void (*schedule_rx)(struct uart_port *port);
179 void (*schedule_tx)(struct uart_port *port);
180 void (*release_rx)(struct uart_port *port);
181 void (*release_tx)(struct uart_port *port);
184 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
185 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
188 static struct console atmel_console;
191 #if defined(CONFIG_OF)
192 static const struct of_device_id atmel_serial_dt_ids[] = {
193 { .compatible = "atmel,at91rm9200-usart" },
194 { .compatible = "atmel,at91sam9260-usart" },
199 static inline struct atmel_uart_port *
200 to_atmel_uart_port(struct uart_port *uart)
202 return container_of(uart, struct atmel_uart_port, uart);
205 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207 return __raw_readl(port->membase + reg);
210 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212 __raw_writel(value, port->membase + reg);
217 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
218 static inline u8 atmel_uart_read_char(struct uart_port *port)
220 return __raw_readl(port->membase + ATMEL_US_RHR);
223 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
225 __raw_writel(value, port->membase + ATMEL_US_THR);
230 static inline u8 atmel_uart_read_char(struct uart_port *port)
232 return __raw_readb(port->membase + ATMEL_US_RHR);
235 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
237 __raw_writeb(value, port->membase + ATMEL_US_THR);
242 #ifdef CONFIG_SERIAL_ATMEL_PDC
243 static bool atmel_use_pdc_rx(struct uart_port *port)
245 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
247 return atmel_port->use_pdc_rx;
250 static bool atmel_use_pdc_tx(struct uart_port *port)
252 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
254 return atmel_port->use_pdc_tx;
257 static bool atmel_use_pdc_rx(struct uart_port *port)
262 static bool atmel_use_pdc_tx(struct uart_port *port)
268 static bool atmel_use_dma_tx(struct uart_port *port)
270 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272 return atmel_port->use_dma_tx;
275 static bool atmel_use_dma_rx(struct uart_port *port)
277 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279 return atmel_port->use_dma_rx;
282 static bool atmel_use_fifo(struct uart_port *port)
284 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
286 return atmel_port->fifo_size;
289 static unsigned int atmel_get_lines_status(struct uart_port *port)
291 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
292 unsigned int status, ret = 0;
294 status = atmel_uart_readl(port, ATMEL_US_CSR);
296 mctrl_gpio_get(atmel_port->gpios, &ret);
298 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
301 status &= ~ATMEL_US_CTS;
303 status |= ATMEL_US_CTS;
306 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
309 status &= ~ATMEL_US_DSR;
311 status |= ATMEL_US_DSR;
314 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
317 status &= ~ATMEL_US_RI;
319 status |= ATMEL_US_RI;
322 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
325 status &= ~ATMEL_US_DCD;
327 status |= ATMEL_US_DCD;
333 /* Enable or disable the rs485 support */
334 static int atmel_config_rs485(struct uart_port *port,
335 struct serial_rs485 *rs485conf)
337 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
340 /* Disable interrupts */
341 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
343 mode = atmel_uart_readl(port, ATMEL_US_MR);
345 /* Resetting serial mode to RS232 (0x0) */
346 mode &= ~ATMEL_US_USMODE;
348 port->rs485 = *rs485conf;
350 if (rs485conf->flags & SER_RS485_ENABLED) {
351 dev_dbg(port->dev, "Setting UART to RS485\n");
352 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
353 atmel_uart_writel(port, ATMEL_US_TTGR,
354 rs485conf->delay_rts_after_send);
355 mode |= ATMEL_US_USMODE_RS485;
357 dev_dbg(port->dev, "Setting UART to RS232\n");
358 if (atmel_use_pdc_tx(port))
359 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
362 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
364 atmel_uart_writel(port, ATMEL_US_MR, mode);
366 /* Enable interrupts */
367 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
373 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
375 static u_int atmel_tx_empty(struct uart_port *port)
377 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
383 * Set state of the modem control output lines
385 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
387 unsigned int control = 0;
388 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
389 unsigned int rts_paused, rts_ready;
390 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
392 /* override mode to RS485 if needed, otherwise keep the current mode */
393 if (port->rs485.flags & SER_RS485_ENABLED) {
394 atmel_uart_writel(port, ATMEL_US_TTGR,
395 port->rs485.delay_rts_after_send);
396 mode &= ~ATMEL_US_USMODE;
397 mode |= ATMEL_US_USMODE_RS485;
400 /* set the RTS line state according to the mode */
401 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
402 /* force RTS line to high level */
403 rts_paused = ATMEL_US_RTSEN;
405 /* give the control of the RTS line back to the hardware */
406 rts_ready = ATMEL_US_RTSDIS;
408 /* force RTS line to high level */
409 rts_paused = ATMEL_US_RTSDIS;
411 /* force RTS line to low level */
412 rts_ready = ATMEL_US_RTSEN;
415 if (mctrl & TIOCM_RTS)
416 control |= rts_ready;
418 control |= rts_paused;
420 if (mctrl & TIOCM_DTR)
421 control |= ATMEL_US_DTREN;
423 control |= ATMEL_US_DTRDIS;
425 atmel_uart_writel(port, ATMEL_US_CR, control);
427 mctrl_gpio_set(atmel_port->gpios, mctrl);
429 /* Local loopback mode? */
430 mode &= ~ATMEL_US_CHMODE;
431 if (mctrl & TIOCM_LOOP)
432 mode |= ATMEL_US_CHMODE_LOC_LOOP;
434 mode |= ATMEL_US_CHMODE_NORMAL;
436 atmel_uart_writel(port, ATMEL_US_MR, mode);
440 * Get state of the modem control input lines
442 static u_int atmel_get_mctrl(struct uart_port *port)
444 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
445 unsigned int ret = 0, status;
447 status = atmel_uart_readl(port, ATMEL_US_CSR);
450 * The control signals are active low.
452 if (!(status & ATMEL_US_DCD))
454 if (!(status & ATMEL_US_CTS))
456 if (!(status & ATMEL_US_DSR))
458 if (!(status & ATMEL_US_RI))
461 return mctrl_gpio_get(atmel_port->gpios, &ret);
467 static void atmel_stop_tx(struct uart_port *port)
469 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
471 if (atmel_use_pdc_tx(port)) {
472 /* disable PDC transmit */
473 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
475 /* Disable interrupts */
476 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
478 if ((port->rs485.flags & SER_RS485_ENABLED) &&
479 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
480 atmel_start_rx(port);
484 * Start transmitting.
486 static void atmel_start_tx(struct uart_port *port)
488 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
490 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
492 /* The transmitter is already running. Yes, we
496 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
497 if ((port->rs485.flags & SER_RS485_ENABLED) &&
498 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
501 if (atmel_use_pdc_tx(port))
502 /* re-enable PDC transmit */
503 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
505 /* Enable interrupts */
506 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
510 * start receiving - port is in process of being opened.
512 static void atmel_start_rx(struct uart_port *port)
514 /* reset status and receiver */
515 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
517 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
519 if (atmel_use_pdc_rx(port)) {
520 /* enable PDC controller */
521 atmel_uart_writel(port, ATMEL_US_IER,
522 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
523 port->read_status_mask);
524 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
526 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
531 * Stop receiving - port is in process of being closed.
533 static void atmel_stop_rx(struct uart_port *port)
535 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
537 if (atmel_use_pdc_rx(port)) {
538 /* disable PDC receive */
539 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
540 atmel_uart_writel(port, ATMEL_US_IDR,
541 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
542 port->read_status_mask);
544 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
549 * Enable modem status interrupts
551 static void atmel_enable_ms(struct uart_port *port)
553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
557 * Interrupt should not be enabled twice
559 if (atmel_port->ms_irq_enabled)
562 atmel_port->ms_irq_enabled = true;
564 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
565 ier |= ATMEL_US_CTSIC;
567 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
568 ier |= ATMEL_US_DSRIC;
570 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
571 ier |= ATMEL_US_RIIC;
573 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
574 ier |= ATMEL_US_DCDIC;
576 atmel_uart_writel(port, ATMEL_US_IER, ier);
578 mctrl_gpio_enable_ms(atmel_port->gpios);
582 * Disable modem status interrupts
584 static void atmel_disable_ms(struct uart_port *port)
586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
590 * Interrupt should not be disabled twice
592 if (!atmel_port->ms_irq_enabled)
595 atmel_port->ms_irq_enabled = false;
597 mctrl_gpio_disable_ms(atmel_port->gpios);
599 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
600 idr |= ATMEL_US_CTSIC;
602 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
603 idr |= ATMEL_US_DSRIC;
605 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
606 idr |= ATMEL_US_RIIC;
608 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
609 idr |= ATMEL_US_DCDIC;
611 atmel_uart_writel(port, ATMEL_US_IDR, idr);
615 * Control the transmission of a break signal
617 static void atmel_break_ctl(struct uart_port *port, int break_state)
619 if (break_state != 0)
621 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
624 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
628 * Stores the incoming character in the ring buffer
631 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
634 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
635 struct circ_buf *ring = &atmel_port->rx_ring;
636 struct atmel_uart_char *c;
638 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
639 /* Buffer overflow, ignore char */
642 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
646 /* Make sure the character is stored before we update head. */
649 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
653 * Deal with parity, framing and overrun errors.
655 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
658 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
660 if (status & ATMEL_US_RXBRK) {
661 /* ignore side-effect */
662 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
665 if (status & ATMEL_US_PARE)
666 port->icount.parity++;
667 if (status & ATMEL_US_FRAME)
668 port->icount.frame++;
669 if (status & ATMEL_US_OVRE)
670 port->icount.overrun++;
674 * Characters received (called from interrupt handler)
676 static void atmel_rx_chars(struct uart_port *port)
678 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
679 unsigned int status, ch;
681 status = atmel_uart_readl(port, ATMEL_US_CSR);
682 while (status & ATMEL_US_RXRDY) {
683 ch = atmel_uart_read_char(port);
686 * note that the error handling code is
687 * out of the main execution path
689 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
690 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
691 || atmel_port->break_active)) {
694 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
696 if (status & ATMEL_US_RXBRK
697 && !atmel_port->break_active) {
698 atmel_port->break_active = 1;
699 atmel_uart_writel(port, ATMEL_US_IER,
703 * This is either the end-of-break
704 * condition or we've received at
705 * least one character without RXBRK
706 * being set. In both cases, the next
707 * RXBRK will indicate start-of-break.
709 atmel_uart_writel(port, ATMEL_US_IDR,
711 status &= ~ATMEL_US_RXBRK;
712 atmel_port->break_active = 0;
716 atmel_buffer_rx_char(port, status, ch);
717 status = atmel_uart_readl(port, ATMEL_US_CSR);
720 tasklet_schedule(&atmel_port->tasklet_rx);
724 * Transmit characters (called from tasklet with TXRDY interrupt
727 static void atmel_tx_chars(struct uart_port *port)
729 struct circ_buf *xmit = &port->state->xmit;
730 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
733 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
734 atmel_uart_write_char(port, port->x_char);
738 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
741 while (atmel_uart_readl(port, ATMEL_US_CSR) &
742 atmel_port->tx_done_mask) {
743 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
744 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
746 if (uart_circ_empty(xmit))
750 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
751 uart_write_wakeup(port);
753 if (!uart_circ_empty(xmit))
754 /* Enable interrupts */
755 atmel_uart_writel(port, ATMEL_US_IER,
756 atmel_port->tx_done_mask);
759 static void atmel_complete_tx_dma(void *arg)
761 struct atmel_uart_port *atmel_port = arg;
762 struct uart_port *port = &atmel_port->uart;
763 struct circ_buf *xmit = &port->state->xmit;
764 struct dma_chan *chan = atmel_port->chan_tx;
767 spin_lock_irqsave(&port->lock, flags);
770 dmaengine_terminate_all(chan);
771 xmit->tail += atmel_port->tx_len;
772 xmit->tail &= UART_XMIT_SIZE - 1;
774 port->icount.tx += atmel_port->tx_len;
776 spin_lock_irq(&atmel_port->lock_tx);
777 async_tx_ack(atmel_port->desc_tx);
778 atmel_port->cookie_tx = -EINVAL;
779 atmel_port->desc_tx = NULL;
780 spin_unlock_irq(&atmel_port->lock_tx);
782 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
783 uart_write_wakeup(port);
786 * xmit is a circular buffer so, if we have just send data from
787 * xmit->tail to the end of xmit->buf, now we have to transmit the
788 * remaining data from the beginning of xmit->buf to xmit->head.
790 if (!uart_circ_empty(xmit))
791 tasklet_schedule(&atmel_port->tasklet_tx);
793 spin_unlock_irqrestore(&port->lock, flags);
796 static void atmel_release_tx_dma(struct uart_port *port)
798 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
799 struct dma_chan *chan = atmel_port->chan_tx;
802 dmaengine_terminate_all(chan);
803 dma_release_channel(chan);
804 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
808 atmel_port->desc_tx = NULL;
809 atmel_port->chan_tx = NULL;
810 atmel_port->cookie_tx = -EINVAL;
814 * Called from tasklet with TXRDY interrupt is disabled.
816 static void atmel_tx_dma(struct uart_port *port)
818 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
819 struct circ_buf *xmit = &port->state->xmit;
820 struct dma_chan *chan = atmel_port->chan_tx;
821 struct dma_async_tx_descriptor *desc;
822 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
823 unsigned int tx_len, part1_len, part2_len, sg_len;
824 dma_addr_t phys_addr;
826 /* Make sure we have an idle channel */
827 if (atmel_port->desc_tx != NULL)
830 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
833 * Port xmit buffer is already mapped,
834 * and it is one page... Just adjust
835 * offsets and lengths. Since it is a circular buffer,
836 * we have to transmit till the end, and then the rest.
837 * Take the port lock to get a
838 * consistent xmit buffer state.
840 tx_len = CIRC_CNT_TO_END(xmit->head,
844 if (atmel_port->fifo_size) {
845 /* multi data mode */
846 part1_len = (tx_len & ~0x3); /* DWORD access */
847 part2_len = (tx_len & 0x3); /* BYTE access */
849 /* single data (legacy) mode */
851 part2_len = tx_len; /* BYTE access only */
854 sg_init_table(sgl, 2);
856 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
859 sg_dma_address(sg) = phys_addr;
860 sg_dma_len(sg) = part1_len;
862 phys_addr += part1_len;
867 sg_dma_address(sg) = phys_addr;
868 sg_dma_len(sg) = part2_len;
872 * save tx_len so atmel_complete_tx_dma() will increase
873 * xmit->tail correctly
875 atmel_port->tx_len = tx_len;
877 desc = dmaengine_prep_slave_sg(chan,
884 dev_err(port->dev, "Failed to send via dma!\n");
888 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
890 atmel_port->desc_tx = desc;
891 desc->callback = atmel_complete_tx_dma;
892 desc->callback_param = atmel_port;
893 atmel_port->cookie_tx = dmaengine_submit(desc);
896 if (port->rs485.flags & SER_RS485_ENABLED) {
897 /* DMA done, stop TX, start RX for RS485 */
898 atmel_start_rx(port);
902 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
903 uart_write_wakeup(port);
906 static int atmel_prepare_tx_dma(struct uart_port *port)
908 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
910 struct dma_slave_config config;
914 dma_cap_set(DMA_SLAVE, mask);
916 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
917 if (atmel_port->chan_tx == NULL)
919 dev_info(port->dev, "using %s for tx DMA transfers\n",
920 dma_chan_name(atmel_port->chan_tx));
922 spin_lock_init(&atmel_port->lock_tx);
923 sg_init_table(&atmel_port->sg_tx, 1);
924 /* UART circular tx buffer is an aligned page. */
925 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
926 sg_set_page(&atmel_port->sg_tx,
927 virt_to_page(port->state->xmit.buf),
929 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
930 nent = dma_map_sg(port->dev,
936 dev_dbg(port->dev, "need to release resource of dma\n");
939 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
940 sg_dma_len(&atmel_port->sg_tx),
941 port->state->xmit.buf,
942 &sg_dma_address(&atmel_port->sg_tx));
945 /* Configure the slave DMA */
946 memset(&config, 0, sizeof(config));
947 config.direction = DMA_MEM_TO_DEV;
948 config.dst_addr_width = (atmel_port->fifo_size) ?
949 DMA_SLAVE_BUSWIDTH_4_BYTES :
950 DMA_SLAVE_BUSWIDTH_1_BYTE;
951 config.dst_addr = port->mapbase + ATMEL_US_THR;
952 config.dst_maxburst = 1;
954 ret = dmaengine_slave_config(atmel_port->chan_tx,
957 dev_err(port->dev, "DMA tx slave configuration failed\n");
964 dev_err(port->dev, "TX channel not available, switch to pio\n");
965 atmel_port->use_dma_tx = 0;
966 if (atmel_port->chan_tx)
967 atmel_release_tx_dma(port);
971 static void atmel_complete_rx_dma(void *arg)
973 struct uart_port *port = arg;
974 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
976 tasklet_schedule(&atmel_port->tasklet_rx);
979 static void atmel_release_rx_dma(struct uart_port *port)
981 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
982 struct dma_chan *chan = atmel_port->chan_rx;
985 dmaengine_terminate_all(chan);
986 dma_release_channel(chan);
987 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
991 atmel_port->desc_rx = NULL;
992 atmel_port->chan_rx = NULL;
993 atmel_port->cookie_rx = -EINVAL;
996 static void atmel_rx_from_dma(struct uart_port *port)
998 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
999 struct tty_port *tport = &port->state->port;
1000 struct circ_buf *ring = &atmel_port->rx_ring;
1001 struct dma_chan *chan = atmel_port->chan_rx;
1002 struct dma_tx_state state;
1003 enum dma_status dmastat;
1007 /* Reset the UART timeout early so that we don't miss one */
1008 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1009 dmastat = dmaengine_tx_status(chan,
1010 atmel_port->cookie_rx,
1012 /* Restart a new tasklet if DMA status is error */
1013 if (dmastat == DMA_ERROR) {
1014 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1015 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1016 tasklet_schedule(&atmel_port->tasklet_rx);
1020 /* CPU claims ownership of RX DMA buffer */
1021 dma_sync_sg_for_cpu(port->dev,
1027 * ring->head points to the end of data already written by the DMA.
1028 * ring->tail points to the beginning of data to be read by the
1030 * The current transfer size should not be larger than the dma buffer
1033 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1034 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1036 * At this point ring->head may point to the first byte right after the
1037 * last byte of the dma buffer:
1038 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1040 * However ring->tail must always points inside the dma buffer:
1041 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1043 * Since we use a ring buffer, we have to handle the case
1044 * where head is lower than tail. In such a case, we first read from
1045 * tail to the end of the buffer then reset tail.
1047 if (ring->head < ring->tail) {
1048 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1050 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1052 port->icount.rx += count;
1055 /* Finally we read data from tail to head */
1056 if (ring->tail < ring->head) {
1057 count = ring->head - ring->tail;
1059 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1060 /* Wrap ring->head if needed */
1061 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1063 ring->tail = ring->head;
1064 port->icount.rx += count;
1067 /* USART retreives ownership of RX DMA buffer */
1068 dma_sync_sg_for_device(port->dev,
1074 * Drop the lock here since it might end up calling
1075 * uart_start(), which takes the lock.
1077 spin_unlock(&port->lock);
1078 tty_flip_buffer_push(tport);
1079 spin_lock(&port->lock);
1081 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1084 static int atmel_prepare_rx_dma(struct uart_port *port)
1086 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1087 struct dma_async_tx_descriptor *desc;
1088 dma_cap_mask_t mask;
1089 struct dma_slave_config config;
1090 struct circ_buf *ring;
1093 ring = &atmel_port->rx_ring;
1096 dma_cap_set(DMA_CYCLIC, mask);
1098 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1099 if (atmel_port->chan_rx == NULL)
1101 dev_info(port->dev, "using %s for rx DMA transfers\n",
1102 dma_chan_name(atmel_port->chan_rx));
1104 spin_lock_init(&atmel_port->lock_rx);
1105 sg_init_table(&atmel_port->sg_rx, 1);
1106 /* UART circular rx buffer is an aligned page. */
1107 BUG_ON(!PAGE_ALIGNED(ring->buf));
1108 sg_set_page(&atmel_port->sg_rx,
1109 virt_to_page(ring->buf),
1110 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1111 (unsigned long)ring->buf & ~PAGE_MASK);
1112 nent = dma_map_sg(port->dev,
1118 dev_dbg(port->dev, "need to release resource of dma\n");
1121 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1122 sg_dma_len(&atmel_port->sg_rx),
1124 &sg_dma_address(&atmel_port->sg_rx));
1127 /* Configure the slave DMA */
1128 memset(&config, 0, sizeof(config));
1129 config.direction = DMA_DEV_TO_MEM;
1130 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1131 config.src_addr = port->mapbase + ATMEL_US_RHR;
1132 config.src_maxburst = 1;
1134 ret = dmaengine_slave_config(atmel_port->chan_rx,
1137 dev_err(port->dev, "DMA rx slave configuration failed\n");
1141 * Prepare a cyclic dma transfer, assign 2 descriptors,
1142 * each one is half ring buffer size
1144 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1145 sg_dma_address(&atmel_port->sg_rx),
1146 sg_dma_len(&atmel_port->sg_rx),
1147 sg_dma_len(&atmel_port->sg_rx)/2,
1149 DMA_PREP_INTERRUPT);
1150 desc->callback = atmel_complete_rx_dma;
1151 desc->callback_param = port;
1152 atmel_port->desc_rx = desc;
1153 atmel_port->cookie_rx = dmaengine_submit(desc);
1158 dev_err(port->dev, "RX channel not available, switch to pio\n");
1159 atmel_port->use_dma_rx = 0;
1160 if (atmel_port->chan_rx)
1161 atmel_release_rx_dma(port);
1165 static void atmel_uart_timer_callback(unsigned long data)
1167 struct uart_port *port = (void *)data;
1168 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1170 tasklet_schedule(&atmel_port->tasklet_rx);
1171 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1175 * receive interrupt handler.
1178 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1180 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1182 if (atmel_use_pdc_rx(port)) {
1184 * PDC receive. Just schedule the tasklet and let it
1185 * figure out the details.
1187 * TODO: We're not handling error flags correctly at
1190 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1191 atmel_uart_writel(port, ATMEL_US_IDR,
1192 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1193 tasklet_schedule(&atmel_port->tasklet_rx);
1196 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1197 ATMEL_US_FRAME | ATMEL_US_PARE))
1198 atmel_pdc_rxerr(port, pending);
1201 if (atmel_use_dma_rx(port)) {
1202 if (pending & ATMEL_US_TIMEOUT) {
1203 atmel_uart_writel(port, ATMEL_US_IDR,
1205 tasklet_schedule(&atmel_port->tasklet_rx);
1209 /* Interrupt receive */
1210 if (pending & ATMEL_US_RXRDY)
1211 atmel_rx_chars(port);
1212 else if (pending & ATMEL_US_RXBRK) {
1214 * End of break detected. If it came along with a
1215 * character, atmel_rx_chars will handle it.
1217 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1218 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1219 atmel_port->break_active = 0;
1224 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1227 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1229 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1231 if (pending & atmel_port->tx_done_mask) {
1232 /* Either PDC or interrupt transmission */
1233 atmel_uart_writel(port, ATMEL_US_IDR,
1234 atmel_port->tx_done_mask);
1235 tasklet_schedule(&atmel_port->tasklet_tx);
1240 * status flags interrupt handler.
1243 atmel_handle_status(struct uart_port *port, unsigned int pending,
1244 unsigned int status)
1246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1247 unsigned int status_change;
1249 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1250 | ATMEL_US_CTSIC)) {
1251 status_change = status ^ atmel_port->irq_status_prev;
1252 atmel_port->irq_status_prev = status;
1254 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1255 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1256 /* TODO: All reads to CSR will clear these interrupts! */
1257 if (status_change & ATMEL_US_RI)
1259 if (status_change & ATMEL_US_DSR)
1261 if (status_change & ATMEL_US_DCD)
1262 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1263 if (status_change & ATMEL_US_CTS)
1264 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1266 wake_up_interruptible(&port->state->port.delta_msr_wait);
1274 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1276 struct uart_port *port = dev_id;
1277 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1278 unsigned int status, pending, mask, pass_counter = 0;
1280 spin_lock(&atmel_port->lock_suspended);
1283 status = atmel_get_lines_status(port);
1284 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1285 pending = status & mask;
1289 if (atmel_port->suspended) {
1290 atmel_port->pending |= pending;
1291 atmel_port->pending_status = status;
1292 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1297 atmel_handle_receive(port, pending);
1298 atmel_handle_status(port, pending, status);
1299 atmel_handle_transmit(port, pending);
1300 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1302 spin_unlock(&atmel_port->lock_suspended);
1304 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1307 static void atmel_release_tx_pdc(struct uart_port *port)
1309 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1310 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1312 dma_unmap_single(port->dev,
1319 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1321 static void atmel_tx_pdc(struct uart_port *port)
1323 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1324 struct circ_buf *xmit = &port->state->xmit;
1325 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1328 /* nothing left to transmit? */
1329 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1332 xmit->tail += pdc->ofs;
1333 xmit->tail &= UART_XMIT_SIZE - 1;
1335 port->icount.tx += pdc->ofs;
1338 /* more to transmit - setup next transfer */
1340 /* disable PDC transmit */
1341 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1343 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1344 dma_sync_single_for_device(port->dev,
1349 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1352 atmel_uart_writel(port, ATMEL_PDC_TPR,
1353 pdc->dma_addr + xmit->tail);
1354 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1355 /* re-enable PDC transmit */
1356 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1357 /* Enable interrupts */
1358 atmel_uart_writel(port, ATMEL_US_IER,
1359 atmel_port->tx_done_mask);
1361 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1362 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1363 /* DMA done, stop TX, start RX for RS485 */
1364 atmel_start_rx(port);
1368 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1369 uart_write_wakeup(port);
1372 static int atmel_prepare_tx_pdc(struct uart_port *port)
1374 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1375 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1376 struct circ_buf *xmit = &port->state->xmit;
1378 pdc->buf = xmit->buf;
1379 pdc->dma_addr = dma_map_single(port->dev,
1383 pdc->dma_size = UART_XMIT_SIZE;
1389 static void atmel_rx_from_ring(struct uart_port *port)
1391 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1392 struct circ_buf *ring = &atmel_port->rx_ring;
1394 unsigned int status;
1396 while (ring->head != ring->tail) {
1397 struct atmel_uart_char c;
1399 /* Make sure c is loaded after head. */
1402 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1404 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1411 * note that the error handling code is
1412 * out of the main execution path
1414 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1415 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1416 if (status & ATMEL_US_RXBRK) {
1417 /* ignore side-effect */
1418 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1421 if (uart_handle_break(port))
1424 if (status & ATMEL_US_PARE)
1425 port->icount.parity++;
1426 if (status & ATMEL_US_FRAME)
1427 port->icount.frame++;
1428 if (status & ATMEL_US_OVRE)
1429 port->icount.overrun++;
1431 status &= port->read_status_mask;
1433 if (status & ATMEL_US_RXBRK)
1435 else if (status & ATMEL_US_PARE)
1437 else if (status & ATMEL_US_FRAME)
1442 if (uart_handle_sysrq_char(port, c.ch))
1445 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1449 * Drop the lock here since it might end up calling
1450 * uart_start(), which takes the lock.
1452 spin_unlock(&port->lock);
1453 tty_flip_buffer_push(&port->state->port);
1454 spin_lock(&port->lock);
1457 static void atmel_release_rx_pdc(struct uart_port *port)
1459 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1462 for (i = 0; i < 2; i++) {
1463 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1465 dma_unmap_single(port->dev,
1473 static void atmel_rx_from_pdc(struct uart_port *port)
1475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1476 struct tty_port *tport = &port->state->port;
1477 struct atmel_dma_buffer *pdc;
1478 int rx_idx = atmel_port->pdc_rx_idx;
1484 /* Reset the UART timeout early so that we don't miss one */
1485 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1487 pdc = &atmel_port->pdc_rx[rx_idx];
1488 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1491 /* If the PDC has switched buffers, RPR won't contain
1492 * any address within the current buffer. Since head
1493 * is unsigned, we just need a one-way comparison to
1496 * In this case, we just need to consume the entire
1497 * buffer and resubmit it for DMA. This will clear the
1498 * ENDRX bit as well, so that we can safely re-enable
1499 * all interrupts below.
1501 head = min(head, pdc->dma_size);
1503 if (likely(head != tail)) {
1504 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1505 pdc->dma_size, DMA_FROM_DEVICE);
1508 * head will only wrap around when we recycle
1509 * the DMA buffer, and when that happens, we
1510 * explicitly set tail to 0. So head will
1511 * always be greater than tail.
1513 count = head - tail;
1515 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1518 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1519 pdc->dma_size, DMA_FROM_DEVICE);
1521 port->icount.rx += count;
1526 * If the current buffer is full, we need to check if
1527 * the next one contains any additional data.
1529 if (head >= pdc->dma_size) {
1531 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1532 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1535 atmel_port->pdc_rx_idx = rx_idx;
1537 } while (head >= pdc->dma_size);
1540 * Drop the lock here since it might end up calling
1541 * uart_start(), which takes the lock.
1543 spin_unlock(&port->lock);
1544 tty_flip_buffer_push(tport);
1545 spin_lock(&port->lock);
1547 atmel_uart_writel(port, ATMEL_US_IER,
1548 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1551 static int atmel_prepare_rx_pdc(struct uart_port *port)
1553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1556 for (i = 0; i < 2; i++) {
1557 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1559 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1560 if (pdc->buf == NULL) {
1562 dma_unmap_single(port->dev,
1563 atmel_port->pdc_rx[0].dma_addr,
1566 kfree(atmel_port->pdc_rx[0].buf);
1568 atmel_port->use_pdc_rx = 0;
1571 pdc->dma_addr = dma_map_single(port->dev,
1575 pdc->dma_size = PDC_BUFFER_SIZE;
1579 atmel_port->pdc_rx_idx = 0;
1581 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1582 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1584 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1585 atmel_port->pdc_rx[1].dma_addr);
1586 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1592 * tasklet handling tty stuff outside the interrupt handler.
1594 static void atmel_tasklet_rx_func(unsigned long data)
1596 struct uart_port *port = (struct uart_port *)data;
1597 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1599 /* The interrupt handler does not take the lock */
1600 spin_lock(&port->lock);
1601 atmel_port->schedule_rx(port);
1602 spin_unlock(&port->lock);
1605 static void atmel_tasklet_tx_func(unsigned long data)
1607 struct uart_port *port = (struct uart_port *)data;
1608 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1610 /* The interrupt handler does not take the lock */
1611 spin_lock(&port->lock);
1612 atmel_port->schedule_tx(port);
1613 spin_unlock(&port->lock);
1616 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1617 struct platform_device *pdev)
1619 struct device_node *np = pdev->dev.of_node;
1620 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1623 /* DMA/PDC usage specification */
1624 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1625 if (of_get_property(np, "dmas", NULL)) {
1626 atmel_port->use_dma_rx = true;
1627 atmel_port->use_pdc_rx = false;
1629 atmel_port->use_dma_rx = false;
1630 atmel_port->use_pdc_rx = true;
1633 atmel_port->use_dma_rx = false;
1634 atmel_port->use_pdc_rx = false;
1637 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1638 if (of_get_property(np, "dmas", NULL)) {
1639 atmel_port->use_dma_tx = true;
1640 atmel_port->use_pdc_tx = false;
1642 atmel_port->use_dma_tx = false;
1643 atmel_port->use_pdc_tx = true;
1646 atmel_port->use_dma_tx = false;
1647 atmel_port->use_pdc_tx = false;
1651 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1652 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1653 atmel_port->use_dma_rx = false;
1654 atmel_port->use_dma_tx = false;
1659 static void atmel_init_rs485(struct uart_port *port,
1660 struct platform_device *pdev)
1662 struct device_node *np = pdev->dev.of_node;
1663 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1666 struct serial_rs485 *rs485conf = &port->rs485;
1668 /* rs485 properties */
1669 if (of_property_read_u32_array(np, "rs485-rts-delay",
1670 rs485_delay, 2) == 0) {
1671 rs485conf->delay_rts_before_send = rs485_delay[0];
1672 rs485conf->delay_rts_after_send = rs485_delay[1];
1673 rs485conf->flags = 0;
1676 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1677 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1679 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1681 rs485conf->flags |= SER_RS485_ENABLED;
1683 port->rs485 = pdata->rs485;
1688 static void atmel_set_ops(struct uart_port *port)
1690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1692 if (atmel_use_dma_rx(port)) {
1693 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1694 atmel_port->schedule_rx = &atmel_rx_from_dma;
1695 atmel_port->release_rx = &atmel_release_rx_dma;
1696 } else if (atmel_use_pdc_rx(port)) {
1697 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1698 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1699 atmel_port->release_rx = &atmel_release_rx_pdc;
1701 atmel_port->prepare_rx = NULL;
1702 atmel_port->schedule_rx = &atmel_rx_from_ring;
1703 atmel_port->release_rx = NULL;
1706 if (atmel_use_dma_tx(port)) {
1707 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1708 atmel_port->schedule_tx = &atmel_tx_dma;
1709 atmel_port->release_tx = &atmel_release_tx_dma;
1710 } else if (atmel_use_pdc_tx(port)) {
1711 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1712 atmel_port->schedule_tx = &atmel_tx_pdc;
1713 atmel_port->release_tx = &atmel_release_tx_pdc;
1715 atmel_port->prepare_tx = NULL;
1716 atmel_port->schedule_tx = &atmel_tx_chars;
1717 atmel_port->release_tx = NULL;
1722 * Get ip name usart or uart
1724 static void atmel_get_ip_name(struct uart_port *port)
1726 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1727 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1729 u32 usart, dbgu_uart, new_uart;
1730 /* ASCII decoding for IP version */
1731 usart = 0x55534152; /* USAR(T) */
1732 dbgu_uart = 0x44424755; /* DBGU */
1733 new_uart = 0x55415254; /* UART */
1735 atmel_port->has_hw_timer = false;
1737 if (name == new_uart) {
1738 dev_dbg(port->dev, "Uart with hw timer");
1739 atmel_port->has_hw_timer = true;
1740 atmel_port->rtor = ATMEL_UA_RTOR;
1741 } else if (name == usart) {
1742 dev_dbg(port->dev, "Usart\n");
1743 atmel_port->has_hw_timer = true;
1744 atmel_port->rtor = ATMEL_US_RTOR;
1745 } else if (name == dbgu_uart) {
1746 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1748 /* fallback for older SoCs: use version field */
1749 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1753 dev_dbg(port->dev, "This version is usart\n");
1754 atmel_port->has_hw_timer = true;
1755 atmel_port->rtor = ATMEL_US_RTOR;
1759 dev_dbg(port->dev, "This version is uart\n");
1762 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1768 * Perform initialization and enable port for reception
1770 static int atmel_startup(struct uart_port *port)
1772 struct platform_device *pdev = to_platform_device(port->dev);
1773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1774 struct tty_struct *tty = port->state->port.tty;
1778 * Ensure that no interrupts are enabled otherwise when
1779 * request_irq() is called we could get stuck trying to
1780 * handle an unexpected interrupt
1782 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1783 atmel_port->ms_irq_enabled = false;
1788 retval = request_irq(port->irq, atmel_interrupt,
1789 IRQF_SHARED | IRQF_COND_SUSPEND,
1790 tty ? tty->name : "atmel_serial", port);
1792 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1796 tasklet_enable(&atmel_port->tasklet_rx);
1797 tasklet_enable(&atmel_port->tasklet_tx);
1800 * Initialize DMA (if necessary)
1802 atmel_init_property(atmel_port, pdev);
1803 atmel_set_ops(port);
1805 if (atmel_port->prepare_rx) {
1806 retval = atmel_port->prepare_rx(port);
1808 atmel_set_ops(port);
1811 if (atmel_port->prepare_tx) {
1812 retval = atmel_port->prepare_tx(port);
1814 atmel_set_ops(port);
1818 * Enable FIFO when available
1820 if (atmel_port->fifo_size) {
1821 unsigned int txrdym = ATMEL_US_ONE_DATA;
1822 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1825 atmel_uart_writel(port, ATMEL_US_CR,
1830 if (atmel_use_dma_tx(port))
1831 txrdym = ATMEL_US_FOUR_DATA;
1833 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1834 if (atmel_port->rts_high &&
1835 atmel_port->rts_low)
1836 fmr |= ATMEL_US_FRTSC |
1837 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1838 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1840 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1843 /* Save current CSR for comparison in atmel_tasklet_func() */
1844 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1847 * Finally, enable the serial port
1849 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1850 /* enable xmit & rcvr */
1851 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1853 setup_timer(&atmel_port->uart_timer,
1854 atmel_uart_timer_callback,
1855 (unsigned long)port);
1857 if (atmel_use_pdc_rx(port)) {
1858 /* set UART timeout */
1859 if (!atmel_port->has_hw_timer) {
1860 mod_timer(&atmel_port->uart_timer,
1861 jiffies + uart_poll_timeout(port));
1862 /* set USART timeout */
1864 atmel_uart_writel(port, atmel_port->rtor,
1866 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1868 atmel_uart_writel(port, ATMEL_US_IER,
1869 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1871 /* enable PDC controller */
1872 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1873 } else if (atmel_use_dma_rx(port)) {
1874 /* set UART timeout */
1875 if (!atmel_port->has_hw_timer) {
1876 mod_timer(&atmel_port->uart_timer,
1877 jiffies + uart_poll_timeout(port));
1878 /* set USART timeout */
1880 atmel_uart_writel(port, atmel_port->rtor,
1882 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1884 atmel_uart_writel(port, ATMEL_US_IER,
1888 /* enable receive only */
1889 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1896 * Flush any TX data submitted for DMA. Called when the TX circular
1899 static void atmel_flush_buffer(struct uart_port *port)
1901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1903 if (atmel_use_pdc_tx(port)) {
1904 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1905 atmel_port->pdc_tx.ofs = 0;
1912 static void atmel_shutdown(struct uart_port *port)
1914 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1917 * Prevent any tasklets being scheduled during
1920 del_timer_sync(&atmel_port->uart_timer);
1923 * Clear out any scheduled tasklets before
1924 * we destroy the buffers
1926 tasklet_disable(&atmel_port->tasklet_rx);
1927 tasklet_disable(&atmel_port->tasklet_tx);
1928 tasklet_kill(&atmel_port->tasklet_rx);
1929 tasklet_kill(&atmel_port->tasklet_tx);
1932 * Ensure everything is stopped and
1933 * disable all interrupts, port and break condition.
1935 atmel_stop_rx(port);
1936 atmel_stop_tx(port);
1938 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1939 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1943 * Shut-down the DMA.
1945 if (atmel_port->release_rx)
1946 atmel_port->release_rx(port);
1947 if (atmel_port->release_tx)
1948 atmel_port->release_tx(port);
1951 * Reset ring buffer pointers
1953 atmel_port->rx_ring.head = 0;
1954 atmel_port->rx_ring.tail = 0;
1957 * Free the interrupts
1959 free_irq(port->irq, port);
1961 atmel_port->ms_irq_enabled = false;
1963 atmel_flush_buffer(port);
1967 * Power / Clock management.
1969 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1970 unsigned int oldstate)
1972 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1977 * Enable the peripheral clock for this serial port.
1978 * This is called on uart_open() or a resume event.
1980 clk_prepare_enable(atmel_port->clk);
1982 /* re-enable interrupts if we disabled some on suspend */
1983 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
1986 /* Back up the interrupt mask and disable all interrupts */
1987 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
1988 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1991 * Disable the peripheral clock for this serial port.
1992 * This is called on uart_close() or a suspend event.
1994 clk_disable_unprepare(atmel_port->clk);
1997 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2002 * Change the port parameters
2004 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2005 struct ktermios *old)
2007 unsigned long flags;
2008 unsigned int old_mode, mode, imr, quot, baud;
2010 /* save the current mode register */
2011 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2013 /* reset the mode, clock divisor, parity, stop bits and data size */
2014 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2015 ATMEL_US_PAR | ATMEL_US_USMODE);
2017 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2018 quot = uart_get_divisor(port, baud);
2020 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2022 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2026 switch (termios->c_cflag & CSIZE) {
2028 mode |= ATMEL_US_CHRL_5;
2031 mode |= ATMEL_US_CHRL_6;
2034 mode |= ATMEL_US_CHRL_7;
2037 mode |= ATMEL_US_CHRL_8;
2042 if (termios->c_cflag & CSTOPB)
2043 mode |= ATMEL_US_NBSTOP_2;
2046 if (termios->c_cflag & PARENB) {
2047 /* Mark or Space parity */
2048 if (termios->c_cflag & CMSPAR) {
2049 if (termios->c_cflag & PARODD)
2050 mode |= ATMEL_US_PAR_MARK;
2052 mode |= ATMEL_US_PAR_SPACE;
2053 } else if (termios->c_cflag & PARODD)
2054 mode |= ATMEL_US_PAR_ODD;
2056 mode |= ATMEL_US_PAR_EVEN;
2058 mode |= ATMEL_US_PAR_NONE;
2060 spin_lock_irqsave(&port->lock, flags);
2062 port->read_status_mask = ATMEL_US_OVRE;
2063 if (termios->c_iflag & INPCK)
2064 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2065 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2066 port->read_status_mask |= ATMEL_US_RXBRK;
2068 if (atmel_use_pdc_rx(port))
2069 /* need to enable error interrupts */
2070 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2073 * Characters to ignore
2075 port->ignore_status_mask = 0;
2076 if (termios->c_iflag & IGNPAR)
2077 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2078 if (termios->c_iflag & IGNBRK) {
2079 port->ignore_status_mask |= ATMEL_US_RXBRK;
2081 * If we're ignoring parity and break indicators,
2082 * ignore overruns too (for real raw support).
2084 if (termios->c_iflag & IGNPAR)
2085 port->ignore_status_mask |= ATMEL_US_OVRE;
2087 /* TODO: Ignore all characters if CREAD is set.*/
2089 /* update the per-port timeout */
2090 uart_update_timeout(port, termios->c_cflag, baud);
2093 * save/disable interrupts. The tty layer will ensure that the
2094 * transmitter is empty if requested by the caller, so there's
2095 * no need to wait for it here.
2097 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2098 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2100 /* disable receiver and transmitter */
2101 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2104 if (port->rs485.flags & SER_RS485_ENABLED) {
2105 atmel_uart_writel(port, ATMEL_US_TTGR,
2106 port->rs485.delay_rts_after_send);
2107 mode |= ATMEL_US_USMODE_RS485;
2108 } else if (termios->c_cflag & CRTSCTS) {
2109 /* RS232 with hardware handshake (RTS/CTS) */
2110 if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
2111 dev_info(port->dev, "not enabling hardware flow control because DMA is used");
2112 termios->c_cflag &= ~CRTSCTS;
2114 mode |= ATMEL_US_USMODE_HWHS;
2117 /* RS232 without hadware handshake */
2118 mode |= ATMEL_US_USMODE_NORMAL;
2121 /* set the mode, clock divisor, parity, stop bits and data size */
2122 atmel_uart_writel(port, ATMEL_US_MR, mode);
2125 * when switching the mode, set the RTS line state according to the
2126 * new mode, otherwise keep the former state
2128 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2129 unsigned int rts_state;
2131 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2132 /* let the hardware control the RTS line */
2133 rts_state = ATMEL_US_RTSDIS;
2135 /* force RTS line to low level */
2136 rts_state = ATMEL_US_RTSEN;
2139 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2142 /* set the baud rate */
2143 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2144 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2145 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2147 /* restore interrupts */
2148 atmel_uart_writel(port, ATMEL_US_IER, imr);
2150 /* CTS flow-control and modem-status interrupts */
2151 if (UART_ENABLE_MS(port, termios->c_cflag))
2152 atmel_enable_ms(port);
2154 atmel_disable_ms(port);
2156 spin_unlock_irqrestore(&port->lock, flags);
2159 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2161 if (termios->c_line == N_PPS) {
2162 port->flags |= UPF_HARDPPS_CD;
2163 spin_lock_irq(&port->lock);
2164 atmel_enable_ms(port);
2165 spin_unlock_irq(&port->lock);
2167 port->flags &= ~UPF_HARDPPS_CD;
2168 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2169 spin_lock_irq(&port->lock);
2170 atmel_disable_ms(port);
2171 spin_unlock_irq(&port->lock);
2177 * Return string describing the specified port
2179 static const char *atmel_type(struct uart_port *port)
2181 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2185 * Release the memory region(s) being used by 'port'.
2187 static void atmel_release_port(struct uart_port *port)
2189 struct platform_device *pdev = to_platform_device(port->dev);
2190 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2192 release_mem_region(port->mapbase, size);
2194 if (port->flags & UPF_IOREMAP) {
2195 iounmap(port->membase);
2196 port->membase = NULL;
2201 * Request the memory region(s) being used by 'port'.
2203 static int atmel_request_port(struct uart_port *port)
2205 struct platform_device *pdev = to_platform_device(port->dev);
2206 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2208 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2211 if (port->flags & UPF_IOREMAP) {
2212 port->membase = ioremap(port->mapbase, size);
2213 if (port->membase == NULL) {
2214 release_mem_region(port->mapbase, size);
2223 * Configure/autoconfigure the port.
2225 static void atmel_config_port(struct uart_port *port, int flags)
2227 if (flags & UART_CONFIG_TYPE) {
2228 port->type = PORT_ATMEL;
2229 atmel_request_port(port);
2234 * Verify the new serial_struct (for TIOCSSERIAL).
2236 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2239 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2241 if (port->irq != ser->irq)
2243 if (ser->io_type != SERIAL_IO_MEM)
2245 if (port->uartclk / 16 != ser->baud_base)
2247 if (port->mapbase != (unsigned long)ser->iomem_base)
2249 if (port->iobase != ser->port)
2256 #ifdef CONFIG_CONSOLE_POLL
2257 static int atmel_poll_get_char(struct uart_port *port)
2259 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2262 return atmel_uart_read_char(port);
2265 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2267 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2270 atmel_uart_write_char(port, ch);
2274 static struct uart_ops atmel_pops = {
2275 .tx_empty = atmel_tx_empty,
2276 .set_mctrl = atmel_set_mctrl,
2277 .get_mctrl = atmel_get_mctrl,
2278 .stop_tx = atmel_stop_tx,
2279 .start_tx = atmel_start_tx,
2280 .stop_rx = atmel_stop_rx,
2281 .enable_ms = atmel_enable_ms,
2282 .break_ctl = atmel_break_ctl,
2283 .startup = atmel_startup,
2284 .shutdown = atmel_shutdown,
2285 .flush_buffer = atmel_flush_buffer,
2286 .set_termios = atmel_set_termios,
2287 .set_ldisc = atmel_set_ldisc,
2289 .release_port = atmel_release_port,
2290 .request_port = atmel_request_port,
2291 .config_port = atmel_config_port,
2292 .verify_port = atmel_verify_port,
2293 .pm = atmel_serial_pm,
2294 #ifdef CONFIG_CONSOLE_POLL
2295 .poll_get_char = atmel_poll_get_char,
2296 .poll_put_char = atmel_poll_put_char,
2301 * Configure the port from the platform device resource info.
2303 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2304 struct platform_device *pdev)
2307 struct uart_port *port = &atmel_port->uart;
2308 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2310 atmel_init_property(atmel_port, pdev);
2311 atmel_set_ops(port);
2313 atmel_init_rs485(port, pdev);
2315 port->iotype = UPIO_MEM;
2316 port->flags = UPF_BOOT_AUTOCONF;
2317 port->ops = &atmel_pops;
2319 port->dev = &pdev->dev;
2320 port->mapbase = pdev->resource[0].start;
2321 port->irq = pdev->resource[1].start;
2322 port->rs485_config = atmel_config_rs485;
2324 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
2325 (unsigned long)port);
2326 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
2327 (unsigned long)port);
2328 tasklet_disable(&atmel_port->tasklet_rx);
2329 tasklet_disable(&atmel_port->tasklet_tx);
2331 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2333 if (pdata && pdata->regs) {
2334 /* Already mapped by setup code */
2335 port->membase = pdata->regs;
2337 port->flags |= UPF_IOREMAP;
2338 port->membase = NULL;
2341 /* for console, the clock could already be configured */
2342 if (!atmel_port->clk) {
2343 atmel_port->clk = clk_get(&pdev->dev, "usart");
2344 if (IS_ERR(atmel_port->clk)) {
2345 ret = PTR_ERR(atmel_port->clk);
2346 atmel_port->clk = NULL;
2349 ret = clk_prepare_enable(atmel_port->clk);
2351 clk_put(atmel_port->clk);
2352 atmel_port->clk = NULL;
2355 port->uartclk = clk_get_rate(atmel_port->clk);
2356 clk_disable_unprepare(atmel_port->clk);
2357 /* only enable clock when USART is in use */
2360 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2361 if (port->rs485.flags & SER_RS485_ENABLED)
2362 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2363 else if (atmel_use_pdc_tx(port)) {
2364 port->fifosize = PDC_BUFFER_SIZE;
2365 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2367 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2373 struct platform_device *atmel_default_console_device; /* the serial console device */
2375 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2376 static void atmel_console_putchar(struct uart_port *port, int ch)
2378 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2380 atmel_uart_write_char(port, ch);
2384 * Interrupts are disabled on entering
2386 static void atmel_console_write(struct console *co, const char *s, u_int count)
2388 struct uart_port *port = &atmel_ports[co->index].uart;
2389 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2390 unsigned int status, imr;
2391 unsigned int pdc_tx;
2394 * First, save IMR and then disable interrupts
2396 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2397 atmel_uart_writel(port, ATMEL_US_IDR,
2398 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2400 /* Store PDC transmit status and disable it */
2401 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2402 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2404 uart_console_write(port, s, count, atmel_console_putchar);
2407 * Finally, wait for transmitter to become empty
2411 status = atmel_uart_readl(port, ATMEL_US_CSR);
2412 } while (!(status & ATMEL_US_TXRDY));
2414 /* Restore PDC transmit status */
2416 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2418 /* set interrupts back the way they were */
2419 atmel_uart_writel(port, ATMEL_US_IER, imr);
2423 * If the port was already initialised (eg, by a boot loader),
2424 * try to determine the current setup.
2426 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2427 int *parity, int *bits)
2429 unsigned int mr, quot;
2432 * If the baud rate generator isn't running, the port wasn't
2433 * initialized by the boot loader.
2435 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2439 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2440 if (mr == ATMEL_US_CHRL_8)
2445 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2446 if (mr == ATMEL_US_PAR_EVEN)
2448 else if (mr == ATMEL_US_PAR_ODD)
2452 * The serial core only rounds down when matching this to a
2453 * supported baud rate. Make sure we don't end up slightly
2454 * lower than one of those, as it would make us fall through
2455 * to a much lower baud rate than we really want.
2457 *baud = port->uartclk / (16 * (quot - 1));
2460 static int __init atmel_console_setup(struct console *co, char *options)
2463 struct uart_port *port = &atmel_ports[co->index].uart;
2469 if (port->membase == NULL) {
2470 /* Port not initialized yet - delay setup */
2474 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2478 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2479 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2480 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2483 uart_parse_options(options, &baud, &parity, &bits, &flow);
2485 atmel_console_get_options(port, &baud, &parity, &bits);
2487 return uart_set_options(port, co, baud, parity, bits, flow);
2490 static struct uart_driver atmel_uart;
2492 static struct console atmel_console = {
2493 .name = ATMEL_DEVICENAME,
2494 .write = atmel_console_write,
2495 .device = uart_console_device,
2496 .setup = atmel_console_setup,
2497 .flags = CON_PRINTBUFFER,
2499 .data = &atmel_uart,
2502 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2505 * Early console initialization (before VM subsystem initialized).
2507 static int __init atmel_console_init(void)
2510 if (atmel_default_console_device) {
2511 struct atmel_uart_data *pdata =
2512 dev_get_platdata(&atmel_default_console_device->dev);
2513 int id = pdata->num;
2514 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2516 atmel_port->backup_imr = 0;
2517 atmel_port->uart.line = id;
2519 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2520 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2523 register_console(&atmel_console);
2529 console_initcall(atmel_console_init);
2532 * Late console initialization.
2534 static int __init atmel_late_console_init(void)
2536 if (atmel_default_console_device
2537 && !(atmel_console.flags & CON_ENABLED))
2538 register_console(&atmel_console);
2543 core_initcall(atmel_late_console_init);
2545 static inline bool atmel_is_console_port(struct uart_port *port)
2547 return port->cons && port->cons->index == port->line;
2551 #define ATMEL_CONSOLE_DEVICE NULL
2553 static inline bool atmel_is_console_port(struct uart_port *port)
2559 static struct uart_driver atmel_uart = {
2560 .owner = THIS_MODULE,
2561 .driver_name = "atmel_serial",
2562 .dev_name = ATMEL_DEVICENAME,
2563 .major = SERIAL_ATMEL_MAJOR,
2564 .minor = MINOR_START,
2565 .nr = ATMEL_MAX_UART,
2566 .cons = ATMEL_CONSOLE_DEVICE,
2570 static bool atmel_serial_clk_will_stop(void)
2572 #ifdef CONFIG_ARCH_AT91
2573 return at91_suspend_entering_slow_clock();
2579 static int atmel_serial_suspend(struct platform_device *pdev,
2582 struct uart_port *port = platform_get_drvdata(pdev);
2583 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2585 if (atmel_is_console_port(port) && console_suspend_enabled) {
2586 /* Drain the TX shifter */
2587 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2592 /* we can not wake up if we're running on slow clock */
2593 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2594 if (atmel_serial_clk_will_stop()) {
2595 unsigned long flags;
2597 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2598 atmel_port->suspended = true;
2599 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2600 device_set_wakeup_enable(&pdev->dev, 0);
2603 uart_suspend_port(&atmel_uart, port);
2608 static int atmel_serial_resume(struct platform_device *pdev)
2610 struct uart_port *port = platform_get_drvdata(pdev);
2611 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2612 unsigned long flags;
2614 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2615 if (atmel_port->pending) {
2616 atmel_handle_receive(port, atmel_port->pending);
2617 atmel_handle_status(port, atmel_port->pending,
2618 atmel_port->pending_status);
2619 atmel_handle_transmit(port, atmel_port->pending);
2620 atmel_port->pending = 0;
2622 atmel_port->suspended = false;
2623 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2625 uart_resume_port(&atmel_uart, port);
2626 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2631 #define atmel_serial_suspend NULL
2632 #define atmel_serial_resume NULL
2635 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2636 struct platform_device *pdev)
2638 atmel_port->fifo_size = 0;
2639 atmel_port->rts_low = 0;
2640 atmel_port->rts_high = 0;
2642 if (of_property_read_u32(pdev->dev.of_node,
2644 &atmel_port->fifo_size))
2647 if (!atmel_port->fifo_size)
2650 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2651 atmel_port->fifo_size = 0;
2652 dev_err(&pdev->dev, "Invalid FIFO size\n");
2657 * 0 <= rts_low <= rts_high <= fifo_size
2658 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2659 * to flush their internal TX FIFO, commonly up to 16 data, before
2660 * actually stopping to send new data. So we try to set the RTS High
2661 * Threshold to a reasonably high value respecting this 16 data
2662 * empirical rule when possible.
2664 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2665 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2666 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2667 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2669 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2670 atmel_port->fifo_size);
2671 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2672 atmel_port->rts_high);
2673 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2674 atmel_port->rts_low);
2677 static int atmel_serial_probe(struct platform_device *pdev)
2679 struct atmel_uart_port *atmel_port;
2680 struct device_node *np = pdev->dev.of_node;
2681 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2686 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2689 ret = of_alias_get_id(np, "serial");
2695 /* port id not found in platform data nor device-tree aliases:
2696 * auto-enumerate it */
2697 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2699 if (ret >= ATMEL_MAX_UART) {
2704 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2705 /* port already in use */
2710 atmel_port = &atmel_ports[ret];
2711 atmel_port->backup_imr = 0;
2712 atmel_port->uart.line = ret;
2713 atmel_serial_probe_fifos(atmel_port, pdev);
2715 spin_lock_init(&atmel_port->lock_suspended);
2717 ret = atmel_init_port(atmel_port, pdev);
2721 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2722 if (IS_ERR(atmel_port->gpios)) {
2723 ret = PTR_ERR(atmel_port->gpios);
2727 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2729 data = kmalloc(sizeof(struct atmel_uart_char)
2730 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2732 goto err_alloc_ring;
2733 atmel_port->rx_ring.buf = data;
2736 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2738 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2742 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2743 if (atmel_is_console_port(&atmel_port->uart)
2744 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2746 * The serial core enabled the clock for us, so undo
2747 * the clk_prepare_enable() in atmel_console_setup()
2749 clk_disable_unprepare(atmel_port->clk);
2753 device_init_wakeup(&pdev->dev, 1);
2754 platform_set_drvdata(pdev, atmel_port);
2757 * The peripheral clock has been disabled by atmel_init_port():
2758 * enable it before accessing I/O registers
2760 clk_prepare_enable(atmel_port->clk);
2762 if (rs485_enabled) {
2763 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2764 ATMEL_US_USMODE_NORMAL);
2765 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2770 * Get port name of usart or uart
2772 atmel_get_ip_name(&atmel_port->uart);
2775 * The peripheral clock can now safely be disabled till the port
2778 clk_disable_unprepare(atmel_port->clk);
2783 kfree(atmel_port->rx_ring.buf);
2784 atmel_port->rx_ring.buf = NULL;
2786 if (!atmel_is_console_port(&atmel_port->uart)) {
2787 clk_put(atmel_port->clk);
2788 atmel_port->clk = NULL;
2791 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2797 * Even if the driver is not modular, it makes sense to be able to
2798 * unbind a device: there can be many bound devices, and there are
2799 * situations where dynamic binding and unbinding can be useful.
2801 * For example, a connected device can require a specific firmware update
2802 * protocol that needs bitbanging on IO lines, but use the regular serial
2803 * port in the normal case.
2805 static int atmel_serial_remove(struct platform_device *pdev)
2807 struct uart_port *port = platform_get_drvdata(pdev);
2808 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2811 tasklet_kill(&atmel_port->tasklet_rx);
2812 tasklet_kill(&atmel_port->tasklet_tx);
2814 device_init_wakeup(&pdev->dev, 0);
2816 ret = uart_remove_one_port(&atmel_uart, port);
2818 kfree(atmel_port->rx_ring.buf);
2820 /* "port" is allocated statically, so we shouldn't free it */
2822 clear_bit(port->line, atmel_ports_in_use);
2824 clk_put(atmel_port->clk);
2825 atmel_port->clk = NULL;
2830 static struct platform_driver atmel_serial_driver = {
2831 .probe = atmel_serial_probe,
2832 .remove = atmel_serial_remove,
2833 .suspend = atmel_serial_suspend,
2834 .resume = atmel_serial_resume,
2836 .name = "atmel_usart",
2837 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2841 static int __init atmel_serial_init(void)
2845 ret = uart_register_driver(&atmel_uart);
2849 ret = platform_driver_register(&atmel_serial_driver);
2851 uart_unregister_driver(&atmel_uart);
2855 device_initcall(atmel_serial_init);