2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
117 #define ATMEL_SERIAL_RINGSIZE 1024
120 * at91: 6 USARTs and one DBGU port (SAM9260)
123 #define ATMEL_MAX_UART 7
126 * We wrap our port structure around the generic uart_port.
128 struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 atomic_t tasklet_shutdown;
157 unsigned int irq_status_prev;
160 struct circ_buf rx_ring;
162 struct mctrl_gpios *gpios;
163 unsigned int tx_done_mask;
168 u32 rtor; /* address of receiver timeout register if it exists */
169 bool has_frac_baudrate;
171 struct timer_list uart_timer;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
189 int (*prepare_rx)(struct uart_port *port);
190 int (*prepare_tx)(struct uart_port *port);
191 void (*schedule_rx)(struct uart_port *port);
192 void (*schedule_tx)(struct uart_port *port);
193 void (*release_rx)(struct uart_port *port);
194 void (*release_tx)(struct uart_port *port);
197 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
198 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
201 static struct console atmel_console;
204 #if defined(CONFIG_OF)
205 static const struct of_device_id atmel_serial_dt_ids[] = {
206 { .compatible = "atmel,at91rm9200-usart" },
207 { .compatible = "atmel,at91sam9260-usart" },
212 static inline struct atmel_uart_port *
213 to_atmel_uart_port(struct uart_port *uart)
215 return container_of(uart, struct atmel_uart_port, uart);
218 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
220 return __raw_readl(port->membase + reg);
223 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
225 __raw_writel(value, port->membase + reg);
230 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
231 static inline u8 atmel_uart_read_char(struct uart_port *port)
233 return __raw_readl(port->membase + ATMEL_US_RHR);
236 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
238 __raw_writel(value, port->membase + ATMEL_US_THR);
243 static inline u8 atmel_uart_read_char(struct uart_port *port)
245 return __raw_readb(port->membase + ATMEL_US_RHR);
248 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
250 __raw_writeb(value, port->membase + ATMEL_US_THR);
255 #ifdef CONFIG_SERIAL_ATMEL_PDC
256 static bool atmel_use_pdc_rx(struct uart_port *port)
258 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
260 return atmel_port->use_pdc_rx;
263 static bool atmel_use_pdc_tx(struct uart_port *port)
265 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
267 return atmel_port->use_pdc_tx;
270 static bool atmel_use_pdc_rx(struct uart_port *port)
275 static bool atmel_use_pdc_tx(struct uart_port *port)
281 static bool atmel_use_dma_tx(struct uart_port *port)
283 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
285 return atmel_port->use_dma_tx;
288 static bool atmel_use_dma_rx(struct uart_port *port)
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
292 return atmel_port->use_dma_rx;
295 static bool atmel_use_fifo(struct uart_port *port)
297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
299 return atmel_port->fifo_size;
302 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
303 struct tasklet_struct *t)
305 if (!atomic_read(&atmel_port->tasklet_shutdown))
309 static unsigned int atmel_get_lines_status(struct uart_port *port)
311 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
312 unsigned int status, ret = 0;
314 status = atmel_uart_readl(port, ATMEL_US_CSR);
316 mctrl_gpio_get(atmel_port->gpios, &ret);
318 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
321 status &= ~ATMEL_US_CTS;
323 status |= ATMEL_US_CTS;
326 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
329 status &= ~ATMEL_US_DSR;
331 status |= ATMEL_US_DSR;
334 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
337 status &= ~ATMEL_US_RI;
339 status |= ATMEL_US_RI;
342 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
345 status &= ~ATMEL_US_DCD;
347 status |= ATMEL_US_DCD;
353 /* Enable or disable the rs485 support */
354 static int atmel_config_rs485(struct uart_port *port,
355 struct serial_rs485 *rs485conf)
357 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
360 /* Disable interrupts */
361 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
363 mode = atmel_uart_readl(port, ATMEL_US_MR);
365 /* Resetting serial mode to RS232 (0x0) */
366 mode &= ~ATMEL_US_USMODE;
368 port->rs485 = *rs485conf;
370 if (rs485conf->flags & SER_RS485_ENABLED) {
371 dev_dbg(port->dev, "Setting UART to RS485\n");
372 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
373 atmel_uart_writel(port, ATMEL_US_TTGR,
374 rs485conf->delay_rts_after_send);
375 mode |= ATMEL_US_USMODE_RS485;
377 dev_dbg(port->dev, "Setting UART to RS232\n");
378 if (atmel_use_pdc_tx(port))
379 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
382 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
384 atmel_uart_writel(port, ATMEL_US_MR, mode);
386 /* Enable interrupts */
387 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
393 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
395 static u_int atmel_tx_empty(struct uart_port *port)
397 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
403 * Set state of the modem control output lines
405 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
407 unsigned int control = 0;
408 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
409 unsigned int rts_paused, rts_ready;
410 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
412 /* override mode to RS485 if needed, otherwise keep the current mode */
413 if (port->rs485.flags & SER_RS485_ENABLED) {
414 atmel_uart_writel(port, ATMEL_US_TTGR,
415 port->rs485.delay_rts_after_send);
416 mode &= ~ATMEL_US_USMODE;
417 mode |= ATMEL_US_USMODE_RS485;
420 /* set the RTS line state according to the mode */
421 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
422 /* force RTS line to high level */
423 rts_paused = ATMEL_US_RTSEN;
425 /* give the control of the RTS line back to the hardware */
426 rts_ready = ATMEL_US_RTSDIS;
428 /* force RTS line to high level */
429 rts_paused = ATMEL_US_RTSDIS;
431 /* force RTS line to low level */
432 rts_ready = ATMEL_US_RTSEN;
435 if (mctrl & TIOCM_RTS)
436 control |= rts_ready;
438 control |= rts_paused;
440 if (mctrl & TIOCM_DTR)
441 control |= ATMEL_US_DTREN;
443 control |= ATMEL_US_DTRDIS;
445 atmel_uart_writel(port, ATMEL_US_CR, control);
447 mctrl_gpio_set(atmel_port->gpios, mctrl);
449 /* Local loopback mode? */
450 mode &= ~ATMEL_US_CHMODE;
451 if (mctrl & TIOCM_LOOP)
452 mode |= ATMEL_US_CHMODE_LOC_LOOP;
454 mode |= ATMEL_US_CHMODE_NORMAL;
456 atmel_uart_writel(port, ATMEL_US_MR, mode);
460 * Get state of the modem control input lines
462 static u_int atmel_get_mctrl(struct uart_port *port)
464 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
465 unsigned int ret = 0, status;
467 status = atmel_uart_readl(port, ATMEL_US_CSR);
470 * The control signals are active low.
472 if (!(status & ATMEL_US_DCD))
474 if (!(status & ATMEL_US_CTS))
476 if (!(status & ATMEL_US_DSR))
478 if (!(status & ATMEL_US_RI))
481 return mctrl_gpio_get(atmel_port->gpios, &ret);
487 static void atmel_stop_tx(struct uart_port *port)
489 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
491 if (atmel_use_pdc_tx(port)) {
492 /* disable PDC transmit */
493 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
497 * Disable the transmitter.
498 * This is mandatory when DMA is used, otherwise the DMA buffer
499 * is fully transmitted.
501 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
503 /* Disable interrupts */
504 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
506 if ((port->rs485.flags & SER_RS485_ENABLED) &&
507 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
508 atmel_start_rx(port);
512 * Start transmitting.
514 static void atmel_start_tx(struct uart_port *port)
516 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
518 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
520 /* The transmitter is already running. Yes, we
524 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
525 if ((port->rs485.flags & SER_RS485_ENABLED) &&
526 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
529 if (atmel_use_pdc_tx(port))
530 /* re-enable PDC transmit */
531 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
533 /* Enable interrupts */
534 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
536 /* re-enable the transmitter */
537 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
541 * start receiving - port is in process of being opened.
543 static void atmel_start_rx(struct uart_port *port)
545 /* reset status and receiver */
546 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
548 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
550 if (atmel_use_pdc_rx(port)) {
551 /* enable PDC controller */
552 atmel_uart_writel(port, ATMEL_US_IER,
553 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
554 port->read_status_mask);
555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
557 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
562 * Stop receiving - port is in process of being closed.
564 static void atmel_stop_rx(struct uart_port *port)
566 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
568 if (atmel_use_pdc_rx(port)) {
569 /* disable PDC receive */
570 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
571 atmel_uart_writel(port, ATMEL_US_IDR,
572 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
573 port->read_status_mask);
575 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
580 * Enable modem status interrupts
582 static void atmel_enable_ms(struct uart_port *port)
584 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
588 * Interrupt should not be enabled twice
590 if (atmel_port->ms_irq_enabled)
593 atmel_port->ms_irq_enabled = true;
595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
596 ier |= ATMEL_US_CTSIC;
598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
599 ier |= ATMEL_US_DSRIC;
601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
602 ier |= ATMEL_US_RIIC;
604 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
605 ier |= ATMEL_US_DCDIC;
607 atmel_uart_writel(port, ATMEL_US_IER, ier);
609 mctrl_gpio_enable_ms(atmel_port->gpios);
613 * Disable modem status interrupts
615 static void atmel_disable_ms(struct uart_port *port)
617 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
621 * Interrupt should not be disabled twice
623 if (!atmel_port->ms_irq_enabled)
626 atmel_port->ms_irq_enabled = false;
628 mctrl_gpio_disable_ms(atmel_port->gpios);
630 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
631 idr |= ATMEL_US_CTSIC;
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
634 idr |= ATMEL_US_DSRIC;
636 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
637 idr |= ATMEL_US_RIIC;
639 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
640 idr |= ATMEL_US_DCDIC;
642 atmel_uart_writel(port, ATMEL_US_IDR, idr);
646 * Control the transmission of a break signal
648 static void atmel_break_ctl(struct uart_port *port, int break_state)
650 if (break_state != 0)
652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
655 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
659 * Stores the incoming character in the ring buffer
662 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
665 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
666 struct circ_buf *ring = &atmel_port->rx_ring;
667 struct atmel_uart_char *c;
669 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
670 /* Buffer overflow, ignore char */
673 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
677 /* Make sure the character is stored before we update head. */
680 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
684 * Deal with parity, framing and overrun errors.
686 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
689 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
691 if (status & ATMEL_US_RXBRK) {
692 /* ignore side-effect */
693 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
696 if (status & ATMEL_US_PARE)
697 port->icount.parity++;
698 if (status & ATMEL_US_FRAME)
699 port->icount.frame++;
700 if (status & ATMEL_US_OVRE)
701 port->icount.overrun++;
705 * Characters received (called from interrupt handler)
707 static void atmel_rx_chars(struct uart_port *port)
709 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
710 unsigned int status, ch;
712 status = atmel_uart_readl(port, ATMEL_US_CSR);
713 while (status & ATMEL_US_RXRDY) {
714 ch = atmel_uart_read_char(port);
717 * note that the error handling code is
718 * out of the main execution path
720 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
721 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
722 || atmel_port->break_active)) {
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
727 if (status & ATMEL_US_RXBRK
728 && !atmel_port->break_active) {
729 atmel_port->break_active = 1;
730 atmel_uart_writel(port, ATMEL_US_IER,
734 * This is either the end-of-break
735 * condition or we've received at
736 * least one character without RXBRK
737 * being set. In both cases, the next
738 * RXBRK will indicate start-of-break.
740 atmel_uart_writel(port, ATMEL_US_IDR,
742 status &= ~ATMEL_US_RXBRK;
743 atmel_port->break_active = 0;
747 atmel_buffer_rx_char(port, status, ch);
748 status = atmel_uart_readl(port, ATMEL_US_CSR);
751 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
755 * Transmit characters (called from tasklet with TXRDY interrupt
758 static void atmel_tx_chars(struct uart_port *port)
760 struct circ_buf *xmit = &port->state->xmit;
761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
764 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
765 atmel_uart_write_char(port, port->x_char);
769 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
772 while (atmel_uart_readl(port, ATMEL_US_CSR) &
773 atmel_port->tx_done_mask) {
774 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
775 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
777 if (uart_circ_empty(xmit))
781 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
782 uart_write_wakeup(port);
784 if (!uart_circ_empty(xmit))
785 /* Enable interrupts */
786 atmel_uart_writel(port, ATMEL_US_IER,
787 atmel_port->tx_done_mask);
790 static void atmel_complete_tx_dma(void *arg)
792 struct atmel_uart_port *atmel_port = arg;
793 struct uart_port *port = &atmel_port->uart;
794 struct circ_buf *xmit = &port->state->xmit;
795 struct dma_chan *chan = atmel_port->chan_tx;
798 spin_lock_irqsave(&port->lock, flags);
801 dmaengine_terminate_all(chan);
802 xmit->tail += atmel_port->tx_len;
803 xmit->tail &= UART_XMIT_SIZE - 1;
805 port->icount.tx += atmel_port->tx_len;
807 spin_lock_irq(&atmel_port->lock_tx);
808 async_tx_ack(atmel_port->desc_tx);
809 atmel_port->cookie_tx = -EINVAL;
810 atmel_port->desc_tx = NULL;
811 spin_unlock_irq(&atmel_port->lock_tx);
813 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
814 uart_write_wakeup(port);
817 * xmit is a circular buffer so, if we have just send data from
818 * xmit->tail to the end of xmit->buf, now we have to transmit the
819 * remaining data from the beginning of xmit->buf to xmit->head.
821 if (!uart_circ_empty(xmit))
822 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
823 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
824 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
825 /* DMA done, stop TX, start RX for RS485 */
826 atmel_start_rx(port);
829 spin_unlock_irqrestore(&port->lock, flags);
832 static void atmel_release_tx_dma(struct uart_port *port)
834 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
835 struct dma_chan *chan = atmel_port->chan_tx;
838 dmaengine_terminate_all(chan);
839 dma_release_channel(chan);
840 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
844 atmel_port->desc_tx = NULL;
845 atmel_port->chan_tx = NULL;
846 atmel_port->cookie_tx = -EINVAL;
850 * Called from tasklet with TXRDY interrupt is disabled.
852 static void atmel_tx_dma(struct uart_port *port)
854 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
855 struct circ_buf *xmit = &port->state->xmit;
856 struct dma_chan *chan = atmel_port->chan_tx;
857 struct dma_async_tx_descriptor *desc;
858 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
859 unsigned int tx_len, part1_len, part2_len, sg_len;
860 dma_addr_t phys_addr;
862 /* Make sure we have an idle channel */
863 if (atmel_port->desc_tx != NULL)
866 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
869 * Port xmit buffer is already mapped,
870 * and it is one page... Just adjust
871 * offsets and lengths. Since it is a circular buffer,
872 * we have to transmit till the end, and then the rest.
873 * Take the port lock to get a
874 * consistent xmit buffer state.
876 tx_len = CIRC_CNT_TO_END(xmit->head,
880 if (atmel_port->fifo_size) {
881 /* multi data mode */
882 part1_len = (tx_len & ~0x3); /* DWORD access */
883 part2_len = (tx_len & 0x3); /* BYTE access */
885 /* single data (legacy) mode */
887 part2_len = tx_len; /* BYTE access only */
890 sg_init_table(sgl, 2);
892 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
895 sg_dma_address(sg) = phys_addr;
896 sg_dma_len(sg) = part1_len;
898 phys_addr += part1_len;
903 sg_dma_address(sg) = phys_addr;
904 sg_dma_len(sg) = part2_len;
908 * save tx_len so atmel_complete_tx_dma() will increase
909 * xmit->tail correctly
911 atmel_port->tx_len = tx_len;
913 desc = dmaengine_prep_slave_sg(chan,
920 dev_err(port->dev, "Failed to send via dma!\n");
924 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
926 atmel_port->desc_tx = desc;
927 desc->callback = atmel_complete_tx_dma;
928 desc->callback_param = atmel_port;
929 atmel_port->cookie_tx = dmaengine_submit(desc);
932 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
933 uart_write_wakeup(port);
936 static int atmel_prepare_tx_dma(struct uart_port *port)
938 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
940 struct dma_slave_config config;
944 dma_cap_set(DMA_SLAVE, mask);
946 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
947 if (atmel_port->chan_tx == NULL)
949 dev_info(port->dev, "using %s for tx DMA transfers\n",
950 dma_chan_name(atmel_port->chan_tx));
952 spin_lock_init(&atmel_port->lock_tx);
953 sg_init_table(&atmel_port->sg_tx, 1);
954 /* UART circular tx buffer is an aligned page. */
955 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
956 sg_set_page(&atmel_port->sg_tx,
957 virt_to_page(port->state->xmit.buf),
959 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
960 nent = dma_map_sg(port->dev,
966 dev_dbg(port->dev, "need to release resource of dma\n");
969 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
970 sg_dma_len(&atmel_port->sg_tx),
971 port->state->xmit.buf,
972 &sg_dma_address(&atmel_port->sg_tx));
975 /* Configure the slave DMA */
976 memset(&config, 0, sizeof(config));
977 config.direction = DMA_MEM_TO_DEV;
978 config.dst_addr_width = (atmel_port->fifo_size) ?
979 DMA_SLAVE_BUSWIDTH_4_BYTES :
980 DMA_SLAVE_BUSWIDTH_1_BYTE;
981 config.dst_addr = port->mapbase + ATMEL_US_THR;
982 config.dst_maxburst = 1;
984 ret = dmaengine_slave_config(atmel_port->chan_tx,
987 dev_err(port->dev, "DMA tx slave configuration failed\n");
994 dev_err(port->dev, "TX channel not available, switch to pio\n");
995 atmel_port->use_dma_tx = 0;
996 if (atmel_port->chan_tx)
997 atmel_release_tx_dma(port);
1001 static void atmel_complete_rx_dma(void *arg)
1003 struct uart_port *port = arg;
1004 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1006 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1009 static void atmel_release_rx_dma(struct uart_port *port)
1011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1012 struct dma_chan *chan = atmel_port->chan_rx;
1015 dmaengine_terminate_all(chan);
1016 dma_release_channel(chan);
1017 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1021 atmel_port->desc_rx = NULL;
1022 atmel_port->chan_rx = NULL;
1023 atmel_port->cookie_rx = -EINVAL;
1026 static void atmel_rx_from_dma(struct uart_port *port)
1028 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1029 struct tty_port *tport = &port->state->port;
1030 struct circ_buf *ring = &atmel_port->rx_ring;
1031 struct dma_chan *chan = atmel_port->chan_rx;
1032 struct dma_tx_state state;
1033 enum dma_status dmastat;
1037 /* Reset the UART timeout early so that we don't miss one */
1038 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1039 dmastat = dmaengine_tx_status(chan,
1040 atmel_port->cookie_rx,
1042 /* Restart a new tasklet if DMA status is error */
1043 if (dmastat == DMA_ERROR) {
1044 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1045 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1046 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1050 /* CPU claims ownership of RX DMA buffer */
1051 dma_sync_sg_for_cpu(port->dev,
1057 * ring->head points to the end of data already written by the DMA.
1058 * ring->tail points to the beginning of data to be read by the
1060 * The current transfer size should not be larger than the dma buffer
1063 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1064 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1066 * At this point ring->head may point to the first byte right after the
1067 * last byte of the dma buffer:
1068 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1070 * However ring->tail must always points inside the dma buffer:
1071 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1073 * Since we use a ring buffer, we have to handle the case
1074 * where head is lower than tail. In such a case, we first read from
1075 * tail to the end of the buffer then reset tail.
1077 if (ring->head < ring->tail) {
1078 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1080 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1082 port->icount.rx += count;
1085 /* Finally we read data from tail to head */
1086 if (ring->tail < ring->head) {
1087 count = ring->head - ring->tail;
1089 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1090 /* Wrap ring->head if needed */
1091 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1093 ring->tail = ring->head;
1094 port->icount.rx += count;
1097 /* USART retreives ownership of RX DMA buffer */
1098 dma_sync_sg_for_device(port->dev,
1104 * Drop the lock here since it might end up calling
1105 * uart_start(), which takes the lock.
1107 spin_unlock(&port->lock);
1108 tty_flip_buffer_push(tport);
1109 spin_lock(&port->lock);
1111 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1114 static int atmel_prepare_rx_dma(struct uart_port *port)
1116 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1117 struct dma_async_tx_descriptor *desc;
1118 dma_cap_mask_t mask;
1119 struct dma_slave_config config;
1120 struct circ_buf *ring;
1123 ring = &atmel_port->rx_ring;
1126 dma_cap_set(DMA_CYCLIC, mask);
1128 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1129 if (atmel_port->chan_rx == NULL)
1131 dev_info(port->dev, "using %s for rx DMA transfers\n",
1132 dma_chan_name(atmel_port->chan_rx));
1134 spin_lock_init(&atmel_port->lock_rx);
1135 sg_init_table(&atmel_port->sg_rx, 1);
1136 /* UART circular rx buffer is an aligned page. */
1137 BUG_ON(!PAGE_ALIGNED(ring->buf));
1138 sg_set_page(&atmel_port->sg_rx,
1139 virt_to_page(ring->buf),
1140 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1141 (unsigned long)ring->buf & ~PAGE_MASK);
1142 nent = dma_map_sg(port->dev,
1148 dev_dbg(port->dev, "need to release resource of dma\n");
1151 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1152 sg_dma_len(&atmel_port->sg_rx),
1154 &sg_dma_address(&atmel_port->sg_rx));
1157 /* Configure the slave DMA */
1158 memset(&config, 0, sizeof(config));
1159 config.direction = DMA_DEV_TO_MEM;
1160 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1161 config.src_addr = port->mapbase + ATMEL_US_RHR;
1162 config.src_maxburst = 1;
1164 ret = dmaengine_slave_config(atmel_port->chan_rx,
1167 dev_err(port->dev, "DMA rx slave configuration failed\n");
1171 * Prepare a cyclic dma transfer, assign 2 descriptors,
1172 * each one is half ring buffer size
1174 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1175 sg_dma_address(&atmel_port->sg_rx),
1176 sg_dma_len(&atmel_port->sg_rx),
1177 sg_dma_len(&atmel_port->sg_rx)/2,
1179 DMA_PREP_INTERRUPT);
1180 desc->callback = atmel_complete_rx_dma;
1181 desc->callback_param = port;
1182 atmel_port->desc_rx = desc;
1183 atmel_port->cookie_rx = dmaengine_submit(desc);
1188 dev_err(port->dev, "RX channel not available, switch to pio\n");
1189 atmel_port->use_dma_rx = 0;
1190 if (atmel_port->chan_rx)
1191 atmel_release_rx_dma(port);
1195 static void atmel_uart_timer_callback(unsigned long data)
1197 struct uart_port *port = (void *)data;
1198 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1200 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1201 tasklet_schedule(&atmel_port->tasklet_rx);
1202 mod_timer(&atmel_port->uart_timer,
1203 jiffies + uart_poll_timeout(port));
1208 * receive interrupt handler.
1211 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1213 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1215 if (atmel_use_pdc_rx(port)) {
1217 * PDC receive. Just schedule the tasklet and let it
1218 * figure out the details.
1220 * TODO: We're not handling error flags correctly at
1223 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1224 atmel_uart_writel(port, ATMEL_US_IDR,
1225 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1226 atmel_tasklet_schedule(atmel_port,
1227 &atmel_port->tasklet_rx);
1230 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1231 ATMEL_US_FRAME | ATMEL_US_PARE))
1232 atmel_pdc_rxerr(port, pending);
1235 if (atmel_use_dma_rx(port)) {
1236 if (pending & ATMEL_US_TIMEOUT) {
1237 atmel_uart_writel(port, ATMEL_US_IDR,
1239 atmel_tasklet_schedule(atmel_port,
1240 &atmel_port->tasklet_rx);
1244 /* Interrupt receive */
1245 if (pending & ATMEL_US_RXRDY)
1246 atmel_rx_chars(port);
1247 else if (pending & ATMEL_US_RXBRK) {
1249 * End of break detected. If it came along with a
1250 * character, atmel_rx_chars will handle it.
1252 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1253 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1254 atmel_port->break_active = 0;
1259 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1262 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1266 if (pending & atmel_port->tx_done_mask) {
1267 /* Either PDC or interrupt transmission */
1268 atmel_uart_writel(port, ATMEL_US_IDR,
1269 atmel_port->tx_done_mask);
1270 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1275 * status flags interrupt handler.
1278 atmel_handle_status(struct uart_port *port, unsigned int pending,
1279 unsigned int status)
1281 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1282 unsigned int status_change;
1284 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1285 | ATMEL_US_CTSIC)) {
1286 status_change = status ^ atmel_port->irq_status_prev;
1287 atmel_port->irq_status_prev = status;
1289 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1290 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1291 /* TODO: All reads to CSR will clear these interrupts! */
1292 if (status_change & ATMEL_US_RI)
1294 if (status_change & ATMEL_US_DSR)
1296 if (status_change & ATMEL_US_DCD)
1297 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1298 if (status_change & ATMEL_US_CTS)
1299 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1301 wake_up_interruptible(&port->state->port.delta_msr_wait);
1309 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1311 struct uart_port *port = dev_id;
1312 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1313 unsigned int status, pending, mask, pass_counter = 0;
1315 spin_lock(&atmel_port->lock_suspended);
1318 status = atmel_get_lines_status(port);
1319 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1320 pending = status & mask;
1324 if (atmel_port->suspended) {
1325 atmel_port->pending |= pending;
1326 atmel_port->pending_status = status;
1327 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1332 atmel_handle_receive(port, pending);
1333 atmel_handle_status(port, pending, status);
1334 atmel_handle_transmit(port, pending);
1335 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1337 spin_unlock(&atmel_port->lock_suspended);
1339 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1342 static void atmel_release_tx_pdc(struct uart_port *port)
1344 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1345 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1347 dma_unmap_single(port->dev,
1354 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1356 static void atmel_tx_pdc(struct uart_port *port)
1358 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1359 struct circ_buf *xmit = &port->state->xmit;
1360 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1363 /* nothing left to transmit? */
1364 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1367 xmit->tail += pdc->ofs;
1368 xmit->tail &= UART_XMIT_SIZE - 1;
1370 port->icount.tx += pdc->ofs;
1373 /* more to transmit - setup next transfer */
1375 /* disable PDC transmit */
1376 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1378 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1379 dma_sync_single_for_device(port->dev,
1384 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1387 atmel_uart_writel(port, ATMEL_PDC_TPR,
1388 pdc->dma_addr + xmit->tail);
1389 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1390 /* re-enable PDC transmit */
1391 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1392 /* Enable interrupts */
1393 atmel_uart_writel(port, ATMEL_US_IER,
1394 atmel_port->tx_done_mask);
1396 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1397 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1398 /* DMA done, stop TX, start RX for RS485 */
1399 atmel_start_rx(port);
1403 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1404 uart_write_wakeup(port);
1407 static int atmel_prepare_tx_pdc(struct uart_port *port)
1409 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1410 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1411 struct circ_buf *xmit = &port->state->xmit;
1413 pdc->buf = xmit->buf;
1414 pdc->dma_addr = dma_map_single(port->dev,
1418 pdc->dma_size = UART_XMIT_SIZE;
1424 static void atmel_rx_from_ring(struct uart_port *port)
1426 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1427 struct circ_buf *ring = &atmel_port->rx_ring;
1429 unsigned int status;
1431 while (ring->head != ring->tail) {
1432 struct atmel_uart_char c;
1434 /* Make sure c is loaded after head. */
1437 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1439 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1446 * note that the error handling code is
1447 * out of the main execution path
1449 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1450 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1451 if (status & ATMEL_US_RXBRK) {
1452 /* ignore side-effect */
1453 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1456 if (uart_handle_break(port))
1459 if (status & ATMEL_US_PARE)
1460 port->icount.parity++;
1461 if (status & ATMEL_US_FRAME)
1462 port->icount.frame++;
1463 if (status & ATMEL_US_OVRE)
1464 port->icount.overrun++;
1466 status &= port->read_status_mask;
1468 if (status & ATMEL_US_RXBRK)
1470 else if (status & ATMEL_US_PARE)
1472 else if (status & ATMEL_US_FRAME)
1477 if (uart_handle_sysrq_char(port, c.ch))
1480 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1484 * Drop the lock here since it might end up calling
1485 * uart_start(), which takes the lock.
1487 spin_unlock(&port->lock);
1488 tty_flip_buffer_push(&port->state->port);
1489 spin_lock(&port->lock);
1492 static void atmel_release_rx_pdc(struct uart_port *port)
1494 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1497 for (i = 0; i < 2; i++) {
1498 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1500 dma_unmap_single(port->dev,
1508 static void atmel_rx_from_pdc(struct uart_port *port)
1510 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1511 struct tty_port *tport = &port->state->port;
1512 struct atmel_dma_buffer *pdc;
1513 int rx_idx = atmel_port->pdc_rx_idx;
1519 /* Reset the UART timeout early so that we don't miss one */
1520 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1522 pdc = &atmel_port->pdc_rx[rx_idx];
1523 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1526 /* If the PDC has switched buffers, RPR won't contain
1527 * any address within the current buffer. Since head
1528 * is unsigned, we just need a one-way comparison to
1531 * In this case, we just need to consume the entire
1532 * buffer and resubmit it for DMA. This will clear the
1533 * ENDRX bit as well, so that we can safely re-enable
1534 * all interrupts below.
1536 head = min(head, pdc->dma_size);
1538 if (likely(head != tail)) {
1539 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1540 pdc->dma_size, DMA_FROM_DEVICE);
1543 * head will only wrap around when we recycle
1544 * the DMA buffer, and when that happens, we
1545 * explicitly set tail to 0. So head will
1546 * always be greater than tail.
1548 count = head - tail;
1550 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1553 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1554 pdc->dma_size, DMA_FROM_DEVICE);
1556 port->icount.rx += count;
1561 * If the current buffer is full, we need to check if
1562 * the next one contains any additional data.
1564 if (head >= pdc->dma_size) {
1566 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1567 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1570 atmel_port->pdc_rx_idx = rx_idx;
1572 } while (head >= pdc->dma_size);
1575 * Drop the lock here since it might end up calling
1576 * uart_start(), which takes the lock.
1578 spin_unlock(&port->lock);
1579 tty_flip_buffer_push(tport);
1580 spin_lock(&port->lock);
1582 atmel_uart_writel(port, ATMEL_US_IER,
1583 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1586 static int atmel_prepare_rx_pdc(struct uart_port *port)
1588 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1591 for (i = 0; i < 2; i++) {
1592 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1594 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1595 if (pdc->buf == NULL) {
1597 dma_unmap_single(port->dev,
1598 atmel_port->pdc_rx[0].dma_addr,
1601 kfree(atmel_port->pdc_rx[0].buf);
1603 atmel_port->use_pdc_rx = 0;
1606 pdc->dma_addr = dma_map_single(port->dev,
1610 pdc->dma_size = PDC_BUFFER_SIZE;
1614 atmel_port->pdc_rx_idx = 0;
1616 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1617 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1619 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1620 atmel_port->pdc_rx[1].dma_addr);
1621 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1627 * tasklet handling tty stuff outside the interrupt handler.
1629 static void atmel_tasklet_rx_func(unsigned long data)
1631 struct uart_port *port = (struct uart_port *)data;
1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1634 /* The interrupt handler does not take the lock */
1635 spin_lock(&port->lock);
1636 atmel_port->schedule_rx(port);
1637 spin_unlock(&port->lock);
1640 static void atmel_tasklet_tx_func(unsigned long data)
1642 struct uart_port *port = (struct uart_port *)data;
1643 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1645 /* The interrupt handler does not take the lock */
1646 spin_lock(&port->lock);
1647 atmel_port->schedule_tx(port);
1648 spin_unlock(&port->lock);
1651 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1652 struct platform_device *pdev)
1654 struct device_node *np = pdev->dev.of_node;
1655 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1658 /* DMA/PDC usage specification */
1659 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1660 if (of_property_read_bool(np, "dmas")) {
1661 atmel_port->use_dma_rx = true;
1662 atmel_port->use_pdc_rx = false;
1664 atmel_port->use_dma_rx = false;
1665 atmel_port->use_pdc_rx = true;
1668 atmel_port->use_dma_rx = false;
1669 atmel_port->use_pdc_rx = false;
1672 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1673 if (of_property_read_bool(np, "dmas")) {
1674 atmel_port->use_dma_tx = true;
1675 atmel_port->use_pdc_tx = false;
1677 atmel_port->use_dma_tx = false;
1678 atmel_port->use_pdc_tx = true;
1681 atmel_port->use_dma_tx = false;
1682 atmel_port->use_pdc_tx = false;
1686 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1687 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1688 atmel_port->use_dma_rx = false;
1689 atmel_port->use_dma_tx = false;
1694 static void atmel_init_rs485(struct uart_port *port,
1695 struct platform_device *pdev)
1697 struct device_node *np = pdev->dev.of_node;
1698 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1701 struct serial_rs485 *rs485conf = &port->rs485;
1703 /* rs485 properties */
1704 if (of_property_read_u32_array(np, "rs485-rts-delay",
1705 rs485_delay, 2) == 0) {
1706 rs485conf->delay_rts_before_send = rs485_delay[0];
1707 rs485conf->delay_rts_after_send = rs485_delay[1];
1708 rs485conf->flags = 0;
1711 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1712 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1714 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1716 rs485conf->flags |= SER_RS485_ENABLED;
1718 port->rs485 = pdata->rs485;
1723 static void atmel_set_ops(struct uart_port *port)
1725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1727 if (atmel_use_dma_rx(port)) {
1728 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1729 atmel_port->schedule_rx = &atmel_rx_from_dma;
1730 atmel_port->release_rx = &atmel_release_rx_dma;
1731 } else if (atmel_use_pdc_rx(port)) {
1732 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1733 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1734 atmel_port->release_rx = &atmel_release_rx_pdc;
1736 atmel_port->prepare_rx = NULL;
1737 atmel_port->schedule_rx = &atmel_rx_from_ring;
1738 atmel_port->release_rx = NULL;
1741 if (atmel_use_dma_tx(port)) {
1742 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1743 atmel_port->schedule_tx = &atmel_tx_dma;
1744 atmel_port->release_tx = &atmel_release_tx_dma;
1745 } else if (atmel_use_pdc_tx(port)) {
1746 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1747 atmel_port->schedule_tx = &atmel_tx_pdc;
1748 atmel_port->release_tx = &atmel_release_tx_pdc;
1750 atmel_port->prepare_tx = NULL;
1751 atmel_port->schedule_tx = &atmel_tx_chars;
1752 atmel_port->release_tx = NULL;
1757 * Get ip name usart or uart
1759 static void atmel_get_ip_name(struct uart_port *port)
1761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1762 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1764 u32 usart, dbgu_uart, new_uart;
1765 /* ASCII decoding for IP version */
1766 usart = 0x55534152; /* USAR(T) */
1767 dbgu_uart = 0x44424755; /* DBGU */
1768 new_uart = 0x55415254; /* UART */
1771 * Only USART devices from at91sam9260 SOC implement fractional
1772 * baudrate. It is available for all asynchronous modes, with the
1773 * following restriction: the sampling clock's duty cycle is not
1776 atmel_port->has_frac_baudrate = false;
1777 atmel_port->has_hw_timer = false;
1779 if (name == new_uart) {
1780 dev_dbg(port->dev, "Uart with hw timer");
1781 atmel_port->has_hw_timer = true;
1782 atmel_port->rtor = ATMEL_UA_RTOR;
1783 } else if (name == usart) {
1784 dev_dbg(port->dev, "Usart\n");
1785 atmel_port->has_frac_baudrate = true;
1786 atmel_port->has_hw_timer = true;
1787 atmel_port->rtor = ATMEL_US_RTOR;
1788 } else if (name == dbgu_uart) {
1789 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1791 /* fallback for older SoCs: use version field */
1792 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1796 dev_dbg(port->dev, "This version is usart\n");
1797 atmel_port->has_frac_baudrate = true;
1798 atmel_port->has_hw_timer = true;
1799 atmel_port->rtor = ATMEL_US_RTOR;
1803 dev_dbg(port->dev, "This version is uart\n");
1806 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1812 * Perform initialization and enable port for reception
1814 static int atmel_startup(struct uart_port *port)
1816 struct platform_device *pdev = to_platform_device(port->dev);
1817 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1818 struct tty_struct *tty = port->state->port.tty;
1822 * Ensure that no interrupts are enabled otherwise when
1823 * request_irq() is called we could get stuck trying to
1824 * handle an unexpected interrupt
1826 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1827 atmel_port->ms_irq_enabled = false;
1832 retval = request_irq(port->irq, atmel_interrupt,
1833 IRQF_SHARED | IRQF_COND_SUSPEND,
1834 tty ? tty->name : "atmel_serial", port);
1836 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1840 atomic_set(&atmel_port->tasklet_shutdown, 0);
1841 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1842 (unsigned long)port);
1843 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1844 (unsigned long)port);
1847 * Initialize DMA (if necessary)
1849 atmel_init_property(atmel_port, pdev);
1850 atmel_set_ops(port);
1852 if (atmel_port->prepare_rx) {
1853 retval = atmel_port->prepare_rx(port);
1855 atmel_set_ops(port);
1858 if (atmel_port->prepare_tx) {
1859 retval = atmel_port->prepare_tx(port);
1861 atmel_set_ops(port);
1865 * Enable FIFO when available
1867 if (atmel_port->fifo_size) {
1868 unsigned int txrdym = ATMEL_US_ONE_DATA;
1869 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1872 atmel_uart_writel(port, ATMEL_US_CR,
1877 if (atmel_use_dma_tx(port))
1878 txrdym = ATMEL_US_FOUR_DATA;
1880 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1881 if (atmel_port->rts_high &&
1882 atmel_port->rts_low)
1883 fmr |= ATMEL_US_FRTSC |
1884 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1885 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1887 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1890 /* Save current CSR for comparison in atmel_tasklet_func() */
1891 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1894 * Finally, enable the serial port
1896 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1897 /* enable xmit & rcvr */
1898 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1900 setup_timer(&atmel_port->uart_timer,
1901 atmel_uart_timer_callback,
1902 (unsigned long)port);
1904 if (atmel_use_pdc_rx(port)) {
1905 /* set UART timeout */
1906 if (!atmel_port->has_hw_timer) {
1907 mod_timer(&atmel_port->uart_timer,
1908 jiffies + uart_poll_timeout(port));
1909 /* set USART timeout */
1911 atmel_uart_writel(port, atmel_port->rtor,
1913 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1915 atmel_uart_writel(port, ATMEL_US_IER,
1916 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1918 /* enable PDC controller */
1919 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1920 } else if (atmel_use_dma_rx(port)) {
1921 /* set UART timeout */
1922 if (!atmel_port->has_hw_timer) {
1923 mod_timer(&atmel_port->uart_timer,
1924 jiffies + uart_poll_timeout(port));
1925 /* set USART timeout */
1927 atmel_uart_writel(port, atmel_port->rtor,
1929 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1931 atmel_uart_writel(port, ATMEL_US_IER,
1935 /* enable receive only */
1936 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1943 * Flush any TX data submitted for DMA. Called when the TX circular
1946 static void atmel_flush_buffer(struct uart_port *port)
1948 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1950 if (atmel_use_pdc_tx(port)) {
1951 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1952 atmel_port->pdc_tx.ofs = 0;
1959 static void atmel_shutdown(struct uart_port *port)
1961 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1963 /* Disable modem control lines interrupts */
1964 atmel_disable_ms(port);
1966 /* Disable interrupts at device level */
1967 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1969 /* Prevent spurious interrupts from scheduling the tasklet */
1970 atomic_inc(&atmel_port->tasklet_shutdown);
1973 * Prevent any tasklets being scheduled during
1976 del_timer_sync(&atmel_port->uart_timer);
1978 /* Make sure that no interrupt is on the fly */
1979 synchronize_irq(port->irq);
1982 * Clear out any scheduled tasklets before
1983 * we destroy the buffers
1985 tasklet_kill(&atmel_port->tasklet_rx);
1986 tasklet_kill(&atmel_port->tasklet_tx);
1989 * Ensure everything is stopped and
1990 * disable port and break condition.
1992 atmel_stop_rx(port);
1993 atmel_stop_tx(port);
1995 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1998 * Shut-down the DMA.
2000 if (atmel_port->release_rx)
2001 atmel_port->release_rx(port);
2002 if (atmel_port->release_tx)
2003 atmel_port->release_tx(port);
2006 * Reset ring buffer pointers
2008 atmel_port->rx_ring.head = 0;
2009 atmel_port->rx_ring.tail = 0;
2012 * Free the interrupts
2014 free_irq(port->irq, port);
2016 atmel_flush_buffer(port);
2020 * Power / Clock management.
2022 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2023 unsigned int oldstate)
2025 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2030 * Enable the peripheral clock for this serial port.
2031 * This is called on uart_open() or a resume event.
2033 clk_prepare_enable(atmel_port->clk);
2035 /* re-enable interrupts if we disabled some on suspend */
2036 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2039 /* Back up the interrupt mask and disable all interrupts */
2040 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2041 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2044 * Disable the peripheral clock for this serial port.
2045 * This is called on uart_close() or a suspend event.
2047 clk_disable_unprepare(atmel_port->clk);
2050 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2055 * Change the port parameters
2057 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2058 struct ktermios *old)
2060 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2061 unsigned long flags;
2062 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2064 /* save the current mode register */
2065 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2067 /* reset the mode, clock divisor, parity, stop bits and data size */
2068 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2069 ATMEL_US_PAR | ATMEL_US_USMODE);
2071 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2074 switch (termios->c_cflag & CSIZE) {
2076 mode |= ATMEL_US_CHRL_5;
2079 mode |= ATMEL_US_CHRL_6;
2082 mode |= ATMEL_US_CHRL_7;
2085 mode |= ATMEL_US_CHRL_8;
2090 if (termios->c_cflag & CSTOPB)
2091 mode |= ATMEL_US_NBSTOP_2;
2094 if (termios->c_cflag & PARENB) {
2095 /* Mark or Space parity */
2096 if (termios->c_cflag & CMSPAR) {
2097 if (termios->c_cflag & PARODD)
2098 mode |= ATMEL_US_PAR_MARK;
2100 mode |= ATMEL_US_PAR_SPACE;
2101 } else if (termios->c_cflag & PARODD)
2102 mode |= ATMEL_US_PAR_ODD;
2104 mode |= ATMEL_US_PAR_EVEN;
2106 mode |= ATMEL_US_PAR_NONE;
2108 spin_lock_irqsave(&port->lock, flags);
2110 port->read_status_mask = ATMEL_US_OVRE;
2111 if (termios->c_iflag & INPCK)
2112 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2113 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2114 port->read_status_mask |= ATMEL_US_RXBRK;
2116 if (atmel_use_pdc_rx(port))
2117 /* need to enable error interrupts */
2118 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2121 * Characters to ignore
2123 port->ignore_status_mask = 0;
2124 if (termios->c_iflag & IGNPAR)
2125 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2126 if (termios->c_iflag & IGNBRK) {
2127 port->ignore_status_mask |= ATMEL_US_RXBRK;
2129 * If we're ignoring parity and break indicators,
2130 * ignore overruns too (for real raw support).
2132 if (termios->c_iflag & IGNPAR)
2133 port->ignore_status_mask |= ATMEL_US_OVRE;
2135 /* TODO: Ignore all characters if CREAD is set.*/
2137 /* update the per-port timeout */
2138 uart_update_timeout(port, termios->c_cflag, baud);
2141 * save/disable interrupts. The tty layer will ensure that the
2142 * transmitter is empty if requested by the caller, so there's
2143 * no need to wait for it here.
2145 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2146 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2148 /* disable receiver and transmitter */
2149 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2152 if (port->rs485.flags & SER_RS485_ENABLED) {
2153 atmel_uart_writel(port, ATMEL_US_TTGR,
2154 port->rs485.delay_rts_after_send);
2155 mode |= ATMEL_US_USMODE_RS485;
2156 } else if (termios->c_cflag & CRTSCTS) {
2157 /* RS232 with hardware handshake (RTS/CTS) */
2158 if (atmel_use_fifo(port) &&
2159 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2161 * with ATMEL_US_USMODE_HWHS set, the controller will
2162 * be able to drive the RTS pin high/low when the RX
2163 * FIFO is above RXFTHRES/below RXFTHRES2.
2164 * It will also disable the transmitter when the CTS
2166 * This mode is not activated if CTS pin is a GPIO
2167 * because in this case, the transmitter is always
2168 * disabled (there must be an internal pull-up
2169 * responsible for this behaviour).
2170 * If the RTS pin is a GPIO, the controller won't be
2171 * able to drive it according to the FIFO thresholds,
2172 * but it will be handled by the driver.
2174 mode |= ATMEL_US_USMODE_HWHS;
2177 * For platforms without FIFO, the flow control is
2178 * handled by the driver.
2180 mode |= ATMEL_US_USMODE_NORMAL;
2183 /* RS232 without hadware handshake */
2184 mode |= ATMEL_US_USMODE_NORMAL;
2187 /* set the mode, clock divisor, parity, stop bits and data size */
2188 atmel_uart_writel(port, ATMEL_US_MR, mode);
2191 * when switching the mode, set the RTS line state according to the
2192 * new mode, otherwise keep the former state
2194 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2195 unsigned int rts_state;
2197 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2198 /* let the hardware control the RTS line */
2199 rts_state = ATMEL_US_RTSDIS;
2201 /* force RTS line to low level */
2202 rts_state = ATMEL_US_RTSEN;
2205 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2209 * Set the baud rate:
2210 * Fractional baudrate allows to setup output frequency more
2211 * accurately. This feature is enabled only when using normal mode.
2212 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2213 * Currently, OVER is always set to 0 so we get
2214 * baudrate = selected clock / (16 * (CD + FP / 8))
2216 * 8 CD + FP = selected clock / (2 * baudrate)
2218 if (atmel_port->has_frac_baudrate) {
2219 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2221 fp = div & ATMEL_US_FP_MASK;
2223 cd = uart_get_divisor(port, baud);
2226 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2228 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2230 quot = cd | fp << ATMEL_US_FP_OFFSET;
2232 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2233 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2234 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2236 /* restore interrupts */
2237 atmel_uart_writel(port, ATMEL_US_IER, imr);
2239 /* CTS flow-control and modem-status interrupts */
2240 if (UART_ENABLE_MS(port, termios->c_cflag))
2241 atmel_enable_ms(port);
2243 atmel_disable_ms(port);
2245 spin_unlock_irqrestore(&port->lock, flags);
2248 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2250 if (termios->c_line == N_PPS) {
2251 port->flags |= UPF_HARDPPS_CD;
2252 spin_lock_irq(&port->lock);
2253 atmel_enable_ms(port);
2254 spin_unlock_irq(&port->lock);
2256 port->flags &= ~UPF_HARDPPS_CD;
2257 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2258 spin_lock_irq(&port->lock);
2259 atmel_disable_ms(port);
2260 spin_unlock_irq(&port->lock);
2266 * Return string describing the specified port
2268 static const char *atmel_type(struct uart_port *port)
2270 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2274 * Release the memory region(s) being used by 'port'.
2276 static void atmel_release_port(struct uart_port *port)
2278 struct platform_device *pdev = to_platform_device(port->dev);
2279 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2281 release_mem_region(port->mapbase, size);
2283 if (port->flags & UPF_IOREMAP) {
2284 iounmap(port->membase);
2285 port->membase = NULL;
2290 * Request the memory region(s) being used by 'port'.
2292 static int atmel_request_port(struct uart_port *port)
2294 struct platform_device *pdev = to_platform_device(port->dev);
2295 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2297 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2300 if (port->flags & UPF_IOREMAP) {
2301 port->membase = ioremap(port->mapbase, size);
2302 if (port->membase == NULL) {
2303 release_mem_region(port->mapbase, size);
2312 * Configure/autoconfigure the port.
2314 static void atmel_config_port(struct uart_port *port, int flags)
2316 if (flags & UART_CONFIG_TYPE) {
2317 port->type = PORT_ATMEL;
2318 atmel_request_port(port);
2323 * Verify the new serial_struct (for TIOCSSERIAL).
2325 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2328 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2330 if (port->irq != ser->irq)
2332 if (ser->io_type != SERIAL_IO_MEM)
2334 if (port->uartclk / 16 != ser->baud_base)
2336 if (port->mapbase != (unsigned long)ser->iomem_base)
2338 if (port->iobase != ser->port)
2345 #ifdef CONFIG_CONSOLE_POLL
2346 static int atmel_poll_get_char(struct uart_port *port)
2348 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2351 return atmel_uart_read_char(port);
2354 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2356 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2359 atmel_uart_write_char(port, ch);
2363 static const struct uart_ops atmel_pops = {
2364 .tx_empty = atmel_tx_empty,
2365 .set_mctrl = atmel_set_mctrl,
2366 .get_mctrl = atmel_get_mctrl,
2367 .stop_tx = atmel_stop_tx,
2368 .start_tx = atmel_start_tx,
2369 .stop_rx = atmel_stop_rx,
2370 .enable_ms = atmel_enable_ms,
2371 .break_ctl = atmel_break_ctl,
2372 .startup = atmel_startup,
2373 .shutdown = atmel_shutdown,
2374 .flush_buffer = atmel_flush_buffer,
2375 .set_termios = atmel_set_termios,
2376 .set_ldisc = atmel_set_ldisc,
2378 .release_port = atmel_release_port,
2379 .request_port = atmel_request_port,
2380 .config_port = atmel_config_port,
2381 .verify_port = atmel_verify_port,
2382 .pm = atmel_serial_pm,
2383 #ifdef CONFIG_CONSOLE_POLL
2384 .poll_get_char = atmel_poll_get_char,
2385 .poll_put_char = atmel_poll_put_char,
2390 * Configure the port from the platform device resource info.
2392 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2393 struct platform_device *pdev)
2396 struct uart_port *port = &atmel_port->uart;
2397 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2399 atmel_init_property(atmel_port, pdev);
2400 atmel_set_ops(port);
2402 atmel_init_rs485(port, pdev);
2404 port->iotype = UPIO_MEM;
2405 port->flags = UPF_BOOT_AUTOCONF;
2406 port->ops = &atmel_pops;
2408 port->dev = &pdev->dev;
2409 port->mapbase = pdev->resource[0].start;
2410 port->irq = pdev->resource[1].start;
2411 port->rs485_config = atmel_config_rs485;
2413 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2415 if (pdata && pdata->regs) {
2416 /* Already mapped by setup code */
2417 port->membase = pdata->regs;
2419 port->flags |= UPF_IOREMAP;
2420 port->membase = NULL;
2423 /* for console, the clock could already be configured */
2424 if (!atmel_port->clk) {
2425 atmel_port->clk = clk_get(&pdev->dev, "usart");
2426 if (IS_ERR(atmel_port->clk)) {
2427 ret = PTR_ERR(atmel_port->clk);
2428 atmel_port->clk = NULL;
2431 ret = clk_prepare_enable(atmel_port->clk);
2433 clk_put(atmel_port->clk);
2434 atmel_port->clk = NULL;
2437 port->uartclk = clk_get_rate(atmel_port->clk);
2438 clk_disable_unprepare(atmel_port->clk);
2439 /* only enable clock when USART is in use */
2442 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2443 if (port->rs485.flags & SER_RS485_ENABLED)
2444 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2445 else if (atmel_use_pdc_tx(port)) {
2446 port->fifosize = PDC_BUFFER_SIZE;
2447 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2449 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2455 struct platform_device *atmel_default_console_device; /* the serial console device */
2457 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2458 static void atmel_console_putchar(struct uart_port *port, int ch)
2460 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2462 atmel_uart_write_char(port, ch);
2466 * Interrupts are disabled on entering
2468 static void atmel_console_write(struct console *co, const char *s, u_int count)
2470 struct uart_port *port = &atmel_ports[co->index].uart;
2471 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2472 unsigned int status, imr;
2473 unsigned int pdc_tx;
2476 * First, save IMR and then disable interrupts
2478 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2479 atmel_uart_writel(port, ATMEL_US_IDR,
2480 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2482 /* Store PDC transmit status and disable it */
2483 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2484 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2486 uart_console_write(port, s, count, atmel_console_putchar);
2489 * Finally, wait for transmitter to become empty
2493 status = atmel_uart_readl(port, ATMEL_US_CSR);
2494 } while (!(status & ATMEL_US_TXRDY));
2496 /* Restore PDC transmit status */
2498 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2500 /* set interrupts back the way they were */
2501 atmel_uart_writel(port, ATMEL_US_IER, imr);
2505 * If the port was already initialised (eg, by a boot loader),
2506 * try to determine the current setup.
2508 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2509 int *parity, int *bits)
2511 unsigned int mr, quot;
2514 * If the baud rate generator isn't running, the port wasn't
2515 * initialized by the boot loader.
2517 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2521 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2522 if (mr == ATMEL_US_CHRL_8)
2527 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2528 if (mr == ATMEL_US_PAR_EVEN)
2530 else if (mr == ATMEL_US_PAR_ODD)
2534 * The serial core only rounds down when matching this to a
2535 * supported baud rate. Make sure we don't end up slightly
2536 * lower than one of those, as it would make us fall through
2537 * to a much lower baud rate than we really want.
2539 *baud = port->uartclk / (16 * (quot - 1));
2542 static int __init atmel_console_setup(struct console *co, char *options)
2545 struct uart_port *port = &atmel_ports[co->index].uart;
2551 if (port->membase == NULL) {
2552 /* Port not initialized yet - delay setup */
2556 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2560 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2561 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2562 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2565 uart_parse_options(options, &baud, &parity, &bits, &flow);
2567 atmel_console_get_options(port, &baud, &parity, &bits);
2569 return uart_set_options(port, co, baud, parity, bits, flow);
2572 static struct uart_driver atmel_uart;
2574 static struct console atmel_console = {
2575 .name = ATMEL_DEVICENAME,
2576 .write = atmel_console_write,
2577 .device = uart_console_device,
2578 .setup = atmel_console_setup,
2579 .flags = CON_PRINTBUFFER,
2581 .data = &atmel_uart,
2584 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2587 * Early console initialization (before VM subsystem initialized).
2589 static int __init atmel_console_init(void)
2592 if (atmel_default_console_device) {
2593 struct atmel_uart_data *pdata =
2594 dev_get_platdata(&atmel_default_console_device->dev);
2595 int id = pdata->num;
2596 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2598 atmel_port->backup_imr = 0;
2599 atmel_port->uart.line = id;
2601 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2602 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2605 register_console(&atmel_console);
2611 console_initcall(atmel_console_init);
2614 * Late console initialization.
2616 static int __init atmel_late_console_init(void)
2618 if (atmel_default_console_device
2619 && !(atmel_console.flags & CON_ENABLED))
2620 register_console(&atmel_console);
2625 core_initcall(atmel_late_console_init);
2627 static inline bool atmel_is_console_port(struct uart_port *port)
2629 return port->cons && port->cons->index == port->line;
2633 #define ATMEL_CONSOLE_DEVICE NULL
2635 static inline bool atmel_is_console_port(struct uart_port *port)
2641 static struct uart_driver atmel_uart = {
2642 .owner = THIS_MODULE,
2643 .driver_name = "atmel_serial",
2644 .dev_name = ATMEL_DEVICENAME,
2645 .major = SERIAL_ATMEL_MAJOR,
2646 .minor = MINOR_START,
2647 .nr = ATMEL_MAX_UART,
2648 .cons = ATMEL_CONSOLE_DEVICE,
2652 static bool atmel_serial_clk_will_stop(void)
2654 #ifdef CONFIG_ARCH_AT91
2655 return at91_suspend_entering_slow_clock();
2661 static int atmel_serial_suspend(struct platform_device *pdev,
2664 struct uart_port *port = platform_get_drvdata(pdev);
2665 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2667 if (atmel_is_console_port(port) && console_suspend_enabled) {
2668 /* Drain the TX shifter */
2669 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2674 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2675 /* Cache register values as we won't get a full shutdown/startup
2678 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2679 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2680 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2681 atmel_port->cache.rtor = atmel_uart_readl(port,
2683 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2684 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2685 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2688 /* we can not wake up if we're running on slow clock */
2689 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2690 if (atmel_serial_clk_will_stop()) {
2691 unsigned long flags;
2693 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2694 atmel_port->suspended = true;
2695 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2696 device_set_wakeup_enable(&pdev->dev, 0);
2699 uart_suspend_port(&atmel_uart, port);
2704 static int atmel_serial_resume(struct platform_device *pdev)
2706 struct uart_port *port = platform_get_drvdata(pdev);
2707 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2708 unsigned long flags;
2710 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2711 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2712 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2713 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2714 atmel_uart_writel(port, atmel_port->rtor,
2715 atmel_port->cache.rtor);
2716 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2718 if (atmel_port->fifo_size) {
2719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2720 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2721 atmel_uart_writel(port, ATMEL_US_FMR,
2722 atmel_port->cache.fmr);
2723 atmel_uart_writel(port, ATMEL_US_FIER,
2724 atmel_port->cache.fimr);
2726 atmel_start_rx(port);
2729 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2730 if (atmel_port->pending) {
2731 atmel_handle_receive(port, atmel_port->pending);
2732 atmel_handle_status(port, atmel_port->pending,
2733 atmel_port->pending_status);
2734 atmel_handle_transmit(port, atmel_port->pending);
2735 atmel_port->pending = 0;
2737 atmel_port->suspended = false;
2738 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2740 uart_resume_port(&atmel_uart, port);
2741 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2746 #define atmel_serial_suspend NULL
2747 #define atmel_serial_resume NULL
2750 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2751 struct platform_device *pdev)
2753 atmel_port->fifo_size = 0;
2754 atmel_port->rts_low = 0;
2755 atmel_port->rts_high = 0;
2757 if (of_property_read_u32(pdev->dev.of_node,
2759 &atmel_port->fifo_size))
2762 if (!atmel_port->fifo_size)
2765 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2766 atmel_port->fifo_size = 0;
2767 dev_err(&pdev->dev, "Invalid FIFO size\n");
2772 * 0 <= rts_low <= rts_high <= fifo_size
2773 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2774 * to flush their internal TX FIFO, commonly up to 16 data, before
2775 * actually stopping to send new data. So we try to set the RTS High
2776 * Threshold to a reasonably high value respecting this 16 data
2777 * empirical rule when possible.
2779 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2780 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2781 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2782 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2784 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2785 atmel_port->fifo_size);
2786 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2787 atmel_port->rts_high);
2788 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2789 atmel_port->rts_low);
2792 static int atmel_serial_probe(struct platform_device *pdev)
2794 struct atmel_uart_port *atmel_port;
2795 struct device_node *np = pdev->dev.of_node;
2796 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2801 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2804 ret = of_alias_get_id(np, "serial");
2810 /* port id not found in platform data nor device-tree aliases:
2811 * auto-enumerate it */
2812 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2814 if (ret >= ATMEL_MAX_UART) {
2819 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2820 /* port already in use */
2825 atmel_port = &atmel_ports[ret];
2826 atmel_port->backup_imr = 0;
2827 atmel_port->uart.line = ret;
2828 atmel_serial_probe_fifos(atmel_port, pdev);
2830 atomic_set(&atmel_port->tasklet_shutdown, 0);
2831 spin_lock_init(&atmel_port->lock_suspended);
2833 ret = atmel_init_port(atmel_port, pdev);
2837 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2838 if (IS_ERR(atmel_port->gpios)) {
2839 ret = PTR_ERR(atmel_port->gpios);
2843 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2845 data = kmalloc(sizeof(struct atmel_uart_char)
2846 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2848 goto err_alloc_ring;
2849 atmel_port->rx_ring.buf = data;
2852 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2854 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2858 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2859 if (atmel_is_console_port(&atmel_port->uart)
2860 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2862 * The serial core enabled the clock for us, so undo
2863 * the clk_prepare_enable() in atmel_console_setup()
2865 clk_disable_unprepare(atmel_port->clk);
2869 device_init_wakeup(&pdev->dev, 1);
2870 platform_set_drvdata(pdev, atmel_port);
2873 * The peripheral clock has been disabled by atmel_init_port():
2874 * enable it before accessing I/O registers
2876 clk_prepare_enable(atmel_port->clk);
2878 if (rs485_enabled) {
2879 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2880 ATMEL_US_USMODE_NORMAL);
2881 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2886 * Get port name of usart or uart
2888 atmel_get_ip_name(&atmel_port->uart);
2891 * The peripheral clock can now safely be disabled till the port
2894 clk_disable_unprepare(atmel_port->clk);
2899 kfree(atmel_port->rx_ring.buf);
2900 atmel_port->rx_ring.buf = NULL;
2902 if (!atmel_is_console_port(&atmel_port->uart)) {
2903 clk_put(atmel_port->clk);
2904 atmel_port->clk = NULL;
2907 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2913 * Even if the driver is not modular, it makes sense to be able to
2914 * unbind a device: there can be many bound devices, and there are
2915 * situations where dynamic binding and unbinding can be useful.
2917 * For example, a connected device can require a specific firmware update
2918 * protocol that needs bitbanging on IO lines, but use the regular serial
2919 * port in the normal case.
2921 static int atmel_serial_remove(struct platform_device *pdev)
2923 struct uart_port *port = platform_get_drvdata(pdev);
2924 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2927 tasklet_kill(&atmel_port->tasklet_rx);
2928 tasklet_kill(&atmel_port->tasklet_tx);
2930 device_init_wakeup(&pdev->dev, 0);
2932 ret = uart_remove_one_port(&atmel_uart, port);
2934 kfree(atmel_port->rx_ring.buf);
2936 /* "port" is allocated statically, so we shouldn't free it */
2938 clear_bit(port->line, atmel_ports_in_use);
2940 clk_put(atmel_port->clk);
2941 atmel_port->clk = NULL;
2946 static struct platform_driver atmel_serial_driver = {
2947 .probe = atmel_serial_probe,
2948 .remove = atmel_serial_remove,
2949 .suspend = atmel_serial_suspend,
2950 .resume = atmel_serial_resume,
2952 .name = "atmel_usart",
2953 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2957 static int __init atmel_serial_init(void)
2961 ret = uart_register_driver(&atmel_uart);
2965 ret = platform_driver_register(&atmel_serial_driver);
2967 uart_unregister_driver(&atmel_uart);
2971 device_initcall(atmel_serial_init);