drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 /* Register definitions */
  48 #define URXD0 0x0  /* Receiver Register */
  49 #define URTX0 0x40 /* Transmitter Register */
  50 #define UCR1  0x80 /* Control Register 1 */
  51 #define UCR2  0x84 /* Control Register 2 */
  52 #define UCR3  0x88 /* Control Register 3 */
  53 #define UCR4  0x8c /* Control Register 4 */
  54 #define UFCR  0x90 /* FIFO Control Register */
  55 #define USR1  0x94 /* Status Register 1 */
  56 #define USR2  0x98 /* Status Register 2 */
  57 #define UESC  0x9c /* Escape Character Register */
  58 #define UTIM  0xa0 /* Escape Timer Register */
  59 #define UBIR  0xa4 /* BRM Incremental Register */
  60 #define UBMR  0xa8 /* BRM Modulator Register */
  61 #define UBRC  0xac /* Baud Rate Count Register */
  62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  65
  66 /* UART Control Register Bit Fields.*/
  67 #define URXD_DUMMY_READ (1<<16)
  68 #define URXD_CHARRDY    (1<<15)
  69 #define URXD_ERR        (1<<14)
  70 #define URXD_OVRRUN     (1<<13)
  71 #define URXD_FRMERR     (1<<12)
  72 #define URXD_BRK        (1<<11)
  73 #define URXD_PRERR      (1<<10)
  74 #define URXD_RX_DATA    (0xFF<<0)
  75 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  76 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  77 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  78 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  80 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  81 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  82 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  83 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  84 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  85 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  86 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  88 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  89 #define UCR1_DOZE       (1<<1)  /* Doze */
  90 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  91 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  92 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  93 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  94 #define UCR2_CTS        (1<<12) /* Clear to send */
  95 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  96 #define UCR2_PREN       (1<<8)  /* Parity enable */
  97 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
  98 #define UCR2_STPB       (1<<6)  /* Stop */
  99 #define UCR2_WS         (1<<5)  /* Word size */
 100 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 101 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 102 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 103 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 104 #define UCR2_SRST       (1<<0)  /* SW reset */
 105 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 106 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 107 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 108 #define UCR3_DSR        (1<<10) /* Data set ready */
 109 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 110 #define UCR3_RI         (1<<8)  /* Ring indicator */
 111 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 112 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 113 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 114 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 115 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 116 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 117 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 118 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 119 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 120 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 121 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 122 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 123 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 124 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 125 #define UCR4_IRSC       (1<<5)  /* IR special case */
 126 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 127 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 128 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 129 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 130 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 131 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 132 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 133 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 134 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 135 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 136 #define USR1_RTSS       (1<<14) /* RTS pin status */
 137 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 138 #define USR1_RTSD       (1<<12) /* RTS delta */
 139 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 140 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 141 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 142 #define USR1_TIMEOUT    (1<<7)   /* Receive timeout interrupt status */
 143 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 144 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 145 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 146 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 147 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 148 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 149 #define USR2_IDLE        (1<<12) /* Idle condition */
 150 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 151 #define USR2_WAKE        (1<<7)  /* Wake */
 152 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 153 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 154 #define USR2_BRCD        (1<<2)  /* Break condition */
 155 #define USR2_ORE        (1<<1)   /* Overrun error */
 156 #define USR2_RDR        (1<<0)   /* Recv data ready */
 157 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 158 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 159 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 160 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 161 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 162 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 163 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 164
 165 /* We've been assigned a range on the "Low-density serial ports" major */
 166 #define SERIAL_IMX_MAJOR        207
 167 #define MINOR_START             16
 168 #define DEV_NAME                "ttymxc"
 169
 170 /*
 171  * This determines how often we check the modem status signals
 172  * for any change.  They generally aren't connected to an IRQ
 173  * so we have to poll them.  We also check immediately before
 174  * filling the TX fifo incase CTS has been dropped.
 175  */
 176 #define MCTRL_TIMEOUT   (250*HZ/1000)
 177
 178 #define DRIVER_NAME "IMX-uart"
 179
 180 #define UART_NR 8
 181
 182 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 183 enum imx_uart_type {
 184         IMX1_UART,
 185         IMX21_UART,
 186         IMX6Q_UART,
 187 };
 188
 189 /* device type dependent stuff */
 190 struct imx_uart_data {
 191         unsigned uts_reg;
 192         enum imx_uart_type devtype;
 193 };
 194
 195 struct imx_port {
 196         struct uart_port        port;
 197         struct timer_list       timer;
 198         unsigned int            old_status;
 199         unsigned int            have_rtscts:1;
 200         unsigned int            dte_mode:1;
 201         unsigned int            irda_inv_rx:1;
 202         unsigned int            irda_inv_tx:1;
 203         unsigned short          trcv_delay; /* transceiver delay */
 204         struct clk              *clk_ipg;
 205         struct clk              *clk_per;
 206         const struct imx_uart_data *devdata;
 207
 208         /* DMA fields */
 209         unsigned int            dma_is_inited:1;
 210         unsigned int            dma_is_enabled:1;
 211         unsigned int            dma_is_rxing:1;
 212         unsigned int            dma_is_txing:1;
 213         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 214         struct scatterlist      rx_sgl, tx_sgl[2];
 215         void                    *rx_buf;
 216         unsigned int            tx_bytes;
 217         unsigned int            dma_tx_nents;
 218         wait_queue_head_t       dma_wait;
 219         unsigned int            saved_reg[10];
 220         bool                    context_saved;
 221 };
 222
 223 struct imx_port_ucrs {
 224         unsigned int    ucr1;
 225         unsigned int    ucr2;
 226         unsigned int    ucr3;
 227 };
 228
 229 static struct imx_uart_data imx_uart_devdata[] = {
 230         [IMX1_UART] = {
 231                 .uts_reg = IMX1_UTS,
 232                 .devtype = IMX1_UART,
 233         },
 234         [IMX21_UART] = {
 235                 .uts_reg = IMX21_UTS,
 236                 .devtype = IMX21_UART,
 237         },
 238         [IMX6Q_UART] = {
 239                 .uts_reg = IMX21_UTS,
 240                 .devtype = IMX6Q_UART,
 241         },
 242 };
 243
 244 static const struct platform_device_id imx_uart_devtype[] = {
 245         {
 246                 .name = "imx1-uart",
 247                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 248         }, {
 249                 .name = "imx21-uart",
 250                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 251         }, {
 252                 .name = "imx6q-uart",
 253                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 254         }, {
 255                 /* sentinel */
 256         }
 257 };
 258 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 259
 260 static const struct of_device_id imx_uart_dt_ids[] = {
 261         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 262         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 263         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 264         { /* sentinel */ }
 265 };
 266 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 267
 268 static inline unsigned uts_reg(struct imx_port *sport)
 269 {
 270         return sport->devdata->uts_reg;
 271 }
 272
 273 static inline int is_imx1_uart(struct imx_port *sport)
 274 {
 275         return sport->devdata->devtype == IMX1_UART;
 276 }
 277
 278 static inline int is_imx21_uart(struct imx_port *sport)
 279 {
 280         return sport->devdata->devtype == IMX21_UART;
 281 }
 282
 283 static inline int is_imx6q_uart(struct imx_port *sport)
 284 {
 285         return sport->devdata->devtype == IMX6Q_UART;
 286 }
 287 /*
 288  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 289  */
 290 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 291 static void imx_port_ucrs_save(struct uart_port *port,
 292                                struct imx_port_ucrs *ucr)
 293 {
 294         /* save control registers */
 295         ucr->ucr1 = readl(port->membase + UCR1);
 296         ucr->ucr2 = readl(port->membase + UCR2);
 297         ucr->ucr3 = readl(port->membase + UCR3);
 298 }
 299
 300 static void imx_port_ucrs_restore(struct uart_port *port,
 301                                   struct imx_port_ucrs *ucr)
 302 {
 303         /* restore control registers */
 304         writel(ucr->ucr1, port->membase + UCR1);
 305         writel(ucr->ucr2, port->membase + UCR2);
 306         writel(ucr->ucr3, port->membase + UCR3);
 307 }
 308 #endif
 309
 310 /*
 311  * Handle any change of modem status signal since we were last called.
 312  */
 313 static void imx_mctrl_check(struct imx_port *sport)
 314 {
 315         unsigned int status, changed;
 316
 317         status = sport->port.ops->get_mctrl(&sport->port);
 318         changed = status ^ sport->old_status;
 319
 320         if (changed == 0)
 321                 return;
 322
 323         sport->old_status = status;
 324
 325         if (changed & TIOCM_RI)
 326                 sport->port.icount.rng++;
 327         if (changed & TIOCM_DSR)
 328                 sport->port.icount.dsr++;
 329         if (changed & TIOCM_CAR)
 330                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 331         if (changed & TIOCM_CTS)
 332                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 333
 334         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 335 }
 336
 337 /*
 338  * This is our per-port timeout handler, for checking the
 339  * modem status signals.
 340  */
 341 static void imx_timeout(unsigned long data)
 342 {
 343         struct imx_port *sport = (struct imx_port *)data;
 344         unsigned long flags;
 345
 346         if (sport->port.state) {
 347                 spin_lock_irqsave(&sport->port.lock, flags);
 348                 imx_mctrl_check(sport);
 349                 spin_unlock_irqrestore(&sport->port.lock, flags);
 350
 351                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 352         }
 353 }
 354
 355 /*
 356  * interrupts disabled on entry
 357  */
 358 static void imx_stop_tx(struct uart_port *port)
 359 {
 360         struct imx_port *sport = (struct imx_port *)port;
 361         unsigned long temp;
 362
 363         /*
 364          * We are maybe in the SMP context, so if the DMA TX thread is running
 365          * on other cpu, we have to wait for it to finish.
 366          */
 367         if (sport->dma_is_enabled && sport->dma_is_txing)
 368                 return;
 369
 370         temp = readl(port->membase + UCR1);
 371         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 372
 373         /* in rs485 mode disable transmitter if shifter is empty */
 374         if (port->rs485.flags & SER_RS485_ENABLED &&
 375             readl(port->membase + USR2) & USR2_TXDC) {
 376                 temp = readl(port->membase + UCR2);
 377                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 378                         temp &= ~UCR2_CTS;
 379                 else
 380                         temp |= UCR2_CTS;
 381                 writel(temp, port->membase + UCR2);
 382
 383                 temp = readl(port->membase + UCR4);
 384                 temp &= ~UCR4_TCEN;
 385                 writel(temp, port->membase + UCR4);
 386         }
 387 }
 388
 389 /*
 390  * interrupts disabled on entry
 391  */
 392 static void imx_stop_rx(struct uart_port *port)
 393 {
 394         struct imx_port *sport = (struct imx_port *)port;
 395         unsigned long temp;
 396
 397         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 398                 if (sport->port.suspended) {
 399                         dmaengine_terminate_all(sport->dma_chan_rx);
 400                         sport->dma_is_rxing = 0;
 401                 } else {
 402                         return;
 403                 }
 404         }
 405
 406         temp = readl(sport->port.membase + UCR2);
 407         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 408
 409         /* disable the `Receiver Ready Interrrupt` */
 410         temp = readl(sport->port.membase + UCR1);
 411         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 412 }
 413
 414 /*
 415  * Set the modem control timer to fire immediately.
 416  */
 417 static void imx_enable_ms(struct uart_port *port)
 418 {
 419         struct imx_port *sport = (struct imx_port *)port;
 420
 421         mod_timer(&sport->timer, jiffies);
 422 }
 423
 424 static void imx_dma_tx(struct imx_port *sport);
 425 static inline void imx_transmit_buffer(struct imx_port *sport)
 426 {
 427         struct circ_buf *xmit = &sport->port.state->xmit;
 428         unsigned long temp;
 429
 430         if (sport->port.x_char) {
 431                 /* Send next char */
 432                 writel(sport->port.x_char, sport->port.membase + URTX0);
 433                 sport->port.icount.tx++;
 434                 sport->port.x_char = 0;
 435                 return;
 436         }
 437
 438         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 439                 imx_stop_tx(&sport->port);
 440                 return;
 441         }
 442
 443         if (sport->dma_is_enabled) {
 444                 /*
 445                  * We've just sent a X-char Ensure the TX DMA is enabled
 446                  * and the TX IRQ is disabled.
 447                  **/
 448                 temp = readl(sport->port.membase + UCR1);
 449                 temp &= ~UCR1_TXMPTYEN;
 450                 if (sport->dma_is_txing) {
 451                         temp |= UCR1_TDMAEN;
 452                         writel(temp, sport->port.membase + UCR1);
 453                 } else {
 454                         writel(temp, sport->port.membase + UCR1);
 455                         imx_dma_tx(sport);
 456                 }
 457         }
 458
 459         while (!uart_circ_empty(xmit) &&
 460                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 461                 /* send xmit->buf[xmit->tail]
 462                  * out the port here */
 463                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 464                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 465                 sport->port.icount.tx++;
 466         }
 467
 468         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 469                 uart_write_wakeup(&sport->port);
 470
 471         if (uart_circ_empty(xmit))
 472                 imx_stop_tx(&sport->port);
 473 }
 474
 475 static void dma_tx_callback(void *data)
 476 {
 477         struct imx_port *sport = data;
 478         struct scatterlist *sgl = &sport->tx_sgl[0];
 479         struct circ_buf *xmit = &sport->port.state->xmit;
 480         unsigned long flags;
 481         unsigned long temp;
 482
 483         spin_lock_irqsave(&sport->port.lock, flags);
 484
 485         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 486
 487         temp = readl(sport->port.membase + UCR1);
 488         temp &= ~UCR1_TDMAEN;
 489         writel(temp, sport->port.membase + UCR1);
 490
 491         /* update the stat */
 492         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 493         sport->port.icount.tx += sport->tx_bytes;
 494
 495         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 496
 497         sport->dma_is_txing = 0;
 498
 499         spin_unlock_irqrestore(&sport->port.lock, flags);
 500
 501         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 502                 uart_write_wakeup(&sport->port);
 503
 504         if (waitqueue_active(&sport->dma_wait)) {
 505                 wake_up(&sport->dma_wait);
 506                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
 507                 return;
 508         }
 509
 510         spin_lock_irqsave(&sport->port.lock, flags);
 511         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 512                 imx_dma_tx(sport);
 513         spin_unlock_irqrestore(&sport->port.lock, flags);
 514 }
 515
 516 static void imx_dma_tx(struct imx_port *sport)
 517 {
 518         struct circ_buf *xmit = &sport->port.state->xmit;
 519         struct scatterlist *sgl = sport->tx_sgl;
 520         struct dma_async_tx_descriptor *desc;
 521         struct dma_chan *chan = sport->dma_chan_tx;
 522         struct device *dev = sport->port.dev;
 523         unsigned long temp;
 524         int ret;
 525
 526         if (sport->dma_is_txing)
 527                 return;
 528
 529         sport->tx_bytes = uart_circ_chars_pending(xmit);
 530
 531         if (xmit->tail < xmit->head) {
 532                 sport->dma_tx_nents = 1;
 533                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 534         } else {
 535                 sport->dma_tx_nents = 2;
 536                 sg_init_table(sgl, 2);
 537                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 538                                 UART_XMIT_SIZE - xmit->tail);
 539                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 540         }
 541
 542         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 543         if (ret == 0) {
 544                 dev_err(dev, "DMA mapping error for TX.\n");
 545                 return;
 546         }
 547         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 548                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 549         if (!desc) {
 550                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 551                              DMA_TO_DEVICE);
 552                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 553                 return;
 554         }
 555         desc->callback = dma_tx_callback;
 556         desc->callback_param = sport;
 557
 558         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 559                         uart_circ_chars_pending(xmit));
 560
 561         temp = readl(sport->port.membase + UCR1);
 562         temp |= UCR1_TDMAEN;
 563         writel(temp, sport->port.membase + UCR1);
 564
 565         /* fire it */
 566         sport->dma_is_txing = 1;
 567         dmaengine_submit(desc);
 568         dma_async_issue_pending(chan);
 569         return;
 570 }
 571
 572 /*
 573  * interrupts disabled on entry
 574  */
 575 static void imx_start_tx(struct uart_port *port)
 576 {
 577         struct imx_port *sport = (struct imx_port *)port;
 578         unsigned long temp;
 579
 580         if (port->rs485.flags & SER_RS485_ENABLED) {
 581                 /* enable transmitter and shifter empty irq */
 582                 temp = readl(port->membase + UCR2);
 583                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 584                         temp &= ~UCR2_CTS;
 585                 else
 586                         temp |= UCR2_CTS;
 587                 writel(temp, port->membase + UCR2);
 588
 589                 temp = readl(port->membase + UCR4);
 590                 temp |= UCR4_TCEN;
 591                 writel(temp, port->membase + UCR4);
 592         }
 593
 594         if (!sport->dma_is_enabled) {
 595                 temp = readl(sport->port.membase + UCR1);
 596                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 597         }
 598
 599         if (sport->dma_is_enabled) {
 600                 if (sport->port.x_char) {
 601                         /* We have X-char to send, so enable TX IRQ and
 602                          * disable TX DMA to let TX interrupt to send X-char */
 603                         temp = readl(sport->port.membase + UCR1);
 604                         temp &= ~UCR1_TDMAEN;
 605                         temp |= UCR1_TXMPTYEN;
 606                         writel(temp, sport->port.membase + UCR1);
 607                         return;
 608                 }
 609
 610                 if (!uart_circ_empty(&port->state->xmit) &&
 611                     !uart_tx_stopped(port))
 612                         imx_dma_tx(sport);
 613                 return;
 614         }
 615 }
 616
 617 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 618 {
 619         struct imx_port *sport = dev_id;
 620         unsigned int val;
 621         unsigned long flags;
 622
 623         spin_lock_irqsave(&sport->port.lock, flags);
 624
 625         writel(USR1_RTSD, sport->port.membase + USR1);
 626         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 627         uart_handle_cts_change(&sport->port, !!val);
 628         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 629
 630         spin_unlock_irqrestore(&sport->port.lock, flags);
 631         return IRQ_HANDLED;
 632 }
 633
 634 static irqreturn_t imx_txint(int irq, void *dev_id)
 635 {
 636         struct imx_port *sport = dev_id;
 637         unsigned long flags;
 638
 639         spin_lock_irqsave(&sport->port.lock, flags);
 640         imx_transmit_buffer(sport);
 641         spin_unlock_irqrestore(&sport->port.lock, flags);
 642         return IRQ_HANDLED;
 643 }
 644
 645 static irqreturn_t imx_rxint(int irq, void *dev_id)
 646 {
 647         struct imx_port *sport = dev_id;
 648         unsigned int rx, flg, ignored = 0;
 649         struct tty_port *port = &sport->port.state->port;
 650         unsigned long flags, temp;
 651
 652         spin_lock_irqsave(&sport->port.lock, flags);
 653
 654         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 655                 flg = TTY_NORMAL;
 656                 sport->port.icount.rx++;
 657
 658                 rx = readl(sport->port.membase + URXD0);
 659
 660                 temp = readl(sport->port.membase + USR2);
 661                 if (temp & USR2_BRCD) {
 662                         writel(USR2_BRCD, sport->port.membase + USR2);
 663                         if (uart_handle_break(&sport->port))
 664                                 continue;
 665                 }
 666
 667                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 668                         continue;
 669
 670                 if (unlikely(rx & URXD_ERR)) {
 671                         if (rx & URXD_BRK)
 672                                 sport->port.icount.brk++;
 673                         else if (rx & URXD_PRERR)
 674                                 sport->port.icount.parity++;
 675                         else if (rx & URXD_FRMERR)
 676                                 sport->port.icount.frame++;
 677                         if (rx & URXD_OVRRUN)
 678                                 sport->port.icount.overrun++;
 679
 680                         if (rx & sport->port.ignore_status_mask) {
 681                                 if (++ignored > 100)
 682                                         goto out;
 683                                 continue;
 684                         }
 685
 686                         rx &= (sport->port.read_status_mask | 0xFF);
 687
 688                         if (rx & URXD_BRK)
 689                                 flg = TTY_BREAK;
 690                         else if (rx & URXD_PRERR)
 691                                 flg = TTY_PARITY;
 692                         else if (rx & URXD_FRMERR)
 693                                 flg = TTY_FRAME;
 694                         if (rx & URXD_OVRRUN)
 695                                 flg = TTY_OVERRUN;
 696
 697 #ifdef SUPPORT_SYSRQ
 698                         sport->port.sysrq = 0;
 699 #endif
 700                 }
 701
 702                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 703                         goto out;
 704
 705                 if (tty_insert_flip_char(port, rx, flg) == 0)
 706                         sport->port.icount.buf_overrun++;
 707         }
 708
 709 out:
 710         spin_unlock_irqrestore(&sport->port.lock, flags);
 711         tty_flip_buffer_push(port);
 712         return IRQ_HANDLED;
 713 }
 714
 715 static int start_rx_dma(struct imx_port *sport);
 716 /*
 717  * If the RXFIFO is filled with some data, and then we
 718  * arise a DMA operation to receive them.
 719  */
 720 static void imx_dma_rxint(struct imx_port *sport)
 721 {
 722         unsigned long temp;
 723         unsigned long flags;
 724
 725         spin_lock_irqsave(&sport->port.lock, flags);
 726
 727         temp = readl(sport->port.membase + USR2);
 728         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 729                 sport->dma_is_rxing = 1;
 730
 731                 /* disable the `Recerver Ready Interrrupt` */
 732                 temp = readl(sport->port.membase + UCR1);
 733                 temp &= ~(UCR1_RRDYEN);
 734                 writel(temp, sport->port.membase + UCR1);
 735
 736                 /* tell the DMA to receive the data. */
 737                 start_rx_dma(sport);
 738         }
 739
 740         spin_unlock_irqrestore(&sport->port.lock, flags);
 741 }
 742
 743 static irqreturn_t imx_int(int irq, void *dev_id)
 744 {
 745         struct imx_port *sport = dev_id;
 746         unsigned int sts;
 747         unsigned int sts2;
 748
 749         sts = readl(sport->port.membase + USR1);
 750         sts2 = readl(sport->port.membase + USR2);
 751
 752         if (sts & USR1_RRDY) {
 753                 if (sport->dma_is_enabled)
 754                         imx_dma_rxint(sport);
 755                 else
 756                         imx_rxint(irq, dev_id);
 757         }
 758
 759         if ((sts & USR1_TRDY &&
 760              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 761             (sts2 & USR2_TXDC &&
 762              readl(sport->port.membase + UCR4) & UCR4_TCEN))
 763                 imx_txint(irq, dev_id);
 764
 765         if (sts & USR1_RTSD)
 766                 imx_rtsint(irq, dev_id);
 767
 768         if (sts & USR1_AWAKE)
 769                 writel(USR1_AWAKE, sport->port.membase + USR1);
 770
 771         if (sts2 & USR2_ORE) {
 772                 sport->port.icount.overrun++;
 773                 writel(USR2_ORE, sport->port.membase + USR2);
 774         }
 775
 776         return IRQ_HANDLED;
 777 }
 778
 779 /*
 780  * Return TIOCSER_TEMT when transmitter is not busy.
 781  */
 782 static unsigned int imx_tx_empty(struct uart_port *port)
 783 {
 784         struct imx_port *sport = (struct imx_port *)port;
 785         unsigned int ret;
 786
 787         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 788
 789         /* If the TX DMA is working, return 0. */
 790         if (sport->dma_is_enabled && sport->dma_is_txing)
 791                 ret = 0;
 792
 793         return ret;
 794 }
 795
 796 /*
 797  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 798  */
 799 static unsigned int imx_get_mctrl(struct uart_port *port)
 800 {
 801         struct imx_port *sport = (struct imx_port *)port;
 802         unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
 803
 804         if (readl(sport->port.membase + USR1) & USR1_RTSS)
 805                 tmp |= TIOCM_CTS;
 806
 807         if (readl(sport->port.membase + UCR2) & UCR2_CTS)
 808                 tmp |= TIOCM_RTS;
 809
 810         if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
 811                 tmp |= TIOCM_LOOP;
 812
 813         return tmp;
 814 }
 815
 816 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 817 {
 818         struct imx_port *sport = (struct imx_port *)port;
 819         unsigned long temp;
 820
 821         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 822                 temp = readl(sport->port.membase + UCR2);
 823                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 824                 if (mctrl & TIOCM_RTS)
 825                         temp |= UCR2_CTS | UCR2_CTSC;
 826                 writel(temp, sport->port.membase + UCR2);
 827         }
 828
 829         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 830         if (mctrl & TIOCM_LOOP)
 831                 temp |= UTS_LOOP;
 832         writel(temp, sport->port.membase + uts_reg(sport));
 833 }
 834
 835 /*
 836  * Interrupts always disabled.
 837  */
 838 static void imx_break_ctl(struct uart_port *port, int break_state)
 839 {
 840         struct imx_port *sport = (struct imx_port *)port;
 841         unsigned long flags, temp;
 842
 843         spin_lock_irqsave(&sport->port.lock, flags);
 844
 845         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 846
 847         if (break_state != 0)
 848                 temp |= UCR1_SNDBRK;
 849
 850         writel(temp, sport->port.membase + UCR1);
 851
 852         spin_unlock_irqrestore(&sport->port.lock, flags);
 853 }
 854
 855 #define RX_BUF_SIZE     (PAGE_SIZE)
 856 static void imx_rx_dma_done(struct imx_port *sport)
 857 {
 858         unsigned long temp;
 859         unsigned long flags;
 860
 861         spin_lock_irqsave(&sport->port.lock, flags);
 862
 863         /* Enable this interrupt when the RXFIFO is empty. */
 864         temp = readl(sport->port.membase + UCR1);
 865         temp |= UCR1_RRDYEN;
 866         writel(temp, sport->port.membase + UCR1);
 867
 868         sport->dma_is_rxing = 0;
 869
 870         /* Is the shutdown waiting for us? */
 871         if (waitqueue_active(&sport->dma_wait))
 872                 wake_up(&sport->dma_wait);
 873
 874         spin_unlock_irqrestore(&sport->port.lock, flags);
 875 }
 876
 877 /*
 878  * There are three kinds of RX DMA interrupts(such as in the MX6Q):
 879  *   [1] the RX DMA buffer is full.
 880  *   [2] the Aging timer expires(wait for 8 bytes long)
 881  *   [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
 882  *
 883  * The [2] is trigger when a character was been sitting in the FIFO
 884  * meanwhile [3] can wait for 32 bytes long when the RX line is
 885  * on IDLE state and RxFIFO is empty.
 886  */
 887 static void dma_rx_callback(void *data)
 888 {
 889         struct imx_port *sport = data;
 890         struct dma_chan *chan = sport->dma_chan_rx;
 891         struct scatterlist *sgl = &sport->rx_sgl;
 892         struct tty_port *port = &sport->port.state->port;
 893         struct dma_tx_state state;
 894         enum dma_status status;
 895         unsigned int count;
 896
 897         /* unmap it first */
 898         dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
 899
 900         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 901         count = RX_BUF_SIZE - state.residue;
 902
 903         if (readl(sport->port.membase + USR2) & USR2_IDLE) {
 904                 /* In condition [3] the SDMA counted up too early */
 905                 count--;
 906
 907                 writel(USR2_IDLE, sport->port.membase + USR2);
 908         }
 909
 910         dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
 911
 912         if (count) {
 913                 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 914                         int bytes = tty_insert_flip_string(port, sport->rx_buf,
 915                                         count);
 916
 917                         if (bytes != count)
 918                                 sport->port.icount.buf_overrun++;
 919                 }
 920                 tty_flip_buffer_push(port);
 921
 922                 start_rx_dma(sport);
 923         } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
 924                 /*
 925                  * start rx_dma directly once data in RXFIFO, more efficient
 926                  * than before:
 927                  *      1. call imx_rx_dma_done to stop dma if no data received
 928                  *      2. wait next  RDR interrupt to start dma transfer.
 929                  */
 930                 start_rx_dma(sport);
 931         } else {
 932                 /*
 933                  * stop dma to prevent too many IDLE event trigged if no data
 934                  * in RXFIFO
 935                  */
 936                 imx_rx_dma_done(sport);
 937         }
 938 }
 939
 940 static int start_rx_dma(struct imx_port *sport)
 941 {
 942         struct scatterlist *sgl = &sport->rx_sgl;
 943         struct dma_chan *chan = sport->dma_chan_rx;
 944         struct device *dev = sport->port.dev;
 945         struct dma_async_tx_descriptor *desc;
 946         int ret;
 947
 948         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
 949         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
 950         if (ret == 0) {
 951                 dev_err(dev, "DMA mapping error for RX.\n");
 952                 return -EINVAL;
 953         }
 954         desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
 955                                         DMA_PREP_INTERRUPT);
 956         if (!desc) {
 957                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
 958                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
 959                 return -EINVAL;
 960         }
 961         desc->callback = dma_rx_callback;
 962         desc->callback_param = sport;
 963
 964         dev_dbg(dev, "RX: prepare for the DMA.\n");
 965         dmaengine_submit(desc);
 966         dma_async_issue_pending(chan);
 967         return 0;
 968 }
 969
 970 #define TXTL_DEFAULT 2 /* reset default */
 971 #define RXTL_DEFAULT 1 /* reset default */
 972
 973 static void imx_setup_ufcr(struct imx_port *sport,
 974                           unsigned char txwl, unsigned char rxwl)
 975 {
 976         unsigned int val;
 977
 978         /* set receiver / transmitter trigger level */
 979         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
 980         val |= txwl << UFCR_TXTL_SHF | rxwl;
 981         writel(val, sport->port.membase + UFCR);
 982 }
 983
 984 static void imx_uart_dma_exit(struct imx_port *sport)
 985 {
 986         if (sport->dma_chan_rx) {
 987                 dma_release_channel(sport->dma_chan_rx);
 988                 sport->dma_chan_rx = NULL;
 989
 990                 kfree(sport->rx_buf);
 991                 sport->rx_buf = NULL;
 992         }
 993
 994         if (sport->dma_chan_tx) {
 995                 dma_release_channel(sport->dma_chan_tx);
 996                 sport->dma_chan_tx = NULL;
 997         }
 998
 999         sport->dma_is_inited = 0;
1000 }
1001
1002 static int imx_uart_dma_init(struct imx_port *sport)
1003 {
1004         struct dma_slave_config slave_config = {};
1005         struct device *dev = sport->port.dev;
1006         int ret;
1007
1008         /* Prepare for RX : */
1009         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1010         if (!sport->dma_chan_rx) {
1011                 dev_dbg(dev, "cannot get the DMA channel.\n");
1012                 ret = -EINVAL;
1013                 goto err;
1014         }
1015
1016         slave_config.direction = DMA_DEV_TO_MEM;
1017         slave_config.src_addr = sport->port.mapbase + URXD0;
1018         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1019         slave_config.src_maxburst = RXTL_DEFAULT;
1020         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1021         if (ret) {
1022                 dev_err(dev, "error in RX dma configuration.\n");
1023                 goto err;
1024         }
1025
1026         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1027         if (!sport->rx_buf) {
1028                 ret = -ENOMEM;
1029                 goto err;
1030         }
1031
1032         /* Prepare for TX : */
1033         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1034         if (!sport->dma_chan_tx) {
1035                 dev_err(dev, "cannot get the TX DMA channel!\n");
1036                 ret = -EINVAL;
1037                 goto err;
1038         }
1039
1040         slave_config.direction = DMA_MEM_TO_DEV;
1041         slave_config.dst_addr = sport->port.mapbase + URTX0;
1042         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1043         slave_config.dst_maxburst = TXTL_DEFAULT;
1044         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1045         if (ret) {
1046                 dev_err(dev, "error in TX dma configuration.");
1047                 goto err;
1048         }
1049
1050         sport->dma_is_inited = 1;
1051
1052         return 0;
1053 err:
1054         imx_uart_dma_exit(sport);
1055         return ret;
1056 }
1057
1058 static void imx_enable_dma(struct imx_port *sport)
1059 {
1060         unsigned long temp;
1061
1062         init_waitqueue_head(&sport->dma_wait);
1063
1064         /* set UCR1 */
1065         temp = readl(sport->port.membase + UCR1);
1066         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1067                 /* wait for 32 idle frames for IDDMA interrupt */
1068                 UCR1_ICD_REG(3);
1069         writel(temp, sport->port.membase + UCR1);
1070
1071         /* set UCR4 */
1072         temp = readl(sport->port.membase + UCR4);
1073         temp |= UCR4_IDDMAEN;
1074         writel(temp, sport->port.membase + UCR4);
1075
1076         sport->dma_is_enabled = 1;
1077 }
1078
1079 static void imx_disable_dma(struct imx_port *sport)
1080 {
1081         unsigned long temp;
1082
1083         /* clear UCR1 */
1084         temp = readl(sport->port.membase + UCR1);
1085         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1086         writel(temp, sport->port.membase + UCR1);
1087
1088         /* clear UCR2 */
1089         temp = readl(sport->port.membase + UCR2);
1090         temp &= ~(UCR2_CTSC | UCR2_CTS);
1091         writel(temp, sport->port.membase + UCR2);
1092
1093         /* clear UCR4 */
1094         temp = readl(sport->port.membase + UCR4);
1095         temp &= ~UCR4_IDDMAEN;
1096         writel(temp, sport->port.membase + UCR4);
1097
1098         sport->dma_is_enabled = 0;
1099 }
1100
1101 /* half the RX buffer size */
1102 #define CTSTL 16
1103
1104 static int imx_startup(struct uart_port *port)
1105 {
1106         struct imx_port *sport = (struct imx_port *)port;
1107         int retval, i;
1108         unsigned long flags, temp;
1109
1110         retval = clk_prepare_enable(sport->clk_per);
1111         if (retval)
1112                 return retval;
1113         retval = clk_prepare_enable(sport->clk_ipg);
1114         if (retval) {
1115                 clk_disable_unprepare(sport->clk_per);
1116                 return retval;
1117         }
1118
1119         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1120
1121         /* disable the DREN bit (Data Ready interrupt enable) before
1122          * requesting IRQs
1123          */
1124         temp = readl(sport->port.membase + UCR4);
1125
1126         /* set the trigger level for CTS */
1127         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1128         temp |= CTSTL << UCR4_CTSTL_SHF;
1129
1130         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1131
1132         spin_lock_irqsave(&sport->port.lock, flags);
1133         /* Reset fifo's and state machines */
1134         i = 100;
1135
1136         temp = readl(sport->port.membase + UCR2);
1137         temp &= ~UCR2_SRST;
1138         writel(temp, sport->port.membase + UCR2);
1139
1140         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1141                 udelay(1);
1142
1143         /*
1144          * Finally, clear and enable interrupts
1145          */
1146         writel(USR1_RTSD, sport->port.membase + USR1);
1147         writel(USR2_ORE, sport->port.membase + USR2);
1148
1149         temp = readl(sport->port.membase + UCR1);
1150         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1151
1152         writel(temp, sport->port.membase + UCR1);
1153
1154         temp = readl(sport->port.membase + UCR4);
1155         temp |= UCR4_OREN;
1156         writel(temp, sport->port.membase + UCR4);
1157
1158         temp = readl(sport->port.membase + UCR2);
1159         temp |= (UCR2_RXEN | UCR2_TXEN);
1160         if (!sport->have_rtscts)
1161                 temp |= UCR2_IRTS;
1162         writel(temp, sport->port.membase + UCR2);
1163
1164         if (!is_imx1_uart(sport)) {
1165                 temp = readl(sport->port.membase + UCR3);
1166                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1167                 writel(temp, sport->port.membase + UCR3);
1168         }
1169
1170         /*
1171          * Enable modem status interrupts
1172          */
1173         imx_enable_ms(&sport->port);
1174         spin_unlock_irqrestore(&sport->port.lock, flags);
1175
1176         return 0;
1177 }
1178
1179 static void imx_shutdown(struct uart_port *port)
1180 {
1181         struct imx_port *sport = (struct imx_port *)port;
1182         unsigned long temp;
1183         unsigned long flags;
1184
1185         if (sport->dma_is_enabled) {
1186                 int ret;
1187
1188                 /* We have to wait for the DMA to finish. */
1189                 ret = wait_event_interruptible(sport->dma_wait,
1190                         !sport->dma_is_rxing && !sport->dma_is_txing);
1191                 if (ret != 0) {
1192                         sport->dma_is_rxing = 0;
1193                         sport->dma_is_txing = 0;
1194                         dmaengine_terminate_all(sport->dma_chan_tx);
1195                         dmaengine_terminate_all(sport->dma_chan_rx);
1196                 }
1197                 spin_lock_irqsave(&sport->port.lock, flags);
1198                 imx_stop_tx(port);
1199                 imx_stop_rx(port);
1200                 imx_disable_dma(sport);
1201                 spin_unlock_irqrestore(&sport->port.lock, flags);
1202                 imx_uart_dma_exit(sport);
1203         }
1204
1205         spin_lock_irqsave(&sport->port.lock, flags);
1206         temp = readl(sport->port.membase + UCR2);
1207         temp &= ~(UCR2_TXEN);
1208         writel(temp, sport->port.membase + UCR2);
1209         spin_unlock_irqrestore(&sport->port.lock, flags);
1210
1211         /*
1212          * Stop our timer.
1213          */
1214         del_timer_sync(&sport->timer);
1215
1216         /*
1217          * Disable all interrupts, port and break condition.
1218          */
1219
1220         spin_lock_irqsave(&sport->port.lock, flags);
1221         temp = readl(sport->port.membase + UCR1);
1222         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1223
1224         writel(temp, sport->port.membase + UCR1);
1225         spin_unlock_irqrestore(&sport->port.lock, flags);
1226
1227         clk_disable_unprepare(sport->clk_per);
1228         clk_disable_unprepare(sport->clk_ipg);
1229 }
1230
1231 static void imx_flush_buffer(struct uart_port *port)
1232 {
1233         struct imx_port *sport = (struct imx_port *)port;
1234         struct scatterlist *sgl = &sport->tx_sgl[0];
1235         unsigned long temp;
1236         int i = 100, ubir, ubmr, uts;
1237
1238         if (!sport->dma_chan_tx)
1239                 return;
1240
1241         sport->tx_bytes = 0;
1242         dmaengine_terminate_all(sport->dma_chan_tx);
1243         if (sport->dma_is_txing) {
1244                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1245                              DMA_TO_DEVICE);
1246                 temp = readl(sport->port.membase + UCR1);
1247                 temp &= ~UCR1_TDMAEN;
1248                 writel(temp, sport->port.membase + UCR1);
1249                 sport->dma_is_txing = false;
1250         }
1251
1252         /*
1253          * According to the Reference Manual description of the UART SRST bit:
1254          * "Reset the transmit and receive state machines,
1255          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1256          * and UTS[6-3]". As we don't need to restore the old values from
1257          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1258          */
1259         ubir = readl(sport->port.membase + UBIR);
1260         ubmr = readl(sport->port.membase + UBMR);
1261         uts = readl(sport->port.membase + IMX21_UTS);
1262
1263         temp = readl(sport->port.membase + UCR2);
1264         temp &= ~UCR2_SRST;
1265         writel(temp, sport->port.membase + UCR2);
1266
1267         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1268                 udelay(1);
1269
1270         /* Restore the registers */
1271         writel(ubir, sport->port.membase + UBIR);
1272         writel(ubmr, sport->port.membase + UBMR);
1273         writel(uts, sport->port.membase + IMX21_UTS);
1274 }
1275
1276 static void
1277 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1278                    struct ktermios *old)
1279 {
1280         struct imx_port *sport = (struct imx_port *)port;
1281         unsigned long flags;
1282         unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1283         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1284         unsigned int div, ufcr;
1285         unsigned long num, denom;
1286         uint64_t tdiv64;
1287
1288         /*
1289          * We only support CS7 and CS8.
1290          */
1291         while ((termios->c_cflag & CSIZE) != CS7 &&
1292                (termios->c_cflag & CSIZE) != CS8) {
1293                 termios->c_cflag &= ~CSIZE;
1294                 termios->c_cflag |= old_csize;
1295                 old_csize = CS8;
1296         }
1297
1298         if ((termios->c_cflag & CSIZE) == CS8)
1299                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1300         else
1301                 ucr2 = UCR2_SRST | UCR2_IRTS;
1302
1303         if (termios->c_cflag & CRTSCTS) {
1304                 if (sport->have_rtscts) {
1305                         ucr2 &= ~UCR2_IRTS;
1306
1307                         if (port->rs485.flags & SER_RS485_ENABLED) {
1308                                 /*
1309                                  * RTS is mandatory for rs485 operation, so keep
1310                                  * it under manual control and keep transmitter
1311                                  * disabled.
1312                                  */
1313                                 if (!(port->rs485.flags &
1314                                       SER_RS485_RTS_AFTER_SEND))
1315                                         ucr2 |= UCR2_CTS;
1316                         } else {
1317                                 ucr2 |= UCR2_CTSC;
1318                         }
1319
1320                         /* Can we enable the DMA support? */
1321                         if (is_imx6q_uart(sport) && !uart_console(port)
1322                                 && !sport->dma_is_inited)
1323                                 imx_uart_dma_init(sport);
1324                 } else {
1325                         termios->c_cflag &= ~CRTSCTS;
1326                 }
1327         } else if (port->rs485.flags & SER_RS485_ENABLED)
1328                 /* disable transmitter */
1329                 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1330                         ucr2 |= UCR2_CTS;
1331
1332         if (termios->c_cflag & CSTOPB)
1333                 ucr2 |= UCR2_STPB;
1334         if (termios->c_cflag & PARENB) {
1335                 ucr2 |= UCR2_PREN;
1336                 if (termios->c_cflag & PARODD)
1337                         ucr2 |= UCR2_PROE;
1338         }
1339
1340         del_timer_sync(&sport->timer);
1341
1342         /*
1343          * Ask the core to calculate the divisor for us.
1344          */
1345         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1346         quot = uart_get_divisor(port, baud);
1347
1348         spin_lock_irqsave(&sport->port.lock, flags);
1349
1350         sport->port.read_status_mask = 0;
1351         if (termios->c_iflag & INPCK)
1352                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1353         if (termios->c_iflag & (BRKINT | PARMRK))
1354                 sport->port.read_status_mask |= URXD_BRK;
1355
1356         /*
1357          * Characters to ignore
1358          */
1359         sport->port.ignore_status_mask = 0;
1360         if (termios->c_iflag & IGNPAR)
1361                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1362         if (termios->c_iflag & IGNBRK) {
1363                 sport->port.ignore_status_mask |= URXD_BRK;
1364                 /*
1365                  * If we're ignoring parity and break indicators,
1366                  * ignore overruns too (for real raw support).
1367                  */
1368                 if (termios->c_iflag & IGNPAR)
1369                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1370         }
1371
1372         if ((termios->c_cflag & CREAD) == 0)
1373                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1374
1375         /*
1376          * Update the per-port timeout.
1377          */
1378         uart_update_timeout(port, termios->c_cflag, baud);
1379
1380         /*
1381          * disable interrupts and drain transmitter
1382          */
1383         old_ucr1 = readl(sport->port.membase + UCR1);
1384         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1385                         sport->port.membase + UCR1);
1386
1387         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1388                 barrier();
1389
1390         /* then, disable everything */
1391         old_txrxen = readl(sport->port.membase + UCR2);
1392         writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1393                         sport->port.membase + UCR2);
1394         old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1395
1396         /* custom-baudrate handling */
1397         div = sport->port.uartclk / (baud * 16);
1398         if (baud == 38400 && quot != div)
1399                 baud = sport->port.uartclk / (quot * 16);
1400
1401         div = sport->port.uartclk / (baud * 16);
1402         if (div > 7)
1403                 div = 7;
1404         if (!div)
1405                 div = 1;
1406
1407         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1408                 1 << 16, 1 << 16, &num, &denom);
1409
1410         tdiv64 = sport->port.uartclk;
1411         tdiv64 *= num;
1412         do_div(tdiv64, denom * 16 * div);
1413         tty_termios_encode_baud_rate(termios,
1414                                 (speed_t)tdiv64, (speed_t)tdiv64);
1415
1416         num -= 1;
1417         denom -= 1;
1418
1419         ufcr = readl(sport->port.membase + UFCR);
1420         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1421         if (sport->dte_mode)
1422                 ufcr |= UFCR_DCEDTE;
1423         writel(ufcr, sport->port.membase + UFCR);
1424
1425         writel(num, sport->port.membase + UBIR);
1426         writel(denom, sport->port.membase + UBMR);
1427
1428         if (!is_imx1_uart(sport))
1429                 writel(sport->port.uartclk / div / 1000,
1430                                 sport->port.membase + IMX21_ONEMS);
1431
1432         writel(old_ucr1, sport->port.membase + UCR1);
1433
1434         /* set the parity, stop bits and data size */
1435         writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1436
1437         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1438                 imx_enable_ms(&sport->port);
1439
1440         if (sport->dma_is_inited && !sport->dma_is_enabled)
1441                 imx_enable_dma(sport);
1442         spin_unlock_irqrestore(&sport->port.lock, flags);
1443 }
1444
1445 static const char *imx_type(struct uart_port *port)
1446 {
1447         struct imx_port *sport = (struct imx_port *)port;
1448
1449         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1450 }
1451
1452 /*
1453  * Configure/autoconfigure the port.
1454  */
1455 static void imx_config_port(struct uart_port *port, int flags)
1456 {
1457         struct imx_port *sport = (struct imx_port *)port;
1458
1459         if (flags & UART_CONFIG_TYPE)
1460                 sport->port.type = PORT_IMX;
1461 }
1462
1463 /*
1464  * Verify the new serial_struct (for TIOCSSERIAL).
1465  * The only change we allow are to the flags and type, and
1466  * even then only between PORT_IMX and PORT_UNKNOWN
1467  */
1468 static int
1469 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1470 {
1471         struct imx_port *sport = (struct imx_port *)port;
1472         int ret = 0;
1473
1474         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1475                 ret = -EINVAL;
1476         if (sport->port.irq != ser->irq)
1477                 ret = -EINVAL;
1478         if (ser->io_type != UPIO_MEM)
1479                 ret = -EINVAL;
1480         if (sport->port.uartclk / 16 != ser->baud_base)
1481                 ret = -EINVAL;
1482         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1483                 ret = -EINVAL;
1484         if (sport->port.iobase != ser->port)
1485                 ret = -EINVAL;
1486         if (ser->hub6 != 0)
1487                 ret = -EINVAL;
1488         return ret;
1489 }
1490
1491 #if defined(CONFIG_CONSOLE_POLL)
1492
1493 static int imx_poll_init(struct uart_port *port)
1494 {
1495         struct imx_port *sport = (struct imx_port *)port;
1496         unsigned long flags;
1497         unsigned long temp;
1498         int retval;
1499
1500         retval = clk_prepare_enable(sport->clk_ipg);
1501         if (retval)
1502                 return retval;
1503         retval = clk_prepare_enable(sport->clk_per);
1504         if (retval)
1505                 clk_disable_unprepare(sport->clk_ipg);
1506
1507         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1508
1509         spin_lock_irqsave(&sport->port.lock, flags);
1510
1511         temp = readl(sport->port.membase + UCR1);
1512         if (is_imx1_uart(sport))
1513                 temp |= IMX1_UCR1_UARTCLKEN;
1514         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1515         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1516         writel(temp, sport->port.membase + UCR1);
1517
1518         temp = readl(sport->port.membase + UCR2);
1519         temp |= UCR2_RXEN;
1520         writel(temp, sport->port.membase + UCR2);
1521
1522         spin_unlock_irqrestore(&sport->port.lock, flags);
1523
1524         return 0;
1525 }
1526
1527 static int imx_poll_get_char(struct uart_port *port)
1528 {
1529         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1530                 return NO_POLL_CHAR;
1531
1532         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1533 }
1534
1535 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1536 {
1537         unsigned int status;
1538
1539         /* drain */
1540         do {
1541                 status = readl_relaxed(port->membase + USR1);
1542         } while (~status & USR1_TRDY);
1543
1544         /* write */
1545         writel_relaxed(c, port->membase + URTX0);
1546
1547         /* flush */
1548         do {
1549                 status = readl_relaxed(port->membase + USR2);
1550         } while (~status & USR2_TXDC);
1551 }
1552 #endif
1553
1554 static int imx_rs485_config(struct uart_port *port,
1555                             struct serial_rs485 *rs485conf)
1556 {
1557         struct imx_port *sport = (struct imx_port *)port;
1558
1559         /* unimplemented */
1560         rs485conf->delay_rts_before_send = 0;
1561         rs485conf->delay_rts_after_send = 0;
1562         rs485conf->flags |= SER_RS485_RX_DURING_TX;
1563
1564         /* RTS is required to control the transmitter */
1565         if (!sport->have_rtscts)
1566                 rs485conf->flags &= ~SER_RS485_ENABLED;
1567
1568         if (rs485conf->flags & SER_RS485_ENABLED) {
1569                 unsigned long temp;
1570
1571                 /* disable transmitter */
1572                 temp = readl(sport->port.membase + UCR2);
1573                 temp &= ~UCR2_CTSC;
1574                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1575                         temp &= ~UCR2_CTS;
1576                 else
1577                         temp |= UCR2_CTS;
1578                 writel(temp, sport->port.membase + UCR2);
1579         }
1580
1581         port->rs485 = *rs485conf;
1582
1583         return 0;
1584 }
1585
1586 static struct uart_ops imx_pops = {
1587         .tx_empty       = imx_tx_empty,
1588         .set_mctrl      = imx_set_mctrl,
1589         .get_mctrl      = imx_get_mctrl,
1590         .stop_tx        = imx_stop_tx,
1591         .start_tx       = imx_start_tx,
1592         .stop_rx        = imx_stop_rx,
1593         .enable_ms      = imx_enable_ms,
1594         .break_ctl      = imx_break_ctl,
1595         .startup        = imx_startup,
1596         .shutdown       = imx_shutdown,
1597         .flush_buffer   = imx_flush_buffer,
1598         .set_termios    = imx_set_termios,
1599         .type           = imx_type,
1600         .config_port    = imx_config_port,
1601         .verify_port    = imx_verify_port,
1602 #if defined(CONFIG_CONSOLE_POLL)
1603         .poll_init      = imx_poll_init,
1604         .poll_get_char  = imx_poll_get_char,
1605         .poll_put_char  = imx_poll_put_char,
1606 #endif
1607 };
1608
1609 static struct imx_port *imx_ports[UART_NR];
1610
1611 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1612 static void imx_console_putchar(struct uart_port *port, int ch)
1613 {
1614         struct imx_port *sport = (struct imx_port *)port;
1615
1616         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1617                 barrier();
1618
1619         writel(ch, sport->port.membase + URTX0);
1620 }
1621
1622 /*
1623  * Interrupts are disabled on entering
1624  */
1625 static void
1626 imx_console_write(struct console *co, const char *s, unsigned int count)
1627 {
1628         struct imx_port *sport = imx_ports[co->index];
1629         struct imx_port_ucrs old_ucr;
1630         unsigned int ucr1;
1631         unsigned long flags = 0;
1632         int locked = 1;
1633         int retval;
1634
1635         retval = clk_prepare_enable(sport->clk_per);
1636         if (retval)
1637                 return;
1638         retval = clk_prepare_enable(sport->clk_ipg);
1639         if (retval) {
1640                 clk_disable_unprepare(sport->clk_per);
1641                 return;
1642         }
1643
1644         if (sport->port.sysrq)
1645                 locked = 0;
1646         else if (oops_in_progress)
1647                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1648         else
1649                 spin_lock_irqsave(&sport->port.lock, flags);
1650
1651         /*
1652          *      First, save UCR1/2/3 and then disable interrupts
1653          */
1654         imx_port_ucrs_save(&sport->port, &old_ucr);
1655         ucr1 = old_ucr.ucr1;
1656
1657         if (is_imx1_uart(sport))
1658                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1659         ucr1 |= UCR1_UARTEN;
1660         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1661
1662         writel(ucr1, sport->port.membase + UCR1);
1663
1664         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1665
1666         uart_console_write(&sport->port, s, count, imx_console_putchar);
1667
1668         /*
1669          *      Finally, wait for transmitter to become empty
1670          *      and restore UCR1/2/3
1671          */
1672         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1673
1674         imx_port_ucrs_restore(&sport->port, &old_ucr);
1675
1676         if (locked)
1677                 spin_unlock_irqrestore(&sport->port.lock, flags);
1678
1679         clk_disable_unprepare(sport->clk_ipg);
1680         clk_disable_unprepare(sport->clk_per);
1681 }
1682
1683 /*
1684  * If the port was already initialised (eg, by a boot loader),
1685  * try to determine the current setup.
1686  */
1687 static void __init
1688 imx_console_get_options(struct imx_port *sport, int *baud,
1689                            int *parity, int *bits)
1690 {
1691
1692         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1693                 /* ok, the port was enabled */
1694                 unsigned int ucr2, ubir, ubmr, uartclk;
1695                 unsigned int baud_raw;
1696                 unsigned int ucfr_rfdiv;
1697
1698                 ucr2 = readl(sport->port.membase + UCR2);
1699
1700                 *parity = 'n';
1701                 if (ucr2 & UCR2_PREN) {
1702                         if (ucr2 & UCR2_PROE)
1703                                 *parity = 'o';
1704                         else
1705                                 *parity = 'e';
1706                 }
1707
1708                 if (ucr2 & UCR2_WS)
1709                         *bits = 8;
1710                 else
1711                         *bits = 7;
1712
1713                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1714                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1715
1716                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1717                 if (ucfr_rfdiv == 6)
1718                         ucfr_rfdiv = 7;
1719                 else
1720                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1721
1722                 uartclk = clk_get_rate(sport->clk_per);
1723                 uartclk /= ucfr_rfdiv;
1724
1725                 {       /*
1726                          * The next code provides exact computation of
1727                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1728                          * without need of float support or long long division,
1729                          * which would be required to prevent 32bit arithmetic overflow
1730                          */
1731                         unsigned int mul = ubir + 1;
1732                         unsigned int div = 16 * (ubmr + 1);
1733                         unsigned int rem = uartclk % div;
1734
1735                         baud_raw = (uartclk / div) * mul;
1736                         baud_raw += (rem * mul + div / 2) / div;
1737                         *baud = (baud_raw + 50) / 100 * 100;
1738                 }
1739
1740                 if (*baud != baud_raw)
1741                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1742                                 baud_raw, *baud);
1743         }
1744 }
1745
1746 static int __init
1747 imx_console_setup(struct console *co, char *options)
1748 {
1749         struct imx_port *sport;
1750         int baud = 9600;
1751         int bits = 8;
1752         int parity = 'n';
1753         int flow = 'n';
1754         int retval;
1755
1756         /*
1757          * Check whether an invalid uart number has been specified, and
1758          * if so, search for the first available port that does have
1759          * console support.
1760          */
1761         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1762                 co->index = 0;
1763         sport = imx_ports[co->index];
1764         if (sport == NULL)
1765                 return -ENODEV;
1766
1767         /* For setting the registers, we only need to enable the ipg clock. */
1768         retval = clk_prepare_enable(sport->clk_ipg);
1769         if (retval)
1770                 goto error_console;
1771
1772         if (options)
1773                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1774         else
1775                 imx_console_get_options(sport, &baud, &parity, &bits);
1776
1777         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1778
1779         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1780
1781         clk_disable_unprepare(sport->clk_ipg);
1782
1783 error_console:
1784         return retval;
1785 }
1786
1787 static struct uart_driver imx_reg;
1788 static struct console imx_console = {
1789         .name           = DEV_NAME,
1790         .write          = imx_console_write,
1791         .device         = uart_console_device,
1792         .setup          = imx_console_setup,
1793         .flags          = CON_PRINTBUFFER,
1794         .index          = -1,
1795         .data           = &imx_reg,
1796 };
1797
1798 #define IMX_CONSOLE     &imx_console
1799
1800 #ifdef CONFIG_OF
1801 static void imx_console_early_putchar(struct uart_port *port, int ch)
1802 {
1803         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1804                 cpu_relax();
1805
1806         writel_relaxed(ch, port->membase + URTX0);
1807 }
1808
1809 static void imx_console_early_write(struct console *con, const char *s,
1810                                     unsigned count)
1811 {
1812         struct earlycon_device *dev = con->data;
1813
1814         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1815 }
1816
1817 static int __init
1818 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1819 {
1820         if (!dev->port.membase)
1821                 return -ENODEV;
1822
1823         dev->con->write = imx_console_early_write;
1824
1825         return 0;
1826 }
1827 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1828 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1829 #endif
1830
1831 #else
1832 #define IMX_CONSOLE     NULL
1833 #endif
1834
1835 static struct uart_driver imx_reg = {
1836         .owner          = THIS_MODULE,
1837         .driver_name    = DRIVER_NAME,
1838         .dev_name       = DEV_NAME,
1839         .major          = SERIAL_IMX_MAJOR,
1840         .minor          = MINOR_START,
1841         .nr             = ARRAY_SIZE(imx_ports),
1842         .cons           = IMX_CONSOLE,
1843 };
1844
1845 #ifdef CONFIG_OF
1846 /*
1847  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1848  * could successfully get all information from dt or a negative errno.
1849  */
1850 static int serial_imx_probe_dt(struct imx_port *sport,
1851                 struct platform_device *pdev)
1852 {
1853         struct device_node *np = pdev->dev.of_node;
1854         const struct of_device_id *of_id =
1855                         of_match_device(imx_uart_dt_ids, &pdev->dev);
1856         int ret;
1857
1858         if (!np)
1859                 /* no device tree device */
1860                 return 1;
1861
1862         ret = of_alias_get_id(np, "serial");
1863         if (ret < 0) {
1864                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1865                 return ret;
1866         }
1867         sport->port.line = ret;
1868
1869         if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1870                 sport->have_rtscts = 1;
1871
1872         if (of_get_property(np, "fsl,dte-mode", NULL))
1873                 sport->dte_mode = 1;
1874
1875         sport->devdata = of_id->data;
1876
1877         return 0;
1878 }
1879 #else
1880 static inline int serial_imx_probe_dt(struct imx_port *sport,
1881                 struct platform_device *pdev)
1882 {
1883         return 1;
1884 }
1885 #endif
1886
1887 static void serial_imx_probe_pdata(struct imx_port *sport,
1888                 struct platform_device *pdev)
1889 {
1890         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1891
1892         sport->port.line = pdev->id;
1893         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
1894
1895         if (!pdata)
1896                 return;
1897
1898         if (pdata->flags & IMXUART_HAVE_RTSCTS)
1899                 sport->have_rtscts = 1;
1900 }
1901
1902 static int serial_imx_probe(struct platform_device *pdev)
1903 {
1904         struct imx_port *sport;
1905         void __iomem *base;
1906         int ret = 0, reg;
1907         struct resource *res;
1908         int txirq, rxirq, rtsirq;
1909
1910         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1911         if (!sport)
1912                 return -ENOMEM;
1913
1914         ret = serial_imx_probe_dt(sport, pdev);
1915         if (ret > 0)
1916                 serial_imx_probe_pdata(sport, pdev);
1917         else if (ret < 0)
1918                 return ret;
1919
1920         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1921         base = devm_ioremap_resource(&pdev->dev, res);
1922         if (IS_ERR(base))
1923                 return PTR_ERR(base);
1924
1925         rxirq = platform_get_irq(pdev, 0);
1926         txirq = platform_get_irq(pdev, 1);
1927         rtsirq = platform_get_irq(pdev, 2);
1928
1929         sport->port.dev = &pdev->dev;
1930         sport->port.mapbase = res->start;
1931         sport->port.membase = base;
1932         sport->port.type = PORT_IMX,
1933         sport->port.iotype = UPIO_MEM;
1934         sport->port.irq = rxirq;
1935         sport->port.fifosize = 32;
1936         sport->port.ops = &imx_pops;
1937         sport->port.rs485_config = imx_rs485_config;
1938         sport->port.rs485.flags =
1939                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1940         sport->port.flags = UPF_BOOT_AUTOCONF;
1941         init_timer(&sport->timer);
1942         sport->timer.function = imx_timeout;
1943         sport->timer.data     = (unsigned long)sport;
1944
1945         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1946         if (IS_ERR(sport->clk_ipg)) {
1947                 ret = PTR_ERR(sport->clk_ipg);
1948                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1949                 return ret;
1950         }
1951
1952         sport->clk_per = devm_clk_get(&pdev->dev, "per");
1953         if (IS_ERR(sport->clk_per)) {
1954                 ret = PTR_ERR(sport->clk_per);
1955                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1956                 return ret;
1957         }
1958
1959         sport->port.uartclk = clk_get_rate(sport->clk_per);
1960
1961         /* For register access, we only need to enable the ipg clock. */
1962         ret = clk_prepare_enable(sport->clk_ipg);
1963         if (ret)
1964                 return ret;
1965
1966         /* Disable interrupts before requesting them */
1967         reg = readl_relaxed(sport->port.membase + UCR1);
1968         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
1969                  UCR1_TXMPTYEN | UCR1_RTSDEN);
1970         writel_relaxed(reg, sport->port.membase + UCR1);
1971
1972         clk_disable_unprepare(sport->clk_ipg);
1973
1974         /*
1975          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1976          * chips only have one interrupt.
1977          */
1978         if (txirq > 0) {
1979                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
1980                                        dev_name(&pdev->dev), sport);
1981                 if (ret)
1982                         return ret;
1983
1984                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
1985                                        dev_name(&pdev->dev), sport);
1986                 if (ret)
1987                         return ret;
1988         } else {
1989                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
1990                                        dev_name(&pdev->dev), sport);
1991                 if (ret)
1992                         return ret;
1993         }
1994
1995         imx_ports[sport->port.line] = sport;
1996
1997         platform_set_drvdata(pdev, sport);
1998
1999         return uart_add_one_port(&imx_reg, &sport->port);
2000 }
2001
2002 static int serial_imx_remove(struct platform_device *pdev)
2003 {
2004         struct imx_port *sport = platform_get_drvdata(pdev);
2005
2006         return uart_remove_one_port(&imx_reg, &sport->port);
2007 }
2008
2009 static void serial_imx_restore_context(struct imx_port *sport)
2010 {
2011         if (!sport->context_saved)
2012                 return;
2013
2014         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2015         writel(sport->saved_reg[5], sport->port.membase + UESC);
2016         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2017         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2018         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2019         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2020         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2021         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2022         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2023         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2024         sport->context_saved = false;
2025 }
2026
2027 static void serial_imx_save_context(struct imx_port *sport)
2028 {
2029         /* Save necessary regs */
2030         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2031         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2032         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2033         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2034         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2035         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2036         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2037         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2038         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2039         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2040         sport->context_saved = true;
2041 }
2042
2043 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2044 {
2045         unsigned int val;
2046
2047         val = readl(sport->port.membase + UCR3);
2048         if (on)
2049                 val |= UCR3_AWAKEN;
2050         else
2051                 val &= ~UCR3_AWAKEN;
2052         writel(val, sport->port.membase + UCR3);
2053
2054         val = readl(sport->port.membase + UCR1);
2055         if (on)
2056                 val |= UCR1_RTSDEN;
2057         else
2058                 val &= ~UCR1_RTSDEN;
2059         writel(val, sport->port.membase + UCR1);
2060 }
2061
2062 static int imx_serial_port_suspend_noirq(struct device *dev)
2063 {
2064         struct platform_device *pdev = to_platform_device(dev);
2065         struct imx_port *sport = platform_get_drvdata(pdev);
2066         int ret;
2067
2068         ret = clk_enable(sport->clk_ipg);
2069         if (ret)
2070                 return ret;
2071
2072         serial_imx_save_context(sport);
2073
2074         clk_disable(sport->clk_ipg);
2075
2076         return 0;
2077 }
2078
2079 static int imx_serial_port_resume_noirq(struct device *dev)
2080 {
2081         struct platform_device *pdev = to_platform_device(dev);
2082         struct imx_port *sport = platform_get_drvdata(pdev);
2083         int ret;
2084
2085         ret = clk_enable(sport->clk_ipg);
2086         if (ret)
2087                 return ret;
2088
2089         serial_imx_restore_context(sport);
2090
2091         clk_disable(sport->clk_ipg);
2092
2093         return 0;
2094 }
2095
2096 static int imx_serial_port_suspend(struct device *dev)
2097 {
2098         struct platform_device *pdev = to_platform_device(dev);
2099         struct imx_port *sport = platform_get_drvdata(pdev);
2100
2101         /* enable wakeup from i.MX UART */
2102         serial_imx_enable_wakeup(sport, true);
2103
2104         uart_suspend_port(&imx_reg, &sport->port);
2105
2106         return 0;
2107 }
2108
2109 static int imx_serial_port_resume(struct device *dev)
2110 {
2111         struct platform_device *pdev = to_platform_device(dev);
2112         struct imx_port *sport = platform_get_drvdata(pdev);
2113
2114         /* disable wakeup from i.MX UART */
2115         serial_imx_enable_wakeup(sport, false);
2116
2117         uart_resume_port(&imx_reg, &sport->port);
2118
2119         return 0;
2120 }
2121
2122 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2123         .suspend_noirq = imx_serial_port_suspend_noirq,
2124         .resume_noirq = imx_serial_port_resume_noirq,
2125         .suspend = imx_serial_port_suspend,
2126         .resume = imx_serial_port_resume,
2127 };
2128
2129 static struct platform_driver serial_imx_driver = {
2130         .probe          = serial_imx_probe,
2131         .remove         = serial_imx_remove,
2132
2133         .id_table       = imx_uart_devtype,
2134         .driver         = {
2135                 .name   = "imx-uart",
2136                 .of_match_table = imx_uart_dt_ids,
2137                 .pm     = &imx_serial_port_pm_ops,
2138         },
2139 };
2140
2141 static int __init imx_serial_init(void)
2142 {
2143         int ret = uart_register_driver(&imx_reg);
2144
2145         if (ret)
2146                 return ret;
2147
2148         ret = platform_driver_register(&serial_imx_driver);
2149         if (ret != 0)
2150                 uart_unregister_driver(&imx_reg);
2151
2152         return ret;
2153 }
2154
2155 static void __exit imx_serial_exit(void)
2156 {
2157         platform_driver_unregister(&serial_imx_driver);
2158         uart_unregister_driver(&imx_reg);
2159 }
2160
2161 module_init(imx_serial_init);
2162 module_exit(imx_serial_exit);
2163
2164 MODULE_AUTHOR("Sascha Hauer");
2165 MODULE_DESCRIPTION("IMX generic serial port driver");
2166 MODULE_LICENSE("GPL");
2167 MODULE_ALIAS("platform:imx-uart");