drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 #include "serial_mctrl_gpio.h"
  48
  49 /* Register definitions */
  50 #define URXD0 0x0  /* Receiver Register */
  51 #define URTX0 0x40 /* Transmitter Register */
  52 #define UCR1  0x80 /* Control Register 1 */
  53 #define UCR2  0x84 /* Control Register 2 */
  54 #define UCR3  0x88 /* Control Register 3 */
  55 #define UCR4  0x8c /* Control Register 4 */
  56 #define UFCR  0x90 /* FIFO Control Register */
  57 #define USR1  0x94 /* Status Register 1 */
  58 #define USR2  0x98 /* Status Register 2 */
  59 #define UESC  0x9c /* Escape Character Register */
  60 #define UTIM  0xa0 /* Escape Timer Register */
  61 #define UBIR  0xa4 /* BRM Incremental Register */
  62 #define UBMR  0xa8 /* BRM Modulator Register */
  63 #define UBRC  0xac /* Baud Rate Count Register */
  64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  67
  68 /* UART Control Register Bit Fields.*/
  69 #define URXD_DUMMY_READ (1<<16)
  70 #define URXD_CHARRDY    (1<<15)
  71 #define URXD_ERR        (1<<14)
  72 #define URXD_OVRRUN     (1<<13)
  73 #define URXD_FRMERR     (1<<12)
  74 #define URXD_BRK        (1<<11)
  75 #define URXD_PRERR      (1<<10)
  76 #define URXD_RX_DATA    (0xFF<<0)
  77 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  78 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  79 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  80 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  82 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  83 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  84 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  85 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  86 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  87 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  88 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  90 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  91 #define UCR1_DOZE       (1<<1)  /* Doze */
  92 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  93 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  94 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  95 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  96 #define UCR2_CTS        (1<<12) /* Clear to send */
  97 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  98 #define UCR2_PREN       (1<<8)  /* Parity enable */
  99 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
 100 #define UCR2_STPB       (1<<6)  /* Stop */
 101 #define UCR2_WS         (1<<5)  /* Word size */
 102 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 103 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 104 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 105 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 106 #define UCR2_SRST       (1<<0)  /* SW reset */
 107 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 108 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 109 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 110 #define UCR3_DSR        (1<<10) /* Data set ready */
 111 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 112 #define UCR3_RI         (1<<8)  /* Ring indicator */
 113 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 114 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 115 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 116 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 117 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 118 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 119 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 120 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 121 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 122 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 123 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 124 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 125 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 126 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 127 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 128 #define UCR4_IRSC       (1<<5)  /* IR special case */
 129 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 130 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 131 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 132 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 133 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 134 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 135 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 136 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 137 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 138 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 139 #define USR1_RTSS       (1<<14) /* RTS pin status */
 140 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 141 #define USR1_RTSD       (1<<12) /* RTS delta */
 142 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 143 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 144 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 145 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 146 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 147 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 148 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 149 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 150 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 151 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 152 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 153 #define USR2_IDLE        (1<<12) /* Idle condition */
 154 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 155 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 156 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 157 #define USR2_WAKE        (1<<7)  /* Wake */
 158 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 159 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 160 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 161 #define USR2_BRCD        (1<<2)  /* Break condition */
 162 #define USR2_ORE        (1<<1)   /* Overrun error */
 163 #define USR2_RDR        (1<<0)   /* Recv data ready */
 164 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 165 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 166 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 167 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 168 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 169 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 170 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 171
 172 /* We've been assigned a range on the "Low-density serial ports" major */
 173 #define SERIAL_IMX_MAJOR        207
 174 #define MINOR_START             16
 175 #define DEV_NAME                "ttymxc"
 176
 177 /*
 178  * This determines how often we check the modem status signals
 179  * for any change.  They generally aren't connected to an IRQ
 180  * so we have to poll them.  We also check immediately before
 181  * filling the TX fifo incase CTS has been dropped.
 182  */
 183 #define MCTRL_TIMEOUT   (250*HZ/1000)
 184
 185 #define DRIVER_NAME "IMX-uart"
 186
 187 #define UART_NR 8
 188
 189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 190 enum imx_uart_type {
 191         IMX1_UART,
 192         IMX21_UART,
 193         IMX53_UART,
 194         IMX6Q_UART,
 195 };
 196
 197 /* device type dependent stuff */
 198 struct imx_uart_data {
 199         unsigned uts_reg;
 200         enum imx_uart_type devtype;
 201 };
 202
 203 struct imx_port {
 204         struct uart_port        port;
 205         struct timer_list       timer;
 206         unsigned int            old_status;
 207         unsigned int            have_rtscts:1;
 208         unsigned int            dte_mode:1;
 209         unsigned int            irda_inv_rx:1;
 210         unsigned int            irda_inv_tx:1;
 211         unsigned short          trcv_delay; /* transceiver delay */
 212         struct clk              *clk_ipg;
 213         struct clk              *clk_per;
 214         const struct imx_uart_data *devdata;
 215
 216         struct mctrl_gpios *gpios;
 217
 218         /* DMA fields */
 219         unsigned int            dma_is_inited:1;
 220         unsigned int            dma_is_enabled:1;
 221         unsigned int            dma_is_rxing:1;
 222         unsigned int            dma_is_txing:1;
 223         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 224         struct scatterlist      rx_sgl, tx_sgl[2];
 225         void                    *rx_buf;
 226         struct circ_buf         rx_ring;
 227         unsigned int            rx_periods;
 228         dma_cookie_t            rx_cookie;
 229         unsigned int            tx_bytes;
 230         unsigned int            dma_tx_nents;
 231         wait_queue_head_t       dma_wait;
 232         unsigned int            saved_reg[10];
 233         bool                    context_saved;
 234 };
 235
 236 struct imx_port_ucrs {
 237         unsigned int    ucr1;
 238         unsigned int    ucr2;
 239         unsigned int    ucr3;
 240 };
 241
 242 static struct imx_uart_data imx_uart_devdata[] = {
 243         [IMX1_UART] = {
 244                 .uts_reg = IMX1_UTS,
 245                 .devtype = IMX1_UART,
 246         },
 247         [IMX21_UART] = {
 248                 .uts_reg = IMX21_UTS,
 249                 .devtype = IMX21_UART,
 250         },
 251         [IMX53_UART] = {
 252                 .uts_reg = IMX21_UTS,
 253                 .devtype = IMX53_UART,
 254         },
 255         [IMX6Q_UART] = {
 256                 .uts_reg = IMX21_UTS,
 257                 .devtype = IMX6Q_UART,
 258         },
 259 };
 260
 261 static const struct platform_device_id imx_uart_devtype[] = {
 262         {
 263                 .name = "imx1-uart",
 264                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 265         }, {
 266                 .name = "imx21-uart",
 267                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 268         }, {
 269                 .name = "imx53-uart",
 270                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 271         }, {
 272                 .name = "imx6q-uart",
 273                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 274         }, {
 275                 /* sentinel */
 276         }
 277 };
 278 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 279
 280 static const struct of_device_id imx_uart_dt_ids[] = {
 281         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 282         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 283         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 284         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 285         { /* sentinel */ }
 286 };
 287 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 288
 289 static inline unsigned uts_reg(struct imx_port *sport)
 290 {
 291         return sport->devdata->uts_reg;
 292 }
 293
 294 static inline int is_imx1_uart(struct imx_port *sport)
 295 {
 296         return sport->devdata->devtype == IMX1_UART;
 297 }
 298
 299 static inline int is_imx21_uart(struct imx_port *sport)
 300 {
 301         return sport->devdata->devtype == IMX21_UART;
 302 }
 303
 304 static inline int is_imx53_uart(struct imx_port *sport)
 305 {
 306         return sport->devdata->devtype == IMX53_UART;
 307 }
 308
 309 static inline int is_imx6q_uart(struct imx_port *sport)
 310 {
 311         return sport->devdata->devtype == IMX6Q_UART;
 312 }
 313 /*
 314  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 315  */
 316 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 317 static void imx_port_ucrs_save(struct uart_port *port,
 318                                struct imx_port_ucrs *ucr)
 319 {
 320         /* save control registers */
 321         ucr->ucr1 = readl(port->membase + UCR1);
 322         ucr->ucr2 = readl(port->membase + UCR2);
 323         ucr->ucr3 = readl(port->membase + UCR3);
 324 }
 325
 326 static void imx_port_ucrs_restore(struct uart_port *port,
 327                                   struct imx_port_ucrs *ucr)
 328 {
 329         /* restore control registers */
 330         writel(ucr->ucr1, port->membase + UCR1);
 331         writel(ucr->ucr2, port->membase + UCR2);
 332         writel(ucr->ucr3, port->membase + UCR3);
 333 }
 334 #endif
 335
 336 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 337 {
 338         *ucr2 &= ~UCR2_CTSC;
 339         *ucr2 |= UCR2_CTS;
 340
 341         mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
 342 }
 343
 344 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 345 {
 346         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 347
 348         mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
 349 }
 350
 351 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 352 {
 353         *ucr2 |= UCR2_CTSC;
 354 }
 355
 356 /*
 357  * interrupts disabled on entry
 358  */
 359 static void imx_stop_tx(struct uart_port *port)
 360 {
 361         struct imx_port *sport = (struct imx_port *)port;
 362         unsigned long temp;
 363
 364         /*
 365          * We are maybe in the SMP context, so if the DMA TX thread is running
 366          * on other cpu, we have to wait for it to finish.
 367          */
 368         if (sport->dma_is_enabled && sport->dma_is_txing)
 369                 return;
 370
 371         temp = readl(port->membase + UCR1);
 372         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 373
 374         /* in rs485 mode disable transmitter if shifter is empty */
 375         if (port->rs485.flags & SER_RS485_ENABLED &&
 376             readl(port->membase + USR2) & USR2_TXDC) {
 377                 temp = readl(port->membase + UCR2);
 378                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 379                         imx_port_rts_inactive(sport, &temp);
 380                 else
 381                         imx_port_rts_active(sport, &temp);
 382                 temp |= UCR2_RXEN;
 383                 writel(temp, port->membase + UCR2);
 384
 385                 temp = readl(port->membase + UCR4);
 386                 temp &= ~UCR4_TCEN;
 387                 writel(temp, port->membase + UCR4);
 388         }
 389 }
 390
 391 /*
 392  * interrupts disabled on entry
 393  */
 394 static void imx_stop_rx(struct uart_port *port)
 395 {
 396         struct imx_port *sport = (struct imx_port *)port;
 397         unsigned long temp;
 398
 399         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 400                 if (sport->port.suspended) {
 401                         dmaengine_terminate_all(sport->dma_chan_rx);
 402                         sport->dma_is_rxing = 0;
 403                 } else {
 404                         return;
 405                 }
 406         }
 407
 408         temp = readl(sport->port.membase + UCR2);
 409         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 410
 411         /* disable the `Receiver Ready Interrrupt` */
 412         temp = readl(sport->port.membase + UCR1);
 413         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 414 }
 415
 416 /*
 417  * Set the modem control timer to fire immediately.
 418  */
 419 static void imx_enable_ms(struct uart_port *port)
 420 {
 421         struct imx_port *sport = (struct imx_port *)port;
 422
 423         mod_timer(&sport->timer, jiffies);
 424
 425         mctrl_gpio_enable_ms(sport->gpios);
 426 }
 427
 428 static void imx_dma_tx(struct imx_port *sport);
 429 static inline void imx_transmit_buffer(struct imx_port *sport)
 430 {
 431         struct circ_buf *xmit = &sport->port.state->xmit;
 432         unsigned long temp;
 433
 434         if (sport->port.x_char) {
 435                 /* Send next char */
 436                 writel(sport->port.x_char, sport->port.membase + URTX0);
 437                 sport->port.icount.tx++;
 438                 sport->port.x_char = 0;
 439                 return;
 440         }
 441
 442         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 443                 imx_stop_tx(&sport->port);
 444                 return;
 445         }
 446
 447         if (sport->dma_is_enabled) {
 448                 /*
 449                  * We've just sent a X-char Ensure the TX DMA is enabled
 450                  * and the TX IRQ is disabled.
 451                  **/
 452                 temp = readl(sport->port.membase + UCR1);
 453                 temp &= ~UCR1_TXMPTYEN;
 454                 if (sport->dma_is_txing) {
 455                         temp |= UCR1_TDMAEN;
 456                         writel(temp, sport->port.membase + UCR1);
 457                 } else {
 458                         writel(temp, sport->port.membase + UCR1);
 459                         imx_dma_tx(sport);
 460                 }
 461         }
 462
 463         while (!uart_circ_empty(xmit) &&
 464                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 465                 /* send xmit->buf[xmit->tail]
 466                  * out the port here */
 467                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 468                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 469                 sport->port.icount.tx++;
 470         }
 471
 472         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 473                 uart_write_wakeup(&sport->port);
 474
 475         if (uart_circ_empty(xmit))
 476                 imx_stop_tx(&sport->port);
 477 }
 478
 479 static void dma_tx_callback(void *data)
 480 {
 481         struct imx_port *sport = data;
 482         struct scatterlist *sgl = &sport->tx_sgl[0];
 483         struct circ_buf *xmit = &sport->port.state->xmit;
 484         unsigned long flags;
 485         unsigned long temp;
 486
 487         spin_lock_irqsave(&sport->port.lock, flags);
 488
 489         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 490
 491         temp = readl(sport->port.membase + UCR1);
 492         temp &= ~UCR1_TDMAEN;
 493         writel(temp, sport->port.membase + UCR1);
 494
 495         /* update the stat */
 496         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 497         sport->port.icount.tx += sport->tx_bytes;
 498
 499         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 500
 501         sport->dma_is_txing = 0;
 502
 503         spin_unlock_irqrestore(&sport->port.lock, flags);
 504
 505         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 506                 uart_write_wakeup(&sport->port);
 507
 508         if (waitqueue_active(&sport->dma_wait)) {
 509                 wake_up(&sport->dma_wait);
 510                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
 511                 return;
 512         }
 513
 514         spin_lock_irqsave(&sport->port.lock, flags);
 515         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 516                 imx_dma_tx(sport);
 517         spin_unlock_irqrestore(&sport->port.lock, flags);
 518 }
 519
 520 static void imx_dma_tx(struct imx_port *sport)
 521 {
 522         struct circ_buf *xmit = &sport->port.state->xmit;
 523         struct scatterlist *sgl = sport->tx_sgl;
 524         struct dma_async_tx_descriptor *desc;
 525         struct dma_chan *chan = sport->dma_chan_tx;
 526         struct device *dev = sport->port.dev;
 527         unsigned long temp;
 528         int ret;
 529
 530         if (sport->dma_is_txing)
 531                 return;
 532
 533         sport->tx_bytes = uart_circ_chars_pending(xmit);
 534
 535         if (xmit->tail < xmit->head) {
 536                 sport->dma_tx_nents = 1;
 537                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 538         } else {
 539                 sport->dma_tx_nents = 2;
 540                 sg_init_table(sgl, 2);
 541                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 542                                 UART_XMIT_SIZE - xmit->tail);
 543                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 544         }
 545
 546         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 547         if (ret == 0) {
 548                 dev_err(dev, "DMA mapping error for TX.\n");
 549                 return;
 550         }
 551         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 552                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 553         if (!desc) {
 554                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 555                              DMA_TO_DEVICE);
 556                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 557                 return;
 558         }
 559         desc->callback = dma_tx_callback;
 560         desc->callback_param = sport;
 561
 562         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 563                         uart_circ_chars_pending(xmit));
 564
 565         temp = readl(sport->port.membase + UCR1);
 566         temp |= UCR1_TDMAEN;
 567         writel(temp, sport->port.membase + UCR1);
 568
 569         /* fire it */
 570         sport->dma_is_txing = 1;
 571         dmaengine_submit(desc);
 572         dma_async_issue_pending(chan);
 573         return;
 574 }
 575
 576 /*
 577  * interrupts disabled on entry
 578  */
 579 static void imx_start_tx(struct uart_port *port)
 580 {
 581         struct imx_port *sport = (struct imx_port *)port;
 582         unsigned long temp;
 583
 584         if (port->rs485.flags & SER_RS485_ENABLED) {
 585                 temp = readl(port->membase + UCR2);
 586                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 587                         imx_port_rts_inactive(sport, &temp);
 588                 else
 589                         imx_port_rts_active(sport, &temp);
 590                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 591                         temp &= ~UCR2_RXEN;
 592                 writel(temp, port->membase + UCR2);
 593
 594                 /* enable transmitter and shifter empty irq */
 595                 temp = readl(port->membase + UCR4);
 596                 temp |= UCR4_TCEN;
 597                 writel(temp, port->membase + UCR4);
 598         }
 599
 600         if (!sport->dma_is_enabled) {
 601                 temp = readl(sport->port.membase + UCR1);
 602                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 603         }
 604
 605         if (sport->dma_is_enabled) {
 606                 if (sport->port.x_char) {
 607                         /* We have X-char to send, so enable TX IRQ and
 608                          * disable TX DMA to let TX interrupt to send X-char */
 609                         temp = readl(sport->port.membase + UCR1);
 610                         temp &= ~UCR1_TDMAEN;
 611                         temp |= UCR1_TXMPTYEN;
 612                         writel(temp, sport->port.membase + UCR1);
 613                         return;
 614                 }
 615
 616                 if (!uart_circ_empty(&port->state->xmit) &&
 617                     !uart_tx_stopped(port))
 618                         imx_dma_tx(sport);
 619                 return;
 620         }
 621 }
 622
 623 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 624 {
 625         struct imx_port *sport = dev_id;
 626         unsigned int val;
 627         unsigned long flags;
 628
 629         spin_lock_irqsave(&sport->port.lock, flags);
 630
 631         writel(USR1_RTSD, sport->port.membase + USR1);
 632         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 633         uart_handle_cts_change(&sport->port, !!val);
 634         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 635
 636         spin_unlock_irqrestore(&sport->port.lock, flags);
 637         return IRQ_HANDLED;
 638 }
 639
 640 static irqreturn_t imx_txint(int irq, void *dev_id)
 641 {
 642         struct imx_port *sport = dev_id;
 643         unsigned long flags;
 644
 645         spin_lock_irqsave(&sport->port.lock, flags);
 646         imx_transmit_buffer(sport);
 647         spin_unlock_irqrestore(&sport->port.lock, flags);
 648         return IRQ_HANDLED;
 649 }
 650
 651 static irqreturn_t imx_rxint(int irq, void *dev_id)
 652 {
 653         struct imx_port *sport = dev_id;
 654         unsigned int rx, flg, ignored = 0;
 655         struct tty_port *port = &sport->port.state->port;
 656         unsigned long flags, temp;
 657
 658         spin_lock_irqsave(&sport->port.lock, flags);
 659
 660         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 661                 flg = TTY_NORMAL;
 662                 sport->port.icount.rx++;
 663
 664                 rx = readl(sport->port.membase + URXD0);
 665
 666                 temp = readl(sport->port.membase + USR2);
 667                 if (temp & USR2_BRCD) {
 668                         writel(USR2_BRCD, sport->port.membase + USR2);
 669                         if (uart_handle_break(&sport->port))
 670                                 continue;
 671                 }
 672
 673                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 674                         continue;
 675
 676                 if (unlikely(rx & URXD_ERR)) {
 677                         if (rx & URXD_BRK)
 678                                 sport->port.icount.brk++;
 679                         else if (rx & URXD_PRERR)
 680                                 sport->port.icount.parity++;
 681                         else if (rx & URXD_FRMERR)
 682                                 sport->port.icount.frame++;
 683                         if (rx & URXD_OVRRUN)
 684                                 sport->port.icount.overrun++;
 685
 686                         if (rx & sport->port.ignore_status_mask) {
 687                                 if (++ignored > 100)
 688                                         goto out;
 689                                 continue;
 690                         }
 691
 692                         rx &= (sport->port.read_status_mask | 0xFF);
 693
 694                         if (rx & URXD_BRK)
 695                                 flg = TTY_BREAK;
 696                         else if (rx & URXD_PRERR)
 697                                 flg = TTY_PARITY;
 698                         else if (rx & URXD_FRMERR)
 699                                 flg = TTY_FRAME;
 700                         if (rx & URXD_OVRRUN)
 701                                 flg = TTY_OVERRUN;
 702
 703 #ifdef SUPPORT_SYSRQ
 704                         sport->port.sysrq = 0;
 705 #endif
 706                 }
 707
 708                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 709                         goto out;
 710
 711                 if (tty_insert_flip_char(port, rx, flg) == 0)
 712                         sport->port.icount.buf_overrun++;
 713         }
 714
 715 out:
 716         spin_unlock_irqrestore(&sport->port.lock, flags);
 717         tty_flip_buffer_push(port);
 718         return IRQ_HANDLED;
 719 }
 720
 721 static void clear_rx_errors(struct imx_port *sport);
 722 static int start_rx_dma(struct imx_port *sport);
 723 /*
 724  * If the RXFIFO is filled with some data, and then we
 725  * arise a DMA operation to receive them.
 726  */
 727 static void imx_dma_rxint(struct imx_port *sport)
 728 {
 729         unsigned long temp;
 730         unsigned long flags;
 731
 732         spin_lock_irqsave(&sport->port.lock, flags);
 733
 734         temp = readl(sport->port.membase + USR2);
 735         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 736                 sport->dma_is_rxing = 1;
 737
 738                 /* disable the receiver ready and aging timer interrupts */
 739                 temp = readl(sport->port.membase + UCR1);
 740                 temp &= ~(UCR1_RRDYEN);
 741                 writel(temp, sport->port.membase + UCR1);
 742
 743                 temp = readl(sport->port.membase + UCR2);
 744                 temp &= ~(UCR2_ATEN);
 745                 writel(temp, sport->port.membase + UCR2);
 746
 747                 /* disable the rx errors interrupts */
 748                 temp = readl(sport->port.membase + UCR4);
 749                 temp &= ~UCR4_OREN;
 750                 writel(temp, sport->port.membase + UCR4);
 751
 752                 /* tell the DMA to receive the data. */
 753                 start_rx_dma(sport);
 754         }
 755
 756         spin_unlock_irqrestore(&sport->port.lock, flags);
 757 }
 758
 759 /*
 760  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 761  */
 762 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 763 {
 764         unsigned int tmp = TIOCM_DSR;
 765         unsigned usr1 = readl(sport->port.membase + USR1);
 766
 767         if (usr1 & USR1_RTSS)
 768                 tmp |= TIOCM_CTS;
 769
 770         /* in DCE mode DCDIN is always 0 */
 771         if (!(usr1 & USR2_DCDIN))
 772                 tmp |= TIOCM_CAR;
 773
 774         if (sport->dte_mode)
 775                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 776                         tmp |= TIOCM_RI;
 777
 778         return tmp;
 779 }
 780
 781 /*
 782  * Handle any change of modem status signal since we were last called.
 783  */
 784 static void imx_mctrl_check(struct imx_port *sport)
 785 {
 786         unsigned int status, changed;
 787
 788         status = imx_get_hwmctrl(sport);
 789         changed = status ^ sport->old_status;
 790
 791         if (changed == 0)
 792                 return;
 793
 794         sport->old_status = status;
 795
 796         if (changed & TIOCM_RI && status & TIOCM_RI)
 797                 sport->port.icount.rng++;
 798         if (changed & TIOCM_DSR)
 799                 sport->port.icount.dsr++;
 800         if (changed & TIOCM_CAR)
 801                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 802         if (changed & TIOCM_CTS)
 803                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 804
 805         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 806 }
 807
 808 static irqreturn_t imx_int(int irq, void *dev_id)
 809 {
 810         struct imx_port *sport = dev_id;
 811         unsigned int sts;
 812         unsigned int sts2;
 813         irqreturn_t ret = IRQ_NONE;
 814
 815         sts = readl(sport->port.membase + USR1);
 816         sts2 = readl(sport->port.membase + USR2);
 817
 818         if (sts & (USR1_RRDY | USR1_AGTIM)) {
 819                 if (sport->dma_is_enabled)
 820                         imx_dma_rxint(sport);
 821                 else
 822                         imx_rxint(irq, dev_id);
 823                 ret = IRQ_HANDLED;
 824         }
 825
 826         if ((sts & USR1_TRDY &&
 827              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 828             (sts2 & USR2_TXDC &&
 829              readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
 830                 imx_txint(irq, dev_id);
 831                 ret = IRQ_HANDLED;
 832         }
 833
 834         if (sts & USR1_DTRD) {
 835                 unsigned long flags;
 836
 837                 if (sts & USR1_DTRD)
 838                         writel(USR1_DTRD, sport->port.membase + USR1);
 839
 840                 spin_lock_irqsave(&sport->port.lock, flags);
 841                 imx_mctrl_check(sport);
 842                 spin_unlock_irqrestore(&sport->port.lock, flags);
 843
 844                 ret = IRQ_HANDLED;
 845         }
 846
 847         if (sts & USR1_RTSD) {
 848                 imx_rtsint(irq, dev_id);
 849                 ret = IRQ_HANDLED;
 850         }
 851
 852         if (sts & USR1_AWAKE) {
 853                 writel(USR1_AWAKE, sport->port.membase + USR1);
 854                 ret = IRQ_HANDLED;
 855         }
 856
 857         if (sts2 & USR2_ORE) {
 858                 sport->port.icount.overrun++;
 859                 writel(USR2_ORE, sport->port.membase + USR2);
 860                 ret = IRQ_HANDLED;
 861         }
 862
 863         return ret;
 864 }
 865
 866 /*
 867  * Return TIOCSER_TEMT when transmitter is not busy.
 868  */
 869 static unsigned int imx_tx_empty(struct uart_port *port)
 870 {
 871         struct imx_port *sport = (struct imx_port *)port;
 872         unsigned int ret;
 873
 874         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 875
 876         /* If the TX DMA is working, return 0. */
 877         if (sport->dma_is_enabled && sport->dma_is_txing)
 878                 ret = 0;
 879
 880         return ret;
 881 }
 882
 883 static unsigned int imx_get_mctrl(struct uart_port *port)
 884 {
 885         struct imx_port *sport = (struct imx_port *)port;
 886         unsigned int ret = imx_get_hwmctrl(sport);
 887
 888         mctrl_gpio_get(sport->gpios, &ret);
 889
 890         return ret;
 891 }
 892
 893 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 894 {
 895         struct imx_port *sport = (struct imx_port *)port;
 896         unsigned long temp;
 897
 898         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 899                 temp = readl(sport->port.membase + UCR2);
 900                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 901                 if (mctrl & TIOCM_RTS)
 902                         temp |= UCR2_CTS | UCR2_CTSC;
 903                 writel(temp, sport->port.membase + UCR2);
 904         }
 905
 906         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 907         if (!(mctrl & TIOCM_DTR))
 908                 temp |= UCR3_DSR;
 909         writel(temp, sport->port.membase + UCR3);
 910
 911         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 912         if (mctrl & TIOCM_LOOP)
 913                 temp |= UTS_LOOP;
 914         writel(temp, sport->port.membase + uts_reg(sport));
 915
 916         mctrl_gpio_set(sport->gpios, mctrl);
 917 }
 918
 919 /*
 920  * Interrupts always disabled.
 921  */
 922 static void imx_break_ctl(struct uart_port *port, int break_state)
 923 {
 924         struct imx_port *sport = (struct imx_port *)port;
 925         unsigned long flags, temp;
 926
 927         spin_lock_irqsave(&sport->port.lock, flags);
 928
 929         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 930
 931         if (break_state != 0)
 932                 temp |= UCR1_SNDBRK;
 933
 934         writel(temp, sport->port.membase + UCR1);
 935
 936         spin_unlock_irqrestore(&sport->port.lock, flags);
 937 }
 938
 939 /*
 940  * This is our per-port timeout handler, for checking the
 941  * modem status signals.
 942  */
 943 static void imx_timeout(unsigned long data)
 944 {
 945         struct imx_port *sport = (struct imx_port *)data;
 946         unsigned long flags;
 947
 948         if (sport->port.state) {
 949                 spin_lock_irqsave(&sport->port.lock, flags);
 950                 imx_mctrl_check(sport);
 951                 spin_unlock_irqrestore(&sport->port.lock, flags);
 952
 953                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 954         }
 955 }
 956
 957 #define RX_BUF_SIZE     (PAGE_SIZE)
 958
 959 /*
 960  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
 961  *   [1] the RX DMA buffer is full.
 962  *   [2] the aging timer expires
 963  *
 964  * Condition [2] is triggered when a character has been sitting in the FIFO
 965  * for at least 8 byte durations.
 966  */
 967 static void dma_rx_callback(void *data)
 968 {
 969         struct imx_port *sport = data;
 970         struct dma_chan *chan = sport->dma_chan_rx;
 971         struct scatterlist *sgl = &sport->rx_sgl;
 972         struct tty_port *port = &sport->port.state->port;
 973         struct dma_tx_state state;
 974         struct circ_buf *rx_ring = &sport->rx_ring;
 975         enum dma_status status;
 976         unsigned int w_bytes = 0;
 977         unsigned int r_bytes;
 978         unsigned int bd_size;
 979
 980         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 981
 982         if (status == DMA_ERROR) {
 983                 dev_err(sport->port.dev, "DMA transaction error.\n");
 984                 clear_rx_errors(sport);
 985                 return;
 986         }
 987
 988         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 989
 990                 /*
 991                  * The state-residue variable represents the empty space
 992                  * relative to the entire buffer. Taking this in consideration
 993                  * the head is always calculated base on the buffer total
 994                  * length - DMA transaction residue. The UART script from the
 995                  * SDMA firmware will jump to the next buffer descriptor,
 996                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
 997                  * Taking this in consideration the tail is always at the
 998                  * beginning of the buffer descriptor that contains the head.
 999                  */
1000
1001                 /* Calculate the head */
1002                 rx_ring->head = sg_dma_len(sgl) - state.residue;
1003
1004                 /* Calculate the tail. */
1005                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1006                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1007
1008                 if (rx_ring->head <= sg_dma_len(sgl) &&
1009                     rx_ring->head > rx_ring->tail) {
1010
1011                         /* Move data from tail to head */
1012                         r_bytes = rx_ring->head - rx_ring->tail;
1013
1014                         /* CPU claims ownership of RX DMA buffer */
1015                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1016                                 DMA_FROM_DEVICE);
1017
1018                         w_bytes = tty_insert_flip_string(port,
1019                                 sport->rx_buf + rx_ring->tail, r_bytes);
1020
1021                         /* UART retrieves ownership of RX DMA buffer */
1022                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1023                                 DMA_FROM_DEVICE);
1024
1025                         if (w_bytes != r_bytes)
1026                                 sport->port.icount.buf_overrun++;
1027
1028                         sport->port.icount.rx += w_bytes;
1029                 } else  {
1030                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
1031                         WARN_ON(rx_ring->head <= rx_ring->tail);
1032                 }
1033         }
1034
1035         if (w_bytes) {
1036                 tty_flip_buffer_push(port);
1037                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1038         }
1039 }
1040
1041 /* RX DMA buffer periods */
1042 #define RX_DMA_PERIODS 4
1043
1044 static int start_rx_dma(struct imx_port *sport)
1045 {
1046         struct scatterlist *sgl = &sport->rx_sgl;
1047         struct dma_chan *chan = sport->dma_chan_rx;
1048         struct device *dev = sport->port.dev;
1049         struct dma_async_tx_descriptor *desc;
1050         int ret;
1051
1052         sport->rx_ring.head = 0;
1053         sport->rx_ring.tail = 0;
1054         sport->rx_periods = RX_DMA_PERIODS;
1055
1056         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1057         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1058         if (ret == 0) {
1059                 dev_err(dev, "DMA mapping error for RX.\n");
1060                 return -EINVAL;
1061         }
1062
1063         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1064                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1065                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1066
1067         if (!desc) {
1068                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1069                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1070                 return -EINVAL;
1071         }
1072         desc->callback = dma_rx_callback;
1073         desc->callback_param = sport;
1074
1075         dev_dbg(dev, "RX: prepare for the DMA.\n");
1076         sport->rx_cookie = dmaengine_submit(desc);
1077         dma_async_issue_pending(chan);
1078         return 0;
1079 }
1080
1081 static void clear_rx_errors(struct imx_port *sport)
1082 {
1083         unsigned int status_usr1, status_usr2;
1084
1085         status_usr1 = readl(sport->port.membase + USR1);
1086         status_usr2 = readl(sport->port.membase + USR2);
1087
1088         if (status_usr2 & USR2_BRCD) {
1089                 sport->port.icount.brk++;
1090                 writel(USR2_BRCD, sport->port.membase + USR2);
1091         } else if (status_usr1 & USR1_FRAMERR) {
1092                 sport->port.icount.frame++;
1093                 writel(USR1_FRAMERR, sport->port.membase + USR1);
1094         } else if (status_usr1 & USR1_PARITYERR) {
1095                 sport->port.icount.parity++;
1096                 writel(USR1_PARITYERR, sport->port.membase + USR1);
1097         }
1098
1099         if (status_usr2 & USR2_ORE) {
1100                 sport->port.icount.overrun++;
1101                 writel(USR2_ORE, sport->port.membase + USR2);
1102         }
1103
1104 }
1105
1106 #define TXTL_DEFAULT 2 /* reset default */
1107 #define RXTL_DEFAULT 1 /* reset default */
1108 #define TXTL_DMA 8 /* DMA burst setting */
1109 #define RXTL_DMA 9 /* DMA burst setting */
1110
1111 static void imx_setup_ufcr(struct imx_port *sport,
1112                           unsigned char txwl, unsigned char rxwl)
1113 {
1114         unsigned int val;
1115
1116         /* set receiver / transmitter trigger level */
1117         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1118         val |= txwl << UFCR_TXTL_SHF | rxwl;
1119         writel(val, sport->port.membase + UFCR);
1120 }
1121
1122 static void imx_uart_dma_exit(struct imx_port *sport)
1123 {
1124         if (sport->dma_chan_rx) {
1125                 dmaengine_terminate_all(sport->dma_chan_rx);
1126                 dma_release_channel(sport->dma_chan_rx);
1127                 sport->dma_chan_rx = NULL;
1128                 sport->rx_cookie = -EINVAL;
1129                 kfree(sport->rx_buf);
1130                 sport->rx_buf = NULL;
1131         }
1132
1133         if (sport->dma_chan_tx) {
1134                 dmaengine_terminate_all(sport->dma_chan_tx);
1135                 dma_release_channel(sport->dma_chan_tx);
1136                 sport->dma_chan_tx = NULL;
1137         }
1138
1139         sport->dma_is_inited = 0;
1140 }
1141
1142 static int imx_uart_dma_init(struct imx_port *sport)
1143 {
1144         struct dma_slave_config slave_config = {};
1145         struct device *dev = sport->port.dev;
1146         int ret;
1147
1148         /* Prepare for RX : */
1149         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1150         if (!sport->dma_chan_rx) {
1151                 dev_dbg(dev, "cannot get the DMA channel.\n");
1152                 ret = -EINVAL;
1153                 goto err;
1154         }
1155
1156         slave_config.direction = DMA_DEV_TO_MEM;
1157         slave_config.src_addr = sport->port.mapbase + URXD0;
1158         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1159         /* one byte less than the watermark level to enable the aging timer */
1160         slave_config.src_maxburst = RXTL_DMA - 1;
1161         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1162         if (ret) {
1163                 dev_err(dev, "error in RX dma configuration.\n");
1164                 goto err;
1165         }
1166
1167         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1168         if (!sport->rx_buf) {
1169                 ret = -ENOMEM;
1170                 goto err;
1171         }
1172         sport->rx_ring.buf = sport->rx_buf;
1173
1174         /* Prepare for TX : */
1175         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1176         if (!sport->dma_chan_tx) {
1177                 dev_err(dev, "cannot get the TX DMA channel!\n");
1178                 ret = -EINVAL;
1179                 goto err;
1180         }
1181
1182         slave_config.direction = DMA_MEM_TO_DEV;
1183         slave_config.dst_addr = sport->port.mapbase + URTX0;
1184         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1185         slave_config.dst_maxburst = TXTL_DMA;
1186         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1187         if (ret) {
1188                 dev_err(dev, "error in TX dma configuration.");
1189                 goto err;
1190         }
1191
1192         sport->dma_is_inited = 1;
1193
1194         return 0;
1195 err:
1196         imx_uart_dma_exit(sport);
1197         return ret;
1198 }
1199
1200 static void imx_enable_dma(struct imx_port *sport)
1201 {
1202         unsigned long temp;
1203
1204         init_waitqueue_head(&sport->dma_wait);
1205
1206         /* set UCR1 */
1207         temp = readl(sport->port.membase + UCR1);
1208         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1209         writel(temp, sport->port.membase + UCR1);
1210
1211         temp = readl(sport->port.membase + UCR2);
1212         temp |= UCR2_ATEN;
1213         writel(temp, sport->port.membase + UCR2);
1214
1215         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1216
1217         sport->dma_is_enabled = 1;
1218 }
1219
1220 static void imx_disable_dma(struct imx_port *sport)
1221 {
1222         unsigned long temp;
1223
1224         /* clear UCR1 */
1225         temp = readl(sport->port.membase + UCR1);
1226         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1227         writel(temp, sport->port.membase + UCR1);
1228
1229         /* clear UCR2 */
1230         temp = readl(sport->port.membase + UCR2);
1231         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1232         writel(temp, sport->port.membase + UCR2);
1233
1234         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1235
1236         sport->dma_is_enabled = 0;
1237 }
1238
1239 /* half the RX buffer size */
1240 #define CTSTL 16
1241
1242 static int imx_startup(struct uart_port *port)
1243 {
1244         struct imx_port *sport = (struct imx_port *)port;
1245         int retval, i;
1246         unsigned long flags, temp;
1247
1248         retval = clk_prepare_enable(sport->clk_per);
1249         if (retval)
1250                 return retval;
1251         retval = clk_prepare_enable(sport->clk_ipg);
1252         if (retval) {
1253                 clk_disable_unprepare(sport->clk_per);
1254                 return retval;
1255         }
1256
1257         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1258
1259         /* disable the DREN bit (Data Ready interrupt enable) before
1260          * requesting IRQs
1261          */
1262         temp = readl(sport->port.membase + UCR4);
1263
1264         /* set the trigger level for CTS */
1265         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1266         temp |= CTSTL << UCR4_CTSTL_SHF;
1267
1268         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1269
1270         /* Can we enable the DMA support? */
1271         if (!uart_console(port) && !sport->dma_is_inited)
1272                 imx_uart_dma_init(sport);
1273
1274         spin_lock_irqsave(&sport->port.lock, flags);
1275         /* Reset fifo's and state machines */
1276         i = 100;
1277
1278         temp = readl(sport->port.membase + UCR2);
1279         temp &= ~UCR2_SRST;
1280         writel(temp, sport->port.membase + UCR2);
1281
1282         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1283                 udelay(1);
1284
1285         /*
1286          * Finally, clear and enable interrupts
1287          */
1288         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1289         writel(USR2_ORE, sport->port.membase + USR2);
1290
1291         if (sport->dma_is_inited && !sport->dma_is_enabled)
1292                 imx_enable_dma(sport);
1293
1294         temp = readl(sport->port.membase + UCR1);
1295         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1296
1297         writel(temp, sport->port.membase + UCR1);
1298
1299         temp = readl(sport->port.membase + UCR4);
1300         temp |= UCR4_OREN;
1301         writel(temp, sport->port.membase + UCR4);
1302
1303         temp = readl(sport->port.membase + UCR2);
1304         temp |= (UCR2_RXEN | UCR2_TXEN);
1305         if (!sport->have_rtscts)
1306                 temp |= UCR2_IRTS;
1307         /*
1308          * make sure the edge sensitive RTS-irq is disabled,
1309          * we're using RTSD instead.
1310          */
1311         if (!is_imx1_uart(sport))
1312                 temp &= ~UCR2_RTSEN;
1313         writel(temp, sport->port.membase + UCR2);
1314
1315         if (!is_imx1_uart(sport)) {
1316                 temp = readl(sport->port.membase + UCR3);
1317
1318                 /*
1319                  * The effect of RI and DCD differs depending on the UFCR_DCEDTE
1320                  * bit. In DCE mode they control the outputs, in DTE mode they
1321                  * enable the respective irqs. At least the DCD irq cannot be
1322                  * cleared on i.MX25 at least, so it's not usable and must be
1323                  * disabled. I don't have test hardware to check if RI has the
1324                  * same problem but I consider this likely so it's disabled for
1325                  * now, too.
1326                  */
1327                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
1328                         UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1329
1330                 if (sport->dte_mode)
1331                         temp &= ~(UCR3_RI | UCR3_DCD);
1332
1333                 writel(temp, sport->port.membase + UCR3);
1334         }
1335
1336         /*
1337          * Enable modem status interrupts
1338          */
1339         imx_enable_ms(&sport->port);
1340         spin_unlock_irqrestore(&sport->port.lock, flags);
1341
1342         return 0;
1343 }
1344
1345 static void imx_shutdown(struct uart_port *port)
1346 {
1347         struct imx_port *sport = (struct imx_port *)port;
1348         unsigned long temp;
1349         unsigned long flags;
1350
1351         if (sport->dma_is_enabled) {
1352                 sport->dma_is_rxing = 0;
1353                 sport->dma_is_txing = 0;
1354                 dmaengine_terminate_all(sport->dma_chan_tx);
1355                 dmaengine_terminate_all(sport->dma_chan_rx);
1356
1357                 spin_lock_irqsave(&sport->port.lock, flags);
1358                 imx_stop_tx(port);
1359                 imx_stop_rx(port);
1360                 imx_disable_dma(sport);
1361                 spin_unlock_irqrestore(&sport->port.lock, flags);
1362                 imx_uart_dma_exit(sport);
1363         }
1364
1365         mctrl_gpio_disable_ms(sport->gpios);
1366
1367         spin_lock_irqsave(&sport->port.lock, flags);
1368         temp = readl(sport->port.membase + UCR2);
1369         temp &= ~(UCR2_TXEN);
1370         writel(temp, sport->port.membase + UCR2);
1371         spin_unlock_irqrestore(&sport->port.lock, flags);
1372
1373         /*
1374          * Stop our timer.
1375          */
1376         del_timer_sync(&sport->timer);
1377
1378         /*
1379          * Disable all interrupts, port and break condition.
1380          */
1381
1382         spin_lock_irqsave(&sport->port.lock, flags);
1383         temp = readl(sport->port.membase + UCR1);
1384         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1385
1386         writel(temp, sport->port.membase + UCR1);
1387         spin_unlock_irqrestore(&sport->port.lock, flags);
1388
1389         clk_disable_unprepare(sport->clk_per);
1390         clk_disable_unprepare(sport->clk_ipg);
1391 }
1392
1393 static void imx_flush_buffer(struct uart_port *port)
1394 {
1395         struct imx_port *sport = (struct imx_port *)port;
1396         struct scatterlist *sgl = &sport->tx_sgl[0];
1397         unsigned long temp;
1398         int i = 100, ubir, ubmr, uts;
1399
1400         if (!sport->dma_chan_tx)
1401                 return;
1402
1403         sport->tx_bytes = 0;
1404         dmaengine_terminate_all(sport->dma_chan_tx);
1405         if (sport->dma_is_txing) {
1406                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1407                              DMA_TO_DEVICE);
1408                 temp = readl(sport->port.membase + UCR1);
1409                 temp &= ~UCR1_TDMAEN;
1410                 writel(temp, sport->port.membase + UCR1);
1411                 sport->dma_is_txing = false;
1412         }
1413
1414         /*
1415          * According to the Reference Manual description of the UART SRST bit:
1416          * "Reset the transmit and receive state machines,
1417          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1418          * and UTS[6-3]". As we don't need to restore the old values from
1419          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1420          */
1421         ubir = readl(sport->port.membase + UBIR);
1422         ubmr = readl(sport->port.membase + UBMR);
1423         uts = readl(sport->port.membase + IMX21_UTS);
1424
1425         temp = readl(sport->port.membase + UCR2);
1426         temp &= ~UCR2_SRST;
1427         writel(temp, sport->port.membase + UCR2);
1428
1429         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1430                 udelay(1);
1431
1432         /* Restore the registers */
1433         writel(ubir, sport->port.membase + UBIR);
1434         writel(ubmr, sport->port.membase + UBMR);
1435         writel(uts, sport->port.membase + IMX21_UTS);
1436 }
1437
1438 static void
1439 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1440                    struct ktermios *old)
1441 {
1442         struct imx_port *sport = (struct imx_port *)port;
1443         unsigned long flags;
1444         unsigned long ucr2, old_ucr1, old_ucr2;
1445         unsigned int baud, quot;
1446         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1447         unsigned long div, ufcr;
1448         unsigned long num, denom;
1449         uint64_t tdiv64;
1450
1451         /*
1452          * We only support CS7 and CS8.
1453          */
1454         while ((termios->c_cflag & CSIZE) != CS7 &&
1455                (termios->c_cflag & CSIZE) != CS8) {
1456                 termios->c_cflag &= ~CSIZE;
1457                 termios->c_cflag |= old_csize;
1458                 old_csize = CS8;
1459         }
1460
1461         if ((termios->c_cflag & CSIZE) == CS8)
1462                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1463         else
1464                 ucr2 = UCR2_SRST | UCR2_IRTS;
1465
1466         if (termios->c_cflag & CRTSCTS) {
1467                 if (sport->have_rtscts) {
1468                         ucr2 &= ~UCR2_IRTS;
1469
1470                         if (port->rs485.flags & SER_RS485_ENABLED) {
1471                                 /*
1472                                  * RTS is mandatory for rs485 operation, so keep
1473                                  * it under manual control and keep transmitter
1474                                  * disabled.
1475                                  */
1476                                 if (port->rs485.flags &
1477                                     SER_RS485_RTS_AFTER_SEND)
1478                                         imx_port_rts_inactive(sport, &ucr2);
1479                                 else
1480                                         imx_port_rts_active(sport, &ucr2);
1481                         } else {
1482                                 imx_port_rts_auto(sport, &ucr2);
1483                         }
1484                 } else {
1485                         termios->c_cflag &= ~CRTSCTS;
1486                 }
1487         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1488                 /* disable transmitter */
1489                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1490                         imx_port_rts_inactive(sport, &ucr2);
1491                 else
1492                         imx_port_rts_active(sport, &ucr2);
1493         }
1494
1495
1496         if (termios->c_cflag & CSTOPB)
1497                 ucr2 |= UCR2_STPB;
1498         if (termios->c_cflag & PARENB) {
1499                 ucr2 |= UCR2_PREN;
1500                 if (termios->c_cflag & PARODD)
1501                         ucr2 |= UCR2_PROE;
1502         }
1503
1504         del_timer_sync(&sport->timer);
1505
1506         /*
1507          * Ask the core to calculate the divisor for us.
1508          */
1509         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1510         quot = uart_get_divisor(port, baud);
1511
1512         spin_lock_irqsave(&sport->port.lock, flags);
1513
1514         sport->port.read_status_mask = 0;
1515         if (termios->c_iflag & INPCK)
1516                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1517         if (termios->c_iflag & (BRKINT | PARMRK))
1518                 sport->port.read_status_mask |= URXD_BRK;
1519
1520         /*
1521          * Characters to ignore
1522          */
1523         sport->port.ignore_status_mask = 0;
1524         if (termios->c_iflag & IGNPAR)
1525                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1526         if (termios->c_iflag & IGNBRK) {
1527                 sport->port.ignore_status_mask |= URXD_BRK;
1528                 /*
1529                  * If we're ignoring parity and break indicators,
1530                  * ignore overruns too (for real raw support).
1531                  */
1532                 if (termios->c_iflag & IGNPAR)
1533                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1534         }
1535
1536         if ((termios->c_cflag & CREAD) == 0)
1537                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1538
1539         /*
1540          * Update the per-port timeout.
1541          */
1542         uart_update_timeout(port, termios->c_cflag, baud);
1543
1544         /*
1545          * disable interrupts and drain transmitter
1546          */
1547         old_ucr1 = readl(sport->port.membase + UCR1);
1548         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1549                         sport->port.membase + UCR1);
1550
1551         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1552                 barrier();
1553
1554         /* then, disable everything */
1555         old_ucr2 = readl(sport->port.membase + UCR2);
1556         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1557                         sport->port.membase + UCR2);
1558         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1559
1560         /* custom-baudrate handling */
1561         div = sport->port.uartclk / (baud * 16);
1562         if (baud == 38400 && quot != div)
1563                 baud = sport->port.uartclk / (quot * 16);
1564
1565         div = sport->port.uartclk / (baud * 16);
1566         if (div > 7)
1567                 div = 7;
1568         if (!div)
1569                 div = 1;
1570
1571         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1572                 1 << 16, 1 << 16, &num, &denom);
1573
1574         tdiv64 = sport->port.uartclk;
1575         tdiv64 *= num;
1576         do_div(tdiv64, denom * 16 * div);
1577         tty_termios_encode_baud_rate(termios,
1578                                 (speed_t)tdiv64, (speed_t)tdiv64);
1579
1580         num -= 1;
1581         denom -= 1;
1582
1583         ufcr = readl(sport->port.membase + UFCR);
1584         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1585         if (sport->dte_mode)
1586                 ufcr |= UFCR_DCEDTE;
1587         writel(ufcr, sport->port.membase + UFCR);
1588
1589         writel(num, sport->port.membase + UBIR);
1590         writel(denom, sport->port.membase + UBMR);
1591
1592         if (!is_imx1_uart(sport))
1593                 writel(sport->port.uartclk / div / 1000,
1594                                 sport->port.membase + IMX21_ONEMS);
1595
1596         writel(old_ucr1, sport->port.membase + UCR1);
1597
1598         /* set the parity, stop bits and data size */
1599         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1600
1601         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1602                 imx_enable_ms(&sport->port);
1603
1604         spin_unlock_irqrestore(&sport->port.lock, flags);
1605 }
1606
1607 static const char *imx_type(struct uart_port *port)
1608 {
1609         struct imx_port *sport = (struct imx_port *)port;
1610
1611         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1612 }
1613
1614 /*
1615  * Configure/autoconfigure the port.
1616  */
1617 static void imx_config_port(struct uart_port *port, int flags)
1618 {
1619         struct imx_port *sport = (struct imx_port *)port;
1620
1621         if (flags & UART_CONFIG_TYPE)
1622                 sport->port.type = PORT_IMX;
1623 }
1624
1625 /*
1626  * Verify the new serial_struct (for TIOCSSERIAL).
1627  * The only change we allow are to the flags and type, and
1628  * even then only between PORT_IMX and PORT_UNKNOWN
1629  */
1630 static int
1631 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1632 {
1633         struct imx_port *sport = (struct imx_port *)port;
1634         int ret = 0;
1635
1636         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1637                 ret = -EINVAL;
1638         if (sport->port.irq != ser->irq)
1639                 ret = -EINVAL;
1640         if (ser->io_type != UPIO_MEM)
1641                 ret = -EINVAL;
1642         if (sport->port.uartclk / 16 != ser->baud_base)
1643                 ret = -EINVAL;
1644         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1645                 ret = -EINVAL;
1646         if (sport->port.iobase != ser->port)
1647                 ret = -EINVAL;
1648         if (ser->hub6 != 0)
1649                 ret = -EINVAL;
1650         return ret;
1651 }
1652
1653 #if defined(CONFIG_CONSOLE_POLL)
1654
1655 static int imx_poll_init(struct uart_port *port)
1656 {
1657         struct imx_port *sport = (struct imx_port *)port;
1658         unsigned long flags;
1659         unsigned long temp;
1660         int retval;
1661
1662         retval = clk_prepare_enable(sport->clk_ipg);
1663         if (retval)
1664                 return retval;
1665         retval = clk_prepare_enable(sport->clk_per);
1666         if (retval)
1667                 clk_disable_unprepare(sport->clk_ipg);
1668
1669         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1670
1671         spin_lock_irqsave(&sport->port.lock, flags);
1672
1673         temp = readl(sport->port.membase + UCR1);
1674         if (is_imx1_uart(sport))
1675                 temp |= IMX1_UCR1_UARTCLKEN;
1676         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1677         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1678         writel(temp, sport->port.membase + UCR1);
1679
1680         temp = readl(sport->port.membase + UCR2);
1681         temp |= UCR2_RXEN;
1682         writel(temp, sport->port.membase + UCR2);
1683
1684         spin_unlock_irqrestore(&sport->port.lock, flags);
1685
1686         return 0;
1687 }
1688
1689 static int imx_poll_get_char(struct uart_port *port)
1690 {
1691         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1692                 return NO_POLL_CHAR;
1693
1694         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1695 }
1696
1697 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1698 {
1699         unsigned int status;
1700
1701         /* drain */
1702         do {
1703                 status = readl_relaxed(port->membase + USR1);
1704         } while (~status & USR1_TRDY);
1705
1706         /* write */
1707         writel_relaxed(c, port->membase + URTX0);
1708
1709         /* flush */
1710         do {
1711                 status = readl_relaxed(port->membase + USR2);
1712         } while (~status & USR2_TXDC);
1713 }
1714 #endif
1715
1716 static int imx_rs485_config(struct uart_port *port,
1717                             struct serial_rs485 *rs485conf)
1718 {
1719         struct imx_port *sport = (struct imx_port *)port;
1720         unsigned long temp;
1721
1722         /* unimplemented */
1723         rs485conf->delay_rts_before_send = 0;
1724         rs485conf->delay_rts_after_send = 0;
1725
1726         /* RTS is required to control the transmitter */
1727         if (!sport->have_rtscts)
1728                 rs485conf->flags &= ~SER_RS485_ENABLED;
1729
1730         if (rs485conf->flags & SER_RS485_ENABLED) {
1731                 /* disable transmitter */
1732                 temp = readl(sport->port.membase + UCR2);
1733                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1734                         imx_port_rts_inactive(sport, &temp);
1735                 else
1736                         imx_port_rts_active(sport, &temp);
1737                 writel(temp, sport->port.membase + UCR2);
1738         }
1739
1740         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1741         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1742             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1743                 temp = readl(sport->port.membase + UCR2);
1744                 temp |= UCR2_RXEN;
1745                 writel(temp, sport->port.membase + UCR2);
1746         }
1747
1748         port->rs485 = *rs485conf;
1749
1750         return 0;
1751 }
1752
1753 static const struct uart_ops imx_pops = {
1754         .tx_empty       = imx_tx_empty,
1755         .set_mctrl      = imx_set_mctrl,
1756         .get_mctrl      = imx_get_mctrl,
1757         .stop_tx        = imx_stop_tx,
1758         .start_tx       = imx_start_tx,
1759         .stop_rx        = imx_stop_rx,
1760         .enable_ms      = imx_enable_ms,
1761         .break_ctl      = imx_break_ctl,
1762         .startup        = imx_startup,
1763         .shutdown       = imx_shutdown,
1764         .flush_buffer   = imx_flush_buffer,
1765         .set_termios    = imx_set_termios,
1766         .type           = imx_type,
1767         .config_port    = imx_config_port,
1768         .verify_port    = imx_verify_port,
1769 #if defined(CONFIG_CONSOLE_POLL)
1770         .poll_init      = imx_poll_init,
1771         .poll_get_char  = imx_poll_get_char,
1772         .poll_put_char  = imx_poll_put_char,
1773 #endif
1774 };
1775
1776 static struct imx_port *imx_ports[UART_NR];
1777
1778 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1779 static void imx_console_putchar(struct uart_port *port, int ch)
1780 {
1781         struct imx_port *sport = (struct imx_port *)port;
1782
1783         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1784                 barrier();
1785
1786         writel(ch, sport->port.membase + URTX0);
1787 }
1788
1789 /*
1790  * Interrupts are disabled on entering
1791  */
1792 static void
1793 imx_console_write(struct console *co, const char *s, unsigned int count)
1794 {
1795         struct imx_port *sport = imx_ports[co->index];
1796         struct imx_port_ucrs old_ucr;
1797         unsigned int ucr1;
1798         unsigned long flags = 0;
1799         int locked = 1;
1800         int retval;
1801
1802         retval = clk_enable(sport->clk_per);
1803         if (retval)
1804                 return;
1805         retval = clk_enable(sport->clk_ipg);
1806         if (retval) {
1807                 clk_disable(sport->clk_per);
1808                 return;
1809         }
1810
1811         if (sport->port.sysrq)
1812                 locked = 0;
1813         else if (oops_in_progress)
1814                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1815         else
1816                 spin_lock_irqsave(&sport->port.lock, flags);
1817
1818         /*
1819          *      First, save UCR1/2/3 and then disable interrupts
1820          */
1821         imx_port_ucrs_save(&sport->port, &old_ucr);
1822         ucr1 = old_ucr.ucr1;
1823
1824         if (is_imx1_uart(sport))
1825                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1826         ucr1 |= UCR1_UARTEN;
1827         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1828
1829         writel(ucr1, sport->port.membase + UCR1);
1830
1831         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1832
1833         uart_console_write(&sport->port, s, count, imx_console_putchar);
1834
1835         /*
1836          *      Finally, wait for transmitter to become empty
1837          *      and restore UCR1/2/3
1838          */
1839         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1840
1841         imx_port_ucrs_restore(&sport->port, &old_ucr);
1842
1843         if (locked)
1844                 spin_unlock_irqrestore(&sport->port.lock, flags);
1845
1846         clk_disable(sport->clk_ipg);
1847         clk_disable(sport->clk_per);
1848 }
1849
1850 /*
1851  * If the port was already initialised (eg, by a boot loader),
1852  * try to determine the current setup.
1853  */
1854 static void __init
1855 imx_console_get_options(struct imx_port *sport, int *baud,
1856                            int *parity, int *bits)
1857 {
1858
1859         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1860                 /* ok, the port was enabled */
1861                 unsigned int ucr2, ubir, ubmr, uartclk;
1862                 unsigned int baud_raw;
1863                 unsigned int ucfr_rfdiv;
1864
1865                 ucr2 = readl(sport->port.membase + UCR2);
1866
1867                 *parity = 'n';
1868                 if (ucr2 & UCR2_PREN) {
1869                         if (ucr2 & UCR2_PROE)
1870                                 *parity = 'o';
1871                         else
1872                                 *parity = 'e';
1873                 }
1874
1875                 if (ucr2 & UCR2_WS)
1876                         *bits = 8;
1877                 else
1878                         *bits = 7;
1879
1880                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1881                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1882
1883                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1884                 if (ucfr_rfdiv == 6)
1885                         ucfr_rfdiv = 7;
1886                 else
1887                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1888
1889                 uartclk = clk_get_rate(sport->clk_per);
1890                 uartclk /= ucfr_rfdiv;
1891
1892                 {       /*
1893                          * The next code provides exact computation of
1894                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1895                          * without need of float support or long long division,
1896                          * which would be required to prevent 32bit arithmetic overflow
1897                          */
1898                         unsigned int mul = ubir + 1;
1899                         unsigned int div = 16 * (ubmr + 1);
1900                         unsigned int rem = uartclk % div;
1901
1902                         baud_raw = (uartclk / div) * mul;
1903                         baud_raw += (rem * mul + div / 2) / div;
1904                         *baud = (baud_raw + 50) / 100 * 100;
1905                 }
1906
1907                 if (*baud != baud_raw)
1908                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1909                                 baud_raw, *baud);
1910         }
1911 }
1912
1913 static int __init
1914 imx_console_setup(struct console *co, char *options)
1915 {
1916         struct imx_port *sport;
1917         int baud = 9600;
1918         int bits = 8;
1919         int parity = 'n';
1920         int flow = 'n';
1921         int retval;
1922
1923         /*
1924          * Check whether an invalid uart number has been specified, and
1925          * if so, search for the first available port that does have
1926          * console support.
1927          */
1928         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1929                 co->index = 0;
1930         sport = imx_ports[co->index];
1931         if (sport == NULL)
1932                 return -ENODEV;
1933
1934         /* For setting the registers, we only need to enable the ipg clock. */
1935         retval = clk_prepare_enable(sport->clk_ipg);
1936         if (retval)
1937                 goto error_console;
1938
1939         if (options)
1940                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1941         else
1942                 imx_console_get_options(sport, &baud, &parity, &bits);
1943
1944         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1945
1946         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1947
1948         clk_disable(sport->clk_ipg);
1949         if (retval) {
1950                 clk_unprepare(sport->clk_ipg);
1951                 goto error_console;
1952         }
1953
1954         retval = clk_prepare(sport->clk_per);
1955         if (retval)
1956                 clk_disable_unprepare(sport->clk_ipg);
1957
1958 error_console:
1959         return retval;
1960 }
1961
1962 static struct uart_driver imx_reg;
1963 static struct console imx_console = {
1964         .name           = DEV_NAME,
1965         .write          = imx_console_write,
1966         .device         = uart_console_device,
1967         .setup          = imx_console_setup,
1968         .flags          = CON_PRINTBUFFER,
1969         .index          = -1,
1970         .data           = &imx_reg,
1971 };
1972
1973 #define IMX_CONSOLE     &imx_console
1974
1975 #ifdef CONFIG_OF
1976 static void imx_console_early_putchar(struct uart_port *port, int ch)
1977 {
1978         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1979                 cpu_relax();
1980
1981         writel_relaxed(ch, port->membase + URTX0);
1982 }
1983
1984 static void imx_console_early_write(struct console *con, const char *s,
1985                                     unsigned count)
1986 {
1987         struct earlycon_device *dev = con->data;
1988
1989         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1990 }
1991
1992 static int __init
1993 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1994 {
1995         if (!dev->port.membase)
1996                 return -ENODEV;
1997
1998         dev->con->write = imx_console_early_write;
1999
2000         return 0;
2001 }
2002 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2003 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2004 #endif
2005
2006 #else
2007 #define IMX_CONSOLE     NULL
2008 #endif
2009
2010 static struct uart_driver imx_reg = {
2011         .owner          = THIS_MODULE,
2012         .driver_name    = DRIVER_NAME,
2013         .dev_name       = DEV_NAME,
2014         .major          = SERIAL_IMX_MAJOR,
2015         .minor          = MINOR_START,
2016         .nr             = ARRAY_SIZE(imx_ports),
2017         .cons           = IMX_CONSOLE,
2018 };
2019
2020 #ifdef CONFIG_OF
2021 /*
2022  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2023  * could successfully get all information from dt or a negative errno.
2024  */
2025 static int serial_imx_probe_dt(struct imx_port *sport,
2026                 struct platform_device *pdev)
2027 {
2028         struct device_node *np = pdev->dev.of_node;
2029         int ret;
2030
2031         sport->devdata = of_device_get_match_data(&pdev->dev);
2032         if (!sport->devdata)
2033                 /* no device tree device */
2034                 return 1;
2035
2036         ret = of_alias_get_id(np, "serial");
2037         if (ret < 0) {
2038                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2039                 return ret;
2040         }
2041         sport->port.line = ret;
2042
2043         if (of_get_property(np, "uart-has-rtscts", NULL) ||
2044             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2045                 sport->have_rtscts = 1;
2046
2047         if (of_get_property(np, "fsl,dte-mode", NULL))
2048                 sport->dte_mode = 1;
2049
2050         return 0;
2051 }
2052 #else
2053 static inline int serial_imx_probe_dt(struct imx_port *sport,
2054                 struct platform_device *pdev)
2055 {
2056         return 1;
2057 }
2058 #endif
2059
2060 static void serial_imx_probe_pdata(struct imx_port *sport,
2061                 struct platform_device *pdev)
2062 {
2063         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2064
2065         sport->port.line = pdev->id;
2066         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2067
2068         if (!pdata)
2069                 return;
2070
2071         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2072                 sport->have_rtscts = 1;
2073 }
2074
2075 static int serial_imx_probe(struct platform_device *pdev)
2076 {
2077         struct imx_port *sport;
2078         void __iomem *base;
2079         int ret = 0, reg;
2080         struct resource *res;
2081         int txirq, rxirq, rtsirq;
2082
2083         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2084         if (!sport)
2085                 return -ENOMEM;
2086
2087         ret = serial_imx_probe_dt(sport, pdev);
2088         if (ret > 0)
2089                 serial_imx_probe_pdata(sport, pdev);
2090         else if (ret < 0)
2091                 return ret;
2092
2093         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2094         base = devm_ioremap_resource(&pdev->dev, res);
2095         if (IS_ERR(base))
2096                 return PTR_ERR(base);
2097
2098         rxirq = platform_get_irq(pdev, 0);
2099         txirq = platform_get_irq(pdev, 1);
2100         rtsirq = platform_get_irq(pdev, 2);
2101
2102         sport->port.dev = &pdev->dev;
2103         sport->port.mapbase = res->start;
2104         sport->port.membase = base;
2105         sport->port.type = PORT_IMX,
2106         sport->port.iotype = UPIO_MEM;
2107         sport->port.irq = rxirq;
2108         sport->port.fifosize = 32;
2109         sport->port.ops = &imx_pops;
2110         sport->port.rs485_config = imx_rs485_config;
2111         sport->port.rs485.flags =
2112                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2113         sport->port.flags = UPF_BOOT_AUTOCONF;
2114         init_timer(&sport->timer);
2115         sport->timer.function = imx_timeout;
2116         sport->timer.data     = (unsigned long)sport;
2117
2118         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2119         if (IS_ERR(sport->gpios))
2120                 return PTR_ERR(sport->gpios);
2121
2122         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2123         if (IS_ERR(sport->clk_ipg)) {
2124                 ret = PTR_ERR(sport->clk_ipg);
2125                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2126                 return ret;
2127         }
2128
2129         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2130         if (IS_ERR(sport->clk_per)) {
2131                 ret = PTR_ERR(sport->clk_per);
2132                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2133                 return ret;
2134         }
2135
2136         sport->port.uartclk = clk_get_rate(sport->clk_per);
2137
2138         /* For register access, we only need to enable the ipg clock. */
2139         ret = clk_prepare_enable(sport->clk_ipg);
2140         if (ret)
2141                 return ret;
2142
2143         /* Disable interrupts before requesting them */
2144         reg = readl_relaxed(sport->port.membase + UCR1);
2145         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2146                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2147         writel_relaxed(reg, sport->port.membase + UCR1);
2148
2149         clk_disable_unprepare(sport->clk_ipg);
2150
2151         /*
2152          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2153          * chips only have one interrupt.
2154          */
2155         if (txirq > 0) {
2156                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2157                                        dev_name(&pdev->dev), sport);
2158                 if (ret)
2159                         return ret;
2160
2161                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2162                                        dev_name(&pdev->dev), sport);
2163                 if (ret)
2164                         return ret;
2165         } else {
2166                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2167                                        dev_name(&pdev->dev), sport);
2168                 if (ret)
2169                         return ret;
2170         }
2171
2172         imx_ports[sport->port.line] = sport;
2173
2174         platform_set_drvdata(pdev, sport);
2175
2176         return uart_add_one_port(&imx_reg, &sport->port);
2177 }
2178
2179 static int serial_imx_remove(struct platform_device *pdev)
2180 {
2181         struct imx_port *sport = platform_get_drvdata(pdev);
2182
2183         return uart_remove_one_port(&imx_reg, &sport->port);
2184 }
2185
2186 static void serial_imx_restore_context(struct imx_port *sport)
2187 {
2188         if (!sport->context_saved)
2189                 return;
2190
2191         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2192         writel(sport->saved_reg[5], sport->port.membase + UESC);
2193         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2194         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2195         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2196         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2197         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2198         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2199         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2200         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2201         sport->context_saved = false;
2202 }
2203
2204 static void serial_imx_save_context(struct imx_port *sport)
2205 {
2206         /* Save necessary regs */
2207         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2208         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2209         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2210         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2211         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2212         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2213         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2214         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2215         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2216         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2217         sport->context_saved = true;
2218 }
2219
2220 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2221 {
2222         unsigned int val;
2223
2224         val = readl(sport->port.membase + UCR3);
2225         if (on)
2226                 val |= UCR3_AWAKEN;
2227         else
2228                 val &= ~UCR3_AWAKEN;
2229         writel(val, sport->port.membase + UCR3);
2230
2231         val = readl(sport->port.membase + UCR1);
2232         if (on)
2233                 val |= UCR1_RTSDEN;
2234         else
2235                 val &= ~UCR1_RTSDEN;
2236         writel(val, sport->port.membase + UCR1);
2237 }
2238
2239 static int imx_serial_port_suspend_noirq(struct device *dev)
2240 {
2241         struct platform_device *pdev = to_platform_device(dev);
2242         struct imx_port *sport = platform_get_drvdata(pdev);
2243         int ret;
2244
2245         ret = clk_enable(sport->clk_ipg);
2246         if (ret)
2247                 return ret;
2248
2249         serial_imx_save_context(sport);
2250
2251         clk_disable(sport->clk_ipg);
2252
2253         return 0;
2254 }
2255
2256 static int imx_serial_port_resume_noirq(struct device *dev)
2257 {
2258         struct platform_device *pdev = to_platform_device(dev);
2259         struct imx_port *sport = platform_get_drvdata(pdev);
2260         int ret;
2261
2262         ret = clk_enable(sport->clk_ipg);
2263         if (ret)
2264                 return ret;
2265
2266         serial_imx_restore_context(sport);
2267
2268         clk_disable(sport->clk_ipg);
2269
2270         return 0;
2271 }
2272
2273 static int imx_serial_port_suspend(struct device *dev)
2274 {
2275         struct platform_device *pdev = to_platform_device(dev);
2276         struct imx_port *sport = platform_get_drvdata(pdev);
2277
2278         /* enable wakeup from i.MX UART */
2279         serial_imx_enable_wakeup(sport, true);
2280
2281         uart_suspend_port(&imx_reg, &sport->port);
2282
2283         /* Needed to enable clock in suspend_noirq */
2284         return clk_prepare(sport->clk_ipg);
2285 }
2286
2287 static int imx_serial_port_resume(struct device *dev)
2288 {
2289         struct platform_device *pdev = to_platform_device(dev);
2290         struct imx_port *sport = platform_get_drvdata(pdev);
2291
2292         /* disable wakeup from i.MX UART */
2293         serial_imx_enable_wakeup(sport, false);
2294
2295         uart_resume_port(&imx_reg, &sport->port);
2296
2297         clk_unprepare(sport->clk_ipg);
2298
2299         return 0;
2300 }
2301
2302 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2303         .suspend_noirq = imx_serial_port_suspend_noirq,
2304         .resume_noirq = imx_serial_port_resume_noirq,
2305         .suspend = imx_serial_port_suspend,
2306         .resume = imx_serial_port_resume,
2307 };
2308
2309 static struct platform_driver serial_imx_driver = {
2310         .probe          = serial_imx_probe,
2311         .remove         = serial_imx_remove,
2312
2313         .id_table       = imx_uart_devtype,
2314         .driver         = {
2315                 .name   = "imx-uart",
2316                 .of_match_table = imx_uart_dt_ids,
2317                 .pm     = &imx_serial_port_pm_ops,
2318         },
2319 };
2320
2321 static int __init imx_serial_init(void)
2322 {
2323         int ret = uart_register_driver(&imx_reg);
2324
2325         if (ret)
2326                 return ret;
2327
2328         ret = platform_driver_register(&serial_imx_driver);
2329         if (ret != 0)
2330                 uart_unregister_driver(&imx_reg);
2331
2332         return ret;
2333 }
2334
2335 static void __exit imx_serial_exit(void)
2336 {
2337         platform_driver_unregister(&serial_imx_driver);
2338         uart_unregister_driver(&imx_reg);
2339 }
2340
2341 module_init(imx_serial_init);
2342 module_exit(imx_serial_exit);
2343
2344 MODULE_AUTHOR("Sascha Hauer");
2345 MODULE_DESCRIPTION("IMX generic serial port driver");
2346 MODULE_LICENSE("GPL");
2347 MODULE_ALIAS("platform:imx-uart");