drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 #include "serial_mctrl_gpio.h"
  48
  49 /* Register definitions */
  50 #define URXD0 0x0  /* Receiver Register */
  51 #define URTX0 0x40 /* Transmitter Register */
  52 #define UCR1  0x80 /* Control Register 1 */
  53 #define UCR2  0x84 /* Control Register 2 */
  54 #define UCR3  0x88 /* Control Register 3 */
  55 #define UCR4  0x8c /* Control Register 4 */
  56 #define UFCR  0x90 /* FIFO Control Register */
  57 #define USR1  0x94 /* Status Register 1 */
  58 #define USR2  0x98 /* Status Register 2 */
  59 #define UESC  0x9c /* Escape Character Register */
  60 #define UTIM  0xa0 /* Escape Timer Register */
  61 #define UBIR  0xa4 /* BRM Incremental Register */
  62 #define UBMR  0xa8 /* BRM Modulator Register */
  63 #define UBRC  0xac /* Baud Rate Count Register */
  64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  67
  68 /* UART Control Register Bit Fields.*/
  69 #define URXD_DUMMY_READ (1<<16)
  70 #define URXD_CHARRDY    (1<<15)
  71 #define URXD_ERR        (1<<14)
  72 #define URXD_OVRRUN     (1<<13)
  73 #define URXD_FRMERR     (1<<12)
  74 #define URXD_BRK        (1<<11)
  75 #define URXD_PRERR      (1<<10)
  76 #define URXD_RX_DATA    (0xFF<<0)
  77 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  78 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  79 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  80 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  82 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  83 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  84 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  85 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  86 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  87 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  88 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  90 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  91 #define UCR1_DOZE       (1<<1)  /* Doze */
  92 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  93 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  94 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  95 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  96 #define UCR2_CTS        (1<<12) /* Clear to send */
  97 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  98 #define UCR2_PREN       (1<<8)  /* Parity enable */
  99 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
 100 #define UCR2_STPB       (1<<6)  /* Stop */
 101 #define UCR2_WS         (1<<5)  /* Word size */
 102 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 103 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 104 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 105 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 106 #define UCR2_SRST       (1<<0)  /* SW reset */
 107 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 108 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 109 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 110 #define UCR3_DSR        (1<<10) /* Data set ready */
 111 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 112 #define UCR3_RI         (1<<8)  /* Ring indicator */
 113 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 114 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 115 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 116 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 117 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 118 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 119 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 120 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 121 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 122 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 123 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 124 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 125 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 126 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 127 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 128 #define UCR4_IRSC       (1<<5)  /* IR special case */
 129 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 130 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 131 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 132 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 133 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 134 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 135 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 136 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 137 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 138 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 139 #define USR1_RTSS       (1<<14) /* RTS pin status */
 140 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 141 #define USR1_RTSD       (1<<12) /* RTS delta */
 142 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 143 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 144 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 145 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 146 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 147 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 148 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 149 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 150 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 151 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 152 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 153 #define USR2_IDLE        (1<<12) /* Idle condition */
 154 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 155 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 156 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 157 #define USR2_WAKE        (1<<7)  /* Wake */
 158 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 159 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 160 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 161 #define USR2_BRCD        (1<<2)  /* Break condition */
 162 #define USR2_ORE        (1<<1)   /* Overrun error */
 163 #define USR2_RDR        (1<<0)   /* Recv data ready */
 164 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 165 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 166 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 167 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 168 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 169 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 170 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 171
 172 /* We've been assigned a range on the "Low-density serial ports" major */
 173 #define SERIAL_IMX_MAJOR        207
 174 #define MINOR_START             16
 175 #define DEV_NAME                "ttymxc"
 176
 177 /*
 178  * This determines how often we check the modem status signals
 179  * for any change.  They generally aren't connected to an IRQ
 180  * so we have to poll them.  We also check immediately before
 181  * filling the TX fifo incase CTS has been dropped.
 182  */
 183 #define MCTRL_TIMEOUT   (250*HZ/1000)
 184
 185 #define DRIVER_NAME "IMX-uart"
 186
 187 #define UART_NR 8
 188
 189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 190 enum imx_uart_type {
 191         IMX1_UART,
 192         IMX21_UART,
 193         IMX53_UART,
 194         IMX6Q_UART,
 195 };
 196
 197 /* device type dependent stuff */
 198 struct imx_uart_data {
 199         unsigned uts_reg;
 200         enum imx_uart_type devtype;
 201 };
 202
 203 struct imx_port {
 204         struct uart_port        port;
 205         struct timer_list       timer;
 206         unsigned int            old_status;
 207         unsigned int            have_rtscts:1;
 208         unsigned int            have_rtsgpio:1;
 209         unsigned int            dte_mode:1;
 210         unsigned int            irda_inv_rx:1;
 211         unsigned int            irda_inv_tx:1;
 212         unsigned short          trcv_delay; /* transceiver delay */
 213         struct clk              *clk_ipg;
 214         struct clk              *clk_per;
 215         const struct imx_uart_data *devdata;
 216
 217         struct mctrl_gpios *gpios;
 218
 219         /* DMA fields */
 220         unsigned int            dma_is_inited:1;
 221         unsigned int            dma_is_enabled:1;
 222         unsigned int            dma_is_rxing:1;
 223         unsigned int            dma_is_txing:1;
 224         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 225         struct scatterlist      rx_sgl, tx_sgl[2];
 226         void                    *rx_buf;
 227         struct circ_buf         rx_ring;
 228         unsigned int            rx_periods;
 229         dma_cookie_t            rx_cookie;
 230         unsigned int            tx_bytes;
 231         unsigned int            dma_tx_nents;
 232         wait_queue_head_t       dma_wait;
 233         unsigned int            saved_reg[10];
 234         bool                    context_saved;
 235 };
 236
 237 struct imx_port_ucrs {
 238         unsigned int    ucr1;
 239         unsigned int    ucr2;
 240         unsigned int    ucr3;
 241 };
 242
 243 static struct imx_uart_data imx_uart_devdata[] = {
 244         [IMX1_UART] = {
 245                 .uts_reg = IMX1_UTS,
 246                 .devtype = IMX1_UART,
 247         },
 248         [IMX21_UART] = {
 249                 .uts_reg = IMX21_UTS,
 250                 .devtype = IMX21_UART,
 251         },
 252         [IMX53_UART] = {
 253                 .uts_reg = IMX21_UTS,
 254                 .devtype = IMX53_UART,
 255         },
 256         [IMX6Q_UART] = {
 257                 .uts_reg = IMX21_UTS,
 258                 .devtype = IMX6Q_UART,
 259         },
 260 };
 261
 262 static const struct platform_device_id imx_uart_devtype[] = {
 263         {
 264                 .name = "imx1-uart",
 265                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 266         }, {
 267                 .name = "imx21-uart",
 268                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 269         }, {
 270                 .name = "imx53-uart",
 271                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 272         }, {
 273                 .name = "imx6q-uart",
 274                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 275         }, {
 276                 /* sentinel */
 277         }
 278 };
 279 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 280
 281 static const struct of_device_id imx_uart_dt_ids[] = {
 282         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 283         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 284         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 285         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 286         { /* sentinel */ }
 287 };
 288 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 289
 290 static inline unsigned uts_reg(struct imx_port *sport)
 291 {
 292         return sport->devdata->uts_reg;
 293 }
 294
 295 static inline int is_imx1_uart(struct imx_port *sport)
 296 {
 297         return sport->devdata->devtype == IMX1_UART;
 298 }
 299
 300 static inline int is_imx21_uart(struct imx_port *sport)
 301 {
 302         return sport->devdata->devtype == IMX21_UART;
 303 }
 304
 305 static inline int is_imx53_uart(struct imx_port *sport)
 306 {
 307         return sport->devdata->devtype == IMX53_UART;
 308 }
 309
 310 static inline int is_imx6q_uart(struct imx_port *sport)
 311 {
 312         return sport->devdata->devtype == IMX6Q_UART;
 313 }
 314 /*
 315  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 316  */
 317 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 318 static void imx_port_ucrs_save(struct uart_port *port,
 319                                struct imx_port_ucrs *ucr)
 320 {
 321         /* save control registers */
 322         ucr->ucr1 = readl(port->membase + UCR1);
 323         ucr->ucr2 = readl(port->membase + UCR2);
 324         ucr->ucr3 = readl(port->membase + UCR3);
 325 }
 326
 327 static void imx_port_ucrs_restore(struct uart_port *port,
 328                                   struct imx_port_ucrs *ucr)
 329 {
 330         /* restore control registers */
 331         writel(ucr->ucr1, port->membase + UCR1);
 332         writel(ucr->ucr2, port->membase + UCR2);
 333         writel(ucr->ucr3, port->membase + UCR3);
 334 }
 335 #endif
 336
 337 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 338 {
 339         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 340
 341         mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
 342 }
 343
 344 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 345 {
 346         *ucr2 &= ~UCR2_CTSC;
 347         *ucr2 |= UCR2_CTS;
 348
 349         mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
 350 }
 351
 352 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 353 {
 354         *ucr2 |= UCR2_CTSC;
 355 }
 356
 357 /*
 358  * interrupts disabled on entry
 359  */
 360 static void imx_stop_tx(struct uart_port *port)
 361 {
 362         struct imx_port *sport = (struct imx_port *)port;
 363         unsigned long temp;
 364
 365         /*
 366          * We are maybe in the SMP context, so if the DMA TX thread is running
 367          * on other cpu, we have to wait for it to finish.
 368          */
 369         if (sport->dma_is_enabled && sport->dma_is_txing)
 370                 return;
 371
 372         temp = readl(port->membase + UCR1);
 373         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 374
 375         /* in rs485 mode disable transmitter if shifter is empty */
 376         if (port->rs485.flags & SER_RS485_ENABLED &&
 377             readl(port->membase + USR2) & USR2_TXDC) {
 378                 temp = readl(port->membase + UCR2);
 379                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 380                         imx_port_rts_active(sport, &temp);
 381                 else
 382                         imx_port_rts_inactive(sport, &temp);
 383                 temp |= UCR2_RXEN;
 384                 writel(temp, port->membase + UCR2);
 385
 386                 temp = readl(port->membase + UCR4);
 387                 temp &= ~UCR4_TCEN;
 388                 writel(temp, port->membase + UCR4);
 389         }
 390 }
 391
 392 /*
 393  * interrupts disabled on entry
 394  */
 395 static void imx_stop_rx(struct uart_port *port)
 396 {
 397         struct imx_port *sport = (struct imx_port *)port;
 398         unsigned long temp;
 399
 400         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 401                 if (sport->port.suspended) {
 402                         dmaengine_terminate_all(sport->dma_chan_rx);
 403                         sport->dma_is_rxing = 0;
 404                 } else {
 405                         return;
 406                 }
 407         }
 408
 409         temp = readl(sport->port.membase + UCR2);
 410         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 411
 412         /* disable the `Receiver Ready Interrrupt` */
 413         temp = readl(sport->port.membase + UCR1);
 414         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 415 }
 416
 417 /*
 418  * Set the modem control timer to fire immediately.
 419  */
 420 static void imx_enable_ms(struct uart_port *port)
 421 {
 422         struct imx_port *sport = (struct imx_port *)port;
 423
 424         mod_timer(&sport->timer, jiffies);
 425
 426         mctrl_gpio_enable_ms(sport->gpios);
 427 }
 428
 429 static void imx_dma_tx(struct imx_port *sport);
 430 static inline void imx_transmit_buffer(struct imx_port *sport)
 431 {
 432         struct circ_buf *xmit = &sport->port.state->xmit;
 433         unsigned long temp;
 434
 435         if (sport->port.x_char) {
 436                 /* Send next char */
 437                 writel(sport->port.x_char, sport->port.membase + URTX0);
 438                 sport->port.icount.tx++;
 439                 sport->port.x_char = 0;
 440                 return;
 441         }
 442
 443         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 444                 imx_stop_tx(&sport->port);
 445                 return;
 446         }
 447
 448         if (sport->dma_is_enabled) {
 449                 /*
 450                  * We've just sent a X-char Ensure the TX DMA is enabled
 451                  * and the TX IRQ is disabled.
 452                  **/
 453                 temp = readl(sport->port.membase + UCR1);
 454                 temp &= ~UCR1_TXMPTYEN;
 455                 if (sport->dma_is_txing) {
 456                         temp |= UCR1_TDMAEN;
 457                         writel(temp, sport->port.membase + UCR1);
 458                 } else {
 459                         writel(temp, sport->port.membase + UCR1);
 460                         imx_dma_tx(sport);
 461                 }
 462         }
 463
 464         while (!uart_circ_empty(xmit) &&
 465                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 466                 /* send xmit->buf[xmit->tail]
 467                  * out the port here */
 468                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 469                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 470                 sport->port.icount.tx++;
 471         }
 472
 473         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 474                 uart_write_wakeup(&sport->port);
 475
 476         if (uart_circ_empty(xmit))
 477                 imx_stop_tx(&sport->port);
 478 }
 479
 480 static void dma_tx_callback(void *data)
 481 {
 482         struct imx_port *sport = data;
 483         struct scatterlist *sgl = &sport->tx_sgl[0];
 484         struct circ_buf *xmit = &sport->port.state->xmit;
 485         unsigned long flags;
 486         unsigned long temp;
 487
 488         spin_lock_irqsave(&sport->port.lock, flags);
 489
 490         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 491
 492         temp = readl(sport->port.membase + UCR1);
 493         temp &= ~UCR1_TDMAEN;
 494         writel(temp, sport->port.membase + UCR1);
 495
 496         /* update the stat */
 497         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 498         sport->port.icount.tx += sport->tx_bytes;
 499
 500         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 501
 502         sport->dma_is_txing = 0;
 503
 504         spin_unlock_irqrestore(&sport->port.lock, flags);
 505
 506         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 507                 uart_write_wakeup(&sport->port);
 508
 509         if (waitqueue_active(&sport->dma_wait)) {
 510                 wake_up(&sport->dma_wait);
 511                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
 512                 return;
 513         }
 514
 515         spin_lock_irqsave(&sport->port.lock, flags);
 516         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 517                 imx_dma_tx(sport);
 518         spin_unlock_irqrestore(&sport->port.lock, flags);
 519 }
 520
 521 static void imx_dma_tx(struct imx_port *sport)
 522 {
 523         struct circ_buf *xmit = &sport->port.state->xmit;
 524         struct scatterlist *sgl = sport->tx_sgl;
 525         struct dma_async_tx_descriptor *desc;
 526         struct dma_chan *chan = sport->dma_chan_tx;
 527         struct device *dev = sport->port.dev;
 528         unsigned long temp;
 529         int ret;
 530
 531         if (sport->dma_is_txing)
 532                 return;
 533
 534         sport->tx_bytes = uart_circ_chars_pending(xmit);
 535
 536         if (xmit->tail < xmit->head) {
 537                 sport->dma_tx_nents = 1;
 538                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 539         } else {
 540                 sport->dma_tx_nents = 2;
 541                 sg_init_table(sgl, 2);
 542                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 543                                 UART_XMIT_SIZE - xmit->tail);
 544                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 545         }
 546
 547         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 548         if (ret == 0) {
 549                 dev_err(dev, "DMA mapping error for TX.\n");
 550                 return;
 551         }
 552         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 553                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 554         if (!desc) {
 555                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 556                              DMA_TO_DEVICE);
 557                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 558                 return;
 559         }
 560         desc->callback = dma_tx_callback;
 561         desc->callback_param = sport;
 562
 563         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 564                         uart_circ_chars_pending(xmit));
 565
 566         temp = readl(sport->port.membase + UCR1);
 567         temp |= UCR1_TDMAEN;
 568         writel(temp, sport->port.membase + UCR1);
 569
 570         /* fire it */
 571         sport->dma_is_txing = 1;
 572         dmaengine_submit(desc);
 573         dma_async_issue_pending(chan);
 574         return;
 575 }
 576
 577 /*
 578  * interrupts disabled on entry
 579  */
 580 static void imx_start_tx(struct uart_port *port)
 581 {
 582         struct imx_port *sport = (struct imx_port *)port;
 583         unsigned long temp;
 584
 585         if (port->rs485.flags & SER_RS485_ENABLED) {
 586                 temp = readl(port->membase + UCR2);
 587                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 588                         imx_port_rts_active(sport, &temp);
 589                 else
 590                         imx_port_rts_inactive(sport, &temp);
 591                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 592                         temp &= ~UCR2_RXEN;
 593                 writel(temp, port->membase + UCR2);
 594
 595                 /* enable transmitter and shifter empty irq */
 596                 temp = readl(port->membase + UCR4);
 597                 temp |= UCR4_TCEN;
 598                 writel(temp, port->membase + UCR4);
 599         }
 600
 601         if (!sport->dma_is_enabled) {
 602                 temp = readl(sport->port.membase + UCR1);
 603                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 604         }
 605
 606         if (sport->dma_is_enabled) {
 607                 if (sport->port.x_char) {
 608                         /* We have X-char to send, so enable TX IRQ and
 609                          * disable TX DMA to let TX interrupt to send X-char */
 610                         temp = readl(sport->port.membase + UCR1);
 611                         temp &= ~UCR1_TDMAEN;
 612                         temp |= UCR1_TXMPTYEN;
 613                         writel(temp, sport->port.membase + UCR1);
 614                         return;
 615                 }
 616
 617                 if (!uart_circ_empty(&port->state->xmit) &&
 618                     !uart_tx_stopped(port))
 619                         imx_dma_tx(sport);
 620                 return;
 621         }
 622 }
 623
 624 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 625 {
 626         struct imx_port *sport = dev_id;
 627         unsigned int val;
 628         unsigned long flags;
 629
 630         spin_lock_irqsave(&sport->port.lock, flags);
 631
 632         writel(USR1_RTSD, sport->port.membase + USR1);
 633         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 634         uart_handle_cts_change(&sport->port, !!val);
 635         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 636
 637         spin_unlock_irqrestore(&sport->port.lock, flags);
 638         return IRQ_HANDLED;
 639 }
 640
 641 static irqreturn_t imx_txint(int irq, void *dev_id)
 642 {
 643         struct imx_port *sport = dev_id;
 644         unsigned long flags;
 645
 646         spin_lock_irqsave(&sport->port.lock, flags);
 647         imx_transmit_buffer(sport);
 648         spin_unlock_irqrestore(&sport->port.lock, flags);
 649         return IRQ_HANDLED;
 650 }
 651
 652 static irqreturn_t imx_rxint(int irq, void *dev_id)
 653 {
 654         struct imx_port *sport = dev_id;
 655         unsigned int rx, flg, ignored = 0;
 656         struct tty_port *port = &sport->port.state->port;
 657         unsigned long flags, temp;
 658
 659         spin_lock_irqsave(&sport->port.lock, flags);
 660
 661         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 662                 flg = TTY_NORMAL;
 663                 sport->port.icount.rx++;
 664
 665                 rx = readl(sport->port.membase + URXD0);
 666
 667                 temp = readl(sport->port.membase + USR2);
 668                 if (temp & USR2_BRCD) {
 669                         writel(USR2_BRCD, sport->port.membase + USR2);
 670                         if (uart_handle_break(&sport->port))
 671                                 continue;
 672                 }
 673
 674                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 675                         continue;
 676
 677                 if (unlikely(rx & URXD_ERR)) {
 678                         if (rx & URXD_BRK)
 679                                 sport->port.icount.brk++;
 680                         else if (rx & URXD_PRERR)
 681                                 sport->port.icount.parity++;
 682                         else if (rx & URXD_FRMERR)
 683                                 sport->port.icount.frame++;
 684                         if (rx & URXD_OVRRUN)
 685                                 sport->port.icount.overrun++;
 686
 687                         if (rx & sport->port.ignore_status_mask) {
 688                                 if (++ignored > 100)
 689                                         goto out;
 690                                 continue;
 691                         }
 692
 693                         rx &= (sport->port.read_status_mask | 0xFF);
 694
 695                         if (rx & URXD_BRK)
 696                                 flg = TTY_BREAK;
 697                         else if (rx & URXD_PRERR)
 698                                 flg = TTY_PARITY;
 699                         else if (rx & URXD_FRMERR)
 700                                 flg = TTY_FRAME;
 701                         if (rx & URXD_OVRRUN)
 702                                 flg = TTY_OVERRUN;
 703
 704 #ifdef SUPPORT_SYSRQ
 705                         sport->port.sysrq = 0;
 706 #endif
 707                 }
 708
 709                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 710                         goto out;
 711
 712                 if (tty_insert_flip_char(port, rx, flg) == 0)
 713                         sport->port.icount.buf_overrun++;
 714         }
 715
 716 out:
 717         spin_unlock_irqrestore(&sport->port.lock, flags);
 718         tty_flip_buffer_push(port);
 719         return IRQ_HANDLED;
 720 }
 721
 722 static void clear_rx_errors(struct imx_port *sport);
 723 static int start_rx_dma(struct imx_port *sport);
 724 /*
 725  * If the RXFIFO is filled with some data, and then we
 726  * arise a DMA operation to receive them.
 727  */
 728 static void imx_dma_rxint(struct imx_port *sport)
 729 {
 730         unsigned long temp;
 731         unsigned long flags;
 732
 733         spin_lock_irqsave(&sport->port.lock, flags);
 734
 735         temp = readl(sport->port.membase + USR2);
 736         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 737                 sport->dma_is_rxing = 1;
 738
 739                 /* disable the receiver ready and aging timer interrupts */
 740                 temp = readl(sport->port.membase + UCR1);
 741                 temp &= ~(UCR1_RRDYEN);
 742                 writel(temp, sport->port.membase + UCR1);
 743
 744                 temp = readl(sport->port.membase + UCR2);
 745                 temp &= ~(UCR2_ATEN);
 746                 writel(temp, sport->port.membase + UCR2);
 747
 748                 /* disable the rx errors interrupts */
 749                 temp = readl(sport->port.membase + UCR4);
 750                 temp &= ~UCR4_OREN;
 751                 writel(temp, sport->port.membase + UCR4);
 752
 753                 /* tell the DMA to receive the data. */
 754                 start_rx_dma(sport);
 755         }
 756
 757         spin_unlock_irqrestore(&sport->port.lock, flags);
 758 }
 759
 760 /*
 761  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 762  */
 763 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 764 {
 765         unsigned int tmp = TIOCM_DSR;
 766         unsigned usr1 = readl(sport->port.membase + USR1);
 767         unsigned usr2 = readl(sport->port.membase + USR2);
 768
 769         if (usr1 & USR1_RTSS)
 770                 tmp |= TIOCM_CTS;
 771
 772         /* in DCE mode DCDIN is always 0 */
 773         if (!(usr2 & USR2_DCDIN))
 774                 tmp |= TIOCM_CAR;
 775
 776         if (sport->dte_mode)
 777                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 778                         tmp |= TIOCM_RI;
 779
 780         return tmp;
 781 }
 782
 783 /*
 784  * Handle any change of modem status signal since we were last called.
 785  */
 786 static void imx_mctrl_check(struct imx_port *sport)
 787 {
 788         unsigned int status, changed;
 789
 790         status = imx_get_hwmctrl(sport);
 791         changed = status ^ sport->old_status;
 792
 793         if (changed == 0)
 794                 return;
 795
 796         sport->old_status = status;
 797
 798         if (changed & TIOCM_RI && status & TIOCM_RI)
 799                 sport->port.icount.rng++;
 800         if (changed & TIOCM_DSR)
 801                 sport->port.icount.dsr++;
 802         if (changed & TIOCM_CAR)
 803                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 804         if (changed & TIOCM_CTS)
 805                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 806
 807         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 808 }
 809
 810 static irqreturn_t imx_int(int irq, void *dev_id)
 811 {
 812         struct imx_port *sport = dev_id;
 813         unsigned int sts;
 814         unsigned int sts2;
 815         irqreturn_t ret = IRQ_NONE;
 816
 817         sts = readl(sport->port.membase + USR1);
 818         sts2 = readl(sport->port.membase + USR2);
 819
 820         if (sts & (USR1_RRDY | USR1_AGTIM)) {
 821                 if (sport->dma_is_enabled)
 822                         imx_dma_rxint(sport);
 823                 else
 824                         imx_rxint(irq, dev_id);
 825                 ret = IRQ_HANDLED;
 826         }
 827
 828         if ((sts & USR1_TRDY &&
 829              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 830             (sts2 & USR2_TXDC &&
 831              readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
 832                 imx_txint(irq, dev_id);
 833                 ret = IRQ_HANDLED;
 834         }
 835
 836         if (sts & USR1_DTRD) {
 837                 unsigned long flags;
 838
 839                 if (sts & USR1_DTRD)
 840                         writel(USR1_DTRD, sport->port.membase + USR1);
 841
 842                 spin_lock_irqsave(&sport->port.lock, flags);
 843                 imx_mctrl_check(sport);
 844                 spin_unlock_irqrestore(&sport->port.lock, flags);
 845
 846                 ret = IRQ_HANDLED;
 847         }
 848
 849         if (sts & USR1_RTSD) {
 850                 imx_rtsint(irq, dev_id);
 851                 ret = IRQ_HANDLED;
 852         }
 853
 854         if (sts & USR1_AWAKE) {
 855                 writel(USR1_AWAKE, sport->port.membase + USR1);
 856                 ret = IRQ_HANDLED;
 857         }
 858
 859         if (sts2 & USR2_ORE) {
 860                 sport->port.icount.overrun++;
 861                 writel(USR2_ORE, sport->port.membase + USR2);
 862                 ret = IRQ_HANDLED;
 863         }
 864
 865         return ret;
 866 }
 867
 868 /*
 869  * Return TIOCSER_TEMT when transmitter is not busy.
 870  */
 871 static unsigned int imx_tx_empty(struct uart_port *port)
 872 {
 873         struct imx_port *sport = (struct imx_port *)port;
 874         unsigned int ret;
 875
 876         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 877
 878         /* If the TX DMA is working, return 0. */
 879         if (sport->dma_is_enabled && sport->dma_is_txing)
 880                 ret = 0;
 881
 882         return ret;
 883 }
 884
 885 static unsigned int imx_get_mctrl(struct uart_port *port)
 886 {
 887         struct imx_port *sport = (struct imx_port *)port;
 888         unsigned int ret = imx_get_hwmctrl(sport);
 889
 890         mctrl_gpio_get(sport->gpios, &ret);
 891
 892         return ret;
 893 }
 894
 895 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 896 {
 897         struct imx_port *sport = (struct imx_port *)port;
 898         unsigned long temp;
 899
 900         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 901                 temp = readl(sport->port.membase + UCR2);
 902                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 903                 if (mctrl & TIOCM_RTS)
 904                         temp |= UCR2_CTS | UCR2_CTSC;
 905                 writel(temp, sport->port.membase + UCR2);
 906         }
 907
 908         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 909         if (!(mctrl & TIOCM_DTR))
 910                 temp |= UCR3_DSR;
 911         writel(temp, sport->port.membase + UCR3);
 912
 913         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 914         if (mctrl & TIOCM_LOOP)
 915                 temp |= UTS_LOOP;
 916         writel(temp, sport->port.membase + uts_reg(sport));
 917
 918         mctrl_gpio_set(sport->gpios, mctrl);
 919 }
 920
 921 /*
 922  * Interrupts always disabled.
 923  */
 924 static void imx_break_ctl(struct uart_port *port, int break_state)
 925 {
 926         struct imx_port *sport = (struct imx_port *)port;
 927         unsigned long flags, temp;
 928
 929         spin_lock_irqsave(&sport->port.lock, flags);
 930
 931         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 932
 933         if (break_state != 0)
 934                 temp |= UCR1_SNDBRK;
 935
 936         writel(temp, sport->port.membase + UCR1);
 937
 938         spin_unlock_irqrestore(&sport->port.lock, flags);
 939 }
 940
 941 /*
 942  * This is our per-port timeout handler, for checking the
 943  * modem status signals.
 944  */
 945 static void imx_timeout(unsigned long data)
 946 {
 947         struct imx_port *sport = (struct imx_port *)data;
 948         unsigned long flags;
 949
 950         if (sport->port.state) {
 951                 spin_lock_irqsave(&sport->port.lock, flags);
 952                 imx_mctrl_check(sport);
 953                 spin_unlock_irqrestore(&sport->port.lock, flags);
 954
 955                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 956         }
 957 }
 958
 959 #define RX_BUF_SIZE     (PAGE_SIZE)
 960
 961 /*
 962  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
 963  *   [1] the RX DMA buffer is full.
 964  *   [2] the aging timer expires
 965  *
 966  * Condition [2] is triggered when a character has been sitting in the FIFO
 967  * for at least 8 byte durations.
 968  */
 969 static void dma_rx_callback(void *data)
 970 {
 971         struct imx_port *sport = data;
 972         struct dma_chan *chan = sport->dma_chan_rx;
 973         struct scatterlist *sgl = &sport->rx_sgl;
 974         struct tty_port *port = &sport->port.state->port;
 975         struct dma_tx_state state;
 976         struct circ_buf *rx_ring = &sport->rx_ring;
 977         enum dma_status status;
 978         unsigned int w_bytes = 0;
 979         unsigned int r_bytes;
 980         unsigned int bd_size;
 981
 982         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 983
 984         if (status == DMA_ERROR) {
 985                 dev_err(sport->port.dev, "DMA transaction error.\n");
 986                 clear_rx_errors(sport);
 987                 return;
 988         }
 989
 990         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 991
 992                 /*
 993                  * The state-residue variable represents the empty space
 994                  * relative to the entire buffer. Taking this in consideration
 995                  * the head is always calculated base on the buffer total
 996                  * length - DMA transaction residue. The UART script from the
 997                  * SDMA firmware will jump to the next buffer descriptor,
 998                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
 999                  * Taking this in consideration the tail is always at the
1000                  * beginning of the buffer descriptor that contains the head.
1001                  */
1002
1003                 /* Calculate the head */
1004                 rx_ring->head = sg_dma_len(sgl) - state.residue;
1005
1006                 /* Calculate the tail. */
1007                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1008                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1009
1010                 if (rx_ring->head <= sg_dma_len(sgl) &&
1011                     rx_ring->head > rx_ring->tail) {
1012
1013                         /* Move data from tail to head */
1014                         r_bytes = rx_ring->head - rx_ring->tail;
1015
1016                         /* CPU claims ownership of RX DMA buffer */
1017                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1018                                 DMA_FROM_DEVICE);
1019
1020                         w_bytes = tty_insert_flip_string(port,
1021                                 sport->rx_buf + rx_ring->tail, r_bytes);
1022
1023                         /* UART retrieves ownership of RX DMA buffer */
1024                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1025                                 DMA_FROM_DEVICE);
1026
1027                         if (w_bytes != r_bytes)
1028                                 sport->port.icount.buf_overrun++;
1029
1030                         sport->port.icount.rx += w_bytes;
1031                 } else  {
1032                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
1033                         WARN_ON(rx_ring->head <= rx_ring->tail);
1034                 }
1035         }
1036
1037         if (w_bytes) {
1038                 tty_flip_buffer_push(port);
1039                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1040         }
1041 }
1042
1043 /* RX DMA buffer periods */
1044 #define RX_DMA_PERIODS 4
1045
1046 static int start_rx_dma(struct imx_port *sport)
1047 {
1048         struct scatterlist *sgl = &sport->rx_sgl;
1049         struct dma_chan *chan = sport->dma_chan_rx;
1050         struct device *dev = sport->port.dev;
1051         struct dma_async_tx_descriptor *desc;
1052         int ret;
1053
1054         sport->rx_ring.head = 0;
1055         sport->rx_ring.tail = 0;
1056         sport->rx_periods = RX_DMA_PERIODS;
1057
1058         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1059         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1060         if (ret == 0) {
1061                 dev_err(dev, "DMA mapping error for RX.\n");
1062                 return -EINVAL;
1063         }
1064
1065         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1066                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1067                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1068
1069         if (!desc) {
1070                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1071                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1072                 return -EINVAL;
1073         }
1074         desc->callback = dma_rx_callback;
1075         desc->callback_param = sport;
1076
1077         dev_dbg(dev, "RX: prepare for the DMA.\n");
1078         sport->rx_cookie = dmaengine_submit(desc);
1079         dma_async_issue_pending(chan);
1080         return 0;
1081 }
1082
1083 static void clear_rx_errors(struct imx_port *sport)
1084 {
1085         unsigned int status_usr1, status_usr2;
1086
1087         status_usr1 = readl(sport->port.membase + USR1);
1088         status_usr2 = readl(sport->port.membase + USR2);
1089
1090         if (status_usr2 & USR2_BRCD) {
1091                 sport->port.icount.brk++;
1092                 writel(USR2_BRCD, sport->port.membase + USR2);
1093         } else if (status_usr1 & USR1_FRAMERR) {
1094                 sport->port.icount.frame++;
1095                 writel(USR1_FRAMERR, sport->port.membase + USR1);
1096         } else if (status_usr1 & USR1_PARITYERR) {
1097                 sport->port.icount.parity++;
1098                 writel(USR1_PARITYERR, sport->port.membase + USR1);
1099         }
1100
1101         if (status_usr2 & USR2_ORE) {
1102                 sport->port.icount.overrun++;
1103                 writel(USR2_ORE, sport->port.membase + USR2);
1104         }
1105
1106 }
1107
1108 #define TXTL_DEFAULT 2 /* reset default */
1109 #define RXTL_DEFAULT 1 /* reset default */
1110 #define TXTL_DMA 8 /* DMA burst setting */
1111 #define RXTL_DMA 9 /* DMA burst setting */
1112
1113 static void imx_setup_ufcr(struct imx_port *sport,
1114                           unsigned char txwl, unsigned char rxwl)
1115 {
1116         unsigned int val;
1117
1118         /* set receiver / transmitter trigger level */
1119         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1120         val |= txwl << UFCR_TXTL_SHF | rxwl;
1121         writel(val, sport->port.membase + UFCR);
1122 }
1123
1124 static void imx_uart_dma_exit(struct imx_port *sport)
1125 {
1126         if (sport->dma_chan_rx) {
1127                 dmaengine_terminate_sync(sport->dma_chan_rx);
1128                 dma_release_channel(sport->dma_chan_rx);
1129                 sport->dma_chan_rx = NULL;
1130                 sport->rx_cookie = -EINVAL;
1131                 kfree(sport->rx_buf);
1132                 sport->rx_buf = NULL;
1133         }
1134
1135         if (sport->dma_chan_tx) {
1136                 dmaengine_terminate_sync(sport->dma_chan_tx);
1137                 dma_release_channel(sport->dma_chan_tx);
1138                 sport->dma_chan_tx = NULL;
1139         }
1140
1141         sport->dma_is_inited = 0;
1142 }
1143
1144 static int imx_uart_dma_init(struct imx_port *sport)
1145 {
1146         struct dma_slave_config slave_config = {};
1147         struct device *dev = sport->port.dev;
1148         int ret;
1149
1150         /* Prepare for RX : */
1151         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1152         if (!sport->dma_chan_rx) {
1153                 dev_dbg(dev, "cannot get the DMA channel.\n");
1154                 ret = -EINVAL;
1155                 goto err;
1156         }
1157
1158         slave_config.direction = DMA_DEV_TO_MEM;
1159         slave_config.src_addr = sport->port.mapbase + URXD0;
1160         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1161         /* one byte less than the watermark level to enable the aging timer */
1162         slave_config.src_maxburst = RXTL_DMA - 1;
1163         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1164         if (ret) {
1165                 dev_err(dev, "error in RX dma configuration.\n");
1166                 goto err;
1167         }
1168
1169         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1170         if (!sport->rx_buf) {
1171                 ret = -ENOMEM;
1172                 goto err;
1173         }
1174         sport->rx_ring.buf = sport->rx_buf;
1175
1176         /* Prepare for TX : */
1177         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1178         if (!sport->dma_chan_tx) {
1179                 dev_err(dev, "cannot get the TX DMA channel!\n");
1180                 ret = -EINVAL;
1181                 goto err;
1182         }
1183
1184         slave_config.direction = DMA_MEM_TO_DEV;
1185         slave_config.dst_addr = sport->port.mapbase + URTX0;
1186         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1187         slave_config.dst_maxburst = TXTL_DMA;
1188         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1189         if (ret) {
1190                 dev_err(dev, "error in TX dma configuration.");
1191                 goto err;
1192         }
1193
1194         sport->dma_is_inited = 1;
1195
1196         return 0;
1197 err:
1198         imx_uart_dma_exit(sport);
1199         return ret;
1200 }
1201
1202 static void imx_enable_dma(struct imx_port *sport)
1203 {
1204         unsigned long temp;
1205
1206         init_waitqueue_head(&sport->dma_wait);
1207
1208         /* set UCR1 */
1209         temp = readl(sport->port.membase + UCR1);
1210         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1211         writel(temp, sport->port.membase + UCR1);
1212
1213         temp = readl(sport->port.membase + UCR2);
1214         temp |= UCR2_ATEN;
1215         writel(temp, sport->port.membase + UCR2);
1216
1217         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1218
1219         sport->dma_is_enabled = 1;
1220 }
1221
1222 static void imx_disable_dma(struct imx_port *sport)
1223 {
1224         unsigned long temp;
1225
1226         /* clear UCR1 */
1227         temp = readl(sport->port.membase + UCR1);
1228         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1229         writel(temp, sport->port.membase + UCR1);
1230
1231         /* clear UCR2 */
1232         temp = readl(sport->port.membase + UCR2);
1233         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1234         writel(temp, sport->port.membase + UCR2);
1235
1236         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1237
1238         sport->dma_is_enabled = 0;
1239 }
1240
1241 /* half the RX buffer size */
1242 #define CTSTL 16
1243
1244 static int imx_startup(struct uart_port *port)
1245 {
1246         struct imx_port *sport = (struct imx_port *)port;
1247         int retval, i;
1248         unsigned long flags, temp;
1249
1250         retval = clk_prepare_enable(sport->clk_per);
1251         if (retval)
1252                 return retval;
1253         retval = clk_prepare_enable(sport->clk_ipg);
1254         if (retval) {
1255                 clk_disable_unprepare(sport->clk_per);
1256                 return retval;
1257         }
1258
1259         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1260
1261         /* disable the DREN bit (Data Ready interrupt enable) before
1262          * requesting IRQs
1263          */
1264         temp = readl(sport->port.membase + UCR4);
1265
1266         /* set the trigger level for CTS */
1267         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1268         temp |= CTSTL << UCR4_CTSTL_SHF;
1269
1270         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1271
1272         /* Can we enable the DMA support? */
1273         if (!uart_console(port) && !sport->dma_is_inited)
1274                 imx_uart_dma_init(sport);
1275
1276         spin_lock_irqsave(&sport->port.lock, flags);
1277         /* Reset fifo's and state machines */
1278         i = 100;
1279
1280         temp = readl(sport->port.membase + UCR2);
1281         temp &= ~UCR2_SRST;
1282         writel(temp, sport->port.membase + UCR2);
1283
1284         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1285                 udelay(1);
1286
1287         /*
1288          * Finally, clear and enable interrupts
1289          */
1290         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1291         writel(USR2_ORE, sport->port.membase + USR2);
1292
1293         if (sport->dma_is_inited && !sport->dma_is_enabled)
1294                 imx_enable_dma(sport);
1295
1296         temp = readl(sport->port.membase + UCR1);
1297         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1298
1299         writel(temp, sport->port.membase + UCR1);
1300
1301         temp = readl(sport->port.membase + UCR4);
1302         temp |= UCR4_OREN;
1303         writel(temp, sport->port.membase + UCR4);
1304
1305         temp = readl(sport->port.membase + UCR2);
1306         temp |= (UCR2_RXEN | UCR2_TXEN);
1307         if (!sport->have_rtscts)
1308                 temp |= UCR2_IRTS;
1309         /*
1310          * make sure the edge sensitive RTS-irq is disabled,
1311          * we're using RTSD instead.
1312          */
1313         if (!is_imx1_uart(sport))
1314                 temp &= ~UCR2_RTSEN;
1315         writel(temp, sport->port.membase + UCR2);
1316
1317         if (!is_imx1_uart(sport)) {
1318                 temp = readl(sport->port.membase + UCR3);
1319
1320                 /*
1321                  * The effect of RI and DCD differs depending on the UFCR_DCEDTE
1322                  * bit. In DCE mode they control the outputs, in DTE mode they
1323                  * enable the respective irqs. At least the DCD irq cannot be
1324                  * cleared on i.MX25 at least, so it's not usable and must be
1325                  * disabled. I don't have test hardware to check if RI has the
1326                  * same problem but I consider this likely so it's disabled for
1327                  * now, too.
1328                  */
1329                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
1330                         UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1331
1332                 if (sport->dte_mode)
1333                         temp &= ~(UCR3_RI | UCR3_DCD);
1334
1335                 writel(temp, sport->port.membase + UCR3);
1336         }
1337
1338         /*
1339          * Enable modem status interrupts
1340          */
1341         imx_enable_ms(&sport->port);
1342         spin_unlock_irqrestore(&sport->port.lock, flags);
1343
1344         return 0;
1345 }
1346
1347 static void imx_shutdown(struct uart_port *port)
1348 {
1349         struct imx_port *sport = (struct imx_port *)port;
1350         unsigned long temp;
1351         unsigned long flags;
1352
1353         if (sport->dma_is_enabled) {
1354                 sport->dma_is_rxing = 0;
1355                 sport->dma_is_txing = 0;
1356                 dmaengine_terminate_sync(sport->dma_chan_tx);
1357                 dmaengine_terminate_sync(sport->dma_chan_rx);
1358
1359                 spin_lock_irqsave(&sport->port.lock, flags);
1360                 imx_stop_tx(port);
1361                 imx_stop_rx(port);
1362                 imx_disable_dma(sport);
1363                 spin_unlock_irqrestore(&sport->port.lock, flags);
1364                 imx_uart_dma_exit(sport);
1365         }
1366
1367         mctrl_gpio_disable_ms(sport->gpios);
1368
1369         spin_lock_irqsave(&sport->port.lock, flags);
1370         temp = readl(sport->port.membase + UCR2);
1371         temp &= ~(UCR2_TXEN);
1372         writel(temp, sport->port.membase + UCR2);
1373         spin_unlock_irqrestore(&sport->port.lock, flags);
1374
1375         /*
1376          * Stop our timer.
1377          */
1378         del_timer_sync(&sport->timer);
1379
1380         /*
1381          * Disable all interrupts, port and break condition.
1382          */
1383
1384         spin_lock_irqsave(&sport->port.lock, flags);
1385         temp = readl(sport->port.membase + UCR1);
1386         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1387
1388         writel(temp, sport->port.membase + UCR1);
1389         spin_unlock_irqrestore(&sport->port.lock, flags);
1390
1391         clk_disable_unprepare(sport->clk_per);
1392         clk_disable_unprepare(sport->clk_ipg);
1393 }
1394
1395 static void imx_flush_buffer(struct uart_port *port)
1396 {
1397         struct imx_port *sport = (struct imx_port *)port;
1398         struct scatterlist *sgl = &sport->tx_sgl[0];
1399         unsigned long temp;
1400         int i = 100, ubir, ubmr, uts;
1401
1402         if (!sport->dma_chan_tx)
1403                 return;
1404
1405         sport->tx_bytes = 0;
1406         dmaengine_terminate_all(sport->dma_chan_tx);
1407         if (sport->dma_is_txing) {
1408                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1409                              DMA_TO_DEVICE);
1410                 temp = readl(sport->port.membase + UCR1);
1411                 temp &= ~UCR1_TDMAEN;
1412                 writel(temp, sport->port.membase + UCR1);
1413                 sport->dma_is_txing = false;
1414         }
1415
1416         /*
1417          * According to the Reference Manual description of the UART SRST bit:
1418          * "Reset the transmit and receive state machines,
1419          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1420          * and UTS[6-3]". As we don't need to restore the old values from
1421          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1422          */
1423         ubir = readl(sport->port.membase + UBIR);
1424         ubmr = readl(sport->port.membase + UBMR);
1425         uts = readl(sport->port.membase + IMX21_UTS);
1426
1427         temp = readl(sport->port.membase + UCR2);
1428         temp &= ~UCR2_SRST;
1429         writel(temp, sport->port.membase + UCR2);
1430
1431         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1432                 udelay(1);
1433
1434         /* Restore the registers */
1435         writel(ubir, sport->port.membase + UBIR);
1436         writel(ubmr, sport->port.membase + UBMR);
1437         writel(uts, sport->port.membase + IMX21_UTS);
1438 }
1439
1440 static void
1441 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1442                    struct ktermios *old)
1443 {
1444         struct imx_port *sport = (struct imx_port *)port;
1445         unsigned long flags;
1446         unsigned long ucr2, old_ucr1, old_ucr2;
1447         unsigned int baud, quot;
1448         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1449         unsigned long div, ufcr;
1450         unsigned long num, denom;
1451         uint64_t tdiv64;
1452
1453         /*
1454          * We only support CS7 and CS8.
1455          */
1456         while ((termios->c_cflag & CSIZE) != CS7 &&
1457                (termios->c_cflag & CSIZE) != CS8) {
1458                 termios->c_cflag &= ~CSIZE;
1459                 termios->c_cflag |= old_csize;
1460                 old_csize = CS8;
1461         }
1462
1463         if ((termios->c_cflag & CSIZE) == CS8)
1464                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1465         else
1466                 ucr2 = UCR2_SRST | UCR2_IRTS;
1467
1468         if (termios->c_cflag & CRTSCTS) {
1469                 if (sport->have_rtscts) {
1470                         ucr2 &= ~UCR2_IRTS;
1471
1472                         if (port->rs485.flags & SER_RS485_ENABLED) {
1473                                 /*
1474                                  * RTS is mandatory for rs485 operation, so keep
1475                                  * it under manual control and keep transmitter
1476                                  * disabled.
1477                                  */
1478                                 if (port->rs485.flags &
1479                                     SER_RS485_RTS_AFTER_SEND)
1480                                         imx_port_rts_active(sport, &ucr2);
1481                                 else
1482                                         imx_port_rts_inactive(sport, &ucr2);
1483                         } else {
1484                                 imx_port_rts_auto(sport, &ucr2);
1485                         }
1486                 } else {
1487                         termios->c_cflag &= ~CRTSCTS;
1488                 }
1489         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1490                 /* disable transmitter */
1491                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1492                         imx_port_rts_active(sport, &ucr2);
1493                 else
1494                         imx_port_rts_inactive(sport, &ucr2);
1495         }
1496
1497
1498         if (termios->c_cflag & CSTOPB)
1499                 ucr2 |= UCR2_STPB;
1500         if (termios->c_cflag & PARENB) {
1501                 ucr2 |= UCR2_PREN;
1502                 if (termios->c_cflag & PARODD)
1503                         ucr2 |= UCR2_PROE;
1504         }
1505
1506         del_timer_sync(&sport->timer);
1507
1508         /*
1509          * Ask the core to calculate the divisor for us.
1510          */
1511         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1512         quot = uart_get_divisor(port, baud);
1513
1514         spin_lock_irqsave(&sport->port.lock, flags);
1515
1516         sport->port.read_status_mask = 0;
1517         if (termios->c_iflag & INPCK)
1518                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1519         if (termios->c_iflag & (BRKINT | PARMRK))
1520                 sport->port.read_status_mask |= URXD_BRK;
1521
1522         /*
1523          * Characters to ignore
1524          */
1525         sport->port.ignore_status_mask = 0;
1526         if (termios->c_iflag & IGNPAR)
1527                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1528         if (termios->c_iflag & IGNBRK) {
1529                 sport->port.ignore_status_mask |= URXD_BRK;
1530                 /*
1531                  * If we're ignoring parity and break indicators,
1532                  * ignore overruns too (for real raw support).
1533                  */
1534                 if (termios->c_iflag & IGNPAR)
1535                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1536         }
1537
1538         if ((termios->c_cflag & CREAD) == 0)
1539                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1540
1541         /*
1542          * Update the per-port timeout.
1543          */
1544         uart_update_timeout(port, termios->c_cflag, baud);
1545
1546         /*
1547          * disable interrupts and drain transmitter
1548          */
1549         old_ucr1 = readl(sport->port.membase + UCR1);
1550         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1551                         sport->port.membase + UCR1);
1552
1553         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1554                 barrier();
1555
1556         /* then, disable everything */
1557         old_ucr2 = readl(sport->port.membase + UCR2);
1558         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1559                         sport->port.membase + UCR2);
1560         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1561
1562         /* custom-baudrate handling */
1563         div = sport->port.uartclk / (baud * 16);
1564         if (baud == 38400 && quot != div)
1565                 baud = sport->port.uartclk / (quot * 16);
1566
1567         div = sport->port.uartclk / (baud * 16);
1568         if (div > 7)
1569                 div = 7;
1570         if (!div)
1571                 div = 1;
1572
1573         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1574                 1 << 16, 1 << 16, &num, &denom);
1575
1576         tdiv64 = sport->port.uartclk;
1577         tdiv64 *= num;
1578         do_div(tdiv64, denom * 16 * div);
1579         tty_termios_encode_baud_rate(termios,
1580                                 (speed_t)tdiv64, (speed_t)tdiv64);
1581
1582         num -= 1;
1583         denom -= 1;
1584
1585         ufcr = readl(sport->port.membase + UFCR);
1586         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1587         if (sport->dte_mode)
1588                 ufcr |= UFCR_DCEDTE;
1589         writel(ufcr, sport->port.membase + UFCR);
1590
1591         writel(num, sport->port.membase + UBIR);
1592         writel(denom, sport->port.membase + UBMR);
1593
1594         if (!is_imx1_uart(sport))
1595                 writel(sport->port.uartclk / div / 1000,
1596                                 sport->port.membase + IMX21_ONEMS);
1597
1598         writel(old_ucr1, sport->port.membase + UCR1);
1599
1600         /* set the parity, stop bits and data size */
1601         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1602
1603         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1604                 imx_enable_ms(&sport->port);
1605
1606         spin_unlock_irqrestore(&sport->port.lock, flags);
1607 }
1608
1609 static const char *imx_type(struct uart_port *port)
1610 {
1611         struct imx_port *sport = (struct imx_port *)port;
1612
1613         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1614 }
1615
1616 /*
1617  * Configure/autoconfigure the port.
1618  */
1619 static void imx_config_port(struct uart_port *port, int flags)
1620 {
1621         struct imx_port *sport = (struct imx_port *)port;
1622
1623         if (flags & UART_CONFIG_TYPE)
1624                 sport->port.type = PORT_IMX;
1625 }
1626
1627 /*
1628  * Verify the new serial_struct (for TIOCSSERIAL).
1629  * The only change we allow are to the flags and type, and
1630  * even then only between PORT_IMX and PORT_UNKNOWN
1631  */
1632 static int
1633 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1634 {
1635         struct imx_port *sport = (struct imx_port *)port;
1636         int ret = 0;
1637
1638         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1639                 ret = -EINVAL;
1640         if (sport->port.irq != ser->irq)
1641                 ret = -EINVAL;
1642         if (ser->io_type != UPIO_MEM)
1643                 ret = -EINVAL;
1644         if (sport->port.uartclk / 16 != ser->baud_base)
1645                 ret = -EINVAL;
1646         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1647                 ret = -EINVAL;
1648         if (sport->port.iobase != ser->port)
1649                 ret = -EINVAL;
1650         if (ser->hub6 != 0)
1651                 ret = -EINVAL;
1652         return ret;
1653 }
1654
1655 #if defined(CONFIG_CONSOLE_POLL)
1656
1657 static int imx_poll_init(struct uart_port *port)
1658 {
1659         struct imx_port *sport = (struct imx_port *)port;
1660         unsigned long flags;
1661         unsigned long temp;
1662         int retval;
1663
1664         retval = clk_prepare_enable(sport->clk_ipg);
1665         if (retval)
1666                 return retval;
1667         retval = clk_prepare_enable(sport->clk_per);
1668         if (retval)
1669                 clk_disable_unprepare(sport->clk_ipg);
1670
1671         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1672
1673         spin_lock_irqsave(&sport->port.lock, flags);
1674
1675         temp = readl(sport->port.membase + UCR1);
1676         if (is_imx1_uart(sport))
1677                 temp |= IMX1_UCR1_UARTCLKEN;
1678         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1679         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1680         writel(temp, sport->port.membase + UCR1);
1681
1682         temp = readl(sport->port.membase + UCR2);
1683         temp |= UCR2_RXEN;
1684         writel(temp, sport->port.membase + UCR2);
1685
1686         spin_unlock_irqrestore(&sport->port.lock, flags);
1687
1688         return 0;
1689 }
1690
1691 static int imx_poll_get_char(struct uart_port *port)
1692 {
1693         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1694                 return NO_POLL_CHAR;
1695
1696         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1697 }
1698
1699 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1700 {
1701         unsigned int status;
1702
1703         /* drain */
1704         do {
1705                 status = readl_relaxed(port->membase + USR1);
1706         } while (~status & USR1_TRDY);
1707
1708         /* write */
1709         writel_relaxed(c, port->membase + URTX0);
1710
1711         /* flush */
1712         do {
1713                 status = readl_relaxed(port->membase + USR2);
1714         } while (~status & USR2_TXDC);
1715 }
1716 #endif
1717
1718 static int imx_rs485_config(struct uart_port *port,
1719                             struct serial_rs485 *rs485conf)
1720 {
1721         struct imx_port *sport = (struct imx_port *)port;
1722         unsigned long temp;
1723
1724         /* unimplemented */
1725         rs485conf->delay_rts_before_send = 0;
1726         rs485conf->delay_rts_after_send = 0;
1727
1728         /* RTS is required to control the transmitter */
1729         if (!sport->have_rtscts && !sport->have_rtsgpio)
1730                 rs485conf->flags &= ~SER_RS485_ENABLED;
1731
1732         if (rs485conf->flags & SER_RS485_ENABLED) {
1733                 /* disable transmitter */
1734                 temp = readl(sport->port.membase + UCR2);
1735                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1736                         imx_port_rts_active(sport, &temp);
1737                 else
1738                         imx_port_rts_inactive(sport, &temp);
1739                 writel(temp, sport->port.membase + UCR2);
1740         }
1741
1742         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1743         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1744             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1745                 temp = readl(sport->port.membase + UCR2);
1746                 temp |= UCR2_RXEN;
1747                 writel(temp, sport->port.membase + UCR2);
1748         }
1749
1750         port->rs485 = *rs485conf;
1751
1752         return 0;
1753 }
1754
1755 static const struct uart_ops imx_pops = {
1756         .tx_empty       = imx_tx_empty,
1757         .set_mctrl      = imx_set_mctrl,
1758         .get_mctrl      = imx_get_mctrl,
1759         .stop_tx        = imx_stop_tx,
1760         .start_tx       = imx_start_tx,
1761         .stop_rx        = imx_stop_rx,
1762         .enable_ms      = imx_enable_ms,
1763         .break_ctl      = imx_break_ctl,
1764         .startup        = imx_startup,
1765         .shutdown       = imx_shutdown,
1766         .flush_buffer   = imx_flush_buffer,
1767         .set_termios    = imx_set_termios,
1768         .type           = imx_type,
1769         .config_port    = imx_config_port,
1770         .verify_port    = imx_verify_port,
1771 #if defined(CONFIG_CONSOLE_POLL)
1772         .poll_init      = imx_poll_init,
1773         .poll_get_char  = imx_poll_get_char,
1774         .poll_put_char  = imx_poll_put_char,
1775 #endif
1776 };
1777
1778 static struct imx_port *imx_ports[UART_NR];
1779
1780 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1781 static void imx_console_putchar(struct uart_port *port, int ch)
1782 {
1783         struct imx_port *sport = (struct imx_port *)port;
1784
1785         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1786                 barrier();
1787
1788         writel(ch, sport->port.membase + URTX0);
1789 }
1790
1791 /*
1792  * Interrupts are disabled on entering
1793  */
1794 static void
1795 imx_console_write(struct console *co, const char *s, unsigned int count)
1796 {
1797         struct imx_port *sport = imx_ports[co->index];
1798         struct imx_port_ucrs old_ucr;
1799         unsigned int ucr1;
1800         unsigned long flags = 0;
1801         int locked = 1;
1802         int retval;
1803
1804         retval = clk_enable(sport->clk_per);
1805         if (retval)
1806                 return;
1807         retval = clk_enable(sport->clk_ipg);
1808         if (retval) {
1809                 clk_disable(sport->clk_per);
1810                 return;
1811         }
1812
1813         if (sport->port.sysrq)
1814                 locked = 0;
1815         else if (oops_in_progress)
1816                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1817         else
1818                 spin_lock_irqsave(&sport->port.lock, flags);
1819
1820         /*
1821          *      First, save UCR1/2/3 and then disable interrupts
1822          */
1823         imx_port_ucrs_save(&sport->port, &old_ucr);
1824         ucr1 = old_ucr.ucr1;
1825
1826         if (is_imx1_uart(sport))
1827                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1828         ucr1 |= UCR1_UARTEN;
1829         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1830
1831         writel(ucr1, sport->port.membase + UCR1);
1832
1833         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1834
1835         uart_console_write(&sport->port, s, count, imx_console_putchar);
1836
1837         /*
1838          *      Finally, wait for transmitter to become empty
1839          *      and restore UCR1/2/3
1840          */
1841         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1842
1843         imx_port_ucrs_restore(&sport->port, &old_ucr);
1844
1845         if (locked)
1846                 spin_unlock_irqrestore(&sport->port.lock, flags);
1847
1848         clk_disable(sport->clk_ipg);
1849         clk_disable(sport->clk_per);
1850 }
1851
1852 /*
1853  * If the port was already initialised (eg, by a boot loader),
1854  * try to determine the current setup.
1855  */
1856 static void __init
1857 imx_console_get_options(struct imx_port *sport, int *baud,
1858                            int *parity, int *bits)
1859 {
1860
1861         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1862                 /* ok, the port was enabled */
1863                 unsigned int ucr2, ubir, ubmr, uartclk;
1864                 unsigned int baud_raw;
1865                 unsigned int ucfr_rfdiv;
1866
1867                 ucr2 = readl(sport->port.membase + UCR2);
1868
1869                 *parity = 'n';
1870                 if (ucr2 & UCR2_PREN) {
1871                         if (ucr2 & UCR2_PROE)
1872                                 *parity = 'o';
1873                         else
1874                                 *parity = 'e';
1875                 }
1876
1877                 if (ucr2 & UCR2_WS)
1878                         *bits = 8;
1879                 else
1880                         *bits = 7;
1881
1882                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1883                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1884
1885                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1886                 if (ucfr_rfdiv == 6)
1887                         ucfr_rfdiv = 7;
1888                 else
1889                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1890
1891                 uartclk = clk_get_rate(sport->clk_per);
1892                 uartclk /= ucfr_rfdiv;
1893
1894                 {       /*
1895                          * The next code provides exact computation of
1896                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1897                          * without need of float support or long long division,
1898                          * which would be required to prevent 32bit arithmetic overflow
1899                          */
1900                         unsigned int mul = ubir + 1;
1901                         unsigned int div = 16 * (ubmr + 1);
1902                         unsigned int rem = uartclk % div;
1903
1904                         baud_raw = (uartclk / div) * mul;
1905                         baud_raw += (rem * mul + div / 2) / div;
1906                         *baud = (baud_raw + 50) / 100 * 100;
1907                 }
1908
1909                 if (*baud != baud_raw)
1910                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1911                                 baud_raw, *baud);
1912         }
1913 }
1914
1915 static int __init
1916 imx_console_setup(struct console *co, char *options)
1917 {
1918         struct imx_port *sport;
1919         int baud = 9600;
1920         int bits = 8;
1921         int parity = 'n';
1922         int flow = 'n';
1923         int retval;
1924
1925         /*
1926          * Check whether an invalid uart number has been specified, and
1927          * if so, search for the first available port that does have
1928          * console support.
1929          */
1930         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1931                 co->index = 0;
1932         sport = imx_ports[co->index];
1933         if (sport == NULL)
1934                 return -ENODEV;
1935
1936         /* For setting the registers, we only need to enable the ipg clock. */
1937         retval = clk_prepare_enable(sport->clk_ipg);
1938         if (retval)
1939                 goto error_console;
1940
1941         if (options)
1942                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1943         else
1944                 imx_console_get_options(sport, &baud, &parity, &bits);
1945
1946         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1947
1948         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1949
1950         clk_disable(sport->clk_ipg);
1951         if (retval) {
1952                 clk_unprepare(sport->clk_ipg);
1953                 goto error_console;
1954         }
1955
1956         retval = clk_prepare(sport->clk_per);
1957         if (retval)
1958                 clk_disable_unprepare(sport->clk_ipg);
1959
1960 error_console:
1961         return retval;
1962 }
1963
1964 static struct uart_driver imx_reg;
1965 static struct console imx_console = {
1966         .name           = DEV_NAME,
1967         .write          = imx_console_write,
1968         .device         = uart_console_device,
1969         .setup          = imx_console_setup,
1970         .flags          = CON_PRINTBUFFER,
1971         .index          = -1,
1972         .data           = &imx_reg,
1973 };
1974
1975 #define IMX_CONSOLE     &imx_console
1976
1977 #ifdef CONFIG_OF
1978 static void imx_console_early_putchar(struct uart_port *port, int ch)
1979 {
1980         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1981                 cpu_relax();
1982
1983         writel_relaxed(ch, port->membase + URTX0);
1984 }
1985
1986 static void imx_console_early_write(struct console *con, const char *s,
1987                                     unsigned count)
1988 {
1989         struct earlycon_device *dev = con->data;
1990
1991         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1992 }
1993
1994 static int __init
1995 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1996 {
1997         if (!dev->port.membase)
1998                 return -ENODEV;
1999
2000         dev->con->write = imx_console_early_write;
2001
2002         return 0;
2003 }
2004 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2005 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2006 #endif
2007
2008 #else
2009 #define IMX_CONSOLE     NULL
2010 #endif
2011
2012 static struct uart_driver imx_reg = {
2013         .owner          = THIS_MODULE,
2014         .driver_name    = DRIVER_NAME,
2015         .dev_name       = DEV_NAME,
2016         .major          = SERIAL_IMX_MAJOR,
2017         .minor          = MINOR_START,
2018         .nr             = ARRAY_SIZE(imx_ports),
2019         .cons           = IMX_CONSOLE,
2020 };
2021
2022 #ifdef CONFIG_OF
2023 /*
2024  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2025  * could successfully get all information from dt or a negative errno.
2026  */
2027 static int serial_imx_probe_dt(struct imx_port *sport,
2028                 struct platform_device *pdev)
2029 {
2030         struct device_node *np = pdev->dev.of_node;
2031         int ret;
2032
2033         sport->devdata = of_device_get_match_data(&pdev->dev);
2034         if (!sport->devdata)
2035                 /* no device tree device */
2036                 return 1;
2037
2038         ret = of_alias_get_id(np, "serial");
2039         if (ret < 0) {
2040                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2041                 return ret;
2042         }
2043         sport->port.line = ret;
2044
2045         if (of_get_property(np, "uart-has-rtscts", NULL) ||
2046             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2047                 sport->have_rtscts = 1;
2048
2049         if (of_get_property(np, "fsl,dte-mode", NULL))
2050                 sport->dte_mode = 1;
2051
2052         if (of_get_property(np, "rts-gpios", NULL))
2053                 sport->have_rtsgpio = 1;
2054
2055         return 0;
2056 }
2057 #else
2058 static inline int serial_imx_probe_dt(struct imx_port *sport,
2059                 struct platform_device *pdev)
2060 {
2061         return 1;
2062 }
2063 #endif
2064
2065 static void serial_imx_probe_pdata(struct imx_port *sport,
2066                 struct platform_device *pdev)
2067 {
2068         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2069
2070         sport->port.line = pdev->id;
2071         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2072
2073         if (!pdata)
2074                 return;
2075
2076         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2077                 sport->have_rtscts = 1;
2078 }
2079
2080 static int serial_imx_probe(struct platform_device *pdev)
2081 {
2082         struct imx_port *sport;
2083         void __iomem *base;
2084         int ret = 0, reg;
2085         struct resource *res;
2086         int txirq, rxirq, rtsirq;
2087
2088         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2089         if (!sport)
2090                 return -ENOMEM;
2091
2092         ret = serial_imx_probe_dt(sport, pdev);
2093         if (ret > 0)
2094                 serial_imx_probe_pdata(sport, pdev);
2095         else if (ret < 0)
2096                 return ret;
2097
2098         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2099         base = devm_ioremap_resource(&pdev->dev, res);
2100         if (IS_ERR(base))
2101                 return PTR_ERR(base);
2102
2103         rxirq = platform_get_irq(pdev, 0);
2104         txirq = platform_get_irq(pdev, 1);
2105         rtsirq = platform_get_irq(pdev, 2);
2106
2107         sport->port.dev = &pdev->dev;
2108         sport->port.mapbase = res->start;
2109         sport->port.membase = base;
2110         sport->port.type = PORT_IMX,
2111         sport->port.iotype = UPIO_MEM;
2112         sport->port.irq = rxirq;
2113         sport->port.fifosize = 32;
2114         sport->port.ops = &imx_pops;
2115         sport->port.rs485_config = imx_rs485_config;
2116         sport->port.rs485.flags =
2117                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2118         sport->port.flags = UPF_BOOT_AUTOCONF;
2119         init_timer(&sport->timer);
2120         sport->timer.function = imx_timeout;
2121         sport->timer.data     = (unsigned long)sport;
2122
2123         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2124         if (IS_ERR(sport->gpios))
2125                 return PTR_ERR(sport->gpios);
2126
2127         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2128         if (IS_ERR(sport->clk_ipg)) {
2129                 ret = PTR_ERR(sport->clk_ipg);
2130                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2131                 return ret;
2132         }
2133
2134         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2135         if (IS_ERR(sport->clk_per)) {
2136                 ret = PTR_ERR(sport->clk_per);
2137                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2138                 return ret;
2139         }
2140
2141         sport->port.uartclk = clk_get_rate(sport->clk_per);
2142
2143         /* For register access, we only need to enable the ipg clock. */
2144         ret = clk_prepare_enable(sport->clk_ipg);
2145         if (ret) {
2146                 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2147                 return ret;
2148         }
2149
2150         /* Disable interrupts before requesting them */
2151         reg = readl_relaxed(sport->port.membase + UCR1);
2152         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2153                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2154         writel_relaxed(reg, sport->port.membase + UCR1);
2155
2156         clk_disable_unprepare(sport->clk_ipg);
2157
2158         /*
2159          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2160          * chips only have one interrupt.
2161          */
2162         if (txirq > 0) {
2163                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2164                                        dev_name(&pdev->dev), sport);
2165                 if (ret) {
2166                         dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2167                                 ret);
2168                         return ret;
2169                 }
2170
2171                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2172                                        dev_name(&pdev->dev), sport);
2173                 if (ret) {
2174                         dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2175                                 ret);
2176                         return ret;
2177                 }
2178         } else {
2179                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2180                                        dev_name(&pdev->dev), sport);
2181                 if (ret) {
2182                         dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2183                         return ret;
2184                 }
2185         }
2186
2187         imx_ports[sport->port.line] = sport;
2188
2189         platform_set_drvdata(pdev, sport);
2190
2191         return uart_add_one_port(&imx_reg, &sport->port);
2192 }
2193
2194 static int serial_imx_remove(struct platform_device *pdev)
2195 {
2196         struct imx_port *sport = platform_get_drvdata(pdev);
2197
2198         return uart_remove_one_port(&imx_reg, &sport->port);
2199 }
2200
2201 static void serial_imx_restore_context(struct imx_port *sport)
2202 {
2203         if (!sport->context_saved)
2204                 return;
2205
2206         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2207         writel(sport->saved_reg[5], sport->port.membase + UESC);
2208         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2209         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2210         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2211         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2212         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2213         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2214         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2215         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2216         sport->context_saved = false;
2217 }
2218
2219 static void serial_imx_save_context(struct imx_port *sport)
2220 {
2221         /* Save necessary regs */
2222         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2223         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2224         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2225         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2226         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2227         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2228         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2229         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2230         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2231         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2232         sport->context_saved = true;
2233 }
2234
2235 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2236 {
2237         unsigned int val;
2238
2239         val = readl(sport->port.membase + UCR3);
2240         if (on)
2241                 val |= UCR3_AWAKEN;
2242         else
2243                 val &= ~UCR3_AWAKEN;
2244         writel(val, sport->port.membase + UCR3);
2245
2246         val = readl(sport->port.membase + UCR1);
2247         if (on)
2248                 val |= UCR1_RTSDEN;
2249         else
2250                 val &= ~UCR1_RTSDEN;
2251         writel(val, sport->port.membase + UCR1);
2252 }
2253
2254 static int imx_serial_port_suspend_noirq(struct device *dev)
2255 {
2256         struct platform_device *pdev = to_platform_device(dev);
2257         struct imx_port *sport = platform_get_drvdata(pdev);
2258         int ret;
2259
2260         ret = clk_enable(sport->clk_ipg);
2261         if (ret)
2262                 return ret;
2263
2264         serial_imx_save_context(sport);
2265
2266         clk_disable(sport->clk_ipg);
2267
2268         return 0;
2269 }
2270
2271 static int imx_serial_port_resume_noirq(struct device *dev)
2272 {
2273         struct platform_device *pdev = to_platform_device(dev);
2274         struct imx_port *sport = platform_get_drvdata(pdev);
2275         int ret;
2276
2277         ret = clk_enable(sport->clk_ipg);
2278         if (ret)
2279                 return ret;
2280
2281         serial_imx_restore_context(sport);
2282
2283         clk_disable(sport->clk_ipg);
2284
2285         return 0;
2286 }
2287
2288 static int imx_serial_port_suspend(struct device *dev)
2289 {
2290         struct platform_device *pdev = to_platform_device(dev);
2291         struct imx_port *sport = platform_get_drvdata(pdev);
2292
2293         /* enable wakeup from i.MX UART */
2294         serial_imx_enable_wakeup(sport, true);
2295
2296         uart_suspend_port(&imx_reg, &sport->port);
2297
2298         /* Needed to enable clock in suspend_noirq */
2299         return clk_prepare(sport->clk_ipg);
2300 }
2301
2302 static int imx_serial_port_resume(struct device *dev)
2303 {
2304         struct platform_device *pdev = to_platform_device(dev);
2305         struct imx_port *sport = platform_get_drvdata(pdev);
2306
2307         /* disable wakeup from i.MX UART */
2308         serial_imx_enable_wakeup(sport, false);
2309
2310         uart_resume_port(&imx_reg, &sport->port);
2311
2312         clk_unprepare(sport->clk_ipg);
2313
2314         return 0;
2315 }
2316
2317 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2318         .suspend_noirq = imx_serial_port_suspend_noirq,
2319         .resume_noirq = imx_serial_port_resume_noirq,
2320         .suspend = imx_serial_port_suspend,
2321         .resume = imx_serial_port_resume,
2322 };
2323
2324 static struct platform_driver serial_imx_driver = {
2325         .probe          = serial_imx_probe,
2326         .remove         = serial_imx_remove,
2327
2328         .id_table       = imx_uart_devtype,
2329         .driver         = {
2330                 .name   = "imx-uart",
2331                 .of_match_table = imx_uart_dt_ids,
2332                 .pm     = &imx_serial_port_pm_ops,
2333         },
2334 };
2335
2336 static int __init imx_serial_init(void)
2337 {
2338         int ret = uart_register_driver(&imx_reg);
2339
2340         if (ret)
2341                 return ret;
2342
2343         ret = platform_driver_register(&serial_imx_driver);
2344         if (ret != 0)
2345                 uart_unregister_driver(&imx_reg);
2346
2347         return ret;
2348 }
2349
2350 static void __exit imx_serial_exit(void)
2351 {
2352         platform_driver_unregister(&serial_imx_driver);
2353         uart_unregister_driver(&imx_reg);
2354 }
2355
2356 module_init(imx_serial_init);
2357 module_exit(imx_serial_exit);
2358
2359 MODULE_AUTHOR("Sascha Hauer");
2360 MODULE_DESCRIPTION("IMX generic serial port driver");
2361 MODULE_LICENSE("GPL");
2362 MODULE_ALIAS("platform:imx-uart");