2 * Driver for Motorola IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
49 #include <linux/of_device.h>
51 #include <linux/dma-mapping.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
76 /* UART Control Register Bit Fields.*/
77 #define URXD_CHARRDY (1<<15)
78 #define URXD_ERR (1<<14)
79 #define URXD_OVRRUN (1<<13)
80 #define URXD_FRMERR (1<<12)
81 #define URXD_BRK (1<<11)
82 #define URXD_PRERR (1<<10)
83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90 #define UCR1_IREN (1<<7) /* Infrared interface enable */
91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93 #define UCR1_SNDBRK (1<<4) /* Send break */
94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
97 #define UCR1_DOZE (1<<1) /* Doze */
98 #define UCR1_UARTEN (1<<0) /* UART enabled */
99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101 #define UCR2_CTSC (1<<13) /* CTS pin control */
102 #define UCR2_CTS (1<<12) /* Clear to send */
103 #define UCR2_ESCEN (1<<11) /* Escape enable */
104 #define UCR2_PREN (1<<8) /* Parity enable */
105 #define UCR2_PROE (1<<7) /* Parity odd/even */
106 #define UCR2_STPB (1<<6) /* Stop */
107 #define UCR2_WS (1<<5) /* Word size */
108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
111 #define UCR2_RXEN (1<<1) /* Receiver enabled */
112 #define UCR2_SRST (1<<0) /* SW reset */
113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114 #define UCR3_PARERREN (1<<12) /* Parity enable */
115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116 #define UCR3_DSR (1<<10) /* Data set ready */
117 #define UCR3_DCD (1<<9) /* Data carrier detect */
118 #define UCR3_RI (1<<8) /* Ring indicator */
119 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125 #define UCR3_BPEN (1<<0) /* Preset registers enable */
126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
133 #define UCR4_IRSC (1<<5) /* IR special case */
134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144 #define USR1_RTSS (1<<14) /* RTS pin status */
145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146 #define USR1_RTSD (1<<12) /* RTS delta */
147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157 #define USR2_IDLE (1<<12) /* Idle condition */
158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159 #define USR2_WAKE (1<<7) /* Wake */
160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161 #define USR2_TXDC (1<<3) /* Transmitter complete */
162 #define USR2_BRCD (1<<2) /* Break condition */
163 #define USR2_ORE (1<<1) /* Overrun error */
164 #define USR2_RDR (1<<0) /* Recv data ready */
165 #define UTS_FRCPERR (1<<13) /* Force parity error */
166 #define UTS_LOOP (1<<12) /* Loop tx and rx */
167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169 #define UTS_TXFULL (1<<4) /* TxFIFO full */
170 #define UTS_RXFULL (1<<3) /* RxFIFO full */
171 #define UTS_SOFTRST (1<<0) /* Software reset */
173 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define SERIAL_IMX_MAJOR 207
175 #define MINOR_START 16
176 #define DEV_NAME "ttymxc"
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
184 #define MCTRL_TIMEOUT (250*HZ/1000)
186 #define DRIVER_NAME "IMX-uart"
190 /* i.mx21 type uart runs on all i.mx except i.mx1 */
197 /* device type dependent stuff */
198 struct imx_uart_data {
200 enum imx_uart_type devtype;
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
207 int txirq, rxirq, rtsirq;
208 unsigned int have_rtscts:1;
209 unsigned int dte_mode:1;
210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
216 const struct imx_uart_data *devdata;
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
226 unsigned int tx_bytes;
227 unsigned int dma_tx_nents;
228 wait_queue_head_t dma_wait;
231 struct imx_port_ucrs {
238 #define USE_IRDA(sport) ((sport)->use_irda)
240 #define USE_IRDA(sport) (0)
243 static struct imx_uart_data imx_uart_devdata[] = {
246 .devtype = IMX1_UART,
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
258 static struct platform_device_id imx_uart_devtype[] = {
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
274 static struct of_device_id imx_uart_dt_ids[] = {
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
282 static inline unsigned uts_reg(struct imx_port *sport)
284 return sport->devdata->uts_reg;
287 static inline int is_imx1_uart(struct imx_port *sport)
289 return sport->devdata->devtype == IMX1_UART;
292 static inline int is_imx21_uart(struct imx_port *sport)
294 return sport->devdata->devtype == IMX21_UART;
297 static inline int is_imx6q_uart(struct imx_port *sport)
299 return sport->devdata->devtype == IMX6Q_UART;
302 * Save and restore functions for UCR1, UCR2 and UCR3 registers
304 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
305 static void imx_port_ucrs_save(struct uart_port *port,
306 struct imx_port_ucrs *ucr)
308 /* save control registers */
309 ucr->ucr1 = readl(port->membase + UCR1);
310 ucr->ucr2 = readl(port->membase + UCR2);
311 ucr->ucr3 = readl(port->membase + UCR3);
314 static void imx_port_ucrs_restore(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
317 /* restore control registers */
318 writel(ucr->ucr1, port->membase + UCR1);
319 writel(ucr->ucr2, port->membase + UCR2);
320 writel(ucr->ucr3, port->membase + UCR3);
325 * Handle any change of modem status signal since we were last called.
327 static void imx_mctrl_check(struct imx_port *sport)
329 unsigned int status, changed;
331 status = sport->port.ops->get_mctrl(&sport->port);
332 changed = status ^ sport->old_status;
337 sport->old_status = status;
339 if (changed & TIOCM_RI)
340 sport->port.icount.rng++;
341 if (changed & TIOCM_DSR)
342 sport->port.icount.dsr++;
343 if (changed & TIOCM_CAR)
344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
345 if (changed & TIOCM_CTS)
346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
352 * This is our per-port timeout handler, for checking the
353 * modem status signals.
355 static void imx_timeout(unsigned long data)
357 struct imx_port *sport = (struct imx_port *)data;
360 if (sport->port.state) {
361 spin_lock_irqsave(&sport->port.lock, flags);
362 imx_mctrl_check(sport);
363 spin_unlock_irqrestore(&sport->port.lock, flags);
365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
370 * interrupts disabled on entry
372 static void imx_stop_tx(struct uart_port *port)
374 struct imx_port *sport = (struct imx_port *)port;
377 if (USE_IRDA(sport)) {
378 /* half duplex - wait for end of transmission */
381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
386 * irda transceiver - wait a bit more to avoid
387 * cutoff, hardware dependent
389 udelay(sport->trcv_delay);
392 * half duplex - reactivate receive mode,
393 * flush receive pipe echo crap
395 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
396 temp = readl(sport->port.membase + UCR1);
397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
398 writel(temp, sport->port.membase + UCR1);
400 temp = readl(sport->port.membase + UCR4);
401 temp &= ~(UCR4_TCEN);
402 writel(temp, sport->port.membase + UCR4);
404 while (readl(sport->port.membase + URXD0) &
408 temp = readl(sport->port.membase + UCR1);
410 writel(temp, sport->port.membase + UCR1);
412 temp = readl(sport->port.membase + UCR4);
414 writel(temp, sport->port.membase + UCR4);
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
423 if (sport->dma_is_enabled && sport->dma_is_txing)
426 temp = readl(sport->port.membase + UCR1);
427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
431 * interrupts disabled on entry
433 static void imx_stop_rx(struct uart_port *port)
435 struct imx_port *sport = (struct imx_port *)port;
439 * We are maybe in the SMP context, so if the DMA TX thread is running
440 * on other cpu, we have to wait for it to finish.
442 if (sport->dma_is_enabled && sport->dma_is_rxing)
445 temp = readl(sport->port.membase + UCR2);
446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
448 /* disable the `Receiver Ready Interrrupt` */
449 temp = readl(sport->port.membase + UCR1);
450 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
454 * Set the modem control timer to fire immediately.
456 static void imx_enable_ms(struct uart_port *port)
458 struct imx_port *sport = (struct imx_port *)port;
460 mod_timer(&sport->timer, jiffies);
463 static inline void imx_transmit_buffer(struct imx_port *sport)
465 struct circ_buf *xmit = &sport->port.state->xmit;
467 while (!uart_circ_empty(xmit) &&
468 !(readl(sport->port.membase + uts_reg(sport))
470 /* send xmit->buf[xmit->tail]
471 * out the port here */
472 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
473 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
474 sport->port.icount.tx++;
477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
478 uart_write_wakeup(&sport->port);
480 if (uart_circ_empty(xmit))
481 imx_stop_tx(&sport->port);
484 static void dma_tx_callback(void *data)
486 struct imx_port *sport = data;
487 struct scatterlist *sgl = &sport->tx_sgl[0];
488 struct circ_buf *xmit = &sport->port.state->xmit;
491 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
493 sport->dma_is_txing = 0;
495 /* update the stat */
496 spin_lock_irqsave(&sport->port.lock, flags);
497 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
498 sport->port.icount.tx += sport->tx_bytes;
499 spin_unlock_irqrestore(&sport->port.lock, flags);
501 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
503 uart_write_wakeup(&sport->port);
505 if (waitqueue_active(&sport->dma_wait)) {
506 wake_up(&sport->dma_wait);
507 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
512 static void imx_dma_tx(struct imx_port *sport)
514 struct circ_buf *xmit = &sport->port.state->xmit;
515 struct scatterlist *sgl = sport->tx_sgl;
516 struct dma_async_tx_descriptor *desc;
517 struct dma_chan *chan = sport->dma_chan_tx;
518 struct device *dev = sport->port.dev;
519 enum dma_status status;
522 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
523 if (DMA_IN_PROGRESS == status)
526 sport->tx_bytes = uart_circ_chars_pending(xmit);
528 if (xmit->tail > xmit->head && xmit->head > 0) {
529 sport->dma_tx_nents = 2;
530 sg_init_table(sgl, 2);
531 sg_set_buf(sgl, xmit->buf + xmit->tail,
532 UART_XMIT_SIZE - xmit->tail);
533 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
535 sport->dma_tx_nents = 1;
536 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
539 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
541 dev_err(dev, "DMA mapping error for TX.\n");
544 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
545 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
547 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
550 desc->callback = dma_tx_callback;
551 desc->callback_param = sport;
553 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
554 uart_circ_chars_pending(xmit));
556 sport->dma_is_txing = 1;
557 dmaengine_submit(desc);
558 dma_async_issue_pending(chan);
563 * interrupts disabled on entry
565 static void imx_start_tx(struct uart_port *port)
567 struct imx_port *sport = (struct imx_port *)port;
570 if (uart_circ_empty(&port->state->xmit))
573 if (USE_IRDA(sport)) {
574 /* half duplex in IrDA mode; have to disable receive mode */
575 temp = readl(sport->port.membase + UCR4);
576 temp &= ~(UCR4_DREN);
577 writel(temp, sport->port.membase + UCR4);
579 temp = readl(sport->port.membase + UCR1);
580 temp &= ~(UCR1_RRDYEN);
581 writel(temp, sport->port.membase + UCR1);
583 /* Clear any pending ORE flag before enabling interrupt */
584 temp = readl(sport->port.membase + USR2);
585 writel(temp | USR2_ORE, sport->port.membase + USR2);
587 temp = readl(sport->port.membase + UCR4);
589 writel(temp, sport->port.membase + UCR4);
591 if (!sport->dma_is_enabled) {
592 temp = readl(sport->port.membase + UCR1);
593 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
596 if (USE_IRDA(sport)) {
597 temp = readl(sport->port.membase + UCR1);
599 writel(temp, sport->port.membase + UCR1);
601 temp = readl(sport->port.membase + UCR4);
603 writel(temp, sport->port.membase + UCR4);
606 if (sport->dma_is_enabled) {
611 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
612 imx_transmit_buffer(sport);
615 static irqreturn_t imx_rtsint(int irq, void *dev_id)
617 struct imx_port *sport = dev_id;
621 spin_lock_irqsave(&sport->port.lock, flags);
623 writel(USR1_RTSD, sport->port.membase + USR1);
624 val = readl(sport->port.membase + USR1) & USR1_RTSS;
625 uart_handle_cts_change(&sport->port, !!val);
626 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
628 spin_unlock_irqrestore(&sport->port.lock, flags);
632 static irqreturn_t imx_txint(int irq, void *dev_id)
634 struct imx_port *sport = dev_id;
635 struct circ_buf *xmit = &sport->port.state->xmit;
638 spin_lock_irqsave(&sport->port.lock, flags);
639 if (sport->port.x_char) {
641 writel(sport->port.x_char, sport->port.membase + URTX0);
645 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
646 imx_stop_tx(&sport->port);
650 imx_transmit_buffer(sport);
652 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
653 uart_write_wakeup(&sport->port);
656 spin_unlock_irqrestore(&sport->port.lock, flags);
660 static irqreturn_t imx_rxint(int irq, void *dev_id)
662 struct imx_port *sport = dev_id;
663 unsigned int rx, flg, ignored = 0;
664 struct tty_port *port = &sport->port.state->port;
665 unsigned long flags, temp;
667 spin_lock_irqsave(&sport->port.lock, flags);
669 while (readl(sport->port.membase + USR2) & USR2_RDR) {
671 sport->port.icount.rx++;
673 rx = readl(sport->port.membase + URXD0);
675 temp = readl(sport->port.membase + USR2);
676 if (temp & USR2_BRCD) {
677 writel(USR2_BRCD, sport->port.membase + USR2);
678 if (uart_handle_break(&sport->port))
682 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
685 if (unlikely(rx & URXD_ERR)) {
687 sport->port.icount.brk++;
688 else if (rx & URXD_PRERR)
689 sport->port.icount.parity++;
690 else if (rx & URXD_FRMERR)
691 sport->port.icount.frame++;
692 if (rx & URXD_OVRRUN)
693 sport->port.icount.overrun++;
695 if (rx & sport->port.ignore_status_mask) {
701 rx &= sport->port.read_status_mask;
705 else if (rx & URXD_PRERR)
707 else if (rx & URXD_FRMERR)
709 if (rx & URXD_OVRRUN)
713 sport->port.sysrq = 0;
717 tty_insert_flip_char(port, rx, flg);
721 spin_unlock_irqrestore(&sport->port.lock, flags);
722 tty_flip_buffer_push(port);
726 static int start_rx_dma(struct imx_port *sport);
728 * If the RXFIFO is filled with some data, and then we
729 * arise a DMA operation to receive them.
731 static void imx_dma_rxint(struct imx_port *sport)
735 temp = readl(sport->port.membase + USR2);
736 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
737 sport->dma_is_rxing = 1;
739 /* disable the `Recerver Ready Interrrupt` */
740 temp = readl(sport->port.membase + UCR1);
741 temp &= ~(UCR1_RRDYEN);
742 writel(temp, sport->port.membase + UCR1);
744 /* tell the DMA to receive the data. */
749 static irqreturn_t imx_int(int irq, void *dev_id)
751 struct imx_port *sport = dev_id;
755 sts = readl(sport->port.membase + USR1);
757 if (sts & USR1_RRDY) {
758 if (sport->dma_is_enabled)
759 imx_dma_rxint(sport);
761 imx_rxint(irq, dev_id);
764 if (sts & USR1_TRDY &&
765 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
766 imx_txint(irq, dev_id);
769 imx_rtsint(irq, dev_id);
771 if (sts & USR1_AWAKE)
772 writel(USR1_AWAKE, sport->port.membase + USR1);
774 sts2 = readl(sport->port.membase + USR2);
775 if (sts2 & USR2_ORE) {
776 dev_err(sport->port.dev, "Rx FIFO overrun\n");
777 sport->port.icount.overrun++;
778 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
785 * Return TIOCSER_TEMT when transmitter is not busy.
787 static unsigned int imx_tx_empty(struct uart_port *port)
789 struct imx_port *sport = (struct imx_port *)port;
792 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
794 /* If the TX DMA is working, return 0. */
795 if (sport->dma_is_enabled && sport->dma_is_txing)
802 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
804 static unsigned int imx_get_mctrl(struct uart_port *port)
806 struct imx_port *sport = (struct imx_port *)port;
807 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
809 if (readl(sport->port.membase + USR1) & USR1_RTSS)
812 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
815 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
821 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
823 struct imx_port *sport = (struct imx_port *)port;
826 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
828 if (mctrl & TIOCM_RTS)
829 if (!sport->dma_is_enabled)
832 writel(temp, sport->port.membase + UCR2);
834 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
835 if (mctrl & TIOCM_LOOP)
837 writel(temp, sport->port.membase + uts_reg(sport));
841 * Interrupts always disabled.
843 static void imx_break_ctl(struct uart_port *port, int break_state)
845 struct imx_port *sport = (struct imx_port *)port;
846 unsigned long flags, temp;
848 spin_lock_irqsave(&sport->port.lock, flags);
850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
852 if (break_state != 0)
855 writel(temp, sport->port.membase + UCR1);
857 spin_unlock_irqrestore(&sport->port.lock, flags);
860 #define TXTL 2 /* reset default */
861 #define RXTL 1 /* reset default */
863 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
867 /* set receiver / transmitter trigger level */
868 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
869 val |= TXTL << UFCR_TXTL_SHF | RXTL;
870 writel(val, sport->port.membase + UFCR);
874 #define RX_BUF_SIZE (PAGE_SIZE)
875 static void imx_rx_dma_done(struct imx_port *sport)
879 /* Enable this interrupt when the RXFIFO is empty. */
880 temp = readl(sport->port.membase + UCR1);
882 writel(temp, sport->port.membase + UCR1);
884 sport->dma_is_rxing = 0;
886 /* Is the shutdown waiting for us? */
887 if (waitqueue_active(&sport->dma_wait))
888 wake_up(&sport->dma_wait);
892 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
893 * [1] the RX DMA buffer is full.
894 * [2] the Aging timer expires(wait for 8 bytes long)
895 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
897 * The [2] is trigger when a character was been sitting in the FIFO
898 * meanwhile [3] can wait for 32 bytes long when the RX line is
899 * on IDLE state and RxFIFO is empty.
901 static void dma_rx_callback(void *data)
903 struct imx_port *sport = data;
904 struct dma_chan *chan = sport->dma_chan_rx;
905 struct scatterlist *sgl = &sport->rx_sgl;
906 struct tty_port *port = &sport->port.state->port;
907 struct dma_tx_state state;
908 enum dma_status status;
912 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
914 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
915 count = RX_BUF_SIZE - state.residue;
916 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
919 tty_insert_flip_string(port, sport->rx_buf, count);
920 tty_flip_buffer_push(port);
924 imx_rx_dma_done(sport);
927 static int start_rx_dma(struct imx_port *sport)
929 struct scatterlist *sgl = &sport->rx_sgl;
930 struct dma_chan *chan = sport->dma_chan_rx;
931 struct device *dev = sport->port.dev;
932 struct dma_async_tx_descriptor *desc;
935 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
936 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
938 dev_err(dev, "DMA mapping error for RX.\n");
941 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
944 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
947 desc->callback = dma_rx_callback;
948 desc->callback_param = sport;
950 dev_dbg(dev, "RX: prepare for the DMA.\n");
951 dmaengine_submit(desc);
952 dma_async_issue_pending(chan);
956 static void imx_uart_dma_exit(struct imx_port *sport)
958 if (sport->dma_chan_rx) {
959 dma_release_channel(sport->dma_chan_rx);
960 sport->dma_chan_rx = NULL;
962 kfree(sport->rx_buf);
963 sport->rx_buf = NULL;
966 if (sport->dma_chan_tx) {
967 dma_release_channel(sport->dma_chan_tx);
968 sport->dma_chan_tx = NULL;
971 sport->dma_is_inited = 0;
974 static int imx_uart_dma_init(struct imx_port *sport)
976 struct dma_slave_config slave_config = {};
977 struct device *dev = sport->port.dev;
980 /* Prepare for RX : */
981 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
982 if (!sport->dma_chan_rx) {
983 dev_dbg(dev, "cannot get the DMA channel.\n");
988 slave_config.direction = DMA_DEV_TO_MEM;
989 slave_config.src_addr = sport->port.mapbase + URXD0;
990 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
991 slave_config.src_maxburst = RXTL;
992 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
994 dev_err(dev, "error in RX dma configuration.\n");
998 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
999 if (!sport->rx_buf) {
1000 dev_err(dev, "cannot alloc DMA buffer.\n");
1005 /* Prepare for TX : */
1006 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1007 if (!sport->dma_chan_tx) {
1008 dev_err(dev, "cannot get the TX DMA channel!\n");
1013 slave_config.direction = DMA_MEM_TO_DEV;
1014 slave_config.dst_addr = sport->port.mapbase + URTX0;
1015 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1016 slave_config.dst_maxburst = TXTL;
1017 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1019 dev_err(dev, "error in TX dma configuration.");
1023 sport->dma_is_inited = 1;
1027 imx_uart_dma_exit(sport);
1031 static void imx_enable_dma(struct imx_port *sport)
1035 init_waitqueue_head(&sport->dma_wait);
1038 temp = readl(sport->port.membase + UCR1);
1039 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1040 /* wait for 32 idle frames for IDDMA interrupt */
1042 writel(temp, sport->port.membase + UCR1);
1045 temp = readl(sport->port.membase + UCR4);
1046 temp |= UCR4_IDDMAEN;
1047 writel(temp, sport->port.membase + UCR4);
1049 sport->dma_is_enabled = 1;
1052 static void imx_disable_dma(struct imx_port *sport)
1057 temp = readl(sport->port.membase + UCR1);
1058 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1059 writel(temp, sport->port.membase + UCR1);
1062 temp = readl(sport->port.membase + UCR2);
1063 temp &= ~(UCR2_CTSC | UCR2_CTS);
1064 writel(temp, sport->port.membase + UCR2);
1067 temp = readl(sport->port.membase + UCR4);
1068 temp &= ~UCR4_IDDMAEN;
1069 writel(temp, sport->port.membase + UCR4);
1071 sport->dma_is_enabled = 0;
1074 /* half the RX buffer size */
1077 static int imx_startup(struct uart_port *port)
1079 struct imx_port *sport = (struct imx_port *)port;
1081 unsigned long flags, temp;
1083 retval = clk_prepare_enable(sport->clk_per);
1086 retval = clk_prepare_enable(sport->clk_ipg);
1088 clk_disable_unprepare(sport->clk_per);
1092 imx_setup_ufcr(sport, 0);
1094 /* disable the DREN bit (Data Ready interrupt enable) before
1097 temp = readl(sport->port.membase + UCR4);
1099 if (USE_IRDA(sport))
1102 /* set the trigger level for CTS */
1103 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1104 temp |= CTSTL << UCR4_CTSTL_SHF;
1106 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1108 /* Reset fifo's and state machines */
1111 temp = readl(sport->port.membase + UCR2);
1113 writel(temp, sport->port.membase + UCR2);
1115 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1119 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1120 * chips only have one interrupt.
1122 if (sport->txirq > 0) {
1123 retval = request_irq(sport->rxirq, imx_rxint, 0,
1124 dev_name(port->dev), sport);
1128 retval = request_irq(sport->txirq, imx_txint, 0,
1129 dev_name(port->dev), sport);
1133 /* do not use RTS IRQ on IrDA */
1134 if (!USE_IRDA(sport)) {
1135 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
1136 dev_name(port->dev), sport);
1141 retval = request_irq(sport->port.irq, imx_int, 0,
1142 dev_name(port->dev), sport);
1144 free_irq(sport->port.irq, sport);
1149 spin_lock_irqsave(&sport->port.lock, flags);
1151 * Finally, clear and enable interrupts
1153 writel(USR1_RTSD, sport->port.membase + USR1);
1155 temp = readl(sport->port.membase + UCR1);
1156 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1158 if (USE_IRDA(sport)) {
1160 temp &= ~(UCR1_RTSDEN);
1163 writel(temp, sport->port.membase + UCR1);
1165 temp = readl(sport->port.membase + UCR2);
1166 temp |= (UCR2_RXEN | UCR2_TXEN);
1167 if (!sport->have_rtscts)
1169 writel(temp, sport->port.membase + UCR2);
1171 if (!is_imx1_uart(sport)) {
1172 temp = readl(sport->port.membase + UCR3);
1173 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1174 writel(temp, sport->port.membase + UCR3);
1177 if (USE_IRDA(sport)) {
1178 temp = readl(sport->port.membase + UCR4);
1179 if (sport->irda_inv_rx)
1182 temp &= ~(UCR4_INVR);
1183 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1185 temp = readl(sport->port.membase + UCR3);
1186 if (sport->irda_inv_tx)
1189 temp &= ~(UCR3_INVT);
1190 writel(temp, sport->port.membase + UCR3);
1194 * Enable modem status interrupts
1196 imx_enable_ms(&sport->port);
1197 spin_unlock_irqrestore(&sport->port.lock, flags);
1199 if (USE_IRDA(sport)) {
1200 struct imxuart_platform_data *pdata;
1201 pdata = dev_get_platdata(sport->port.dev);
1202 sport->irda_inv_rx = pdata->irda_inv_rx;
1203 sport->irda_inv_tx = pdata->irda_inv_tx;
1204 sport->trcv_delay = pdata->transceiver_delay;
1205 if (pdata->irda_enable)
1206 pdata->irda_enable(1);
1213 free_irq(sport->txirq, sport);
1216 free_irq(sport->rxirq, sport);
1221 static void imx_shutdown(struct uart_port *port)
1223 struct imx_port *sport = (struct imx_port *)port;
1225 unsigned long flags;
1227 if (sport->dma_is_enabled) {
1228 /* We have to wait for the DMA to finish. */
1229 wait_event(sport->dma_wait,
1230 !sport->dma_is_rxing && !sport->dma_is_txing);
1232 imx_disable_dma(sport);
1233 imx_uart_dma_exit(sport);
1236 spin_lock_irqsave(&sport->port.lock, flags);
1237 temp = readl(sport->port.membase + UCR2);
1238 temp &= ~(UCR2_TXEN);
1239 writel(temp, sport->port.membase + UCR2);
1240 spin_unlock_irqrestore(&sport->port.lock, flags);
1242 if (USE_IRDA(sport)) {
1243 struct imxuart_platform_data *pdata;
1244 pdata = dev_get_platdata(sport->port.dev);
1245 if (pdata->irda_enable)
1246 pdata->irda_enable(0);
1252 del_timer_sync(&sport->timer);
1255 * Free the interrupts
1257 if (sport->txirq > 0) {
1258 if (!USE_IRDA(sport))
1259 free_irq(sport->rtsirq, sport);
1260 free_irq(sport->txirq, sport);
1261 free_irq(sport->rxirq, sport);
1263 free_irq(sport->port.irq, sport);
1266 * Disable all interrupts, port and break condition.
1269 spin_lock_irqsave(&sport->port.lock, flags);
1270 temp = readl(sport->port.membase + UCR1);
1271 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1272 if (USE_IRDA(sport))
1273 temp &= ~(UCR1_IREN);
1275 writel(temp, sport->port.membase + UCR1);
1276 spin_unlock_irqrestore(&sport->port.lock, flags);
1278 clk_disable_unprepare(sport->clk_per);
1279 clk_disable_unprepare(sport->clk_ipg);
1282 static void imx_flush_buffer(struct uart_port *port)
1284 struct imx_port *sport = (struct imx_port *)port;
1286 if (sport->dma_is_enabled) {
1287 sport->tx_bytes = 0;
1288 dmaengine_terminate_all(sport->dma_chan_tx);
1293 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1294 struct ktermios *old)
1296 struct imx_port *sport = (struct imx_port *)port;
1297 unsigned long flags;
1298 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1299 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1300 unsigned int div, ufcr;
1301 unsigned long num, denom;
1305 * If we don't support modem control lines, don't allow
1309 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1310 termios->c_cflag |= CLOCAL;
1314 * We only support CS7 and CS8.
1316 while ((termios->c_cflag & CSIZE) != CS7 &&
1317 (termios->c_cflag & CSIZE) != CS8) {
1318 termios->c_cflag &= ~CSIZE;
1319 termios->c_cflag |= old_csize;
1323 if ((termios->c_cflag & CSIZE) == CS8)
1324 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1326 ucr2 = UCR2_SRST | UCR2_IRTS;
1328 if (termios->c_cflag & CRTSCTS) {
1329 if (sport->have_rtscts) {
1333 /* Can we enable the DMA support? */
1334 if (is_imx6q_uart(sport) && !uart_console(port)
1335 && !sport->dma_is_inited)
1336 imx_uart_dma_init(sport);
1338 termios->c_cflag &= ~CRTSCTS;
1342 if (termios->c_cflag & CSTOPB)
1344 if (termios->c_cflag & PARENB) {
1346 if (termios->c_cflag & PARODD)
1350 del_timer_sync(&sport->timer);
1353 * Ask the core to calculate the divisor for us.
1355 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1356 quot = uart_get_divisor(port, baud);
1358 spin_lock_irqsave(&sport->port.lock, flags);
1360 sport->port.read_status_mask = 0;
1361 if (termios->c_iflag & INPCK)
1362 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1363 if (termios->c_iflag & (BRKINT | PARMRK))
1364 sport->port.read_status_mask |= URXD_BRK;
1367 * Characters to ignore
1369 sport->port.ignore_status_mask = 0;
1370 if (termios->c_iflag & IGNPAR)
1371 sport->port.ignore_status_mask |= URXD_PRERR;
1372 if (termios->c_iflag & IGNBRK) {
1373 sport->port.ignore_status_mask |= URXD_BRK;
1375 * If we're ignoring parity and break indicators,
1376 * ignore overruns too (for real raw support).
1378 if (termios->c_iflag & IGNPAR)
1379 sport->port.ignore_status_mask |= URXD_OVRRUN;
1383 * Update the per-port timeout.
1385 uart_update_timeout(port, termios->c_cflag, baud);
1388 * disable interrupts and drain transmitter
1390 old_ucr1 = readl(sport->port.membase + UCR1);
1391 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1392 sport->port.membase + UCR1);
1394 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1397 /* then, disable everything */
1398 old_txrxen = readl(sport->port.membase + UCR2);
1399 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1400 sport->port.membase + UCR2);
1401 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1403 if (USE_IRDA(sport)) {
1405 * use maximum available submodule frequency to
1406 * avoid missing short pulses due to low sampling rate
1410 /* custom-baudrate handling */
1411 div = sport->port.uartclk / (baud * 16);
1412 if (baud == 38400 && quot != div)
1413 baud = sport->port.uartclk / (quot * 16);
1415 div = sport->port.uartclk / (baud * 16);
1422 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1423 1 << 16, 1 << 16, &num, &denom);
1425 tdiv64 = sport->port.uartclk;
1427 do_div(tdiv64, denom * 16 * div);
1428 tty_termios_encode_baud_rate(termios,
1429 (speed_t)tdiv64, (speed_t)tdiv64);
1434 ufcr = readl(sport->port.membase + UFCR);
1435 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1436 if (sport->dte_mode)
1437 ufcr |= UFCR_DCEDTE;
1438 writel(ufcr, sport->port.membase + UFCR);
1440 writel(num, sport->port.membase + UBIR);
1441 writel(denom, sport->port.membase + UBMR);
1443 if (!is_imx1_uart(sport))
1444 writel(sport->port.uartclk / div / 1000,
1445 sport->port.membase + IMX21_ONEMS);
1447 writel(old_ucr1, sport->port.membase + UCR1);
1449 /* set the parity, stop bits and data size */
1450 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1452 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1453 imx_enable_ms(&sport->port);
1455 if (sport->dma_is_inited && !sport->dma_is_enabled)
1456 imx_enable_dma(sport);
1457 spin_unlock_irqrestore(&sport->port.lock, flags);
1460 static const char *imx_type(struct uart_port *port)
1462 struct imx_port *sport = (struct imx_port *)port;
1464 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1468 * Configure/autoconfigure the port.
1470 static void imx_config_port(struct uart_port *port, int flags)
1472 struct imx_port *sport = (struct imx_port *)port;
1474 if (flags & UART_CONFIG_TYPE)
1475 sport->port.type = PORT_IMX;
1479 * Verify the new serial_struct (for TIOCSSERIAL).
1480 * The only change we allow are to the flags and type, and
1481 * even then only between PORT_IMX and PORT_UNKNOWN
1484 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1486 struct imx_port *sport = (struct imx_port *)port;
1489 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1491 if (sport->port.irq != ser->irq)
1493 if (ser->io_type != UPIO_MEM)
1495 if (sport->port.uartclk / 16 != ser->baud_base)
1497 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1499 if (sport->port.iobase != ser->port)
1506 #if defined(CONFIG_CONSOLE_POLL)
1507 static int imx_poll_get_char(struct uart_port *port)
1509 struct imx_port_ucrs old_ucr;
1510 unsigned int status;
1513 /* save control registers */
1514 imx_port_ucrs_save(port, &old_ucr);
1516 /* disable interrupts */
1517 writel(UCR1_UARTEN, port->membase + UCR1);
1518 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1519 port->membase + UCR2);
1520 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1521 port->membase + UCR3);
1525 status = readl(port->membase + USR2);
1526 } while (~status & USR2_RDR);
1529 c = readl(port->membase + URXD0);
1531 /* restore control registers */
1532 imx_port_ucrs_restore(port, &old_ucr);
1537 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1539 struct imx_port_ucrs old_ucr;
1540 unsigned int status;
1542 /* save control registers */
1543 imx_port_ucrs_save(port, &old_ucr);
1545 /* disable interrupts */
1546 writel(UCR1_UARTEN, port->membase + UCR1);
1547 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1548 port->membase + UCR2);
1549 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1550 port->membase + UCR3);
1554 status = readl(port->membase + USR1);
1555 } while (~status & USR1_TRDY);
1558 writel(c, port->membase + URTX0);
1562 status = readl(port->membase + USR2);
1563 } while (~status & USR2_TXDC);
1565 /* restore control registers */
1566 imx_port_ucrs_restore(port, &old_ucr);
1570 static struct uart_ops imx_pops = {
1571 .tx_empty = imx_tx_empty,
1572 .set_mctrl = imx_set_mctrl,
1573 .get_mctrl = imx_get_mctrl,
1574 .stop_tx = imx_stop_tx,
1575 .start_tx = imx_start_tx,
1576 .stop_rx = imx_stop_rx,
1577 .enable_ms = imx_enable_ms,
1578 .break_ctl = imx_break_ctl,
1579 .startup = imx_startup,
1580 .shutdown = imx_shutdown,
1581 .flush_buffer = imx_flush_buffer,
1582 .set_termios = imx_set_termios,
1584 .config_port = imx_config_port,
1585 .verify_port = imx_verify_port,
1586 #if defined(CONFIG_CONSOLE_POLL)
1587 .poll_get_char = imx_poll_get_char,
1588 .poll_put_char = imx_poll_put_char,
1592 static struct imx_port *imx_ports[UART_NR];
1594 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1595 static void imx_console_putchar(struct uart_port *port, int ch)
1597 struct imx_port *sport = (struct imx_port *)port;
1599 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1602 writel(ch, sport->port.membase + URTX0);
1606 * Interrupts are disabled on entering
1609 imx_console_write(struct console *co, const char *s, unsigned int count)
1611 struct imx_port *sport = imx_ports[co->index];
1612 struct imx_port_ucrs old_ucr;
1614 unsigned long flags = 0;
1618 retval = clk_enable(sport->clk_per);
1621 retval = clk_enable(sport->clk_ipg);
1623 clk_disable(sport->clk_per);
1627 if (sport->port.sysrq)
1629 else if (oops_in_progress)
1630 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1632 spin_lock_irqsave(&sport->port.lock, flags);
1635 * First, save UCR1/2/3 and then disable interrupts
1637 imx_port_ucrs_save(&sport->port, &old_ucr);
1638 ucr1 = old_ucr.ucr1;
1640 if (is_imx1_uart(sport))
1641 ucr1 |= IMX1_UCR1_UARTCLKEN;
1642 ucr1 |= UCR1_UARTEN;
1643 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1645 writel(ucr1, sport->port.membase + UCR1);
1647 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1649 uart_console_write(&sport->port, s, count, imx_console_putchar);
1652 * Finally, wait for transmitter to become empty
1653 * and restore UCR1/2/3
1655 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1657 imx_port_ucrs_restore(&sport->port, &old_ucr);
1660 spin_unlock_irqrestore(&sport->port.lock, flags);
1662 clk_disable(sport->clk_ipg);
1663 clk_disable(sport->clk_per);
1667 * If the port was already initialised (eg, by a boot loader),
1668 * try to determine the current setup.
1671 imx_console_get_options(struct imx_port *sport, int *baud,
1672 int *parity, int *bits)
1675 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1676 /* ok, the port was enabled */
1677 unsigned int ucr2, ubir, ubmr, uartclk;
1678 unsigned int baud_raw;
1679 unsigned int ucfr_rfdiv;
1681 ucr2 = readl(sport->port.membase + UCR2);
1684 if (ucr2 & UCR2_PREN) {
1685 if (ucr2 & UCR2_PROE)
1696 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1697 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1699 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1700 if (ucfr_rfdiv == 6)
1703 ucfr_rfdiv = 6 - ucfr_rfdiv;
1705 uartclk = clk_get_rate(sport->clk_per);
1706 uartclk /= ucfr_rfdiv;
1709 * The next code provides exact computation of
1710 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1711 * without need of float support or long long division,
1712 * which would be required to prevent 32bit arithmetic overflow
1714 unsigned int mul = ubir + 1;
1715 unsigned int div = 16 * (ubmr + 1);
1716 unsigned int rem = uartclk % div;
1718 baud_raw = (uartclk / div) * mul;
1719 baud_raw += (rem * mul + div / 2) / div;
1720 *baud = (baud_raw + 50) / 100 * 100;
1723 if (*baud != baud_raw)
1724 pr_info("Console IMX rounded baud rate from %d to %d\n",
1730 imx_console_setup(struct console *co, char *options)
1732 struct imx_port *sport;
1740 * Check whether an invalid uart number has been specified, and
1741 * if so, search for the first available port that does have
1744 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1746 sport = imx_ports[co->index];
1750 /* For setting the registers, we only need to enable the ipg clock. */
1751 retval = clk_prepare_enable(sport->clk_ipg);
1756 uart_parse_options(options, &baud, &parity, &bits, &flow);
1758 imx_console_get_options(sport, &baud, &parity, &bits);
1760 imx_setup_ufcr(sport, 0);
1762 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1764 clk_disable(sport->clk_ipg);
1766 clk_unprepare(sport->clk_ipg);
1770 retval = clk_prepare(sport->clk_per);
1772 clk_disable_unprepare(sport->clk_ipg);
1778 static struct uart_driver imx_reg;
1779 static struct console imx_console = {
1781 .write = imx_console_write,
1782 .device = uart_console_device,
1783 .setup = imx_console_setup,
1784 .flags = CON_PRINTBUFFER,
1789 #define IMX_CONSOLE &imx_console
1791 #define IMX_CONSOLE NULL
1794 static struct uart_driver imx_reg = {
1795 .owner = THIS_MODULE,
1796 .driver_name = DRIVER_NAME,
1797 .dev_name = DEV_NAME,
1798 .major = SERIAL_IMX_MAJOR,
1799 .minor = MINOR_START,
1800 .nr = ARRAY_SIZE(imx_ports),
1801 .cons = IMX_CONSOLE,
1804 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1806 struct imx_port *sport = platform_get_drvdata(dev);
1809 /* enable wakeup from i.MX UART */
1810 val = readl(sport->port.membase + UCR3);
1812 writel(val, sport->port.membase + UCR3);
1814 uart_suspend_port(&imx_reg, &sport->port);
1819 static int serial_imx_resume(struct platform_device *dev)
1821 struct imx_port *sport = platform_get_drvdata(dev);
1824 /* disable wakeup from i.MX UART */
1825 val = readl(sport->port.membase + UCR3);
1826 val &= ~UCR3_AWAKEN;
1827 writel(val, sport->port.membase + UCR3);
1829 uart_resume_port(&imx_reg, &sport->port);
1836 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1837 * could successfully get all information from dt or a negative errno.
1839 static int serial_imx_probe_dt(struct imx_port *sport,
1840 struct platform_device *pdev)
1842 struct device_node *np = pdev->dev.of_node;
1843 const struct of_device_id *of_id =
1844 of_match_device(imx_uart_dt_ids, &pdev->dev);
1848 /* no device tree device */
1851 ret = of_alias_get_id(np, "serial");
1853 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1856 sport->port.line = ret;
1858 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1859 sport->have_rtscts = 1;
1861 if (of_get_property(np, "fsl,irda-mode", NULL))
1862 sport->use_irda = 1;
1864 if (of_get_property(np, "fsl,dte-mode", NULL))
1865 sport->dte_mode = 1;
1867 sport->devdata = of_id->data;
1872 static inline int serial_imx_probe_dt(struct imx_port *sport,
1873 struct platform_device *pdev)
1879 static void serial_imx_probe_pdata(struct imx_port *sport,
1880 struct platform_device *pdev)
1882 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1884 sport->port.line = pdev->id;
1885 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1890 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1891 sport->have_rtscts = 1;
1893 if (pdata->flags & IMXUART_IRDA)
1894 sport->use_irda = 1;
1897 static int serial_imx_probe(struct platform_device *pdev)
1899 struct imx_port *sport;
1902 struct resource *res;
1904 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1908 ret = serial_imx_probe_dt(sport, pdev);
1910 serial_imx_probe_pdata(sport, pdev);
1914 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1915 base = devm_ioremap_resource(&pdev->dev, res);
1917 return PTR_ERR(base);
1919 sport->port.dev = &pdev->dev;
1920 sport->port.mapbase = res->start;
1921 sport->port.membase = base;
1922 sport->port.type = PORT_IMX,
1923 sport->port.iotype = UPIO_MEM;
1924 sport->port.irq = platform_get_irq(pdev, 0);
1925 sport->rxirq = platform_get_irq(pdev, 0);
1926 sport->txirq = platform_get_irq(pdev, 1);
1927 sport->rtsirq = platform_get_irq(pdev, 2);
1928 sport->port.fifosize = 32;
1929 sport->port.ops = &imx_pops;
1930 sport->port.flags = UPF_BOOT_AUTOCONF;
1931 init_timer(&sport->timer);
1932 sport->timer.function = imx_timeout;
1933 sport->timer.data = (unsigned long)sport;
1935 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1936 if (IS_ERR(sport->clk_ipg)) {
1937 ret = PTR_ERR(sport->clk_ipg);
1938 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1942 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1943 if (IS_ERR(sport->clk_per)) {
1944 ret = PTR_ERR(sport->clk_per);
1945 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1949 sport->port.uartclk = clk_get_rate(sport->clk_per);
1951 imx_ports[sport->port.line] = sport;
1953 platform_set_drvdata(pdev, sport);
1955 return uart_add_one_port(&imx_reg, &sport->port);
1958 static int serial_imx_remove(struct platform_device *pdev)
1960 struct imx_port *sport = platform_get_drvdata(pdev);
1962 return uart_remove_one_port(&imx_reg, &sport->port);
1965 static struct platform_driver serial_imx_driver = {
1966 .probe = serial_imx_probe,
1967 .remove = serial_imx_remove,
1969 .suspend = serial_imx_suspend,
1970 .resume = serial_imx_resume,
1971 .id_table = imx_uart_devtype,
1974 .owner = THIS_MODULE,
1975 .of_match_table = imx_uart_dt_ids,
1979 static int __init imx_serial_init(void)
1983 pr_info("Serial: IMX driver\n");
1985 ret = uart_register_driver(&imx_reg);
1989 ret = platform_driver_register(&serial_imx_driver);
1991 uart_unregister_driver(&imx_reg);
1996 static void __exit imx_serial_exit(void)
1998 platform_driver_unregister(&serial_imx_driver);
1999 uart_unregister_driver(&imx_reg);
2002 module_init(imx_serial_init);
2003 module_exit(imx_serial_exit);
2005 MODULE_AUTHOR("Sascha Hauer");
2006 MODULE_DESCRIPTION("IMX generic serial port driver");
2007 MODULE_LICENSE("GPL");
2008 MODULE_ALIAS("platform:imx-uart");