2 * Driver for Motorola IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
49 #include <linux/of_device.h>
51 #include <linux/dma-mapping.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
76 /* UART Control Register Bit Fields.*/
77 #define URXD_CHARRDY (1<<15)
78 #define URXD_ERR (1<<14)
79 #define URXD_OVRRUN (1<<13)
80 #define URXD_FRMERR (1<<12)
81 #define URXD_BRK (1<<11)
82 #define URXD_PRERR (1<<10)
83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90 #define UCR1_IREN (1<<7) /* Infrared interface enable */
91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93 #define UCR1_SNDBRK (1<<4) /* Send break */
94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
97 #define UCR1_DOZE (1<<1) /* Doze */
98 #define UCR1_UARTEN (1<<0) /* UART enabled */
99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101 #define UCR2_CTSC (1<<13) /* CTS pin control */
102 #define UCR2_CTS (1<<12) /* Clear to send */
103 #define UCR2_ESCEN (1<<11) /* Escape enable */
104 #define UCR2_PREN (1<<8) /* Parity enable */
105 #define UCR2_PROE (1<<7) /* Parity odd/even */
106 #define UCR2_STPB (1<<6) /* Stop */
107 #define UCR2_WS (1<<5) /* Word size */
108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
111 #define UCR2_RXEN (1<<1) /* Receiver enabled */
112 #define UCR2_SRST (1<<0) /* SW reset */
113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114 #define UCR3_PARERREN (1<<12) /* Parity enable */
115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116 #define UCR3_DSR (1<<10) /* Data set ready */
117 #define UCR3_DCD (1<<9) /* Data carrier detect */
118 #define UCR3_RI (1<<8) /* Ring indicator */
119 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125 #define UCR3_BPEN (1<<0) /* Preset registers enable */
126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
133 #define UCR4_IRSC (1<<5) /* IR special case */
134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144 #define USR1_RTSS (1<<14) /* RTS pin status */
145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146 #define USR1_RTSD (1<<12) /* RTS delta */
147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157 #define USR2_IDLE (1<<12) /* Idle condition */
158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159 #define USR2_WAKE (1<<7) /* Wake */
160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161 #define USR2_TXDC (1<<3) /* Transmitter complete */
162 #define USR2_BRCD (1<<2) /* Break condition */
163 #define USR2_ORE (1<<1) /* Overrun error */
164 #define USR2_RDR (1<<0) /* Recv data ready */
165 #define UTS_FRCPERR (1<<13) /* Force parity error */
166 #define UTS_LOOP (1<<12) /* Loop tx and rx */
167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169 #define UTS_TXFULL (1<<4) /* TxFIFO full */
170 #define UTS_RXFULL (1<<3) /* RxFIFO full */
171 #define UTS_SOFTRST (1<<0) /* Software reset */
173 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define SERIAL_IMX_MAJOR 207
175 #define MINOR_START 16
176 #define DEV_NAME "ttymxc"
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
184 #define MCTRL_TIMEOUT (250*HZ/1000)
186 #define DRIVER_NAME "IMX-uart"
190 /* i.mx21 type uart runs on all i.mx except i.mx1 */
197 /* device type dependent stuff */
198 struct imx_uart_data {
200 enum imx_uart_type devtype;
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
207 int txirq, rxirq, rtsirq;
208 unsigned int have_rtscts:1;
209 unsigned int dte_mode:1;
210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
216 const struct imx_uart_data *devdata;
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
226 unsigned int rx_bytes, tx_bytes;
227 struct work_struct tsk_dma_rx, tsk_dma_tx;
228 unsigned int dma_tx_nents;
229 wait_queue_head_t dma_wait;
232 struct imx_port_ucrs {
239 #define USE_IRDA(sport) ((sport)->use_irda)
241 #define USE_IRDA(sport) (0)
244 static struct imx_uart_data imx_uart_devdata[] = {
247 .devtype = IMX1_UART,
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX21_UART,
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX6Q_UART,
259 static struct platform_device_id imx_uart_devtype[] = {
262 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 .name = "imx21-uart",
265 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 .name = "imx6q-uart",
268 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
273 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275 static struct of_device_id imx_uart_dt_ids[] = {
276 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
281 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283 static inline unsigned uts_reg(struct imx_port *sport)
285 return sport->devdata->uts_reg;
288 static inline int is_imx1_uart(struct imx_port *sport)
290 return sport->devdata->devtype == IMX1_UART;
293 static inline int is_imx21_uart(struct imx_port *sport)
295 return sport->devdata->devtype == IMX21_UART;
298 static inline int is_imx6q_uart(struct imx_port *sport)
300 return sport->devdata->devtype == IMX6Q_UART;
303 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
306 static void imx_port_ucrs_save(struct uart_port *port,
307 struct imx_port_ucrs *ucr)
309 /* save control registers */
310 ucr->ucr1 = readl(port->membase + UCR1);
311 ucr->ucr2 = readl(port->membase + UCR2);
312 ucr->ucr3 = readl(port->membase + UCR3);
315 static void imx_port_ucrs_restore(struct uart_port *port,
316 struct imx_port_ucrs *ucr)
318 /* restore control registers */
319 writel(ucr->ucr1, port->membase + UCR1);
320 writel(ucr->ucr2, port->membase + UCR2);
321 writel(ucr->ucr3, port->membase + UCR3);
326 * Handle any change of modem status signal since we were last called.
328 static void imx_mctrl_check(struct imx_port *sport)
330 unsigned int status, changed;
332 status = sport->port.ops->get_mctrl(&sport->port);
333 changed = status ^ sport->old_status;
338 sport->old_status = status;
340 if (changed & TIOCM_RI)
341 sport->port.icount.rng++;
342 if (changed & TIOCM_DSR)
343 sport->port.icount.dsr++;
344 if (changed & TIOCM_CAR)
345 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
346 if (changed & TIOCM_CTS)
347 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
353 * This is our per-port timeout handler, for checking the
354 * modem status signals.
356 static void imx_timeout(unsigned long data)
358 struct imx_port *sport = (struct imx_port *)data;
361 if (sport->port.state) {
362 spin_lock_irqsave(&sport->port.lock, flags);
363 imx_mctrl_check(sport);
364 spin_unlock_irqrestore(&sport->port.lock, flags);
366 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
371 * interrupts disabled on entry
373 static void imx_stop_tx(struct uart_port *port)
375 struct imx_port *sport = (struct imx_port *)port;
378 if (USE_IRDA(sport)) {
379 /* half duplex - wait for end of transmission */
382 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
387 * irda transceiver - wait a bit more to avoid
388 * cutoff, hardware dependent
390 udelay(sport->trcv_delay);
393 * half duplex - reactivate receive mode,
394 * flush receive pipe echo crap
396 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
397 temp = readl(sport->port.membase + UCR1);
398 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
399 writel(temp, sport->port.membase + UCR1);
401 temp = readl(sport->port.membase + UCR4);
402 temp &= ~(UCR4_TCEN);
403 writel(temp, sport->port.membase + UCR4);
405 while (readl(sport->port.membase + URXD0) &
409 temp = readl(sport->port.membase + UCR1);
411 writel(temp, sport->port.membase + UCR1);
413 temp = readl(sport->port.membase + UCR4);
415 writel(temp, sport->port.membase + UCR4);
421 * We are maybe in the SMP context, so if the DMA TX thread is running
422 * on other cpu, we have to wait for it to finish.
424 if (sport->dma_is_enabled && sport->dma_is_txing)
427 temp = readl(sport->port.membase + UCR1);
428 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
432 * interrupts disabled on entry
434 static void imx_stop_rx(struct uart_port *port)
436 struct imx_port *sport = (struct imx_port *)port;
440 * We are maybe in the SMP context, so if the DMA TX thread is running
441 * on other cpu, we have to wait for it to finish.
443 if (sport->dma_is_enabled && sport->dma_is_rxing)
446 temp = readl(sport->port.membase + UCR2);
447 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
451 * Set the modem control timer to fire immediately.
453 static void imx_enable_ms(struct uart_port *port)
455 struct imx_port *sport = (struct imx_port *)port;
457 mod_timer(&sport->timer, jiffies);
460 static inline void imx_transmit_buffer(struct imx_port *sport)
462 struct circ_buf *xmit = &sport->port.state->xmit;
464 while (!uart_circ_empty(xmit) &&
465 !(readl(sport->port.membase + uts_reg(sport))
467 /* send xmit->buf[xmit->tail]
468 * out the port here */
469 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
470 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
471 sport->port.icount.tx++;
474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
475 uart_write_wakeup(&sport->port);
477 if (uart_circ_empty(xmit))
478 imx_stop_tx(&sport->port);
481 static void dma_tx_callback(void *data)
483 struct imx_port *sport = data;
484 struct scatterlist *sgl = &sport->tx_sgl[0];
485 struct circ_buf *xmit = &sport->port.state->xmit;
488 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
490 sport->dma_is_txing = 0;
492 /* update the stat */
493 spin_lock_irqsave(&sport->port.lock, flags);
494 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
495 sport->port.icount.tx += sport->tx_bytes;
496 spin_unlock_irqrestore(&sport->port.lock, flags);
498 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
501 uart_write_wakeup(&sport->port);
503 if (waitqueue_active(&sport->dma_wait)) {
504 wake_up(&sport->dma_wait);
505 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
509 schedule_work(&sport->tsk_dma_tx);
512 static void dma_tx_work(struct work_struct *w)
514 struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_tx);
515 struct circ_buf *xmit = &sport->port.state->xmit;
516 struct scatterlist *sgl = sport->tx_sgl;
517 struct dma_async_tx_descriptor *desc;
518 struct dma_chan *chan = sport->dma_chan_tx;
519 struct device *dev = sport->port.dev;
520 enum dma_status status;
524 status = chan->device->device_tx_status(chan, (dma_cookie_t)0, NULL);
525 if (DMA_IN_PROGRESS == status)
528 spin_lock_irqsave(&sport->port.lock, flags);
529 sport->tx_bytes = uart_circ_chars_pending(xmit);
530 if (sport->tx_bytes == 0) {
531 spin_unlock_irqrestore(&sport->port.lock, flags);
535 if (xmit->tail > xmit->head) {
536 sport->dma_tx_nents = 2;
537 sg_init_table(sgl, 2);
538 sg_set_buf(sgl, xmit->buf + xmit->tail,
539 UART_XMIT_SIZE - xmit->tail);
540 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
542 sport->dma_tx_nents = 1;
543 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
545 spin_unlock_irqrestore(&sport->port.lock, flags);
547 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
549 dev_err(dev, "DMA mapping error for TX.\n");
552 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
553 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
555 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
558 desc->callback = dma_tx_callback;
559 desc->callback_param = sport;
561 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
562 uart_circ_chars_pending(xmit));
564 sport->dma_is_txing = 1;
565 dmaengine_submit(desc);
566 dma_async_issue_pending(chan);
571 * interrupts disabled on entry
573 static void imx_start_tx(struct uart_port *port)
575 struct imx_port *sport = (struct imx_port *)port;
578 if (USE_IRDA(sport)) {
579 /* half duplex in IrDA mode; have to disable receive mode */
580 temp = readl(sport->port.membase + UCR4);
581 temp &= ~(UCR4_DREN);
582 writel(temp, sport->port.membase + UCR4);
584 temp = readl(sport->port.membase + UCR1);
585 temp &= ~(UCR1_RRDYEN);
586 writel(temp, sport->port.membase + UCR1);
588 /* Clear any pending ORE flag before enabling interrupt */
589 temp = readl(sport->port.membase + USR2);
590 writel(temp | USR2_ORE, sport->port.membase + USR2);
592 temp = readl(sport->port.membase + UCR4);
594 writel(temp, sport->port.membase + UCR4);
596 if (!sport->dma_is_enabled) {
597 temp = readl(sport->port.membase + UCR1);
598 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
601 if (USE_IRDA(sport)) {
602 temp = readl(sport->port.membase + UCR1);
604 writel(temp, sport->port.membase + UCR1);
606 temp = readl(sport->port.membase + UCR4);
608 writel(temp, sport->port.membase + UCR4);
611 if (sport->dma_is_enabled) {
613 * We may in the interrupt context, so arise a work_struct to
616 schedule_work(&sport->tsk_dma_tx);
620 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
621 imx_transmit_buffer(sport);
624 static irqreturn_t imx_rtsint(int irq, void *dev_id)
626 struct imx_port *sport = dev_id;
630 spin_lock_irqsave(&sport->port.lock, flags);
632 writel(USR1_RTSD, sport->port.membase + USR1);
633 val = readl(sport->port.membase + USR1) & USR1_RTSS;
634 uart_handle_cts_change(&sport->port, !!val);
635 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
637 spin_unlock_irqrestore(&sport->port.lock, flags);
641 static irqreturn_t imx_txint(int irq, void *dev_id)
643 struct imx_port *sport = dev_id;
644 struct circ_buf *xmit = &sport->port.state->xmit;
647 spin_lock_irqsave(&sport->port.lock, flags);
648 if (sport->port.x_char) {
650 writel(sport->port.x_char, sport->port.membase + URTX0);
654 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
655 imx_stop_tx(&sport->port);
659 imx_transmit_buffer(sport);
661 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
662 uart_write_wakeup(&sport->port);
665 spin_unlock_irqrestore(&sport->port.lock, flags);
669 static irqreturn_t imx_rxint(int irq, void *dev_id)
671 struct imx_port *sport = dev_id;
672 unsigned int rx, flg, ignored = 0;
673 struct tty_port *port = &sport->port.state->port;
674 unsigned long flags, temp;
676 spin_lock_irqsave(&sport->port.lock, flags);
678 while (readl(sport->port.membase + USR2) & USR2_RDR) {
680 sport->port.icount.rx++;
682 rx = readl(sport->port.membase + URXD0);
684 temp = readl(sport->port.membase + USR2);
685 if (temp & USR2_BRCD) {
686 writel(USR2_BRCD, sport->port.membase + USR2);
687 if (uart_handle_break(&sport->port))
691 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
694 if (unlikely(rx & URXD_ERR)) {
696 sport->port.icount.brk++;
697 else if (rx & URXD_PRERR)
698 sport->port.icount.parity++;
699 else if (rx & URXD_FRMERR)
700 sport->port.icount.frame++;
701 if (rx & URXD_OVRRUN)
702 sport->port.icount.overrun++;
704 if (rx & sport->port.ignore_status_mask) {
710 rx &= sport->port.read_status_mask;
714 else if (rx & URXD_PRERR)
716 else if (rx & URXD_FRMERR)
718 if (rx & URXD_OVRRUN)
722 sport->port.sysrq = 0;
726 tty_insert_flip_char(port, rx, flg);
730 spin_unlock_irqrestore(&sport->port.lock, flags);
731 tty_flip_buffer_push(port);
736 * If the RXFIFO is filled with some data, and then we
737 * arise a DMA operation to receive them.
739 static void imx_dma_rxint(struct imx_port *sport)
743 temp = readl(sport->port.membase + USR2);
744 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
745 sport->dma_is_rxing = 1;
747 /* disable the `Recerver Ready Interrrupt` */
748 temp = readl(sport->port.membase + UCR1);
749 temp &= ~(UCR1_RRDYEN);
750 writel(temp, sport->port.membase + UCR1);
752 /* tell the DMA to receive the data. */
753 schedule_work(&sport->tsk_dma_rx);
757 static irqreturn_t imx_int(int irq, void *dev_id)
759 struct imx_port *sport = dev_id;
763 sts = readl(sport->port.membase + USR1);
765 if (sts & USR1_RRDY) {
766 if (sport->dma_is_enabled)
767 imx_dma_rxint(sport);
769 imx_rxint(irq, dev_id);
772 if (sts & USR1_TRDY &&
773 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
774 imx_txint(irq, dev_id);
777 imx_rtsint(irq, dev_id);
779 if (sts & USR1_AWAKE)
780 writel(USR1_AWAKE, sport->port.membase + USR1);
782 sts2 = readl(sport->port.membase + USR2);
783 if (sts2 & USR2_ORE) {
784 dev_err(sport->port.dev, "Rx FIFO overrun\n");
785 sport->port.icount.overrun++;
786 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
793 * Return TIOCSER_TEMT when transmitter is not busy.
795 static unsigned int imx_tx_empty(struct uart_port *port)
797 struct imx_port *sport = (struct imx_port *)port;
799 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
803 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
805 static unsigned int imx_get_mctrl(struct uart_port *port)
807 struct imx_port *sport = (struct imx_port *)port;
808 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
810 if (readl(sport->port.membase + USR1) & USR1_RTSS)
813 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
819 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
821 struct imx_port *sport = (struct imx_port *)port;
824 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
826 if (mctrl & TIOCM_RTS)
827 if (!sport->dma_is_enabled)
830 writel(temp, sport->port.membase + UCR2);
834 * Interrupts always disabled.
836 static void imx_break_ctl(struct uart_port *port, int break_state)
838 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long flags, temp;
841 spin_lock_irqsave(&sport->port.lock, flags);
843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
845 if (break_state != 0)
848 writel(temp, sport->port.membase + UCR1);
850 spin_unlock_irqrestore(&sport->port.lock, flags);
853 #define TXTL 2 /* reset default */
854 #define RXTL 1 /* reset default */
856 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
860 /* set receiver / transmitter trigger level */
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
862 val |= TXTL << UFCR_TXTL_SHF | RXTL;
863 writel(val, sport->port.membase + UFCR);
867 #define RX_BUF_SIZE (PAGE_SIZE)
868 static int start_rx_dma(struct imx_port *sport);
869 static void dma_rx_work(struct work_struct *w)
871 struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_rx);
872 struct tty_port *port = &sport->port.state->port;
874 if (sport->rx_bytes) {
875 tty_insert_flip_string(port, sport->rx_buf, sport->rx_bytes);
876 tty_flip_buffer_push(port);
880 if (sport->dma_is_rxing)
884 static void imx_rx_dma_done(struct imx_port *sport)
888 /* Enable this interrupt when the RXFIFO is empty. */
889 temp = readl(sport->port.membase + UCR1);
891 writel(temp, sport->port.membase + UCR1);
893 sport->dma_is_rxing = 0;
895 /* Is the shutdown waiting for us? */
896 if (waitqueue_active(&sport->dma_wait))
897 wake_up(&sport->dma_wait);
901 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
902 * [1] the RX DMA buffer is full.
903 * [2] the Aging timer expires(wait for 8 bytes long)
904 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
906 * The [2] is trigger when a character was been sitting in the FIFO
907 * meanwhile [3] can wait for 32 bytes long when the RX line is
908 * on IDLE state and RxFIFO is empty.
910 static void dma_rx_callback(void *data)
912 struct imx_port *sport = data;
913 struct dma_chan *chan = sport->dma_chan_rx;
914 struct scatterlist *sgl = &sport->rx_sgl;
915 struct dma_tx_state state;
916 enum dma_status status;
920 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
922 status = chan->device->device_tx_status(chan, (dma_cookie_t)0, &state);
923 count = RX_BUF_SIZE - state.residue;
924 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
927 sport->rx_bytes = count;
928 schedule_work(&sport->tsk_dma_rx);
930 imx_rx_dma_done(sport);
933 static int start_rx_dma(struct imx_port *sport)
935 struct scatterlist *sgl = &sport->rx_sgl;
936 struct dma_chan *chan = sport->dma_chan_rx;
937 struct device *dev = sport->port.dev;
938 struct dma_async_tx_descriptor *desc;
941 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
942 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
944 dev_err(dev, "DMA mapping error for RX.\n");
947 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
950 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
953 desc->callback = dma_rx_callback;
954 desc->callback_param = sport;
956 dev_dbg(dev, "RX: prepare for the DMA.\n");
957 dmaengine_submit(desc);
958 dma_async_issue_pending(chan);
962 static void imx_uart_dma_exit(struct imx_port *sport)
964 if (sport->dma_chan_rx) {
965 dma_release_channel(sport->dma_chan_rx);
966 sport->dma_chan_rx = NULL;
968 kfree(sport->rx_buf);
969 sport->rx_buf = NULL;
972 if (sport->dma_chan_tx) {
973 dma_release_channel(sport->dma_chan_tx);
974 sport->dma_chan_tx = NULL;
977 sport->dma_is_inited = 0;
980 static int imx_uart_dma_init(struct imx_port *sport)
982 struct dma_slave_config slave_config = {};
983 struct device *dev = sport->port.dev;
986 /* Prepare for RX : */
987 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
988 if (!sport->dma_chan_rx) {
989 dev_dbg(dev, "cannot get the DMA channel.\n");
994 slave_config.direction = DMA_DEV_TO_MEM;
995 slave_config.src_addr = sport->port.mapbase + URXD0;
996 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
997 slave_config.src_maxburst = RXTL;
998 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1000 dev_err(dev, "error in RX dma configuration.\n");
1004 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1005 if (!sport->rx_buf) {
1006 dev_err(dev, "cannot alloc DMA buffer.\n");
1010 sport->rx_bytes = 0;
1012 /* Prepare for TX : */
1013 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1014 if (!sport->dma_chan_tx) {
1015 dev_err(dev, "cannot get the TX DMA channel!\n");
1020 slave_config.direction = DMA_MEM_TO_DEV;
1021 slave_config.dst_addr = sport->port.mapbase + URTX0;
1022 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1023 slave_config.dst_maxburst = TXTL;
1024 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1026 dev_err(dev, "error in TX dma configuration.");
1030 sport->dma_is_inited = 1;
1034 imx_uart_dma_exit(sport);
1038 static void imx_enable_dma(struct imx_port *sport)
1041 struct tty_port *port = &sport->port.state->port;
1043 port->low_latency = 1;
1044 INIT_WORK(&sport->tsk_dma_tx, dma_tx_work);
1045 INIT_WORK(&sport->tsk_dma_rx, dma_rx_work);
1046 init_waitqueue_head(&sport->dma_wait);
1049 temp = readl(sport->port.membase + UCR1);
1050 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1051 /* wait for 32 idle frames for IDDMA interrupt */
1053 writel(temp, sport->port.membase + UCR1);
1056 temp = readl(sport->port.membase + UCR4);
1057 temp |= UCR4_IDDMAEN;
1058 writel(temp, sport->port.membase + UCR4);
1060 sport->dma_is_enabled = 1;
1063 static void imx_disable_dma(struct imx_port *sport)
1066 struct tty_port *port = &sport->port.state->port;
1069 temp = readl(sport->port.membase + UCR1);
1070 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1071 writel(temp, sport->port.membase + UCR1);
1074 temp = readl(sport->port.membase + UCR2);
1075 temp &= ~(UCR2_CTSC | UCR2_CTS);
1076 writel(temp, sport->port.membase + UCR2);
1079 temp = readl(sport->port.membase + UCR4);
1080 temp &= ~UCR4_IDDMAEN;
1081 writel(temp, sport->port.membase + UCR4);
1083 sport->dma_is_enabled = 0;
1084 port->low_latency = 0;
1087 /* half the RX buffer size */
1090 static int imx_startup(struct uart_port *port)
1092 struct imx_port *sport = (struct imx_port *)port;
1094 unsigned long flags, temp;
1096 retval = clk_prepare_enable(sport->clk_per);
1099 retval = clk_prepare_enable(sport->clk_ipg);
1101 clk_disable_unprepare(sport->clk_per);
1105 imx_setup_ufcr(sport, 0);
1107 /* disable the DREN bit (Data Ready interrupt enable) before
1110 temp = readl(sport->port.membase + UCR4);
1112 if (USE_IRDA(sport))
1115 /* set the trigger level for CTS */
1116 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1117 temp |= CTSTL << UCR4_CTSTL_SHF;
1119 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1121 if (USE_IRDA(sport)) {
1122 /* reset fifo's and state machines */
1124 temp = readl(sport->port.membase + UCR2);
1126 writel(temp, sport->port.membase + UCR2);
1127 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
1134 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1135 * chips only have one interrupt.
1137 if (sport->txirq > 0) {
1138 retval = request_irq(sport->rxirq, imx_rxint, 0,
1139 DRIVER_NAME, sport);
1143 retval = request_irq(sport->txirq, imx_txint, 0,
1144 DRIVER_NAME, sport);
1148 /* do not use RTS IRQ on IrDA */
1149 if (!USE_IRDA(sport)) {
1150 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
1151 DRIVER_NAME, sport);
1156 retval = request_irq(sport->port.irq, imx_int, 0,
1157 DRIVER_NAME, sport);
1159 free_irq(sport->port.irq, sport);
1164 spin_lock_irqsave(&sport->port.lock, flags);
1166 * Finally, clear and enable interrupts
1168 writel(USR1_RTSD, sport->port.membase + USR1);
1170 temp = readl(sport->port.membase + UCR1);
1171 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1173 if (USE_IRDA(sport)) {
1175 temp &= ~(UCR1_RTSDEN);
1178 writel(temp, sport->port.membase + UCR1);
1180 temp = readl(sport->port.membase + UCR2);
1181 temp |= (UCR2_RXEN | UCR2_TXEN);
1182 if (!sport->have_rtscts)
1184 writel(temp, sport->port.membase + UCR2);
1186 if (USE_IRDA(sport)) {
1190 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
1195 if (!is_imx1_uart(sport)) {
1196 temp = readl(sport->port.membase + UCR3);
1197 temp |= IMX21_UCR3_RXDMUXSEL;
1198 writel(temp, sport->port.membase + UCR3);
1201 if (USE_IRDA(sport)) {
1202 temp = readl(sport->port.membase + UCR4);
1203 if (sport->irda_inv_rx)
1206 temp &= ~(UCR4_INVR);
1207 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1209 temp = readl(sport->port.membase + UCR3);
1210 if (sport->irda_inv_tx)
1213 temp &= ~(UCR3_INVT);
1214 writel(temp, sport->port.membase + UCR3);
1218 * Enable modem status interrupts
1220 imx_enable_ms(&sport->port);
1221 spin_unlock_irqrestore(&sport->port.lock, flags);
1223 if (USE_IRDA(sport)) {
1224 struct imxuart_platform_data *pdata;
1225 pdata = dev_get_platdata(sport->port.dev);
1226 sport->irda_inv_rx = pdata->irda_inv_rx;
1227 sport->irda_inv_tx = pdata->irda_inv_tx;
1228 sport->trcv_delay = pdata->transceiver_delay;
1229 if (pdata->irda_enable)
1230 pdata->irda_enable(1);
1237 free_irq(sport->txirq, sport);
1240 free_irq(sport->rxirq, sport);
1245 static void imx_shutdown(struct uart_port *port)
1247 struct imx_port *sport = (struct imx_port *)port;
1249 unsigned long flags;
1251 if (sport->dma_is_enabled) {
1252 /* We have to wait for the DMA to finish. */
1253 wait_event(sport->dma_wait,
1254 !sport->dma_is_rxing && !sport->dma_is_txing);
1256 imx_disable_dma(sport);
1257 imx_uart_dma_exit(sport);
1260 spin_lock_irqsave(&sport->port.lock, flags);
1261 temp = readl(sport->port.membase + UCR2);
1262 temp &= ~(UCR2_TXEN);
1263 writel(temp, sport->port.membase + UCR2);
1264 spin_unlock_irqrestore(&sport->port.lock, flags);
1266 if (USE_IRDA(sport)) {
1267 struct imxuart_platform_data *pdata;
1268 pdata = dev_get_platdata(sport->port.dev);
1269 if (pdata->irda_enable)
1270 pdata->irda_enable(0);
1276 del_timer_sync(&sport->timer);
1279 * Free the interrupts
1281 if (sport->txirq > 0) {
1282 if (!USE_IRDA(sport))
1283 free_irq(sport->rtsirq, sport);
1284 free_irq(sport->txirq, sport);
1285 free_irq(sport->rxirq, sport);
1287 free_irq(sport->port.irq, sport);
1290 * Disable all interrupts, port and break condition.
1293 spin_lock_irqsave(&sport->port.lock, flags);
1294 temp = readl(sport->port.membase + UCR1);
1295 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1296 if (USE_IRDA(sport))
1297 temp &= ~(UCR1_IREN);
1299 writel(temp, sport->port.membase + UCR1);
1300 spin_unlock_irqrestore(&sport->port.lock, flags);
1302 clk_disable_unprepare(sport->clk_per);
1303 clk_disable_unprepare(sport->clk_ipg);
1306 static void imx_flush_buffer(struct uart_port *port)
1308 struct imx_port *sport = (struct imx_port *)port;
1310 if (sport->dma_is_enabled) {
1311 sport->tx_bytes = 0;
1312 dmaengine_terminate_all(sport->dma_chan_tx);
1317 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1318 struct ktermios *old)
1320 struct imx_port *sport = (struct imx_port *)port;
1321 unsigned long flags;
1322 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1323 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1324 unsigned int div, ufcr;
1325 unsigned long num, denom;
1329 * If we don't support modem control lines, don't allow
1333 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1334 termios->c_cflag |= CLOCAL;
1338 * We only support CS7 and CS8.
1340 while ((termios->c_cflag & CSIZE) != CS7 &&
1341 (termios->c_cflag & CSIZE) != CS8) {
1342 termios->c_cflag &= ~CSIZE;
1343 termios->c_cflag |= old_csize;
1347 if ((termios->c_cflag & CSIZE) == CS8)
1348 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1350 ucr2 = UCR2_SRST | UCR2_IRTS;
1352 if (termios->c_cflag & CRTSCTS) {
1353 if (sport->have_rtscts) {
1357 /* Can we enable the DMA support? */
1358 if (is_imx6q_uart(sport) && !uart_console(port)
1359 && !sport->dma_is_inited)
1360 imx_uart_dma_init(sport);
1362 termios->c_cflag &= ~CRTSCTS;
1366 if (termios->c_cflag & CSTOPB)
1368 if (termios->c_cflag & PARENB) {
1370 if (termios->c_cflag & PARODD)
1374 del_timer_sync(&sport->timer);
1377 * Ask the core to calculate the divisor for us.
1379 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1380 quot = uart_get_divisor(port, baud);
1382 spin_lock_irqsave(&sport->port.lock, flags);
1384 sport->port.read_status_mask = 0;
1385 if (termios->c_iflag & INPCK)
1386 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1387 if (termios->c_iflag & (BRKINT | PARMRK))
1388 sport->port.read_status_mask |= URXD_BRK;
1391 * Characters to ignore
1393 sport->port.ignore_status_mask = 0;
1394 if (termios->c_iflag & IGNPAR)
1395 sport->port.ignore_status_mask |= URXD_PRERR;
1396 if (termios->c_iflag & IGNBRK) {
1397 sport->port.ignore_status_mask |= URXD_BRK;
1399 * If we're ignoring parity and break indicators,
1400 * ignore overruns too (for real raw support).
1402 if (termios->c_iflag & IGNPAR)
1403 sport->port.ignore_status_mask |= URXD_OVRRUN;
1407 * Update the per-port timeout.
1409 uart_update_timeout(port, termios->c_cflag, baud);
1412 * disable interrupts and drain transmitter
1414 old_ucr1 = readl(sport->port.membase + UCR1);
1415 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1416 sport->port.membase + UCR1);
1418 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1421 /* then, disable everything */
1422 old_txrxen = readl(sport->port.membase + UCR2);
1423 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1424 sport->port.membase + UCR2);
1425 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1427 if (USE_IRDA(sport)) {
1429 * use maximum available submodule frequency to
1430 * avoid missing short pulses due to low sampling rate
1434 /* custom-baudrate handling */
1435 div = sport->port.uartclk / (baud * 16);
1436 if (baud == 38400 && quot != div)
1437 baud = sport->port.uartclk / (quot * 16);
1439 div = sport->port.uartclk / (baud * 16);
1446 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1447 1 << 16, 1 << 16, &num, &denom);
1449 tdiv64 = sport->port.uartclk;
1451 do_div(tdiv64, denom * 16 * div);
1452 tty_termios_encode_baud_rate(termios,
1453 (speed_t)tdiv64, (speed_t)tdiv64);
1458 ufcr = readl(sport->port.membase + UFCR);
1459 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1460 if (sport->dte_mode)
1461 ufcr |= UFCR_DCEDTE;
1462 writel(ufcr, sport->port.membase + UFCR);
1464 writel(num, sport->port.membase + UBIR);
1465 writel(denom, sport->port.membase + UBMR);
1467 if (!is_imx1_uart(sport))
1468 writel(sport->port.uartclk / div / 1000,
1469 sport->port.membase + IMX21_ONEMS);
1471 writel(old_ucr1, sport->port.membase + UCR1);
1473 /* set the parity, stop bits and data size */
1474 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1476 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1477 imx_enable_ms(&sport->port);
1479 if (sport->dma_is_inited && !sport->dma_is_enabled)
1480 imx_enable_dma(sport);
1481 spin_unlock_irqrestore(&sport->port.lock, flags);
1484 static const char *imx_type(struct uart_port *port)
1486 struct imx_port *sport = (struct imx_port *)port;
1488 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1492 * Release the memory region(s) being used by 'port'.
1494 static void imx_release_port(struct uart_port *port)
1496 struct platform_device *pdev = to_platform_device(port->dev);
1497 struct resource *mmres;
1499 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1500 release_mem_region(mmres->start, resource_size(mmres));
1504 * Request the memory region(s) being used by 'port'.
1506 static int imx_request_port(struct uart_port *port)
1508 struct platform_device *pdev = to_platform_device(port->dev);
1509 struct resource *mmres;
1512 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1516 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1518 return ret ? 0 : -EBUSY;
1522 * Configure/autoconfigure the port.
1524 static void imx_config_port(struct uart_port *port, int flags)
1526 struct imx_port *sport = (struct imx_port *)port;
1528 if (flags & UART_CONFIG_TYPE &&
1529 imx_request_port(&sport->port) == 0)
1530 sport->port.type = PORT_IMX;
1534 * Verify the new serial_struct (for TIOCSSERIAL).
1535 * The only change we allow are to the flags and type, and
1536 * even then only between PORT_IMX and PORT_UNKNOWN
1539 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1541 struct imx_port *sport = (struct imx_port *)port;
1544 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1546 if (sport->port.irq != ser->irq)
1548 if (ser->io_type != UPIO_MEM)
1550 if (sport->port.uartclk / 16 != ser->baud_base)
1552 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1554 if (sport->port.iobase != ser->port)
1561 #if defined(CONFIG_CONSOLE_POLL)
1562 static int imx_poll_get_char(struct uart_port *port)
1564 struct imx_port_ucrs old_ucr;
1565 unsigned int status;
1568 /* save control registers */
1569 imx_port_ucrs_save(port, &old_ucr);
1571 /* disable interrupts */
1572 writel(UCR1_UARTEN, port->membase + UCR1);
1573 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1574 port->membase + UCR2);
1575 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1576 port->membase + UCR3);
1580 status = readl(port->membase + USR2);
1581 } while (~status & USR2_RDR);
1584 c = readl(port->membase + URXD0);
1586 /* restore control registers */
1587 imx_port_ucrs_restore(port, &old_ucr);
1592 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1594 struct imx_port_ucrs old_ucr;
1595 unsigned int status;
1597 /* save control registers */
1598 imx_port_ucrs_save(port, &old_ucr);
1600 /* disable interrupts */
1601 writel(UCR1_UARTEN, port->membase + UCR1);
1602 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1603 port->membase + UCR2);
1604 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1605 port->membase + UCR3);
1609 status = readl(port->membase + USR1);
1610 } while (~status & USR1_TRDY);
1613 writel(c, port->membase + URTX0);
1617 status = readl(port->membase + USR2);
1618 } while (~status & USR2_TXDC);
1620 /* restore control registers */
1621 imx_port_ucrs_restore(port, &old_ucr);
1625 static struct uart_ops imx_pops = {
1626 .tx_empty = imx_tx_empty,
1627 .set_mctrl = imx_set_mctrl,
1628 .get_mctrl = imx_get_mctrl,
1629 .stop_tx = imx_stop_tx,
1630 .start_tx = imx_start_tx,
1631 .stop_rx = imx_stop_rx,
1632 .enable_ms = imx_enable_ms,
1633 .break_ctl = imx_break_ctl,
1634 .startup = imx_startup,
1635 .shutdown = imx_shutdown,
1636 .flush_buffer = imx_flush_buffer,
1637 .set_termios = imx_set_termios,
1639 .release_port = imx_release_port,
1640 .request_port = imx_request_port,
1641 .config_port = imx_config_port,
1642 .verify_port = imx_verify_port,
1643 #if defined(CONFIG_CONSOLE_POLL)
1644 .poll_get_char = imx_poll_get_char,
1645 .poll_put_char = imx_poll_put_char,
1649 static struct imx_port *imx_ports[UART_NR];
1651 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1652 static void imx_console_putchar(struct uart_port *port, int ch)
1654 struct imx_port *sport = (struct imx_port *)port;
1656 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1659 writel(ch, sport->port.membase + URTX0);
1663 * Interrupts are disabled on entering
1666 imx_console_write(struct console *co, const char *s, unsigned int count)
1668 struct imx_port *sport = imx_ports[co->index];
1669 struct imx_port_ucrs old_ucr;
1671 unsigned long flags = 0;
1675 retval = clk_enable(sport->clk_per);
1678 retval = clk_enable(sport->clk_ipg);
1680 clk_disable(sport->clk_per);
1684 if (sport->port.sysrq)
1686 else if (oops_in_progress)
1687 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1689 spin_lock_irqsave(&sport->port.lock, flags);
1692 * First, save UCR1/2/3 and then disable interrupts
1694 imx_port_ucrs_save(&sport->port, &old_ucr);
1695 ucr1 = old_ucr.ucr1;
1697 if (is_imx1_uart(sport))
1698 ucr1 |= IMX1_UCR1_UARTCLKEN;
1699 ucr1 |= UCR1_UARTEN;
1700 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1702 writel(ucr1, sport->port.membase + UCR1);
1704 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1706 uart_console_write(&sport->port, s, count, imx_console_putchar);
1709 * Finally, wait for transmitter to become empty
1710 * and restore UCR1/2/3
1712 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1714 imx_port_ucrs_restore(&sport->port, &old_ucr);
1717 spin_unlock_irqrestore(&sport->port.lock, flags);
1719 clk_disable(sport->clk_ipg);
1720 clk_disable(sport->clk_per);
1724 * If the port was already initialised (eg, by a boot loader),
1725 * try to determine the current setup.
1728 imx_console_get_options(struct imx_port *sport, int *baud,
1729 int *parity, int *bits)
1732 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1733 /* ok, the port was enabled */
1734 unsigned int ucr2, ubir, ubmr, uartclk;
1735 unsigned int baud_raw;
1736 unsigned int ucfr_rfdiv;
1738 ucr2 = readl(sport->port.membase + UCR2);
1741 if (ucr2 & UCR2_PREN) {
1742 if (ucr2 & UCR2_PROE)
1753 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1754 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1756 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1757 if (ucfr_rfdiv == 6)
1760 ucfr_rfdiv = 6 - ucfr_rfdiv;
1762 uartclk = clk_get_rate(sport->clk_per);
1763 uartclk /= ucfr_rfdiv;
1766 * The next code provides exact computation of
1767 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1768 * without need of float support or long long division,
1769 * which would be required to prevent 32bit arithmetic overflow
1771 unsigned int mul = ubir + 1;
1772 unsigned int div = 16 * (ubmr + 1);
1773 unsigned int rem = uartclk % div;
1775 baud_raw = (uartclk / div) * mul;
1776 baud_raw += (rem * mul + div / 2) / div;
1777 *baud = (baud_raw + 50) / 100 * 100;
1780 if (*baud != baud_raw)
1781 pr_info("Console IMX rounded baud rate from %d to %d\n",
1787 imx_console_setup(struct console *co, char *options)
1789 struct imx_port *sport;
1797 * Check whether an invalid uart number has been specified, and
1798 * if so, search for the first available port that does have
1801 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1803 sport = imx_ports[co->index];
1807 /* For setting the registers, we only need to enable the ipg clock. */
1808 retval = clk_prepare_enable(sport->clk_ipg);
1813 uart_parse_options(options, &baud, &parity, &bits, &flow);
1815 imx_console_get_options(sport, &baud, &parity, &bits);
1817 imx_setup_ufcr(sport, 0);
1819 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1821 clk_disable(sport->clk_ipg);
1823 clk_unprepare(sport->clk_ipg);
1827 retval = clk_prepare(sport->clk_per);
1829 clk_disable_unprepare(sport->clk_ipg);
1835 static struct uart_driver imx_reg;
1836 static struct console imx_console = {
1838 .write = imx_console_write,
1839 .device = uart_console_device,
1840 .setup = imx_console_setup,
1841 .flags = CON_PRINTBUFFER,
1846 #define IMX_CONSOLE &imx_console
1848 #define IMX_CONSOLE NULL
1851 static struct uart_driver imx_reg = {
1852 .owner = THIS_MODULE,
1853 .driver_name = DRIVER_NAME,
1854 .dev_name = DEV_NAME,
1855 .major = SERIAL_IMX_MAJOR,
1856 .minor = MINOR_START,
1857 .nr = ARRAY_SIZE(imx_ports),
1858 .cons = IMX_CONSOLE,
1861 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1863 struct imx_port *sport = platform_get_drvdata(dev);
1866 /* enable wakeup from i.MX UART */
1867 val = readl(sport->port.membase + UCR3);
1869 writel(val, sport->port.membase + UCR3);
1871 uart_suspend_port(&imx_reg, &sport->port);
1876 static int serial_imx_resume(struct platform_device *dev)
1878 struct imx_port *sport = platform_get_drvdata(dev);
1881 /* disable wakeup from i.MX UART */
1882 val = readl(sport->port.membase + UCR3);
1883 val &= ~UCR3_AWAKEN;
1884 writel(val, sport->port.membase + UCR3);
1886 uart_resume_port(&imx_reg, &sport->port);
1893 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1894 * could successfully get all information from dt or a negative errno.
1896 static int serial_imx_probe_dt(struct imx_port *sport,
1897 struct platform_device *pdev)
1899 struct device_node *np = pdev->dev.of_node;
1900 const struct of_device_id *of_id =
1901 of_match_device(imx_uart_dt_ids, &pdev->dev);
1905 /* no device tree device */
1908 ret = of_alias_get_id(np, "serial");
1910 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1913 sport->port.line = ret;
1915 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1916 sport->have_rtscts = 1;
1918 if (of_get_property(np, "fsl,irda-mode", NULL))
1919 sport->use_irda = 1;
1921 if (of_get_property(np, "fsl,dte-mode", NULL))
1922 sport->dte_mode = 1;
1924 sport->devdata = of_id->data;
1926 if (of_device_is_stdout_path(np))
1927 add_preferred_console(imx_reg.cons->name, sport->port.line,
1933 static inline int serial_imx_probe_dt(struct imx_port *sport,
1934 struct platform_device *pdev)
1940 static void serial_imx_probe_pdata(struct imx_port *sport,
1941 struct platform_device *pdev)
1943 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1945 sport->port.line = pdev->id;
1946 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1951 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1952 sport->have_rtscts = 1;
1954 if (pdata->flags & IMXUART_IRDA)
1955 sport->use_irda = 1;
1958 static int serial_imx_probe(struct platform_device *pdev)
1960 struct imx_port *sport;
1961 struct imxuart_platform_data *pdata;
1964 struct resource *res;
1966 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1970 ret = serial_imx_probe_dt(sport, pdev);
1972 serial_imx_probe_pdata(sport, pdev);
1976 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1980 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1984 sport->port.dev = &pdev->dev;
1985 sport->port.mapbase = res->start;
1986 sport->port.membase = base;
1987 sport->port.type = PORT_IMX,
1988 sport->port.iotype = UPIO_MEM;
1989 sport->port.irq = platform_get_irq(pdev, 0);
1990 sport->rxirq = platform_get_irq(pdev, 0);
1991 sport->txirq = platform_get_irq(pdev, 1);
1992 sport->rtsirq = platform_get_irq(pdev, 2);
1993 sport->port.fifosize = 32;
1994 sport->port.ops = &imx_pops;
1995 sport->port.flags = UPF_BOOT_AUTOCONF;
1996 init_timer(&sport->timer);
1997 sport->timer.function = imx_timeout;
1998 sport->timer.data = (unsigned long)sport;
2000 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2001 if (IS_ERR(sport->clk_ipg)) {
2002 ret = PTR_ERR(sport->clk_ipg);
2003 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2007 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2008 if (IS_ERR(sport->clk_per)) {
2009 ret = PTR_ERR(sport->clk_per);
2010 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2014 sport->port.uartclk = clk_get_rate(sport->clk_per);
2016 imx_ports[sport->port.line] = sport;
2018 pdata = dev_get_platdata(&pdev->dev);
2019 if (pdata && pdata->init) {
2020 ret = pdata->init(pdev);
2025 ret = uart_add_one_port(&imx_reg, &sport->port);
2028 platform_set_drvdata(pdev, sport);
2032 if (pdata && pdata->exit)
2037 static int serial_imx_remove(struct platform_device *pdev)
2039 struct imxuart_platform_data *pdata;
2040 struct imx_port *sport = platform_get_drvdata(pdev);
2042 pdata = dev_get_platdata(&pdev->dev);
2044 uart_remove_one_port(&imx_reg, &sport->port);
2046 if (pdata && pdata->exit)
2052 static struct platform_driver serial_imx_driver = {
2053 .probe = serial_imx_probe,
2054 .remove = serial_imx_remove,
2056 .suspend = serial_imx_suspend,
2057 .resume = serial_imx_resume,
2058 .id_table = imx_uart_devtype,
2061 .owner = THIS_MODULE,
2062 .of_match_table = imx_uart_dt_ids,
2066 static int __init imx_serial_init(void)
2070 pr_info("Serial: IMX driver\n");
2072 ret = uart_register_driver(&imx_reg);
2076 ret = platform_driver_register(&serial_imx_driver);
2078 uart_unregister_driver(&imx_reg);
2083 static void __exit imx_serial_exit(void)
2085 platform_driver_unregister(&serial_imx_driver);
2086 uart_unregister_driver(&imx_reg);
2089 module_init(imx_serial_init);
2090 module_exit(imx_serial_exit);
2092 MODULE_AUTHOR("Sascha Hauer");
2093 MODULE_DESCRIPTION("IMX generic serial port driver");
2094 MODULE_LICENSE("GPL");
2095 MODULE_ALIAS("platform:imx-uart");