2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #include <linux/init.h>
35 #include <asm/sgialib.h>
36 #include <asm/sgi/ioc.h>
37 #include <asm/sgi/hpc3.h>
38 #include <asm/sgi/ip22.h>
40 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #include <linux/serial_core.h>
46 #include "ip22zilog.h"
49 * On IP22 we need to delay after register accesses but we do not need to
52 #define ZSDELAY() udelay(5)
53 #define ZSDELAY_LONG() udelay(20)
54 #define ZS_WSYNC(channel) do { } while (0)
56 #define NUM_IP22ZILOG 1
57 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
59 #define ZS_CLOCK 3672000 /* Zilog input clock rate. */
60 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
63 * We wrap our port structure around the generic uart_port.
65 struct uart_ip22zilog_port {
66 struct uart_port port;
68 /* IRQ servicing chain. */
69 struct uart_ip22zilog_port *next;
71 /* Current values of Zilog write registers. */
72 unsigned char curregs[NUM_ZSREGS];
75 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
76 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
77 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
78 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
79 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
80 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
81 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
82 #define IP22ZILOG_FLAG_RESET_DONE 0x00000200
84 unsigned int tty_break;
86 unsigned char parity_mask;
87 unsigned char prev_status;
90 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
91 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
92 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
93 (UART_ZILOG(PORT)->curregs[REGNUM])
94 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
95 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
96 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
97 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
98 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
99 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
100 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
101 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
102 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
104 /* Reading and writing Zilog8530 registers. The delays are to make this
105 * driver work on the IP22 which needs a settling delay after each chip
106 * register access, other machines handle this in hardware via auxiliary
107 * flip-flops which implement the settle time we do in software.
109 * The port lock must be held and local IRQs must be disabled
110 * when {read,write}_zsreg is invoked.
112 static unsigned char read_zsreg(struct zilog_channel *channel,
115 unsigned char retval;
117 writeb(reg, &channel->control);
119 retval = readb(&channel->control);
125 static void write_zsreg(struct zilog_channel *channel,
126 unsigned char reg, unsigned char value)
128 writeb(reg, &channel->control);
130 writeb(value, &channel->control);
134 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
138 for (i = 0; i < 32; i++) {
139 unsigned char regval;
141 regval = readb(&channel->control);
143 if (regval & Rx_CH_AV)
146 regval = read_zsreg(channel, R1);
147 readb(&channel->data);
150 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
151 writeb(ERR_RES, &channel->control);
158 /* This function must only be called when the TX is not busy. The UART
159 * port lock must be held and local interrupts disabled.
161 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
165 /* Let pending transmits finish. */
166 for (i = 0; i < 1000; i++) {
167 unsigned char stat = read_zsreg(channel, R1);
173 writeb(ERR_RES, &channel->control);
177 ip22zilog_clear_fifo(channel);
179 /* Disable all interrupts. */
180 write_zsreg(channel, R1,
181 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
183 /* Set parity, sync config, stop bits, and clock divisor. */
184 write_zsreg(channel, R4, regs[R4]);
186 /* Set misc. TX/RX control bits. */
187 write_zsreg(channel, R10, regs[R10]);
189 /* Set TX/RX controls sans the enable bits. */
190 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
191 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
193 /* Synchronous mode config. */
194 write_zsreg(channel, R6, regs[R6]);
195 write_zsreg(channel, R7, regs[R7]);
197 /* Don't mess with the interrupt vector (R2, unused by us) and
198 * master interrupt control (R9). We make sure this is setup
199 * properly at probe time then never touch it again.
202 /* Disable baud generator. */
203 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
205 /* Clock mode control. */
206 write_zsreg(channel, R11, regs[R11]);
208 /* Lower and upper byte of baud rate generator divisor. */
209 write_zsreg(channel, R12, regs[R12]);
210 write_zsreg(channel, R13, regs[R13]);
212 /* Now rewrite R14, with BRENAB (if set). */
213 write_zsreg(channel, R14, regs[R14]);
215 /* External status interrupt control. */
216 write_zsreg(channel, R15, regs[R15]);
218 /* Reset external status interrupts. */
219 write_zsreg(channel, R0, RES_EXT_INT);
220 write_zsreg(channel, R0, RES_EXT_INT);
222 /* Rewrite R3/R5, this time without enables masked. */
223 write_zsreg(channel, R3, regs[R3]);
224 write_zsreg(channel, R5, regs[R5]);
226 /* Rewrite R1, this time without IRQ enabled masked. */
227 write_zsreg(channel, R1, regs[R1]);
230 /* Reprogram the Zilog channel HW registers with the copies found in the
231 * software state struct. If the transmitter is busy, we defer this update
232 * until the next TX complete interrupt. Else, we do it right now.
234 * The UART port lock must be held and local interrupts disabled.
236 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
237 struct zilog_channel *channel)
239 if (!ZS_REGS_HELD(up)) {
240 if (ZS_TX_ACTIVE(up)) {
241 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
243 __load_zsregs(channel, up->curregs);
248 #define Rx_BRK 0x0100 /* BREAK event software flag. */
249 #define Rx_SYS 0x0200 /* SysRq event software flag. */
251 static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
252 struct zilog_channel *channel)
254 unsigned char ch, flag;
256 bool push = up->port.state != NULL;
259 ch = readb(&channel->control);
261 if (!(ch & Rx_CH_AV))
264 r1 = read_zsreg(channel, R1);
265 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
266 writeb(ERR_RES, &channel->control);
271 ch = readb(&channel->data);
274 ch &= up->parity_mask;
276 /* Handle the null char got when BREAK is removed. */
280 /* A real serial line, record the character and status. */
282 up->port.icount.rx++;
283 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {
286 if (r1 & (Rx_SYS | Rx_BRK)) {
287 up->port.icount.brk++;
290 r1 &= ~(PAR_ERR | CRC_ERR);
292 else if (r1 & PAR_ERR)
293 up->port.icount.parity++;
294 else if (r1 & CRC_ERR)
295 up->port.icount.frame++;
297 up->port.icount.overrun++;
298 r1 &= up->port.read_status_mask;
301 else if (r1 & PAR_ERR)
303 else if (r1 & CRC_ERR)
307 if (uart_handle_sysrq_char(&up->port, ch))
311 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
316 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
317 struct zilog_channel *channel)
319 unsigned char status;
321 status = readb(&channel->control);
324 writeb(RES_EXT_INT, &channel->control);
328 if (up->curregs[R15] & BRKIE) {
329 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
330 if (uart_handle_break(&up->port))
331 up->tty_break = Rx_SYS;
333 up->tty_break = Rx_BRK;
337 if (ZS_WANTS_MODEM_STATUS(up)) {
339 up->port.icount.dsr++;
341 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
342 * But it does not tell us which bit has changed, we have to keep
343 * track of this ourselves.
345 if ((status ^ up->prev_status) ^ DCD)
346 uart_handle_dcd_change(&up->port,
348 if ((status ^ up->prev_status) ^ CTS)
349 uart_handle_cts_change(&up->port,
352 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
355 up->prev_status = status;
358 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
359 struct zilog_channel *channel)
361 struct circ_buf *xmit;
363 if (ZS_IS_CONS(up)) {
364 unsigned char status = readb(&channel->control);
367 /* TX still busy? Just wait for the next TX done interrupt.
369 * It can occur because of how we do serial console writes. It would
370 * be nice to transmit console writes just like we normally would for
371 * a TTY line. (ie. buffered and TX interrupt driven). That is not
372 * easy because console writes cannot sleep. One solution might be
373 * to poll on enough port->xmit space becoming free. -DaveM
375 if (!(status & Tx_BUF_EMP))
379 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
381 if (ZS_REGS_HELD(up)) {
382 __load_zsregs(channel, up->curregs);
383 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
386 if (ZS_TX_STOPPED(up)) {
387 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
391 if (up->port.x_char) {
392 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
393 writeb(up->port.x_char, &channel->data);
397 up->port.icount.tx++;
402 if (up->port.state == NULL)
404 xmit = &up->port.state->xmit;
405 if (uart_circ_empty(xmit))
407 if (uart_tx_stopped(&up->port))
410 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
411 writeb(xmit->buf[xmit->tail], &channel->data);
415 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
416 up->port.icount.tx++;
418 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
419 uart_write_wakeup(&up->port);
424 writeb(RES_Tx_P, &channel->control);
429 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
431 struct uart_ip22zilog_port *up = dev_id;
434 struct zilog_channel *channel
435 = ZILOG_CHANNEL_FROM_PORT(&up->port);
439 spin_lock(&up->port.lock);
440 r3 = read_zsreg(channel, R3);
443 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
444 writeb(RES_H_IUS, &channel->control);
449 push = ip22zilog_receive_chars(up, channel);
451 ip22zilog_status_handle(up, channel);
453 ip22zilog_transmit_chars(up, channel);
455 spin_unlock(&up->port.lock);
458 tty_flip_buffer_push(&up->port.state->port);
462 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
465 spin_lock(&up->port.lock);
466 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
467 writeb(RES_H_IUS, &channel->control);
472 push = ip22zilog_receive_chars(up, channel);
474 ip22zilog_status_handle(up, channel);
476 ip22zilog_transmit_chars(up, channel);
478 spin_unlock(&up->port.lock);
481 tty_flip_buffer_push(&up->port.state->port);
489 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
490 * port lock, it is acquired here.
492 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
494 struct zilog_channel *channel;
495 unsigned char status;
497 channel = ZILOG_CHANNEL_FROM_PORT(port);
498 status = readb(&channel->control);
504 /* The port lock is not held. */
505 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
508 unsigned char status;
511 spin_lock_irqsave(&port->lock, flags);
513 status = ip22zilog_read_channel_status(port);
515 spin_unlock_irqrestore(&port->lock, flags);
517 if (status & Tx_BUF_EMP)
525 /* The port lock is held and interrupts are disabled. */
526 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
528 unsigned char status;
531 status = ip22zilog_read_channel_status(port);
544 /* The port lock is held and interrupts are disabled. */
545 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
547 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
548 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
549 unsigned char set_bits, clear_bits;
551 set_bits = clear_bits = 0;
553 if (mctrl & TIOCM_RTS)
557 if (mctrl & TIOCM_DTR)
562 /* NOTE: Not subject to 'transmitter active' rule. */
563 up->curregs[R5] |= set_bits;
564 up->curregs[R5] &= ~clear_bits;
565 write_zsreg(channel, R5, up->curregs[R5]);
568 /* The port lock is held and interrupts are disabled. */
569 static void ip22zilog_stop_tx(struct uart_port *port)
571 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
573 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
576 /* The port lock is held and interrupts are disabled. */
577 static void ip22zilog_start_tx(struct uart_port *port)
579 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
580 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
581 unsigned char status;
583 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
584 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
586 status = readb(&channel->control);
589 /* TX busy? Just wait for the TX done interrupt. */
590 if (!(status & Tx_BUF_EMP))
593 /* Send the first character to jump-start the TX done
594 * IRQ sending engine.
597 writeb(port->x_char, &channel->data);
604 struct circ_buf *xmit = &port->state->xmit;
606 if (uart_circ_empty(xmit))
608 writeb(xmit->buf[xmit->tail], &channel->data);
612 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
615 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
616 uart_write_wakeup(&up->port);
620 /* The port lock is held and interrupts are disabled. */
621 static void ip22zilog_stop_rx(struct uart_port *port)
623 struct uart_ip22zilog_port *up = UART_ZILOG(port);
624 struct zilog_channel *channel;
629 channel = ZILOG_CHANNEL_FROM_PORT(port);
631 /* Disable all RX interrupts. */
632 up->curregs[R1] &= ~RxINT_MASK;
633 ip22zilog_maybe_update_regs(up, channel);
636 /* The port lock is held. */
637 static void ip22zilog_enable_ms(struct uart_port *port)
639 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
640 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
641 unsigned char new_reg;
643 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
644 if (new_reg != up->curregs[R15]) {
645 up->curregs[R15] = new_reg;
647 /* NOTE: Not subject to 'transmitter active' rule. */
648 write_zsreg(channel, R15, up->curregs[R15]);
652 /* The port lock is not held. */
653 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
655 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
656 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
657 unsigned char set_bits, clear_bits, new_reg;
660 set_bits = clear_bits = 0;
665 clear_bits |= SND_BRK;
667 spin_lock_irqsave(&port->lock, flags);
669 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
670 if (new_reg != up->curregs[R5]) {
671 up->curregs[R5] = new_reg;
673 /* NOTE: Not subject to 'transmitter active' rule. */
674 write_zsreg(channel, R5, up->curregs[R5]);
677 spin_unlock_irqrestore(&port->lock, flags);
680 static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
682 struct zilog_channel *channel;
685 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
688 /* Let pending transmits finish. */
689 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
690 for (i = 0; i < 1000; i++) {
691 unsigned char stat = read_zsreg(channel, R1);
697 if (!ZS_IS_CHANNEL_A(up)) {
699 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
701 write_zsreg(channel, R9, FHWRES);
703 (void) read_zsreg(channel, R0);
705 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
706 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
709 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
711 struct zilog_channel *channel;
713 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
715 __ip22zilog_reset(up);
717 __load_zsregs(channel, up->curregs);
718 /* set master interrupt enable */
719 write_zsreg(channel, R9, up->curregs[R9]);
720 up->prev_status = readb(&channel->control);
722 /* Enable receiver and transmitter. */
723 up->curregs[R3] |= RxENAB;
724 up->curregs[R5] |= TxENAB;
726 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
727 ip22zilog_maybe_update_regs(up, channel);
730 static int ip22zilog_startup(struct uart_port *port)
732 struct uart_ip22zilog_port *up = UART_ZILOG(port);
738 spin_lock_irqsave(&port->lock, flags);
739 __ip22zilog_startup(up);
740 spin_unlock_irqrestore(&port->lock, flags);
745 * The test for ZS_IS_CONS is explained by the following e-mail:
747 * From: Russell King <rmk@arm.linux.org.uk>
748 * Date: Sun, 8 Dec 2002 10:18:38 +0000
750 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
751 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
752 * > and I noticed that something is not right with reference
753 * > counting in this case. It seems that when the console
754 * > is open by kernel initially, this is not accounted
755 * > as an open, and uart_startup is not called.
757 * That is correct. We are unable to call uart_startup when the serial
758 * console is initialised because it may need to allocate memory (as
759 * request_irq does) and the memory allocators may not have been
762 * 1. initialise the port into a state where it can send characters in the
763 * console write method.
765 * 2. don't do the actual hardware shutdown in your shutdown() method (but
766 * do the normal software shutdown - ie, free irqs etc)
769 static void ip22zilog_shutdown(struct uart_port *port)
771 struct uart_ip22zilog_port *up = UART_ZILOG(port);
772 struct zilog_channel *channel;
778 spin_lock_irqsave(&port->lock, flags);
780 channel = ZILOG_CHANNEL_FROM_PORT(port);
782 /* Disable receiver and transmitter. */
783 up->curregs[R3] &= ~RxENAB;
784 up->curregs[R5] &= ~TxENAB;
786 /* Disable all interrupts and BRK assertion. */
787 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
788 up->curregs[R5] &= ~SND_BRK;
789 ip22zilog_maybe_update_regs(up, channel);
791 spin_unlock_irqrestore(&port->lock, flags);
794 /* Shared by TTY driver and serial console setup. The port lock is held
795 * and local interrupts are disabled.
798 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
799 unsigned int iflag, int brg)
802 up->curregs[R10] = NRZ;
803 up->curregs[R11] = TCBR | RCBR;
805 /* Program BAUD and clock source. */
806 up->curregs[R4] &= ~XCLK_MASK;
807 up->curregs[R4] |= X16CLK;
808 up->curregs[R12] = brg & 0xff;
809 up->curregs[R13] = (brg >> 8) & 0xff;
810 up->curregs[R14] = BRENAB;
812 /* Character size, stop bits, and parity. */
813 up->curregs[3] &= ~RxN_MASK;
814 up->curregs[5] &= ~TxN_MASK;
815 switch (cflag & CSIZE) {
817 up->curregs[3] |= Rx5;
818 up->curregs[5] |= Tx5;
819 up->parity_mask = 0x1f;
822 up->curregs[3] |= Rx6;
823 up->curregs[5] |= Tx6;
824 up->parity_mask = 0x3f;
827 up->curregs[3] |= Rx7;
828 up->curregs[5] |= Tx7;
829 up->parity_mask = 0x7f;
833 up->curregs[3] |= Rx8;
834 up->curregs[5] |= Tx8;
835 up->parity_mask = 0xff;
838 up->curregs[4] &= ~0x0c;
840 up->curregs[4] |= SB2;
842 up->curregs[4] |= SB1;
844 up->curregs[4] |= PAR_ENAB;
846 up->curregs[4] &= ~PAR_ENAB;
847 if (!(cflag & PARODD))
848 up->curregs[4] |= PAR_EVEN;
850 up->curregs[4] &= ~PAR_EVEN;
852 up->port.read_status_mask = Rx_OVR;
854 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
855 if (iflag & (IGNBRK | BRKINT | PARMRK))
856 up->port.read_status_mask |= BRK_ABRT;
858 up->port.ignore_status_mask = 0;
860 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
861 if (iflag & IGNBRK) {
862 up->port.ignore_status_mask |= BRK_ABRT;
864 up->port.ignore_status_mask |= Rx_OVR;
867 if ((cflag & CREAD) == 0)
868 up->port.ignore_status_mask = 0xff;
871 /* The port lock is not held. */
873 ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
874 struct ktermios *old)
876 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
880 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
882 spin_lock_irqsave(&up->port.lock, flags);
884 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
886 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
888 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
889 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
891 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
893 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
894 uart_update_timeout(port, termios->c_cflag, baud);
896 spin_unlock_irqrestore(&up->port.lock, flags);
899 static const char *ip22zilog_type(struct uart_port *port)
904 /* We do not request/release mappings of the registers here, this
905 * happens at early serial probe time.
907 static void ip22zilog_release_port(struct uart_port *port)
911 static int ip22zilog_request_port(struct uart_port *port)
916 /* These do not need to do anything interesting either. */
917 static void ip22zilog_config_port(struct uart_port *port, int flags)
921 /* We do not support letting the user mess with the divisor, IRQ, etc. */
922 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
927 static struct uart_ops ip22zilog_pops = {
928 .tx_empty = ip22zilog_tx_empty,
929 .set_mctrl = ip22zilog_set_mctrl,
930 .get_mctrl = ip22zilog_get_mctrl,
931 .stop_tx = ip22zilog_stop_tx,
932 .start_tx = ip22zilog_start_tx,
933 .stop_rx = ip22zilog_stop_rx,
934 .enable_ms = ip22zilog_enable_ms,
935 .break_ctl = ip22zilog_break_ctl,
936 .startup = ip22zilog_startup,
937 .shutdown = ip22zilog_shutdown,
938 .set_termios = ip22zilog_set_termios,
939 .type = ip22zilog_type,
940 .release_port = ip22zilog_release_port,
941 .request_port = ip22zilog_request_port,
942 .config_port = ip22zilog_config_port,
943 .verify_port = ip22zilog_verify_port,
946 static struct uart_ip22zilog_port *ip22zilog_port_table;
947 static struct zilog_layout **ip22zilog_chip_regs;
949 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
950 static int zilog_irq = -1;
952 static void * __init alloc_one_table(unsigned long size)
954 return kzalloc(size, GFP_KERNEL);
957 static void __init ip22zilog_alloc_tables(void)
959 ip22zilog_port_table = (struct uart_ip22zilog_port *)
960 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
961 ip22zilog_chip_regs = (struct zilog_layout **)
962 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
964 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
965 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
969 /* Get the address of the registers for IP22-Zilog instance CHIP. */
970 static struct zilog_layout * __init get_zs(int chip)
974 if (chip < 0 || chip >= NUM_IP22ZILOG) {
975 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
978 /* Not probe-able, hard code it. */
979 base = (unsigned long) &sgioc->uart;
981 zilog_irq = SGI_SERIAL_IRQ;
982 request_mem_region(base, 8, "IP22-Zilog");
984 return (struct zilog_layout *) base;
987 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
989 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
990 static void ip22zilog_put_char(struct uart_port *port, int ch)
992 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
993 int loops = ZS_PUT_CHAR_MAX_DELAY;
995 /* This is a timed polling loop so do not switch the explicit
996 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
999 unsigned char val = readb(&channel->control);
1000 if (val & Tx_BUF_EMP) {
1007 writeb(ch, &channel->data);
1013 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
1015 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1016 unsigned long flags;
1018 spin_lock_irqsave(&up->port.lock, flags);
1019 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1021 spin_unlock_irqrestore(&up->port.lock, flags);
1024 static int __init ip22zilog_console_setup(struct console *con, char *options)
1026 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1027 unsigned long flags;
1028 int baud = 9600, bits = 8;
1032 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1034 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
1036 spin_lock_irqsave(&up->port.lock, flags);
1038 up->curregs[R15] |= BRKIE;
1040 __ip22zilog_startup(up);
1042 spin_unlock_irqrestore(&up->port.lock, flags);
1045 uart_parse_options(options, &baud, &parity, &bits, &flow);
1046 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1049 static struct uart_driver ip22zilog_reg;
1051 static struct console ip22zilog_console = {
1053 .write = ip22zilog_console_write,
1054 .device = uart_console_device,
1055 .setup = ip22zilog_console_setup,
1056 .flags = CON_PRINTBUFFER,
1058 .data = &ip22zilog_reg,
1060 #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1062 static struct uart_driver ip22zilog_reg = {
1063 .owner = THIS_MODULE,
1064 .driver_name = "serial",
1069 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1070 .cons = &ip22zilog_console,
1074 static void __init ip22zilog_prepare(void)
1076 struct uart_ip22zilog_port *up;
1077 struct zilog_layout *rp;
1083 for (channel = 0; channel < NUM_CHANNELS; channel++)
1084 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1086 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1087 up = &ip22zilog_port_table[0];
1088 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1089 up[channel].next = &up[channel - 1];
1090 up[channel].next = NULL;
1092 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1093 if (!ip22zilog_chip_regs[chip]) {
1094 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1096 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1097 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1099 /* In theory mapbase is the physical address ... */
1100 up[(chip * 2) + 0].port.mapbase =
1101 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1102 up[(chip * 2) + 1].port.mapbase =
1103 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1107 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1108 up[(chip * 2) + 0].port.irq = zilog_irq;
1109 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1110 up[(chip * 2) + 0].port.fifosize = 1;
1111 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1112 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1113 up[(chip * 2) + 0].port.flags = 0;
1114 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1115 up[(chip * 2) + 0].flags = 0;
1118 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1119 up[(chip * 2) + 1].port.irq = zilog_irq;
1120 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1121 up[(chip * 2) + 1].port.fifosize = 1;
1122 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1123 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1124 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1125 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1128 for (channel = 0; channel < NUM_CHANNELS; channel++) {
1129 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1132 /* Normal serial TTY. */
1133 up->parity_mask = 0xff;
1134 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1135 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1136 up->curregs[R3] = RxENAB | Rx8;
1137 up->curregs[R5] = TxENAB | Tx8;
1138 up->curregs[R9] = NV | MIE;
1139 up->curregs[R10] = NRZ;
1140 up->curregs[R11] = TCBR | RCBR;
1141 brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1142 up->curregs[R12] = (brg & 0xff);
1143 up->curregs[R13] = (brg >> 8) & 0xff;
1144 up->curregs[R14] = BRENAB;
1148 static int __init ip22zilog_ports_init(void)
1152 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1154 ip22zilog_prepare();
1156 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1157 "IP22-Zilog", ip22zilog_irq_chain)) {
1158 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1161 ret = uart_register_driver(&ip22zilog_reg);
1165 for (i = 0; i < NUM_CHANNELS; i++) {
1166 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1168 uart_add_one_port(&ip22zilog_reg, &up->port);
1175 static int __init ip22zilog_init(void)
1177 /* IP22 Zilog setup is hard coded, no probing to do. */
1178 ip22zilog_alloc_tables();
1179 ip22zilog_ports_init();
1184 static void __exit ip22zilog_exit(void)
1187 struct uart_ip22zilog_port *up;
1189 for (i = 0; i < NUM_CHANNELS; i++) {
1190 up = &ip22zilog_port_table[i];
1192 uart_remove_one_port(&ip22zilog_reg, &up->port);
1196 up = &ip22zilog_port_table[0];
1197 for (i = 0; i < NUM_IP22ZILOG; i++) {
1198 if (up[(i * 2) + 0].port.mapbase) {
1199 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1200 up[(i * 2) + 0].port.mapbase = 0;
1202 if (up[(i * 2) + 1].port.mapbase) {
1203 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1204 up[(i * 2) + 1].port.mapbase = 0;
1208 uart_unregister_driver(&ip22zilog_reg);
1211 module_init(ip22zilog_init);
1212 module_exit(ip22zilog_exit);
1214 /* David wrote it but I'm to blame for the bugs ... */
1215 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1216 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1217 MODULE_LICENSE("GPL");