2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 * Copyright (C) 2004 Infineon IFAP DC COM CPE
18 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
19 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
20 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/of_platform.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
38 #include <linux/clk.h>
39 #include <linux/gpio.h>
41 #include <lantiq_soc.h>
43 #define PORT_LTQ_ASC 111
45 #define UART_DUMMY_UER_RX 1
46 #define DRVNAME "lantiq,asc"
48 #define LTQ_ASC_TBUF (0x0020 + 3)
49 #define LTQ_ASC_RBUF (0x0024 + 3)
51 #define LTQ_ASC_TBUF 0x0020
52 #define LTQ_ASC_RBUF 0x0024
54 #define LTQ_ASC_FSTAT 0x0048
55 #define LTQ_ASC_WHBSTATE 0x0018
56 #define LTQ_ASC_STATE 0x0014
57 #define LTQ_ASC_IRNCR 0x00F8
58 #define LTQ_ASC_CLC 0x0000
59 #define LTQ_ASC_ID 0x0008
60 #define LTQ_ASC_PISEL 0x0004
61 #define LTQ_ASC_TXFCON 0x0044
62 #define LTQ_ASC_RXFCON 0x0040
63 #define LTQ_ASC_CON 0x0010
64 #define LTQ_ASC_BG 0x0050
65 #define LTQ_ASC_IRNREN 0x00F4
67 #define ASC_IRNREN_TX 0x1
68 #define ASC_IRNREN_RX 0x2
69 #define ASC_IRNREN_ERR 0x4
70 #define ASC_IRNREN_TX_BUF 0x8
71 #define ASC_IRNCR_TIR 0x1
72 #define ASC_IRNCR_RIR 0x2
73 #define ASC_IRNCR_EIR 0x4
75 #define ASCOPT_CSIZE 0x3
78 #define ASCCLC_DISS 0x2
79 #define ASCCLC_RMCMASK 0x0000FF00
80 #define ASCCLC_RMCOFFSET 8
81 #define ASCCON_M_8ASYNC 0x0
82 #define ASCCON_M_7ASYNC 0x2
83 #define ASCCON_ODD 0x00000020
84 #define ASCCON_STP 0x00000080
85 #define ASCCON_BRS 0x00000100
86 #define ASCCON_FDE 0x00000200
87 #define ASCCON_R 0x00008000
88 #define ASCCON_FEN 0x00020000
89 #define ASCCON_ROEN 0x00080000
90 #define ASCCON_TOEN 0x00100000
91 #define ASCSTATE_PE 0x00010000
92 #define ASCSTATE_FE 0x00020000
93 #define ASCSTATE_ROE 0x00080000
94 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
95 #define ASCWHBSTATE_CLRREN 0x00000001
96 #define ASCWHBSTATE_SETREN 0x00000002
97 #define ASCWHBSTATE_CLRPE 0x00000004
98 #define ASCWHBSTATE_CLRFE 0x00000008
99 #define ASCWHBSTATE_CLRROE 0x00000020
100 #define ASCTXFCON_TXFEN 0x0001
101 #define ASCTXFCON_TXFFLU 0x0002
102 #define ASCTXFCON_TXFITLMASK 0x3F00
103 #define ASCTXFCON_TXFITLOFF 8
104 #define ASCRXFCON_RXFEN 0x0001
105 #define ASCRXFCON_RXFFLU 0x0002
106 #define ASCRXFCON_RXFITLMASK 0x3F00
107 #define ASCRXFCON_RXFITLOFF 8
108 #define ASCFSTAT_RXFFLMASK 0x003F
109 #define ASCFSTAT_TXFFLMASK 0x3F00
110 #define ASCFSTAT_TXFREEMASK 0x3F000000
111 #define ASCFSTAT_TXFREEOFF 24
113 static void lqasc_tx_chars(struct uart_port *port);
114 static struct ltq_uart_port *lqasc_port[MAXPORTS];
115 static struct uart_driver lqasc_reg;
116 static DEFINE_SPINLOCK(ltq_asc_lock);
118 struct ltq_uart_port {
119 struct uart_port port;
120 /* clock used to derive divider */
122 /* clock gating of the ASC core */
126 unsigned int err_irq;
130 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
132 return container_of(port, struct ltq_uart_port, port);
136 lqasc_stop_tx(struct uart_port *port)
142 lqasc_start_tx(struct uart_port *port)
145 spin_lock_irqsave(<q_asc_lock, flags);
146 lqasc_tx_chars(port);
147 spin_unlock_irqrestore(<q_asc_lock, flags);
152 lqasc_stop_rx(struct uart_port *port)
154 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
158 lqasc_enable_ms(struct uart_port *port)
163 lqasc_rx_chars(struct uart_port *port)
165 struct tty_port *tport = &port->state->port;
166 struct tty_struct *tty = tty_port_tty_get(tport);
167 unsigned int ch = 0, rsr = 0, fifocnt;
170 dev_dbg(port->dev, "%s:tty is busy now", __func__);
174 ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
176 u8 flag = TTY_NORMAL;
177 ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
178 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
179 & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
180 tty_flip_buffer_push(tty);
184 * Note that the error handling code is
185 * out of the main execution path
187 if (rsr & ASCSTATE_ANY) {
188 if (rsr & ASCSTATE_PE) {
189 port->icount.parity++;
190 ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
191 port->membase + LTQ_ASC_WHBSTATE);
192 } else if (rsr & ASCSTATE_FE) {
193 port->icount.frame++;
194 ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
195 port->membase + LTQ_ASC_WHBSTATE);
197 if (rsr & ASCSTATE_ROE) {
198 port->icount.overrun++;
199 ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
200 port->membase + LTQ_ASC_WHBSTATE);
203 rsr &= port->read_status_mask;
205 if (rsr & ASCSTATE_PE)
207 else if (rsr & ASCSTATE_FE)
211 if ((rsr & port->ignore_status_mask) == 0)
212 tty_insert_flip_char(tport, ch, flag);
214 if (rsr & ASCSTATE_ROE)
216 * Overrun is special, since it's reported
217 * immediately, and doesn't affect the current
220 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
223 tty_flip_buffer_push(tty);
229 lqasc_tx_chars(struct uart_port *port)
231 struct circ_buf *xmit = &port->state->xmit;
232 if (uart_tx_stopped(port)) {
237 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
238 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
240 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
246 if (uart_circ_empty(xmit))
249 ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
250 port->membase + LTQ_ASC_TBUF);
251 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
255 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
256 uart_write_wakeup(port);
260 lqasc_tx_int(int irq, void *_port)
263 struct uart_port *port = (struct uart_port *)_port;
264 spin_lock_irqsave(<q_asc_lock, flags);
265 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
266 spin_unlock_irqrestore(<q_asc_lock, flags);
267 lqasc_start_tx(port);
272 lqasc_err_int(int irq, void *_port)
275 struct uart_port *port = (struct uart_port *)_port;
276 spin_lock_irqsave(<q_asc_lock, flags);
277 /* clear any pending interrupts */
278 ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
279 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
280 spin_unlock_irqrestore(<q_asc_lock, flags);
285 lqasc_rx_int(int irq, void *_port)
288 struct uart_port *port = (struct uart_port *)_port;
289 spin_lock_irqsave(<q_asc_lock, flags);
290 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
291 lqasc_rx_chars(port);
292 spin_unlock_irqrestore(<q_asc_lock, flags);
297 lqasc_tx_empty(struct uart_port *port)
300 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
301 return status ? 0 : TIOCSER_TEMT;
305 lqasc_get_mctrl(struct uart_port *port)
307 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
311 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
316 lqasc_break_ctl(struct uart_port *port, int break_state)
321 lqasc_startup(struct uart_port *port)
323 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
327 clk_enable(ltq_port->clk);
328 port->uartclk = clk_get_rate(ltq_port->fpiclk);
330 ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
331 port->membase + LTQ_ASC_CLC);
333 ltq_w32(0, port->membase + LTQ_ASC_PISEL);
335 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
336 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
337 port->membase + LTQ_ASC_TXFCON);
339 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
340 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
341 port->membase + LTQ_ASC_RXFCON);
342 /* make sure other settings are written to hardware before
343 * setting enable bits
346 ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
347 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
349 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
352 pr_err("failed to request lqasc_tx_int\n");
356 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
359 pr_err("failed to request lqasc_rx_int\n");
363 retval = request_irq(ltq_port->err_irq, lqasc_err_int,
366 pr_err("failed to request lqasc_err_int\n");
370 ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
371 port->membase + LTQ_ASC_IRNREN);
375 free_irq(ltq_port->rx_irq, port);
377 free_irq(ltq_port->tx_irq, port);
382 lqasc_shutdown(struct uart_port *port)
384 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
385 free_irq(ltq_port->tx_irq, port);
386 free_irq(ltq_port->rx_irq, port);
387 free_irq(ltq_port->err_irq, port);
389 ltq_w32(0, port->membase + LTQ_ASC_CON);
390 ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
391 port->membase + LTQ_ASC_RXFCON);
392 ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
393 port->membase + LTQ_ASC_TXFCON);
395 clk_disable(ltq_port->clk);
399 lqasc_set_termios(struct uart_port *port,
400 struct ktermios *new, struct ktermios *old)
404 unsigned int divisor;
406 unsigned int con = 0;
409 cflag = new->c_cflag;
410 iflag = new->c_iflag;
412 switch (cflag & CSIZE) {
414 con = ASCCON_M_7ASYNC;
420 new->c_cflag &= ~ CSIZE;
422 con = ASCCON_M_8ASYNC;
426 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
431 if (cflag & PARENB) {
432 if (!(cflag & PARODD))
438 port->read_status_mask = ASCSTATE_ROE;
440 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
442 port->ignore_status_mask = 0;
444 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
446 if (iflag & IGNBRK) {
448 * If we're ignoring parity and break indicators,
449 * ignore overruns too (for real raw support).
452 port->ignore_status_mask |= ASCSTATE_ROE;
455 if ((cflag & CREAD) == 0)
456 port->ignore_status_mask |= UART_DUMMY_UER_RX;
458 /* set error signals - framing, parity and overrun, enable receiver */
459 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
461 spin_lock_irqsave(<q_asc_lock, flags);
464 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
466 /* Set baud rate - take a divider of 2 into account */
467 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
468 divisor = uart_get_divisor(port, baud);
469 divisor = divisor / 2 - 1;
471 /* disable the baudrate generator */
472 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
474 /* make sure the fractional divider is off */
475 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
477 /* set up to use divisor of 2 */
478 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
480 /* now we can write the new baudrate into the register */
481 ltq_w32(divisor, port->membase + LTQ_ASC_BG);
483 /* turn the baudrate generator back on */
484 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
487 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
489 spin_unlock_irqrestore(<q_asc_lock, flags);
491 /* Don't rewrite B0 */
492 if (tty_termios_baud_rate(new))
493 tty_termios_encode_baud_rate(new, baud, baud);
495 uart_update_timeout(port, cflag, baud);
499 lqasc_type(struct uart_port *port)
501 if (port->type == PORT_LTQ_ASC)
508 lqasc_release_port(struct uart_port *port)
510 if (port->flags & UPF_IOREMAP) {
511 iounmap(port->membase);
512 port->membase = NULL;
517 lqasc_request_port(struct uart_port *port)
519 struct platform_device *pdev = to_platform_device(port->dev);
520 struct resource *res;
523 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 dev_err(&pdev->dev, "cannot obtain I/O memory region");
528 size = resource_size(res);
530 res = devm_request_mem_region(&pdev->dev, res->start,
531 size, dev_name(&pdev->dev));
533 dev_err(&pdev->dev, "cannot request I/O memory region");
537 if (port->flags & UPF_IOREMAP) {
538 port->membase = devm_ioremap_nocache(&pdev->dev,
539 port->mapbase, size);
540 if (port->membase == NULL)
547 lqasc_config_port(struct uart_port *port, int flags)
549 if (flags & UART_CONFIG_TYPE) {
550 port->type = PORT_LTQ_ASC;
551 lqasc_request_port(port);
556 lqasc_verify_port(struct uart_port *port,
557 struct serial_struct *ser)
560 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
562 if (ser->irq < 0 || ser->irq >= NR_IRQS)
564 if (ser->baud_base < 9600)
569 static struct uart_ops lqasc_pops = {
570 .tx_empty = lqasc_tx_empty,
571 .set_mctrl = lqasc_set_mctrl,
572 .get_mctrl = lqasc_get_mctrl,
573 .stop_tx = lqasc_stop_tx,
574 .start_tx = lqasc_start_tx,
575 .stop_rx = lqasc_stop_rx,
576 .enable_ms = lqasc_enable_ms,
577 .break_ctl = lqasc_break_ctl,
578 .startup = lqasc_startup,
579 .shutdown = lqasc_shutdown,
580 .set_termios = lqasc_set_termios,
582 .release_port = lqasc_release_port,
583 .request_port = lqasc_request_port,
584 .config_port = lqasc_config_port,
585 .verify_port = lqasc_verify_port,
589 lqasc_console_putchar(struct uart_port *port, int ch)
597 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
598 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
599 } while (fifofree == 0);
600 ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
605 lqasc_console_write(struct console *co, const char *s, u_int count)
607 struct ltq_uart_port *ltq_port;
608 struct uart_port *port;
611 if (co->index >= MAXPORTS)
614 ltq_port = lqasc_port[co->index];
618 port = <q_port->port;
620 spin_lock_irqsave(<q_asc_lock, flags);
621 uart_console_write(port, s, count, lqasc_console_putchar);
622 spin_unlock_irqrestore(<q_asc_lock, flags);
626 lqasc_console_setup(struct console *co, char *options)
628 struct ltq_uart_port *ltq_port;
629 struct uart_port *port;
635 if (co->index >= MAXPORTS)
638 ltq_port = lqasc_port[co->index];
642 port = <q_port->port;
644 port->uartclk = clk_get_rate(ltq_port->fpiclk);
647 uart_parse_options(options, &baud, &parity, &bits, &flow);
648 return uart_set_options(port, co, baud, parity, bits, flow);
651 static struct console lqasc_console = {
653 .write = lqasc_console_write,
654 .device = uart_console_device,
655 .setup = lqasc_console_setup,
656 .flags = CON_PRINTBUFFER,
662 lqasc_console_init(void)
664 register_console(&lqasc_console);
667 console_initcall(lqasc_console_init);
669 static struct uart_driver lqasc_reg = {
670 .owner = THIS_MODULE,
671 .driver_name = DRVNAME,
672 .dev_name = "ttyLTQ",
676 .cons = &lqasc_console,
680 lqasc_probe(struct platform_device *pdev)
682 struct device_node *node = pdev->dev.of_node;
683 struct ltq_uart_port *ltq_port;
684 struct uart_port *port;
685 struct resource *mmres, irqres[3];
689 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
690 ret = of_irq_to_resource_table(node, irqres, 3);
691 if (!mmres || (ret != 3)) {
693 "failed to get memory/irq for serial port\n");
697 /* check if this is the console port */
698 if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC))
701 if (lqasc_port[line]) {
702 dev_err(&pdev->dev, "port %d already allocated\n", line);
706 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
711 port = <q_port->port;
713 port->iotype = SERIAL_IO_MEM;
714 port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP;
715 port->ops = &lqasc_pops;
717 port->type = PORT_LTQ_ASC,
719 port->dev = &pdev->dev;
720 /* unused, just to be backward-compatible */
721 port->irq = irqres[0].start;
722 port->mapbase = mmres->start;
724 ltq_port->fpiclk = clk_get_fpi();
725 if (IS_ERR(ltq_port->fpiclk)) {
726 pr_err("failed to get fpi clk\n");
730 /* not all asc ports have clock gates, lets ignore the return code */
731 ltq_port->clk = clk_get(&pdev->dev, NULL);
733 ltq_port->tx_irq = irqres[0].start;
734 ltq_port->rx_irq = irqres[1].start;
735 ltq_port->err_irq = irqres[2].start;
737 lqasc_port[line] = ltq_port;
738 platform_set_drvdata(pdev, ltq_port);
740 ret = uart_add_one_port(&lqasc_reg, port);
745 static const struct of_device_id ltq_asc_match[] = {
746 { .compatible = DRVNAME },
749 MODULE_DEVICE_TABLE(of, ltq_asc_match);
751 static struct platform_driver lqasc_driver = {
754 .owner = THIS_MODULE,
755 .of_match_table = ltq_asc_match,
764 ret = uart_register_driver(&lqasc_reg);
768 ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
770 uart_unregister_driver(&lqasc_reg);
775 module_init(init_lqasc);
777 MODULE_DESCRIPTION("Lantiq serial port driver");
778 MODULE_LICENSE("GPL");