2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
54 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #include <linux/module.h>
59 #include <linux/moduleparam.h>
60 #include <linux/tty.h>
61 #include <linux/tty_flip.h>
62 #include <linux/ioport.h>
63 #include <linux/init.h>
64 #include <linux/console.h>
65 #include <linux/sysrq.h>
66 #include <linux/serial.h>
67 #include <linux/serial_core.h>
68 #include <linux/delay.h>
69 #include <linux/device.h>
70 #include <linux/dma-mapping.h>
71 #include <linux/mv643xx.h>
72 #include <linux/platform_device.h>
73 #include <linux/gfp.h>
78 #define MPSC_NUM_CTLRS 2
81 * Descriptors and buffers must be cache line aligned.
82 * Buffers lengths must be multiple of cache line size.
83 * Number of Tx & Rx descriptors must be powers of 2.
85 #define MPSC_RXR_ENTRIES 32
86 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
87 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
88 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
89 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
91 #define MPSC_TXR_ENTRIES 32
92 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
93 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
94 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
95 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
97 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
98 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
100 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
101 struct mpsc_rx_desc {
107 } __attribute((packed));
109 struct mpsc_tx_desc {
115 } __attribute((packed));
118 * Some regs that have the erratum that you can't read them are are shared
119 * between the two MPSC controllers. This struct contains those shared regs.
121 struct mpsc_shared_regs {
122 phys_addr_t mpsc_routing_base_p;
123 phys_addr_t sdma_intr_base_p;
125 void __iomem *mpsc_routing_base;
126 void __iomem *sdma_intr_base;
131 u32 SDMA_INTR_CAUSE_m;
132 u32 SDMA_INTR_MASK_m;
135 /* The main driver data structure */
136 struct mpsc_port_info {
137 struct uart_port port; /* Overlay uart_port structure */
139 /* Internal driver state for this ctlr */
142 tcflag_t c_iflag; /* save termios->c_iflag */
143 tcflag_t c_cflag; /* save termios->c_cflag */
145 /* Info passed in from platform */
146 u8 mirror_regs; /* Need to mirror regs? */
147 u8 cache_mgmt; /* Need manual cache mgmt? */
148 u8 brg_can_tune; /* BRG has baud tuning? */
156 /* Physical addresses of various blocks of registers (from platform) */
157 phys_addr_t mpsc_base_p;
158 phys_addr_t sdma_base_p;
159 phys_addr_t brg_base_p;
161 /* Virtual addresses of various blocks of registers (from platform) */
162 void __iomem *mpsc_base;
163 void __iomem *sdma_base;
164 void __iomem *brg_base;
166 /* Descriptor ring and buffer allocations */
168 dma_addr_t dma_region_p;
170 dma_addr_t rxr; /* Rx descriptor ring */
171 dma_addr_t rxr_p; /* Phys addr of rxr */
172 u8 *rxb; /* Rx Ring I/O buf */
173 u8 *rxb_p; /* Phys addr of rxb */
174 u32 rxr_posn; /* First desc w/ Rx data */
176 dma_addr_t txr; /* Tx descriptor ring */
177 dma_addr_t txr_p; /* Phys addr of txr */
178 u8 *txb; /* Tx Ring I/O buf */
179 u8 *txb_p; /* Phys addr of txb */
180 int txr_head; /* Where new data goes */
181 int txr_tail; /* Where sent data comes off */
182 spinlock_t tx_lock; /* transmit lock */
184 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
190 struct mpsc_shared_regs *shared_regs;
193 /* Hooks to platform-specific code */
194 int mpsc_platform_register_driver(void);
195 void mpsc_platform_unregister_driver(void);
197 /* Hooks back in to mpsc common to be called by platform-specific code */
198 struct mpsc_port_info *mpsc_device_probe(int index);
199 struct mpsc_port_info *mpsc_device_remove(int index);
201 /* Main MPSC Configuration Register Offsets */
202 #define MPSC_MMCRL 0x0000
203 #define MPSC_MMCRH 0x0004
204 #define MPSC_MPCR 0x0008
205 #define MPSC_CHR_1 0x000c
206 #define MPSC_CHR_2 0x0010
207 #define MPSC_CHR_3 0x0014
208 #define MPSC_CHR_4 0x0018
209 #define MPSC_CHR_5 0x001c
210 #define MPSC_CHR_6 0x0020
211 #define MPSC_CHR_7 0x0024
212 #define MPSC_CHR_8 0x0028
213 #define MPSC_CHR_9 0x002c
214 #define MPSC_CHR_10 0x0030
215 #define MPSC_CHR_11 0x0034
217 #define MPSC_MPCR_FRZ (1 << 9)
218 #define MPSC_MPCR_CL_5 0
219 #define MPSC_MPCR_CL_6 1
220 #define MPSC_MPCR_CL_7 2
221 #define MPSC_MPCR_CL_8 3
222 #define MPSC_MPCR_SBL_1 0
223 #define MPSC_MPCR_SBL_2 1
225 #define MPSC_CHR_2_TEV (1<<1)
226 #define MPSC_CHR_2_TA (1<<7)
227 #define MPSC_CHR_2_TTCS (1<<9)
228 #define MPSC_CHR_2_REV (1<<17)
229 #define MPSC_CHR_2_RA (1<<23)
230 #define MPSC_CHR_2_CRD (1<<25)
231 #define MPSC_CHR_2_EH (1<<31)
232 #define MPSC_CHR_2_PAR_ODD 0
233 #define MPSC_CHR_2_PAR_SPACE 1
234 #define MPSC_CHR_2_PAR_EVEN 2
235 #define MPSC_CHR_2_PAR_MARK 3
237 /* MPSC Signal Routing */
238 #define MPSC_MRR 0x0000
239 #define MPSC_RCRR 0x0004
240 #define MPSC_TCRR 0x0008
242 /* Serial DMA Controller Interface Registers */
243 #define SDMA_SDC 0x0000
244 #define SDMA_SDCM 0x0008
245 #define SDMA_RX_DESC 0x0800
246 #define SDMA_RX_BUF_PTR 0x0808
247 #define SDMA_SCRDP 0x0810
248 #define SDMA_TX_DESC 0x0c00
249 #define SDMA_SCTDP 0x0c10
250 #define SDMA_SFTDP 0x0c14
252 #define SDMA_DESC_CMDSTAT_PE (1<<0)
253 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
254 #define SDMA_DESC_CMDSTAT_FR (1<<3)
255 #define SDMA_DESC_CMDSTAT_OR (1<<6)
256 #define SDMA_DESC_CMDSTAT_BR (1<<9)
257 #define SDMA_DESC_CMDSTAT_MI (1<<10)
258 #define SDMA_DESC_CMDSTAT_A (1<<11)
259 #define SDMA_DESC_CMDSTAT_AM (1<<12)
260 #define SDMA_DESC_CMDSTAT_CT (1<<13)
261 #define SDMA_DESC_CMDSTAT_C (1<<14)
262 #define SDMA_DESC_CMDSTAT_ES (1<<15)
263 #define SDMA_DESC_CMDSTAT_L (1<<16)
264 #define SDMA_DESC_CMDSTAT_F (1<<17)
265 #define SDMA_DESC_CMDSTAT_P (1<<18)
266 #define SDMA_DESC_CMDSTAT_EI (1<<23)
267 #define SDMA_DESC_CMDSTAT_O (1<<31)
269 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
270 | SDMA_DESC_CMDSTAT_EI)
272 #define SDMA_SDC_RFT (1<<0)
273 #define SDMA_SDC_SFM (1<<1)
274 #define SDMA_SDC_BLMR (1<<6)
275 #define SDMA_SDC_BLMT (1<<7)
276 #define SDMA_SDC_POVR (1<<8)
277 #define SDMA_SDC_RIFB (1<<9)
279 #define SDMA_SDCM_ERD (1<<7)
280 #define SDMA_SDCM_AR (1<<15)
281 #define SDMA_SDCM_STD (1<<16)
282 #define SDMA_SDCM_TXD (1<<23)
283 #define SDMA_SDCM_AT (1<<31)
285 #define SDMA_0_CAUSE_RXBUF (1<<0)
286 #define SDMA_0_CAUSE_RXERR (1<<1)
287 #define SDMA_0_CAUSE_TXBUF (1<<2)
288 #define SDMA_0_CAUSE_TXEND (1<<3)
289 #define SDMA_1_CAUSE_RXBUF (1<<8)
290 #define SDMA_1_CAUSE_RXERR (1<<9)
291 #define SDMA_1_CAUSE_TXBUF (1<<10)
292 #define SDMA_1_CAUSE_TXEND (1<<11)
294 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
295 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
296 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
297 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
299 /* SDMA Interrupt registers */
300 #define SDMA_INTR_CAUSE 0x0000
301 #define SDMA_INTR_MASK 0x0080
303 /* Baud Rate Generator Interface Registers */
304 #define BRG_BCR 0x0000
305 #define BRG_BTR 0x0004
308 * Define how this driver is known to the outside (we've been assigned a
309 * range on the "Low-density serial ports" major).
311 #define MPSC_MAJOR 204
312 #define MPSC_MINOR_START 44
313 #define MPSC_DRIVER_NAME "MPSC"
314 #define MPSC_DEV_NAME "ttyMM"
315 #define MPSC_VERSION "1.00"
317 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
318 static struct mpsc_shared_regs mpsc_shared_regs;
319 static struct uart_driver mpsc_reg;
321 static void mpsc_start_rx(struct mpsc_port_info *pi);
322 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
323 static void mpsc_release_port(struct uart_port *port);
325 ******************************************************************************
327 * Baud Rate Generator Routines (BRG)
329 ******************************************************************************
331 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
335 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
336 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
338 if (pi->brg_can_tune)
343 writel(v, pi->brg_base + BRG_BCR);
345 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
346 pi->brg_base + BRG_BTR);
349 static void mpsc_brg_enable(struct mpsc_port_info *pi)
353 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
358 writel(v, pi->brg_base + BRG_BCR);
361 static void mpsc_brg_disable(struct mpsc_port_info *pi)
365 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
370 writel(v, pi->brg_base + BRG_BCR);
374 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
375 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
376 * However, the input clock is divided by 16 in the MPSC b/c of how
377 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
378 * calculation by 16 to account for that. So the real calculation
379 * that accounts for the way the mpsc is set up is:
380 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
382 static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
384 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
387 mpsc_brg_disable(pi);
388 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
389 v = (v & 0xffff0000) | (cdv & 0xffff);
393 writel(v, pi->brg_base + BRG_BCR);
398 ******************************************************************************
400 * Serial DMA Routines (SDMA)
402 ******************************************************************************
405 static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
409 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
410 pi->port.line, burst_size);
412 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
415 v = 0x0; /* 1 64-bit word */
416 else if (burst_size < 4)
417 v = 0x1; /* 2 64-bit words */
418 else if (burst_size < 8)
419 v = 0x2; /* 4 64-bit words */
421 v = 0x3; /* 8 64-bit words */
423 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
424 pi->sdma_base + SDMA_SDC);
427 static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
429 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
432 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
433 pi->sdma_base + SDMA_SDC);
434 mpsc_sdma_burstsize(pi, burst_size);
437 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
441 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
443 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
444 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
452 pi->shared_regs->SDMA_INTR_MASK_m = v;
453 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
460 static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
464 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
466 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
467 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
475 pi->shared_regs->SDMA_INTR_MASK_m = v;
476 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
479 static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
481 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
484 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
485 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
489 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
490 struct mpsc_rx_desc *rxre_p)
492 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
493 pi->port.line, (u32)rxre_p);
495 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
498 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
499 struct mpsc_tx_desc *txre_p)
501 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
502 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
505 static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
509 v = readl(pi->sdma_base + SDMA_SDCM);
515 writel(v, pi->sdma_base + SDMA_SDCM);
519 static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
521 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
524 static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
526 struct mpsc_tx_desc *txre, *txre_p;
528 /* If tx isn't running & there's a desc ready to go, start it */
529 if (!mpsc_sdma_tx_active(pi)) {
530 txre = (struct mpsc_tx_desc *)(pi->txr
531 + (pi->txr_tail * MPSC_TXRE_SIZE));
532 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
534 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
535 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
536 invalidate_dcache_range((ulong)txre,
537 (ulong)txre + MPSC_TXRE_SIZE);
540 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
541 txre_p = (struct mpsc_tx_desc *)
542 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
544 mpsc_sdma_set_tx_ring(pi, txre_p);
545 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
550 static void mpsc_sdma_stop(struct mpsc_port_info *pi)
552 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
554 /* Abort any SDMA transfers */
555 mpsc_sdma_cmd(pi, 0);
556 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
558 /* Clear the SDMA current and first TX and RX pointers */
559 mpsc_sdma_set_tx_ring(pi, NULL);
560 mpsc_sdma_set_rx_ring(pi, NULL);
562 /* Disable interrupts */
563 mpsc_sdma_intr_mask(pi, 0xf);
564 mpsc_sdma_intr_ack(pi);
568 ******************************************************************************
570 * Multi-Protocol Serial Controller Routines (MPSC)
572 ******************************************************************************
575 static void mpsc_hw_init(struct mpsc_port_info *pi)
579 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
581 /* Set up clock routing */
582 if (pi->mirror_regs) {
583 v = pi->shared_regs->MPSC_MRR_m;
585 pi->shared_regs->MPSC_MRR_m = v;
586 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
588 v = pi->shared_regs->MPSC_RCRR_m;
589 v = (v & ~0xf0f) | 0x100;
590 pi->shared_regs->MPSC_RCRR_m = v;
591 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
593 v = pi->shared_regs->MPSC_TCRR_m;
594 v = (v & ~0xf0f) | 0x100;
595 pi->shared_regs->MPSC_TCRR_m = v;
596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
598 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
600 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
602 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
603 v = (v & ~0xf0f) | 0x100;
604 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
606 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
607 v = (v & ~0xf0f) | 0x100;
608 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
611 /* Put MPSC in UART mode & enabel Tx/Rx egines */
612 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
614 /* No preamble, 16x divider, low-latency, */
615 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
616 mpsc_set_baudrate(pi, pi->default_baud);
618 if (pi->mirror_regs) {
619 pi->MPSC_CHR_1_m = 0;
620 pi->MPSC_CHR_2_m = 0;
622 writel(0, pi->mpsc_base + MPSC_CHR_1);
623 writel(0, pi->mpsc_base + MPSC_CHR_2);
624 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
625 writel(0, pi->mpsc_base + MPSC_CHR_4);
626 writel(0, pi->mpsc_base + MPSC_CHR_5);
627 writel(0, pi->mpsc_base + MPSC_CHR_6);
628 writel(0, pi->mpsc_base + MPSC_CHR_7);
629 writel(0, pi->mpsc_base + MPSC_CHR_8);
630 writel(0, pi->mpsc_base + MPSC_CHR_9);
631 writel(0, pi->mpsc_base + MPSC_CHR_10);
634 static void mpsc_enter_hunt(struct mpsc_port_info *pi)
636 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
638 if (pi->mirror_regs) {
639 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
640 pi->mpsc_base + MPSC_CHR_2);
641 /* Erratum prevents reading CHR_2 so just delay for a while */
644 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
645 pi->mpsc_base + MPSC_CHR_2);
647 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
652 static void mpsc_freeze(struct mpsc_port_info *pi)
656 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
658 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
659 readl(pi->mpsc_base + MPSC_MPCR);
664 writel(v, pi->mpsc_base + MPSC_MPCR);
667 static void mpsc_unfreeze(struct mpsc_port_info *pi)
671 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
672 readl(pi->mpsc_base + MPSC_MPCR);
677 writel(v, pi->mpsc_base + MPSC_MPCR);
679 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
682 static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
686 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
688 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
689 readl(pi->mpsc_base + MPSC_MPCR);
690 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
694 writel(v, pi->mpsc_base + MPSC_MPCR);
697 static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
701 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
704 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
705 readl(pi->mpsc_base + MPSC_MPCR);
707 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
711 writel(v, pi->mpsc_base + MPSC_MPCR);
714 static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
718 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
720 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
721 readl(pi->mpsc_base + MPSC_CHR_2);
724 v = (v & ~0xc000c) | (p << 18) | (p << 2);
727 pi->MPSC_CHR_2_m = v;
728 writel(v, pi->mpsc_base + MPSC_CHR_2);
732 ******************************************************************************
734 * Driver Init Routines
736 ******************************************************************************
739 static void mpsc_init_hw(struct mpsc_port_info *pi)
741 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
743 mpsc_brg_init(pi, pi->brg_clk_src);
745 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
750 static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
754 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
757 if (!pi->dma_region) {
758 if (!dma_supported(pi->port.dev, 0xffffffff)) {
759 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
761 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
763 &pi->dma_region_p, GFP_KERNEL))
765 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
773 static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
775 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
777 if (pi->dma_region) {
778 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
779 pi->dma_region, pi->dma_region_p);
780 pi->dma_region = NULL;
781 pi->dma_region_p = (dma_addr_t)NULL;
785 static void mpsc_init_rings(struct mpsc_port_info *pi)
787 struct mpsc_rx_desc *rxre;
788 struct mpsc_tx_desc *txre;
793 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
795 BUG_ON(pi->dma_region == NULL);
797 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
800 * Descriptors & buffers are multiples of cacheline size and must be
803 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
804 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
807 * Partition dma region into rx ring descriptor, rx buffers,
808 * tx ring descriptors, and tx buffers.
813 dp_p += MPSC_RXR_SIZE;
816 pi->rxb_p = (u8 *)dp_p;
818 dp_p += MPSC_RXB_SIZE;
825 dp_p += MPSC_TXR_SIZE;
828 pi->txb_p = (u8 *)dp_p;
833 /* Init rx ring descriptors */
839 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
840 rxre = (struct mpsc_rx_desc *)dp;
842 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
843 rxre->bytecnt = cpu_to_be16(0);
844 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
845 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
846 | SDMA_DESC_CMDSTAT_L);
847 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
848 rxre->buf_ptr = cpu_to_be32(bp_p);
850 dp += MPSC_RXRE_SIZE;
851 dp_p += MPSC_RXRE_SIZE;
852 bp += MPSC_RXBE_SIZE;
853 bp_p += MPSC_RXBE_SIZE;
855 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
857 /* Init tx ring descriptors */
863 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
864 txre = (struct mpsc_tx_desc *)dp;
866 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
867 txre->buf_ptr = cpu_to_be32(bp_p);
869 dp += MPSC_TXRE_SIZE;
870 dp_p += MPSC_TXRE_SIZE;
871 bp += MPSC_TXBE_SIZE;
872 bp_p += MPSC_TXBE_SIZE;
874 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
876 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
877 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
878 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
879 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
880 flush_dcache_range((ulong)pi->dma_region,
881 (ulong)pi->dma_region
882 + MPSC_DMA_ALLOC_SIZE);
888 static void mpsc_uninit_rings(struct mpsc_port_info *pi)
890 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
892 BUG_ON(pi->dma_region == NULL);
908 static int mpsc_make_ready(struct mpsc_port_info *pi)
912 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
916 if ((rc = mpsc_alloc_ring_mem(pi)))
925 #ifdef CONFIG_CONSOLE_POLL
926 static int serial_polled;
930 ******************************************************************************
932 * Interrupt Handling Routines
934 ******************************************************************************
937 static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags)
939 struct mpsc_rx_desc *rxre;
940 struct tty_port *port = &pi->port.state->port;
941 u32 cmdstat, bytes_in, i;
944 char flag = TTY_NORMAL;
946 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
948 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
950 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
952 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
953 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
954 invalidate_dcache_range((ulong)rxre,
955 (ulong)rxre + MPSC_RXRE_SIZE);
959 * Loop through Rx descriptors handling ones that have been completed.
961 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
962 & SDMA_DESC_CMDSTAT_O)) {
963 bytes_in = be16_to_cpu(rxre->bytecnt);
964 #ifdef CONFIG_CONSOLE_POLL
965 if (unlikely(serial_polled)) {
970 /* Following use of tty struct directly is deprecated */
971 if (tty_buffer_request_room(port, bytes_in) < bytes_in) {
972 if (port->low_latency) {
973 spin_unlock_irqrestore(&pi->port.lock, *flags);
974 tty_flip_buffer_push(port);
975 spin_lock_irqsave(&pi->port.lock, *flags);
978 * If this failed then we will throw away the bytes
979 * but must do so to clear interrupts.
983 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
984 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
986 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
987 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
988 invalidate_dcache_range((ulong)bp,
989 (ulong)bp + MPSC_RXBE_SIZE);
993 * Other than for parity error, the manual provides little
994 * info on what data will be in a frame flagged by any of
995 * these errors. For parity error, it is the last byte in
996 * the buffer that had the error. As for the rest, I guess
997 * we'll assume there is no data in the buffer.
998 * If there is...it gets lost.
1000 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1001 | SDMA_DESC_CMDSTAT_FR
1002 | SDMA_DESC_CMDSTAT_OR))) {
1004 pi->port.icount.rx++;
1006 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1007 pi->port.icount.brk++;
1009 if (uart_handle_break(&pi->port))
1011 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1012 pi->port.icount.frame++;
1013 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1014 pi->port.icount.overrun++;
1017 cmdstat &= pi->port.read_status_mask;
1019 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1021 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1023 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1025 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1029 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1032 #ifdef CONFIG_CONSOLE_POLL
1033 if (unlikely(serial_polled)) {
1041 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1042 | SDMA_DESC_CMDSTAT_FR
1043 | SDMA_DESC_CMDSTAT_OR)))
1044 && !(cmdstat & pi->port.ignore_status_mask)) {
1045 tty_insert_flip_char(port, *bp, flag);
1047 for (i=0; i<bytes_in; i++)
1048 tty_insert_flip_char(port, *bp++, TTY_NORMAL);
1050 pi->port.icount.rx += bytes_in;
1054 rxre->bytecnt = cpu_to_be16(0);
1056 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1057 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1058 | SDMA_DESC_CMDSTAT_L);
1060 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1062 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1063 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1064 flush_dcache_range((ulong)rxre,
1065 (ulong)rxre + MPSC_RXRE_SIZE);
1068 /* Advance to next descriptor */
1069 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1070 rxre = (struct mpsc_rx_desc *)
1071 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1072 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1074 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1075 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1076 invalidate_dcache_range((ulong)rxre,
1077 (ulong)rxre + MPSC_RXRE_SIZE);
1082 /* Restart rx engine, if its stopped */
1083 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1086 spin_unlock_irqrestore(&pi->port.lock, *flags);
1087 tty_flip_buffer_push(port);
1088 spin_lock_irqsave(&pi->port.lock, *flags);
1092 static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1094 struct mpsc_tx_desc *txre;
1096 txre = (struct mpsc_tx_desc *)(pi->txr
1097 + (pi->txr_head * MPSC_TXRE_SIZE));
1099 txre->bytecnt = cpu_to_be16(count);
1100 txre->shadow = txre->bytecnt;
1101 wmb(); /* ensure cmdstat is last field updated */
1102 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1103 | SDMA_DESC_CMDSTAT_L
1104 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1106 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1108 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1109 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1110 flush_dcache_range((ulong)txre,
1111 (ulong)txre + MPSC_TXRE_SIZE);
1115 static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1117 struct circ_buf *xmit = &pi->port.state->xmit;
1121 /* Make sure the desc ring isn't full */
1122 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1123 < (MPSC_TXR_ENTRIES - 1)) {
1124 if (pi->port.x_char) {
1126 * Ideally, we should use the TCS field in
1127 * CHR_1 to put the x_char out immediately but
1128 * errata prevents us from being able to read
1129 * CHR_2 to know that its safe to write to
1130 * CHR_1. Instead, just put it in-band with
1131 * all the other Tx data.
1133 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1134 *bp = pi->port.x_char;
1135 pi->port.x_char = 0;
1137 } else if (!uart_circ_empty(xmit)
1138 && !uart_tx_stopped(&pi->port)) {
1139 i = min((u32)MPSC_TXBE_SIZE,
1140 (u32)uart_circ_chars_pending(xmit));
1141 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1143 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1144 memcpy(bp, &xmit->buf[xmit->tail], i);
1145 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1147 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1148 uart_write_wakeup(&pi->port);
1149 } else { /* All tx data copied into ring bufs */
1153 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1155 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1156 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1157 flush_dcache_range((ulong)bp,
1158 (ulong)bp + MPSC_TXBE_SIZE);
1160 mpsc_setup_tx_desc(pi, i, 1);
1162 /* Advance to next descriptor */
1163 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1167 static int mpsc_tx_intr(struct mpsc_port_info *pi)
1169 struct mpsc_tx_desc *txre;
1171 unsigned long iflags;
1173 spin_lock_irqsave(&pi->tx_lock, iflags);
1175 if (!mpsc_sdma_tx_active(pi)) {
1176 txre = (struct mpsc_tx_desc *)(pi->txr
1177 + (pi->txr_tail * MPSC_TXRE_SIZE));
1179 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1181 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1182 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1183 invalidate_dcache_range((ulong)txre,
1184 (ulong)txre + MPSC_TXRE_SIZE);
1187 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1189 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1190 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1192 /* If no more data to tx, fall out of loop */
1193 if (pi->txr_head == pi->txr_tail)
1196 txre = (struct mpsc_tx_desc *)(pi->txr
1197 + (pi->txr_tail * MPSC_TXRE_SIZE));
1198 dma_cache_sync(pi->port.dev, (void *)txre,
1199 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1200 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1201 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1202 invalidate_dcache_range((ulong)txre,
1203 (ulong)txre + MPSC_TXRE_SIZE);
1207 mpsc_copy_tx_data(pi);
1208 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1211 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1216 * This is the driver's interrupt handler. To avoid a race, we first clear
1217 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1218 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1220 static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1222 struct mpsc_port_info *pi = dev_id;
1226 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1228 spin_lock_irqsave(&pi->port.lock, iflags);
1229 mpsc_sdma_intr_ack(pi);
1230 if (mpsc_rx_intr(pi, &iflags))
1232 if (mpsc_tx_intr(pi))
1234 spin_unlock_irqrestore(&pi->port.lock, iflags);
1236 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1241 ******************************************************************************
1243 * serial_core.c Interface routines
1245 ******************************************************************************
1247 static uint mpsc_tx_empty(struct uart_port *port)
1249 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1253 spin_lock_irqsave(&pi->port.lock, iflags);
1254 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1255 spin_unlock_irqrestore(&pi->port.lock, iflags);
1260 static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1262 /* Have no way to set modem control lines AFAICT */
1265 static uint mpsc_get_mctrl(struct uart_port *port)
1267 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1270 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1271 : readl(pi->mpsc_base + MPSC_CHR_10);
1275 mflags |= TIOCM_CTS;
1277 mflags |= TIOCM_CAR;
1279 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1282 static void mpsc_stop_tx(struct uart_port *port)
1284 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1286 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1291 static void mpsc_start_tx(struct uart_port *port)
1293 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1294 unsigned long iflags;
1296 spin_lock_irqsave(&pi->tx_lock, iflags);
1299 mpsc_copy_tx_data(pi);
1300 mpsc_sdma_start_tx(pi);
1302 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1304 pr_debug("mpsc_start_tx[%d]\n", port->line);
1307 static void mpsc_start_rx(struct mpsc_port_info *pi)
1309 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1312 mpsc_enter_hunt(pi);
1313 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1317 static void mpsc_stop_rx(struct uart_port *port)
1319 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1321 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1323 if (pi->mirror_regs) {
1324 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1325 pi->mpsc_base + MPSC_CHR_2);
1326 /* Erratum prevents reading CHR_2 so just delay for a while */
1329 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
1330 pi->mpsc_base + MPSC_CHR_2);
1332 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1336 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1339 static void mpsc_break_ctl(struct uart_port *port, int ctl)
1341 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1345 v = ctl ? 0x00ff0000 : 0;
1347 spin_lock_irqsave(&pi->port.lock, flags);
1348 if (pi->mirror_regs)
1349 pi->MPSC_CHR_1_m = v;
1350 writel(v, pi->mpsc_base + MPSC_CHR_1);
1351 spin_unlock_irqrestore(&pi->port.lock, flags);
1354 static int mpsc_startup(struct uart_port *port)
1356 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1360 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1361 port->line, pi->port.irq);
1363 if ((rc = mpsc_make_ready(pi)) == 0) {
1364 /* Setup IRQ handler */
1365 mpsc_sdma_intr_ack(pi);
1367 /* If irq's are shared, need to set flag */
1368 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1371 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1373 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1376 mpsc_sdma_intr_unmask(pi, 0xf);
1377 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1378 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1384 static void mpsc_shutdown(struct uart_port *port)
1386 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1388 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1391 free_irq(pi->port.irq, pi);
1394 static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1395 struct ktermios *old)
1397 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1400 u32 chr_bits, stop_bits, par;
1402 pi->c_iflag = termios->c_iflag;
1403 pi->c_cflag = termios->c_cflag;
1405 switch (termios->c_cflag & CSIZE) {
1407 chr_bits = MPSC_MPCR_CL_5;
1410 chr_bits = MPSC_MPCR_CL_6;
1413 chr_bits = MPSC_MPCR_CL_7;
1417 chr_bits = MPSC_MPCR_CL_8;
1421 if (termios->c_cflag & CSTOPB)
1422 stop_bits = MPSC_MPCR_SBL_2;
1424 stop_bits = MPSC_MPCR_SBL_1;
1426 par = MPSC_CHR_2_PAR_EVEN;
1427 if (termios->c_cflag & PARENB)
1428 if (termios->c_cflag & PARODD)
1429 par = MPSC_CHR_2_PAR_ODD;
1431 if (termios->c_cflag & CMSPAR) {
1432 if (termios->c_cflag & PARODD)
1433 par = MPSC_CHR_2_PAR_MARK;
1435 par = MPSC_CHR_2_PAR_SPACE;
1439 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1441 spin_lock_irqsave(&pi->port.lock, flags);
1443 uart_update_timeout(port, termios->c_cflag, baud);
1445 mpsc_set_char_length(pi, chr_bits);
1446 mpsc_set_stop_bit_length(pi, stop_bits);
1447 mpsc_set_parity(pi, par);
1448 mpsc_set_baudrate(pi, baud);
1450 /* Characters/events to read */
1451 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1453 if (termios->c_iflag & INPCK)
1454 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1455 | SDMA_DESC_CMDSTAT_FR;
1457 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1458 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1460 /* Characters/events to ignore */
1461 pi->port.ignore_status_mask = 0;
1463 if (termios->c_iflag & IGNPAR)
1464 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1465 | SDMA_DESC_CMDSTAT_FR;
1467 if (termios->c_iflag & IGNBRK) {
1468 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1470 if (termios->c_iflag & IGNPAR)
1471 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1474 if ((termios->c_cflag & CREAD)) {
1475 if (!pi->rcv_data) {
1479 } else if (pi->rcv_data) {
1484 spin_unlock_irqrestore(&pi->port.lock, flags);
1487 static const char *mpsc_type(struct uart_port *port)
1489 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1490 return MPSC_DRIVER_NAME;
1493 static int mpsc_request_port(struct uart_port *port)
1495 /* Should make chip/platform specific call */
1499 static void mpsc_release_port(struct uart_port *port)
1501 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1504 mpsc_uninit_rings(pi);
1505 mpsc_free_ring_mem(pi);
1510 static void mpsc_config_port(struct uart_port *port, int flags)
1514 static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1516 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1519 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1521 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1523 else if (pi->port.irq != ser->irq)
1525 else if (ser->io_type != SERIAL_IO_MEM)
1527 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1529 else if ((void *)pi->port.mapbase != ser->iomem_base)
1531 else if (pi->port.iobase != ser->port)
1533 else if (ser->hub6 != 0)
1538 #ifdef CONFIG_CONSOLE_POLL
1539 /* Serial polling routines for writing and reading from the uart while
1540 * in an interrupt or debug context.
1543 static char poll_buf[2048];
1544 static int poll_ptr;
1545 static int poll_cnt;
1546 static void mpsc_put_poll_char(struct uart_port *port,
1549 static int mpsc_get_poll_char(struct uart_port *port)
1551 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1552 struct mpsc_rx_desc *rxre;
1553 u32 cmdstat, bytes_in, i;
1559 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1563 return poll_buf[poll_ptr++];
1568 while (poll_cnt == 0) {
1569 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1570 (pi->rxr_posn*MPSC_RXRE_SIZE));
1571 dma_cache_sync(pi->port.dev, (void *)rxre,
1572 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1573 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1574 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1575 invalidate_dcache_range((ulong)rxre,
1576 (ulong)rxre + MPSC_RXRE_SIZE);
1579 * Loop through Rx descriptors handling ones that have
1582 while (poll_cnt == 0 &&
1583 !((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1584 SDMA_DESC_CMDSTAT_O)){
1585 bytes_in = be16_to_cpu(rxre->bytecnt);
1586 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1587 dma_cache_sync(pi->port.dev, (void *) bp,
1588 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1589 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1590 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1591 invalidate_dcache_range((ulong)bp,
1592 (ulong)bp + MPSC_RXBE_SIZE);
1594 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1595 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1596 !(cmdstat & pi->port.ignore_status_mask)) {
1597 poll_buf[poll_cnt] = *bp;
1600 for (i = 0; i < bytes_in; i++) {
1601 poll_buf[poll_cnt] = *bp++;
1604 pi->port.icount.rx += bytes_in;
1606 rxre->bytecnt = cpu_to_be16(0);
1608 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1609 SDMA_DESC_CMDSTAT_EI |
1610 SDMA_DESC_CMDSTAT_F |
1611 SDMA_DESC_CMDSTAT_L);
1613 dma_cache_sync(pi->port.dev, (void *)rxre,
1614 MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1615 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1616 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1617 flush_dcache_range((ulong)rxre,
1618 (ulong)rxre + MPSC_RXRE_SIZE);
1621 /* Advance to next descriptor */
1622 pi->rxr_posn = (pi->rxr_posn + 1) &
1623 (MPSC_RXR_ENTRIES - 1);
1624 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1625 (pi->rxr_posn * MPSC_RXRE_SIZE));
1626 dma_cache_sync(pi->port.dev, (void *)rxre,
1627 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1628 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1629 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1630 invalidate_dcache_range((ulong)rxre,
1631 (ulong)rxre + MPSC_RXRE_SIZE);
1635 /* Restart rx engine, if its stopped */
1636 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1641 return poll_buf[poll_ptr++];
1648 static void mpsc_put_poll_char(struct uart_port *port,
1651 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1654 data = readl(pi->mpsc_base + MPSC_MPCR);
1655 writeb(c, pi->mpsc_base + MPSC_CHR_1);
1657 data = readl(pi->mpsc_base + MPSC_CHR_2);
1658 data |= MPSC_CHR_2_TTCS;
1659 writel(data, pi->mpsc_base + MPSC_CHR_2);
1662 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1666 static struct uart_ops mpsc_pops = {
1667 .tx_empty = mpsc_tx_empty,
1668 .set_mctrl = mpsc_set_mctrl,
1669 .get_mctrl = mpsc_get_mctrl,
1670 .stop_tx = mpsc_stop_tx,
1671 .start_tx = mpsc_start_tx,
1672 .stop_rx = mpsc_stop_rx,
1673 .break_ctl = mpsc_break_ctl,
1674 .startup = mpsc_startup,
1675 .shutdown = mpsc_shutdown,
1676 .set_termios = mpsc_set_termios,
1678 .release_port = mpsc_release_port,
1679 .request_port = mpsc_request_port,
1680 .config_port = mpsc_config_port,
1681 .verify_port = mpsc_verify_port,
1682 #ifdef CONFIG_CONSOLE_POLL
1683 .poll_get_char = mpsc_get_poll_char,
1684 .poll_put_char = mpsc_put_poll_char,
1689 ******************************************************************************
1691 * Console Interface Routines
1693 ******************************************************************************
1696 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1697 static void mpsc_console_write(struct console *co, const char *s, uint count)
1699 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1700 u8 *bp, *dp, add_cr = 0;
1702 unsigned long iflags;
1704 spin_lock_irqsave(&pi->tx_lock, iflags);
1706 while (pi->txr_head != pi->txr_tail) {
1707 while (mpsc_sdma_tx_active(pi))
1709 mpsc_sdma_intr_ack(pi);
1713 while (mpsc_sdma_tx_active(pi))
1717 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1719 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1729 if (*(s++) == '\n') { /* add '\r' after '\n' */
1738 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1740 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1741 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1742 flush_dcache_range((ulong)bp,
1743 (ulong)bp + MPSC_TXBE_SIZE);
1745 mpsc_setup_tx_desc(pi, i, 0);
1746 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1747 mpsc_sdma_start_tx(pi);
1749 while (mpsc_sdma_tx_active(pi))
1752 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1755 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1758 static int __init mpsc_console_setup(struct console *co, char *options)
1760 struct mpsc_port_info *pi;
1761 int baud, bits, parity, flow;
1763 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1765 if (co->index >= MPSC_NUM_CTLRS)
1768 pi = &mpsc_ports[co->index];
1770 baud = pi->default_baud;
1771 bits = pi->default_bits;
1772 parity = pi->default_parity;
1773 flow = pi->default_flow;
1778 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1781 uart_parse_options(options, &baud, &parity, &bits, &flow);
1783 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1786 static struct console mpsc_console = {
1787 .name = MPSC_DEV_NAME,
1788 .write = mpsc_console_write,
1789 .device = uart_console_device,
1790 .setup = mpsc_console_setup,
1791 .flags = CON_PRINTBUFFER,
1796 static int __init mpsc_late_console_init(void)
1798 pr_debug("mpsc_late_console_init: Enter\n");
1800 if (!(mpsc_console.flags & CON_ENABLED))
1801 register_console(&mpsc_console);
1805 late_initcall(mpsc_late_console_init);
1807 #define MPSC_CONSOLE &mpsc_console
1809 #define MPSC_CONSOLE NULL
1812 ******************************************************************************
1814 * Dummy Platform Driver to extract & map shared register regions
1816 ******************************************************************************
1818 static void mpsc_resource_err(char *s)
1820 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1823 static int mpsc_shared_map_regs(struct platform_device *pd)
1827 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1828 MPSC_ROUTING_BASE_ORDER))
1829 && request_mem_region(r->start,
1830 MPSC_ROUTING_REG_BLOCK_SIZE,
1831 "mpsc_routing_regs")) {
1832 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1833 MPSC_ROUTING_REG_BLOCK_SIZE);
1834 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1836 mpsc_resource_err("MPSC routing base");
1840 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1841 MPSC_SDMA_INTR_BASE_ORDER))
1842 && request_mem_region(r->start,
1843 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1844 "sdma_intr_regs")) {
1845 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1846 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1847 mpsc_shared_regs.sdma_intr_base_p = r->start;
1849 iounmap(mpsc_shared_regs.mpsc_routing_base);
1850 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1851 MPSC_ROUTING_REG_BLOCK_SIZE);
1852 mpsc_resource_err("SDMA intr base");
1859 static void mpsc_shared_unmap_regs(void)
1861 if (!mpsc_shared_regs.mpsc_routing_base) {
1862 iounmap(mpsc_shared_regs.mpsc_routing_base);
1863 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1864 MPSC_ROUTING_REG_BLOCK_SIZE);
1866 if (!mpsc_shared_regs.sdma_intr_base) {
1867 iounmap(mpsc_shared_regs.sdma_intr_base);
1868 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1869 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1872 mpsc_shared_regs.mpsc_routing_base = NULL;
1873 mpsc_shared_regs.sdma_intr_base = NULL;
1875 mpsc_shared_regs.mpsc_routing_base_p = 0;
1876 mpsc_shared_regs.sdma_intr_base_p = 0;
1879 static int mpsc_shared_drv_probe(struct platform_device *dev)
1881 struct mpsc_shared_pdata *pdata;
1885 if (!(rc = mpsc_shared_map_regs(dev))) {
1886 pdata = (struct mpsc_shared_pdata *)
1887 dev_get_platdata(&dev->dev);
1889 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1890 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1891 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1892 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1893 pdata->intr_cause_val;
1894 mpsc_shared_regs.SDMA_INTR_MASK_m =
1895 pdata->intr_mask_val;
1904 static int mpsc_shared_drv_remove(struct platform_device *dev)
1909 mpsc_shared_unmap_regs();
1910 mpsc_shared_regs.MPSC_MRR_m = 0;
1911 mpsc_shared_regs.MPSC_RCRR_m = 0;
1912 mpsc_shared_regs.MPSC_TCRR_m = 0;
1913 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1914 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1921 static struct platform_driver mpsc_shared_driver = {
1922 .probe = mpsc_shared_drv_probe,
1923 .remove = mpsc_shared_drv_remove,
1925 .name = MPSC_SHARED_NAME,
1930 ******************************************************************************
1932 * Driver Interface Routines
1934 ******************************************************************************
1936 static struct uart_driver mpsc_reg = {
1937 .owner = THIS_MODULE,
1938 .driver_name = MPSC_DRIVER_NAME,
1939 .dev_name = MPSC_DEV_NAME,
1940 .major = MPSC_MAJOR,
1941 .minor = MPSC_MINOR_START,
1942 .nr = MPSC_NUM_CTLRS,
1943 .cons = MPSC_CONSOLE,
1946 static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1947 struct platform_device *pd)
1951 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1952 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1954 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1955 pi->mpsc_base_p = r->start;
1957 mpsc_resource_err("MPSC base");
1961 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1962 MPSC_SDMA_BASE_ORDER))
1963 && request_mem_region(r->start,
1964 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1965 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1966 pi->sdma_base_p = r->start;
1968 mpsc_resource_err("SDMA base");
1969 if (pi->mpsc_base) {
1970 iounmap(pi->mpsc_base);
1971 pi->mpsc_base = NULL;
1976 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1977 && request_mem_region(r->start,
1978 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1979 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1980 pi->brg_base_p = r->start;
1982 mpsc_resource_err("BRG base");
1983 if (pi->mpsc_base) {
1984 iounmap(pi->mpsc_base);
1985 pi->mpsc_base = NULL;
1987 if (pi->sdma_base) {
1988 iounmap(pi->sdma_base);
1989 pi->sdma_base = NULL;
1999 static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
2001 if (!pi->mpsc_base) {
2002 iounmap(pi->mpsc_base);
2003 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2005 if (!pi->sdma_base) {
2006 iounmap(pi->sdma_base);
2007 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2009 if (!pi->brg_base) {
2010 iounmap(pi->brg_base);
2011 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2014 pi->mpsc_base = NULL;
2015 pi->sdma_base = NULL;
2016 pi->brg_base = NULL;
2018 pi->mpsc_base_p = 0;
2019 pi->sdma_base_p = 0;
2023 static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2024 struct platform_device *pd, int num)
2026 struct mpsc_pdata *pdata;
2028 pdata = dev_get_platdata(&pd->dev);
2030 pi->port.uartclk = pdata->brg_clk_freq;
2031 pi->port.iotype = UPIO_MEM;
2032 pi->port.line = num;
2033 pi->port.type = PORT_MPSC;
2034 pi->port.fifosize = MPSC_TXBE_SIZE;
2035 pi->port.membase = pi->mpsc_base;
2036 pi->port.mapbase = (ulong)pi->mpsc_base;
2037 pi->port.ops = &mpsc_pops;
2039 pi->mirror_regs = pdata->mirror_regs;
2040 pi->cache_mgmt = pdata->cache_mgmt;
2041 pi->brg_can_tune = pdata->brg_can_tune;
2042 pi->brg_clk_src = pdata->brg_clk_src;
2043 pi->mpsc_max_idle = pdata->max_idle;
2044 pi->default_baud = pdata->default_baud;
2045 pi->default_bits = pdata->default_bits;
2046 pi->default_parity = pdata->default_parity;
2047 pi->default_flow = pdata->default_flow;
2049 /* Initial values of mirrored regs */
2050 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2051 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2052 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2053 pi->MPSC_MPCR_m = pdata->mpcr_val;
2054 pi->BRG_BCR_m = pdata->bcr_val;
2056 pi->shared_regs = &mpsc_shared_regs;
2058 pi->port.irq = platform_get_irq(pd, 0);
2061 static int mpsc_drv_probe(struct platform_device *dev)
2063 struct mpsc_port_info *pi;
2066 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2068 if (dev->id < MPSC_NUM_CTLRS) {
2069 pi = &mpsc_ports[dev->id];
2071 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
2072 mpsc_drv_get_platform_data(pi, dev, dev->id);
2073 pi->port.dev = &dev->dev;
2075 if (!(rc = mpsc_make_ready(pi))) {
2076 spin_lock_init(&pi->tx_lock);
2077 if (!(rc = uart_add_one_port(&mpsc_reg,
2081 mpsc_release_port((struct uart_port *)
2083 mpsc_drv_unmap_regs(pi);
2086 mpsc_drv_unmap_regs(pi);
2094 static int mpsc_drv_remove(struct platform_device *dev)
2096 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2098 if (dev->id < MPSC_NUM_CTLRS) {
2099 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2100 mpsc_release_port((struct uart_port *)
2101 &mpsc_ports[dev->id].port);
2102 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2109 static struct platform_driver mpsc_driver = {
2110 .probe = mpsc_drv_probe,
2111 .remove = mpsc_drv_remove,
2113 .name = MPSC_CTLR_NAME,
2114 .owner = THIS_MODULE,
2118 static int __init mpsc_drv_init(void)
2122 printk(KERN_INFO "Serial: MPSC driver\n");
2124 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2125 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2127 if (!(rc = uart_register_driver(&mpsc_reg))) {
2128 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
2129 if ((rc = platform_driver_register(&mpsc_driver))) {
2130 platform_driver_unregister(&mpsc_shared_driver);
2131 uart_unregister_driver(&mpsc_reg);
2134 uart_unregister_driver(&mpsc_reg);
2141 static void __exit mpsc_drv_exit(void)
2143 platform_driver_unregister(&mpsc_driver);
2144 platform_driver_unregister(&mpsc_shared_driver);
2145 uart_unregister_driver(&mpsc_reg);
2146 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2147 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2150 module_init(mpsc_drv_init);
2151 module_exit(mpsc_drv_exit);
2153 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2154 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
2155 MODULE_VERSION(MPSC_VERSION);
2156 MODULE_LICENSE("GPL");
2157 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
2158 MODULE_ALIAS("platform:" MPSC_CTLR_NAME);