2 * Driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/atomic.h>
23 #include <linux/hrtimer.h>
24 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
38 #include <linux/of_device.h>
40 #include "msm_serial.h"
43 struct uart_port uart;
48 unsigned int *gsbi_base;
50 unsigned int old_snap_state;
53 static inline void wait_for_xmitr(struct uart_port *port, int bits)
55 if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
56 while ((msm_read(port, UART_ISR) & bits) != bits)
60 static void msm_stop_tx(struct uart_port *port)
62 struct msm_port *msm_port = UART_TO_MSM(port);
64 msm_port->imr &= ~UART_IMR_TXLEV;
65 msm_write(port, msm_port->imr, UART_IMR);
68 static void msm_start_tx(struct uart_port *port)
70 struct msm_port *msm_port = UART_TO_MSM(port);
72 msm_port->imr |= UART_IMR_TXLEV;
73 msm_write(port, msm_port->imr, UART_IMR);
76 static void msm_stop_rx(struct uart_port *port)
78 struct msm_port *msm_port = UART_TO_MSM(port);
80 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
81 msm_write(port, msm_port->imr, UART_IMR);
84 static void msm_enable_ms(struct uart_port *port)
86 struct msm_port *msm_port = UART_TO_MSM(port);
88 msm_port->imr |= UART_IMR_DELTA_CTS;
89 msm_write(port, msm_port->imr, UART_IMR);
92 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
94 struct tty_port *tport = &port->state->port;
95 struct tty_struct *tty = tport->tty;
98 struct msm_port *msm_port = UART_TO_MSM(port);
100 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
101 port->icount.overrun++;
102 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
103 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
106 if (misr & UART_IMR_RXSTALE) {
107 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
108 msm_port->old_snap_state;
109 msm_port->old_snap_state = 0;
111 count = 4 * (msm_read(port, UART_RFWR));
112 msm_port->old_snap_state += count;
115 /* TODO: Precise error reporting */
117 port->icount.rx += count;
122 sr = msm_read(port, UART_SR);
123 if ((sr & UART_SR_RX_READY) == 0) {
124 msm_port->old_snap_state -= count;
127 c = msm_read(port, UARTDM_RF);
128 if (sr & UART_SR_RX_BREAK) {
130 if (uart_handle_break(port))
132 } else if (sr & UART_SR_PAR_FRAME_ERR)
133 port->icount.frame++;
135 /* TODO: handle sysrq */
136 tty_insert_flip_string(tport, (char *)&c,
137 (count > 4) ? 4 : count);
141 tty_flip_buffer_push(tty);
142 if (misr & (UART_IMR_RXSTALE))
143 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
144 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
145 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
148 static void handle_rx(struct uart_port *port)
150 struct tty_port *tport = &port->state->port;
151 struct tty_struct *tty = tport->tty;
155 * Handle overrun. My understanding of the hardware is that overrun
156 * is not tied to the RX buffer, so we handle the case out of band.
158 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
159 port->icount.overrun++;
160 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
161 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
164 /* and now the main RX loop */
165 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
167 char flag = TTY_NORMAL;
169 c = msm_read(port, UART_RF);
171 if (sr & UART_SR_RX_BREAK) {
173 if (uart_handle_break(port))
175 } else if (sr & UART_SR_PAR_FRAME_ERR) {
176 port->icount.frame++;
181 /* Mask conditions we're ignorning. */
182 sr &= port->read_status_mask;
184 if (sr & UART_SR_RX_BREAK) {
186 } else if (sr & UART_SR_PAR_FRAME_ERR) {
190 if (!uart_handle_sysrq_char(port, c))
191 tty_insert_flip_char(tport, c, flag);
194 tty_flip_buffer_push(tty);
197 static void reset_dm_count(struct uart_port *port)
199 wait_for_xmitr(port, UART_ISR_TX_READY);
200 msm_write(port, 1, UARTDM_NCF_TX);
203 static void handle_tx(struct uart_port *port)
205 struct circ_buf *xmit = &port->state->xmit;
206 struct msm_port *msm_port = UART_TO_MSM(port);
210 if (msm_port->is_uartdm)
211 reset_dm_count(port);
213 msm_write(port, port->x_char,
214 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
219 if (msm_port->is_uartdm)
220 reset_dm_count(port);
222 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
223 if (uart_circ_empty(xmit)) {
224 /* disable tx interrupts */
225 msm_port->imr &= ~UART_IMR_TXLEV;
226 msm_write(port, msm_port->imr, UART_IMR);
229 msm_write(port, xmit->buf[xmit->tail],
230 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
232 if (msm_port->is_uartdm)
233 reset_dm_count(port);
235 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
240 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
241 uart_write_wakeup(port);
244 static void handle_delta_cts(struct uart_port *port)
246 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
248 wake_up_interruptible(&port->state->port.delta_msr_wait);
251 static irqreturn_t msm_irq(int irq, void *dev_id)
253 struct uart_port *port = dev_id;
254 struct msm_port *msm_port = UART_TO_MSM(port);
257 spin_lock(&port->lock);
258 misr = msm_read(port, UART_MISR);
259 msm_write(port, 0, UART_IMR); /* disable interrupt */
261 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
262 if (msm_port->is_uartdm)
263 handle_rx_dm(port, misr);
267 if (misr & UART_IMR_TXLEV)
269 if (misr & UART_IMR_DELTA_CTS)
270 handle_delta_cts(port);
272 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
273 spin_unlock(&port->lock);
278 static unsigned int msm_tx_empty(struct uart_port *port)
280 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
283 static unsigned int msm_get_mctrl(struct uart_port *port)
285 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
289 static void msm_reset(struct uart_port *port)
291 /* reset everything */
292 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
293 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
294 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
295 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
296 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
297 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
300 void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
303 mr = msm_read(port, UART_MR1);
305 if (!(mctrl & TIOCM_RTS)) {
306 mr &= ~UART_MR1_RX_RDY_CTL;
307 msm_write(port, mr, UART_MR1);
308 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
310 mr |= UART_MR1_RX_RDY_CTL;
311 msm_write(port, mr, UART_MR1);
315 static void msm_break_ctl(struct uart_port *port, int break_ctl)
318 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
320 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
323 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
325 unsigned int baud_code, rxstale, watermark;
326 struct msm_port *msm_port = UART_TO_MSM(port);
330 baud_code = UART_CSR_300;
334 baud_code = UART_CSR_600;
338 baud_code = UART_CSR_1200;
342 baud_code = UART_CSR_2400;
346 baud_code = UART_CSR_4800;
350 baud_code = UART_CSR_9600;
354 baud_code = UART_CSR_14400;
358 baud_code = UART_CSR_19200;
362 baud_code = UART_CSR_28800;
366 baud_code = UART_CSR_38400;
370 baud_code = UART_CSR_57600;
375 baud_code = UART_CSR_115200;
381 if (msm_port->is_uartdm)
382 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
384 msm_write(port, baud_code, UART_CSR);
386 /* RX stale watermark */
387 watermark = UART_IPR_STALE_LSB & rxstale;
388 watermark |= UART_IPR_RXSTALE_LAST;
389 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
390 msm_write(port, watermark, UART_IPR);
392 /* set RX watermark */
393 watermark = (port->fifosize * 3) / 4;
394 msm_write(port, watermark, UART_RFWR);
396 /* set TX watermark */
397 msm_write(port, 10, UART_TFWR);
399 if (msm_port->is_uartdm) {
400 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
401 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
402 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
409 static void msm_init_clock(struct uart_port *port)
411 struct msm_port *msm_port = UART_TO_MSM(port);
413 clk_enable(msm_port->clk);
414 if (!IS_ERR(msm_port->pclk))
415 clk_enable(msm_port->pclk);
416 msm_serial_set_mnd_regs(port);
419 static int msm_startup(struct uart_port *port)
421 struct msm_port *msm_port = UART_TO_MSM(port);
422 unsigned int data, rfr_level;
425 snprintf(msm_port->name, sizeof(msm_port->name),
426 "msm_serial%d", port->line);
428 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
429 msm_port->name, port);
433 msm_init_clock(port);
435 if (likely(port->fifosize > 12))
436 rfr_level = port->fifosize - 12;
438 rfr_level = port->fifosize;
440 /* set automatic RFR level */
441 data = msm_read(port, UART_MR1);
442 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
443 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
444 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
445 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
446 msm_write(port, data, UART_MR1);
448 /* make sure that RXSTALE count is non-zero */
449 data = msm_read(port, UART_IPR);
450 if (unlikely(!data)) {
451 data |= UART_IPR_RXSTALE_LAST;
452 data |= UART_IPR_STALE_LSB;
453 msm_write(port, data, UART_IPR);
457 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
458 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
460 data = UART_CR_TX_ENABLE;
463 data |= UART_CR_RX_ENABLE;
464 msm_write(port, data, UART_CR); /* enable TX & RX */
466 /* Make sure IPR is not 0 to start with*/
467 if (msm_port->is_uartdm)
468 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
470 /* turn on RX and CTS interrupts */
471 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
472 UART_IMR_CURRENT_CTS;
474 if (msm_port->is_uartdm) {
475 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
476 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
477 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
480 msm_write(port, msm_port->imr, UART_IMR);
484 static void msm_shutdown(struct uart_port *port)
486 struct msm_port *msm_port = UART_TO_MSM(port);
489 msm_write(port, 0, UART_IMR); /* disable interrupts */
491 clk_disable(msm_port->clk);
493 free_irq(port->irq, port);
496 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
497 struct ktermios *old)
500 unsigned int baud, mr;
502 spin_lock_irqsave(&port->lock, flags);
504 /* calculate and set baud rate */
505 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
506 baud = msm_set_baud_rate(port, baud);
507 if (tty_termios_baud_rate(termios))
508 tty_termios_encode_baud_rate(termios, baud, baud);
510 /* calculate parity */
511 mr = msm_read(port, UART_MR2);
512 mr &= ~UART_MR2_PARITY_MODE;
513 if (termios->c_cflag & PARENB) {
514 if (termios->c_cflag & PARODD)
515 mr |= UART_MR2_PARITY_MODE_ODD;
516 else if (termios->c_cflag & CMSPAR)
517 mr |= UART_MR2_PARITY_MODE_SPACE;
519 mr |= UART_MR2_PARITY_MODE_EVEN;
522 /* calculate bits per char */
523 mr &= ~UART_MR2_BITS_PER_CHAR;
524 switch (termios->c_cflag & CSIZE) {
526 mr |= UART_MR2_BITS_PER_CHAR_5;
529 mr |= UART_MR2_BITS_PER_CHAR_6;
532 mr |= UART_MR2_BITS_PER_CHAR_7;
536 mr |= UART_MR2_BITS_PER_CHAR_8;
540 /* calculate stop bits */
541 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
542 if (termios->c_cflag & CSTOPB)
543 mr |= UART_MR2_STOP_BIT_LEN_TWO;
545 mr |= UART_MR2_STOP_BIT_LEN_ONE;
547 /* set parity, bits per char, and stop bit */
548 msm_write(port, mr, UART_MR2);
550 /* calculate and set hardware flow control */
551 mr = msm_read(port, UART_MR1);
552 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
553 if (termios->c_cflag & CRTSCTS) {
554 mr |= UART_MR1_CTS_CTL;
555 mr |= UART_MR1_RX_RDY_CTL;
557 msm_write(port, mr, UART_MR1);
559 /* Configure status bits to ignore based on termio flags. */
560 port->read_status_mask = 0;
561 if (termios->c_iflag & INPCK)
562 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
563 if (termios->c_iflag & (BRKINT | PARMRK))
564 port->read_status_mask |= UART_SR_RX_BREAK;
566 uart_update_timeout(port, termios->c_cflag, baud);
568 spin_unlock_irqrestore(&port->lock, flags);
571 static const char *msm_type(struct uart_port *port)
576 static void msm_release_port(struct uart_port *port)
578 struct platform_device *pdev = to_platform_device(port->dev);
579 struct msm_port *msm_port = UART_TO_MSM(port);
580 struct resource *uart_resource;
581 struct resource *gsbi_resource;
582 resource_size_t size;
584 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
585 if (unlikely(!uart_resource))
587 size = resource_size(uart_resource);
589 release_mem_region(port->mapbase, size);
590 iounmap(port->membase);
591 port->membase = NULL;
593 if (msm_port->gsbi_base) {
594 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
597 gsbi_resource = platform_get_resource(pdev,
600 if (unlikely(!gsbi_resource))
603 size = resource_size(gsbi_resource);
604 release_mem_region(gsbi_resource->start, size);
605 iounmap(msm_port->gsbi_base);
606 msm_port->gsbi_base = NULL;
610 static int msm_request_port(struct uart_port *port)
612 struct msm_port *msm_port = UART_TO_MSM(port);
613 struct platform_device *pdev = to_platform_device(port->dev);
614 struct resource *uart_resource;
615 struct resource *gsbi_resource;
616 resource_size_t size;
619 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
620 if (unlikely(!uart_resource))
623 size = resource_size(uart_resource);
625 if (!request_mem_region(port->mapbase, size, "msm_serial"))
628 port->membase = ioremap(port->mapbase, size);
629 if (!port->membase) {
631 goto fail_release_port;
634 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
635 /* Is this a GSBI-based port? */
637 size = resource_size(gsbi_resource);
639 if (!request_mem_region(gsbi_resource->start, size,
642 goto fail_release_port;
645 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
646 if (!msm_port->gsbi_base) {
648 goto fail_release_gsbi;
655 release_mem_region(gsbi_resource->start, size);
657 release_mem_region(port->mapbase, size);
661 static void msm_config_port(struct uart_port *port, int flags)
663 struct msm_port *msm_port = UART_TO_MSM(port);
665 if (flags & UART_CONFIG_TYPE) {
666 port->type = PORT_MSM;
667 ret = msm_request_port(port);
672 if (msm_port->is_uartdm)
673 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
677 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
679 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
681 if (unlikely(port->irq != ser->irq))
686 static void msm_power(struct uart_port *port, unsigned int state,
687 unsigned int oldstate)
689 struct msm_port *msm_port = UART_TO_MSM(port);
693 clk_enable(msm_port->clk);
694 if (!IS_ERR(msm_port->pclk))
695 clk_enable(msm_port->pclk);
698 clk_disable(msm_port->clk);
699 if (!IS_ERR(msm_port->pclk))
700 clk_disable(msm_port->pclk);
703 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
707 static struct uart_ops msm_uart_pops = {
708 .tx_empty = msm_tx_empty,
709 .set_mctrl = msm_set_mctrl,
710 .get_mctrl = msm_get_mctrl,
711 .stop_tx = msm_stop_tx,
712 .start_tx = msm_start_tx,
713 .stop_rx = msm_stop_rx,
714 .enable_ms = msm_enable_ms,
715 .break_ctl = msm_break_ctl,
716 .startup = msm_startup,
717 .shutdown = msm_shutdown,
718 .set_termios = msm_set_termios,
720 .release_port = msm_release_port,
721 .request_port = msm_request_port,
722 .config_port = msm_config_port,
723 .verify_port = msm_verify_port,
727 static struct msm_port msm_uart_ports[] = {
731 .ops = &msm_uart_pops,
732 .flags = UPF_BOOT_AUTOCONF,
740 .ops = &msm_uart_pops,
741 .flags = UPF_BOOT_AUTOCONF,
749 .ops = &msm_uart_pops,
750 .flags = UPF_BOOT_AUTOCONF,
757 #define UART_NR ARRAY_SIZE(msm_uart_ports)
759 static inline struct uart_port *get_port_from_line(unsigned int line)
761 return &msm_uart_ports[line].uart;
764 #ifdef CONFIG_SERIAL_MSM_CONSOLE
766 static void msm_console_putchar(struct uart_port *port, int c)
768 struct msm_port *msm_port = UART_TO_MSM(port);
770 if (msm_port->is_uartdm)
771 reset_dm_count(port);
773 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
775 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
778 static void msm_console_write(struct console *co, const char *s,
781 struct uart_port *port;
782 struct msm_port *msm_port;
784 BUG_ON(co->index < 0 || co->index >= UART_NR);
786 port = get_port_from_line(co->index);
787 msm_port = UART_TO_MSM(port);
789 spin_lock(&port->lock);
790 uart_console_write(port, s, count, msm_console_putchar);
791 spin_unlock(&port->lock);
794 static int __init msm_console_setup(struct console *co, char *options)
796 struct uart_port *port;
797 struct msm_port *msm_port;
798 int baud, flow, bits, parity;
800 if (unlikely(co->index >= UART_NR || co->index < 0))
803 port = get_port_from_line(co->index);
804 msm_port = UART_TO_MSM(port);
806 if (unlikely(!port->membase))
809 msm_init_clock(port);
812 uart_parse_options(options, &baud, &parity, &bits, &flow);
817 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
820 if (baud < 300 || baud > 115200)
822 msm_set_baud_rate(port, baud);
826 if (msm_port->is_uartdm) {
827 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
828 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
831 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
833 return uart_set_options(port, co, baud, parity, bits, flow);
836 static struct uart_driver msm_uart_driver;
838 static struct console msm_console = {
840 .write = msm_console_write,
841 .device = uart_console_device,
842 .setup = msm_console_setup,
843 .flags = CON_PRINTBUFFER,
845 .data = &msm_uart_driver,
848 #define MSM_CONSOLE (&msm_console)
851 #define MSM_CONSOLE NULL
854 static struct uart_driver msm_uart_driver = {
855 .owner = THIS_MODULE,
856 .driver_name = "msm_serial",
857 .dev_name = "ttyMSM",
862 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
864 static int __init msm_serial_probe(struct platform_device *pdev)
866 struct msm_port *msm_port;
867 struct resource *resource;
868 struct uart_port *port;
872 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
874 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
877 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
879 port = get_port_from_line(pdev->id);
880 port->dev = &pdev->dev;
881 msm_port = UART_TO_MSM(port);
883 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
884 msm_port->is_uartdm = 1;
886 msm_port->is_uartdm = 0;
888 if (msm_port->is_uartdm) {
889 msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
890 msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
892 msm_port->clk = clk_get(&pdev->dev, "uart_clk");
893 msm_port->pclk = ERR_PTR(-ENOENT);
896 if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) &&
897 msm_port->is_uartdm)))
898 return PTR_ERR(msm_port->clk);
900 if (msm_port->is_uartdm)
901 clk_set_rate(msm_port->clk, 1843200);
903 port->uartclk = clk_get_rate(msm_port->clk);
904 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
907 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908 if (unlikely(!resource))
910 port->mapbase = resource->start;
912 irq = platform_get_irq(pdev, 0);
913 if (unlikely(irq < 0))
917 platform_set_drvdata(pdev, port);
919 return uart_add_one_port(&msm_uart_driver, port);
922 static int msm_serial_remove(struct platform_device *pdev)
924 struct msm_port *msm_port = platform_get_drvdata(pdev);
926 clk_put(msm_port->clk);
931 static struct of_device_id msm_match_table[] = {
932 { .compatible = "qcom,msm-uart" },
936 static struct platform_driver msm_platform_driver = {
937 .remove = msm_serial_remove,
939 .name = "msm_serial",
940 .owner = THIS_MODULE,
941 .of_match_table = msm_match_table,
945 static int __init msm_serial_init(void)
949 ret = uart_register_driver(&msm_uart_driver);
953 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
955 uart_unregister_driver(&msm_uart_driver);
957 printk(KERN_INFO "msm_serial: driver initialized\n");
962 static void __exit msm_serial_exit(void)
964 #ifdef CONFIG_SERIAL_MSM_CONSOLE
965 unregister_console(&msm_console);
967 platform_driver_unregister(&msm_platform_driver);
968 uart_unregister_driver(&msm_uart_driver);
971 module_init(msm_serial_init);
972 module_exit(msm_serial_exit);
974 MODULE_AUTHOR("Robert Love <rlove@google.com>");
975 MODULE_DESCRIPTION("Driver for msm7x serial device");
976 MODULE_LICENSE("GPL");