2 * Driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/atomic.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/hrtimer.h>
26 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/irq.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_core.h>
35 #include <linux/serial.h>
36 #include <linux/slab.h>
37 #include <linux/clk.h>
38 #include <linux/platform_device.h>
39 #include <linux/delay.h>
41 #include <linux/of_device.h>
43 #include "msm_serial.h"
45 #define UARTDM_BURST_SIZE 16 /* in bytes */
46 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
47 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
48 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
58 struct dma_chan *chan;
59 enum dma_data_direction dir;
65 struct dma_async_tx_descriptor *desc;
69 struct uart_port uart;
75 unsigned int old_snap_state;
77 struct msm_dma tx_dma;
78 struct msm_dma rx_dma;
79 unsigned int last_baud;
82 static void msm_handle_tx(struct uart_port *port);
83 static void msm_start_rx_dma(struct msm_port *msm_port);
85 void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
87 struct device *dev = port->dev;
94 dmaengine_terminate_all(dma->chan);
97 * DMA Stall happens if enqueue and flush command happens concurrently.
98 * For example before changing the baud rate/protocol configuration and
99 * sending flush command to ADM, disable the channel of UARTDM.
100 * Note: should not reset the receiver here immediately as it is not
101 * suggested to do disable/reset or reset/disable at the same time.
103 val = msm_read(port, UARTDM_DMEN);
104 val &= ~dma->enable_bit;
105 msm_write(port, val, UARTDM_DMEN);
108 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
111 static void msm_release_dma(struct msm_port *msm_port)
115 dma = &msm_port->tx_dma;
117 msm_stop_dma(&msm_port->uart, dma);
118 dma_release_channel(dma->chan);
121 memset(dma, 0, sizeof(*dma));
123 dma = &msm_port->rx_dma;
125 msm_stop_dma(&msm_port->uart, dma);
126 dma_release_channel(dma->chan);
130 memset(dma, 0, sizeof(*dma));
133 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
135 struct device *dev = msm_port->uart.dev;
136 struct dma_slave_config conf;
141 dma = &msm_port->tx_dma;
143 /* allocate DMA resources, if available */
144 dma->chan = dma_request_slave_channel_reason(dev, "tx");
145 if (IS_ERR(dma->chan))
148 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
150 memset(&conf, 0, sizeof(conf));
151 conf.direction = DMA_MEM_TO_DEV;
152 conf.device_fc = true;
153 conf.dst_addr = base + UARTDM_TF;
154 conf.dst_maxburst = UARTDM_BURST_SIZE;
155 conf.slave_id = crci;
157 ret = dmaengine_slave_config(dma->chan, &conf);
161 dma->dir = DMA_TO_DEVICE;
163 if (msm_port->is_uartdm < UARTDM_1P4)
164 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
166 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
171 dma_release_channel(dma->chan);
173 memset(dma, 0, sizeof(*dma));
176 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
178 struct device *dev = msm_port->uart.dev;
179 struct dma_slave_config conf;
184 dma = &msm_port->rx_dma;
186 /* allocate DMA resources, if available */
187 dma->chan = dma_request_slave_channel_reason(dev, "rx");
188 if (IS_ERR(dma->chan))
191 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
193 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
197 memset(&conf, 0, sizeof(conf));
198 conf.direction = DMA_DEV_TO_MEM;
199 conf.device_fc = true;
200 conf.src_addr = base + UARTDM_RF;
201 conf.src_maxburst = UARTDM_BURST_SIZE;
202 conf.slave_id = crci;
204 ret = dmaengine_slave_config(dma->chan, &conf);
208 dma->dir = DMA_FROM_DEVICE;
210 if (msm_port->is_uartdm < UARTDM_1P4)
211 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
213 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
219 dma_release_channel(dma->chan);
221 memset(dma, 0, sizeof(*dma));
224 static inline void msm_wait_for_xmitr(struct uart_port *port)
226 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
227 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
231 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
234 static void msm_stop_tx(struct uart_port *port)
236 struct msm_port *msm_port = UART_TO_MSM(port);
238 msm_port->imr &= ~UART_IMR_TXLEV;
239 msm_write(port, msm_port->imr, UART_IMR);
242 static void msm_start_tx(struct uart_port *port)
244 struct msm_port *msm_port = UART_TO_MSM(port);
245 struct msm_dma *dma = &msm_port->tx_dma;
247 /* Already started in DMA mode */
251 msm_port->imr |= UART_IMR_TXLEV;
252 msm_write(port, msm_port->imr, UART_IMR);
255 static void msm_reset_dm_count(struct uart_port *port, int count)
257 msm_wait_for_xmitr(port);
258 msm_write(port, count, UARTDM_NCF_TX);
259 msm_read(port, UARTDM_NCF_TX);
262 static void msm_complete_tx_dma(void *args)
264 struct msm_port *msm_port = args;
265 struct uart_port *port = &msm_port->uart;
266 struct circ_buf *xmit = &port->state->xmit;
267 struct msm_dma *dma = &msm_port->tx_dma;
268 struct dma_tx_state state;
269 enum dma_status status;
274 spin_lock_irqsave(&port->lock, flags);
276 /* Already stopped */
280 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
282 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
284 val = msm_read(port, UARTDM_DMEN);
285 val &= ~dma->enable_bit;
286 msm_write(port, val, UARTDM_DMEN);
288 if (msm_port->is_uartdm > UARTDM_1P3) {
289 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
290 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
293 count = dma->count - state.residue;
294 port->icount.tx += count;
298 xmit->tail &= UART_XMIT_SIZE - 1;
300 /* Restore "Tx FIFO below watermark" interrupt */
301 msm_port->imr |= UART_IMR_TXLEV;
302 msm_write(port, msm_port->imr, UART_IMR);
304 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
305 uart_write_wakeup(port);
309 spin_unlock_irqrestore(&port->lock, flags);
312 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
314 struct circ_buf *xmit = &msm_port->uart.state->xmit;
315 struct uart_port *port = &msm_port->uart;
316 struct msm_dma *dma = &msm_port->tx_dma;
321 cpu_addr = &xmit->buf[xmit->tail];
323 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
324 ret = dma_mapping_error(port->dev, dma->phys);
328 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
329 count, DMA_MEM_TO_DEV,
337 dma->desc->callback = msm_complete_tx_dma;
338 dma->desc->callback_param = msm_port;
340 dma->cookie = dmaengine_submit(dma->desc);
341 ret = dma_submit_error(dma->cookie);
346 * Using DMA complete for Tx FIFO reload, no need for
347 * "Tx FIFO below watermark" one, disable it
349 msm_port->imr &= ~UART_IMR_TXLEV;
350 msm_write(port, msm_port->imr, UART_IMR);
354 val = msm_read(port, UARTDM_DMEN);
355 val |= dma->enable_bit;
357 if (msm_port->is_uartdm < UARTDM_1P4)
358 msm_write(port, val, UARTDM_DMEN);
360 msm_reset_dm_count(port, count);
362 if (msm_port->is_uartdm > UARTDM_1P3)
363 msm_write(port, val, UARTDM_DMEN);
365 dma_async_issue_pending(dma->chan);
368 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
372 static void msm_complete_rx_dma(void *args)
374 struct msm_port *msm_port = args;
375 struct uart_port *port = &msm_port->uart;
376 struct tty_port *tport = &port->state->port;
377 struct msm_dma *dma = &msm_port->rx_dma;
378 int count = 0, i, sysrq;
382 spin_lock_irqsave(&port->lock, flags);
384 /* Already stopped */
388 val = msm_read(port, UARTDM_DMEN);
389 val &= ~dma->enable_bit;
390 msm_write(port, val, UARTDM_DMEN);
392 /* Restore interrupts */
393 msm_port->imr |= UART_IMR_RXLEV | UART_IMR_RXSTALE;
394 msm_write(port, msm_port->imr, UART_IMR);
396 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
397 port->icount.overrun++;
398 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
399 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
402 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
404 port->icount.rx += count;
408 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
410 for (i = 0; i < count; i++) {
411 char flag = TTY_NORMAL;
413 if (msm_port->break_detected && dma->virt[i] == 0) {
416 msm_port->break_detected = false;
417 if (uart_handle_break(port))
421 if (!(port->read_status_mask & UART_SR_RX_BREAK))
424 spin_unlock_irqrestore(&port->lock, flags);
425 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
426 spin_lock_irqsave(&port->lock, flags);
428 tty_insert_flip_char(tport, dma->virt[i], flag);
431 msm_start_rx_dma(msm_port);
433 spin_unlock_irqrestore(&port->lock, flags);
436 tty_flip_buffer_push(tport);
439 static void msm_start_rx_dma(struct msm_port *msm_port)
441 struct msm_dma *dma = &msm_port->rx_dma;
442 struct uart_port *uart = &msm_port->uart;
449 dma->phys = dma_map_single(uart->dev, dma->virt,
450 UARTDM_RX_SIZE, dma->dir);
451 ret = dma_mapping_error(uart->dev, dma->phys);
455 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
456 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
461 dma->desc->callback = msm_complete_rx_dma;
462 dma->desc->callback_param = msm_port;
464 dma->cookie = dmaengine_submit(dma->desc);
465 ret = dma_submit_error(dma->cookie);
469 * Using DMA for FIFO off-load, no need for "Rx FIFO over
470 * watermark" or "stale" interrupts, disable them
472 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
475 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
476 * we need RXSTALE to flush input DMA fifo to memory
478 if (msm_port->is_uartdm < UARTDM_1P4)
479 msm_port->imr |= UART_IMR_RXSTALE;
481 msm_write(uart, msm_port->imr, UART_IMR);
483 dma->count = UARTDM_RX_SIZE;
485 dma_async_issue_pending(dma->chan);
487 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
488 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
490 val = msm_read(uart, UARTDM_DMEN);
491 val |= dma->enable_bit;
493 if (msm_port->is_uartdm < UARTDM_1P4)
494 msm_write(uart, val, UARTDM_DMEN);
496 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
498 if (msm_port->is_uartdm > UARTDM_1P3)
499 msm_write(uart, val, UARTDM_DMEN);
503 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
506 static void msm_stop_rx(struct uart_port *port)
508 struct msm_port *msm_port = UART_TO_MSM(port);
509 struct msm_dma *dma = &msm_port->rx_dma;
511 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
512 msm_write(port, msm_port->imr, UART_IMR);
515 msm_stop_dma(port, dma);
518 static void msm_enable_ms(struct uart_port *port)
520 struct msm_port *msm_port = UART_TO_MSM(port);
522 msm_port->imr |= UART_IMR_DELTA_CTS;
523 msm_write(port, msm_port->imr, UART_IMR);
526 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
528 struct tty_port *tport = &port->state->port;
531 struct msm_port *msm_port = UART_TO_MSM(port);
533 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
534 port->icount.overrun++;
535 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
536 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
539 if (misr & UART_IMR_RXSTALE) {
540 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
541 msm_port->old_snap_state;
542 msm_port->old_snap_state = 0;
544 count = 4 * (msm_read(port, UART_RFWR));
545 msm_port->old_snap_state += count;
548 /* TODO: Precise error reporting */
550 port->icount.rx += count;
553 unsigned char buf[4];
554 int sysrq, r_count, i;
556 sr = msm_read(port, UART_SR);
557 if ((sr & UART_SR_RX_READY) == 0) {
558 msm_port->old_snap_state -= count;
562 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
563 r_count = min_t(int, count, sizeof(buf));
565 for (i = 0; i < r_count; i++) {
566 char flag = TTY_NORMAL;
568 if (msm_port->break_detected && buf[i] == 0) {
571 msm_port->break_detected = false;
572 if (uart_handle_break(port))
576 if (!(port->read_status_mask & UART_SR_RX_BREAK))
579 spin_unlock(&port->lock);
580 sysrq = uart_handle_sysrq_char(port, buf[i]);
581 spin_lock(&port->lock);
583 tty_insert_flip_char(tport, buf[i], flag);
588 spin_unlock(&port->lock);
589 tty_flip_buffer_push(tport);
590 spin_lock(&port->lock);
592 if (misr & (UART_IMR_RXSTALE))
593 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
594 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
595 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
598 msm_start_rx_dma(msm_port);
601 static void msm_handle_rx(struct uart_port *port)
603 struct tty_port *tport = &port->state->port;
607 * Handle overrun. My understanding of the hardware is that overrun
608 * is not tied to the RX buffer, so we handle the case out of band.
610 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
611 port->icount.overrun++;
612 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
613 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
616 /* and now the main RX loop */
617 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
619 char flag = TTY_NORMAL;
622 c = msm_read(port, UART_RF);
624 if (sr & UART_SR_RX_BREAK) {
626 if (uart_handle_break(port))
628 } else if (sr & UART_SR_PAR_FRAME_ERR) {
629 port->icount.frame++;
634 /* Mask conditions we're ignorning. */
635 sr &= port->read_status_mask;
637 if (sr & UART_SR_RX_BREAK)
639 else if (sr & UART_SR_PAR_FRAME_ERR)
642 spin_unlock(&port->lock);
643 sysrq = uart_handle_sysrq_char(port, c);
644 spin_lock(&port->lock);
646 tty_insert_flip_char(tport, c, flag);
649 spin_unlock(&port->lock);
650 tty_flip_buffer_push(tport);
651 spin_lock(&port->lock);
654 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
656 struct circ_buf *xmit = &port->state->xmit;
657 struct msm_port *msm_port = UART_TO_MSM(port);
658 unsigned int num_chars;
659 unsigned int tf_pointer = 0;
662 if (msm_port->is_uartdm)
663 tf = port->membase + UARTDM_TF;
665 tf = port->membase + UART_TF;
667 if (tx_count && msm_port->is_uartdm)
668 msm_reset_dm_count(port, tx_count);
670 while (tf_pointer < tx_count) {
674 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
677 if (msm_port->is_uartdm)
678 num_chars = min(tx_count - tf_pointer,
679 (unsigned int)sizeof(buf));
683 for (i = 0; i < num_chars; i++) {
684 buf[i] = xmit->buf[xmit->tail + i];
688 iowrite32_rep(tf, buf, 1);
689 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
690 tf_pointer += num_chars;
693 /* disable tx interrupts if nothing more to send */
694 if (uart_circ_empty(xmit))
697 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
698 uart_write_wakeup(port);
701 static void msm_handle_tx(struct uart_port *port)
703 struct msm_port *msm_port = UART_TO_MSM(port);
704 struct circ_buf *xmit = &msm_port->uart.state->xmit;
705 struct msm_dma *dma = &msm_port->tx_dma;
706 unsigned int pio_count, dma_count, dma_min;
711 if (msm_port->is_uartdm)
712 tf = port->membase + UARTDM_TF;
714 tf = port->membase + UART_TF;
716 if (msm_port->is_uartdm)
717 msm_reset_dm_count(port, 1);
719 iowrite8_rep(tf, &port->x_char, 1);
725 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
730 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
731 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
733 dma_min = 1; /* Always DMA */
734 if (msm_port->is_uartdm > UARTDM_1P3) {
735 dma_count = UARTDM_TX_AIGN(dma_count);
736 dma_min = UARTDM_BURST_SIZE;
738 if (dma_count > UARTDM_TX_MAX)
739 dma_count = UARTDM_TX_MAX;
742 if (pio_count > port->fifosize)
743 pio_count = port->fifosize;
745 if (!dma->chan || dma_count < dma_min)
746 msm_handle_tx_pio(port, pio_count);
748 err = msm_handle_tx_dma(msm_port, dma_count);
750 if (err) /* fall back to PIO mode */
751 msm_handle_tx_pio(port, pio_count);
754 static void msm_handle_delta_cts(struct uart_port *port)
756 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
758 wake_up_interruptible(&port->state->port.delta_msr_wait);
761 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
763 struct uart_port *port = dev_id;
764 struct msm_port *msm_port = UART_TO_MSM(port);
765 struct msm_dma *dma = &msm_port->rx_dma;
770 spin_lock_irqsave(&port->lock, flags);
771 misr = msm_read(port, UART_MISR);
772 msm_write(port, 0, UART_IMR); /* disable interrupt */
774 if (misr & UART_IMR_RXBREAK_START) {
775 msm_port->break_detected = true;
776 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
779 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
781 val = UART_CR_CMD_STALE_EVENT_DISABLE;
782 msm_write(port, val, UART_CR);
783 val = UART_CR_CMD_RESET_STALE_INT;
784 msm_write(port, val, UART_CR);
786 * Flush DMA input fifo to memory, this will also
787 * trigger DMA RX completion
789 dmaengine_terminate_all(dma->chan);
790 } else if (msm_port->is_uartdm) {
791 msm_handle_rx_dm(port, misr);
796 if (misr & UART_IMR_TXLEV)
798 if (misr & UART_IMR_DELTA_CTS)
799 msm_handle_delta_cts(port);
801 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
802 spin_unlock_irqrestore(&port->lock, flags);
807 static unsigned int msm_tx_empty(struct uart_port *port)
809 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
812 static unsigned int msm_get_mctrl(struct uart_port *port)
814 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
817 static void msm_reset(struct uart_port *port)
819 struct msm_port *msm_port = UART_TO_MSM(port);
821 /* reset everything */
822 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
823 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
824 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
825 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
826 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
827 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
829 /* Disable DM modes */
830 if (msm_port->is_uartdm)
831 msm_write(port, 0, UARTDM_DMEN);
834 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
838 mr = msm_read(port, UART_MR1);
840 if (!(mctrl & TIOCM_RTS)) {
841 mr &= ~UART_MR1_RX_RDY_CTL;
842 msm_write(port, mr, UART_MR1);
843 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
845 mr |= UART_MR1_RX_RDY_CTL;
846 msm_write(port, mr, UART_MR1);
850 static void msm_break_ctl(struct uart_port *port, int break_ctl)
853 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
855 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
858 struct msm_baud_map {
864 static const struct msm_baud_map *
865 msm_find_best_baud(struct uart_port *port, unsigned int baud)
867 unsigned int i, divisor;
868 const struct msm_baud_map *entry;
869 static const struct msm_baud_map table[] = {
889 divisor = uart_get_divisor(port, baud);
891 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
892 if (entry->divisor <= divisor)
895 return entry; /* Default to smallest divider */
898 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
899 unsigned long *saved_flags)
901 unsigned int rxstale, watermark, mask;
902 struct msm_port *msm_port = UART_TO_MSM(port);
903 const struct msm_baud_map *entry;
906 entry = msm_find_best_baud(port, baud);
908 msm_write(port, entry->code, UART_CSR);
911 port->uartclk = baud * 16;
913 flags = *saved_flags;
914 spin_unlock_irqrestore(&port->lock, flags);
916 clk_set_rate(msm_port->clk, port->uartclk);
918 spin_lock_irqsave(&port->lock, flags);
919 *saved_flags = flags;
921 /* RX stale watermark */
922 rxstale = entry->rxstale;
923 watermark = UART_IPR_STALE_LSB & rxstale;
924 if (msm_port->is_uartdm) {
925 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
927 watermark |= UART_IPR_RXSTALE_LAST;
928 mask = UART_IPR_STALE_TIMEOUT_MSB;
931 watermark |= mask & (rxstale << 2);
933 msm_write(port, watermark, UART_IPR);
935 /* set RX watermark */
936 watermark = (port->fifosize * 3) / 4;
937 msm_write(port, watermark, UART_RFWR);
939 /* set TX watermark */
940 msm_write(port, 10, UART_TFWR);
942 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
945 /* Enable RX and TX */
946 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
948 /* turn on RX and CTS interrupts */
949 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
950 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
952 msm_write(port, msm_port->imr, UART_IMR);
954 if (msm_port->is_uartdm) {
955 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
956 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
957 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
963 static void msm_init_clock(struct uart_port *port)
965 struct msm_port *msm_port = UART_TO_MSM(port);
967 clk_prepare_enable(msm_port->clk);
968 clk_prepare_enable(msm_port->pclk);
969 msm_serial_set_mnd_regs(port);
972 static int msm_startup(struct uart_port *port)
974 struct msm_port *msm_port = UART_TO_MSM(port);
975 unsigned int data, rfr_level, mask;
978 snprintf(msm_port->name, sizeof(msm_port->name),
979 "msm_serial%d", port->line);
981 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
982 msm_port->name, port);
986 msm_init_clock(port);
988 if (likely(port->fifosize > 12))
989 rfr_level = port->fifosize - 12;
991 rfr_level = port->fifosize;
993 /* set automatic RFR level */
994 data = msm_read(port, UART_MR1);
996 if (msm_port->is_uartdm)
997 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
999 mask = UART_MR1_AUTO_RFR_LEVEL1;
1002 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1003 data |= mask & (rfr_level << 2);
1004 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1005 msm_write(port, data, UART_MR1);
1007 if (msm_port->is_uartdm) {
1008 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1009 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1015 static void msm_shutdown(struct uart_port *port)
1017 struct msm_port *msm_port = UART_TO_MSM(port);
1020 msm_write(port, 0, UART_IMR); /* disable interrupts */
1022 if (msm_port->is_uartdm)
1023 msm_release_dma(msm_port);
1025 clk_disable_unprepare(msm_port->clk);
1027 free_irq(port->irq, port);
1030 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1031 struct ktermios *old)
1033 struct msm_port *msm_port = UART_TO_MSM(port);
1034 struct msm_dma *dma = &msm_port->rx_dma;
1035 unsigned long flags;
1036 unsigned int baud, mr;
1038 spin_lock_irqsave(&port->lock, flags);
1040 if (dma->chan) /* Terminate if any */
1041 msm_stop_dma(port, dma);
1043 /* calculate and set baud rate, if changed from last request */
1044 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1045 if (baud != msm_port->last_baud) {
1046 msm_port->last_baud = baud;
1048 baud = msm_set_baud_rate(port, baud, &flags);
1049 if (tty_termios_baud_rate(termios))
1050 tty_termios_encode_baud_rate(termios, baud, baud);
1051 uart_update_timeout(port, termios->c_cflag, baud);
1054 /* calculate parity */
1055 mr = msm_read(port, UART_MR2);
1056 mr &= ~UART_MR2_PARITY_MODE;
1057 if (termios->c_cflag & PARENB) {
1058 if (termios->c_cflag & PARODD)
1059 mr |= UART_MR2_PARITY_MODE_ODD;
1060 else if (termios->c_cflag & CMSPAR)
1061 mr |= UART_MR2_PARITY_MODE_SPACE;
1063 mr |= UART_MR2_PARITY_MODE_EVEN;
1066 /* calculate bits per char */
1067 mr &= ~UART_MR2_BITS_PER_CHAR;
1068 switch (termios->c_cflag & CSIZE) {
1070 mr |= UART_MR2_BITS_PER_CHAR_5;
1073 mr |= UART_MR2_BITS_PER_CHAR_6;
1076 mr |= UART_MR2_BITS_PER_CHAR_7;
1080 mr |= UART_MR2_BITS_PER_CHAR_8;
1084 /* calculate stop bits */
1085 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1086 if (termios->c_cflag & CSTOPB)
1087 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1089 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1091 /* set parity, bits per char, and stop bit */
1092 msm_write(port, mr, UART_MR2);
1094 /* calculate and set hardware flow control */
1095 mr = msm_read(port, UART_MR1);
1096 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1097 if (termios->c_cflag & CRTSCTS) {
1098 mr |= UART_MR1_CTS_CTL;
1099 mr |= UART_MR1_RX_RDY_CTL;
1101 msm_write(port, mr, UART_MR1);
1103 /* Configure status bits to ignore based on termio flags. */
1104 port->read_status_mask = 0;
1105 if (termios->c_iflag & INPCK)
1106 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1107 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1108 port->read_status_mask |= UART_SR_RX_BREAK;
1110 /* Try to use DMA */
1111 msm_start_rx_dma(msm_port);
1113 spin_unlock_irqrestore(&port->lock, flags);
1116 static const char *msm_type(struct uart_port *port)
1121 static void msm_release_port(struct uart_port *port)
1123 struct platform_device *pdev = to_platform_device(port->dev);
1124 struct resource *uart_resource;
1125 resource_size_t size;
1127 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1128 if (unlikely(!uart_resource))
1130 size = resource_size(uart_resource);
1132 release_mem_region(port->mapbase, size);
1133 iounmap(port->membase);
1134 port->membase = NULL;
1137 static int msm_request_port(struct uart_port *port)
1139 struct platform_device *pdev = to_platform_device(port->dev);
1140 struct resource *uart_resource;
1141 resource_size_t size;
1144 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 if (unlikely(!uart_resource))
1148 size = resource_size(uart_resource);
1150 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1153 port->membase = ioremap(port->mapbase, size);
1154 if (!port->membase) {
1156 goto fail_release_port;
1162 release_mem_region(port->mapbase, size);
1166 static void msm_config_port(struct uart_port *port, int flags)
1170 if (flags & UART_CONFIG_TYPE) {
1171 port->type = PORT_MSM;
1172 ret = msm_request_port(port);
1178 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1180 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1182 if (unlikely(port->irq != ser->irq))
1187 static void msm_power(struct uart_port *port, unsigned int state,
1188 unsigned int oldstate)
1190 struct msm_port *msm_port = UART_TO_MSM(port);
1194 clk_prepare_enable(msm_port->clk);
1195 clk_prepare_enable(msm_port->pclk);
1198 clk_disable_unprepare(msm_port->clk);
1199 clk_disable_unprepare(msm_port->pclk);
1202 pr_err("msm_serial: Unknown PM state %d\n", state);
1206 #ifdef CONFIG_CONSOLE_POLL
1207 static int msm_poll_get_char_single(struct uart_port *port)
1209 struct msm_port *msm_port = UART_TO_MSM(port);
1210 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1212 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1213 return NO_POLL_CHAR;
1215 return msm_read(port, rf_reg) & 0xff;
1218 static int msm_poll_get_char_dm(struct uart_port *port)
1223 unsigned char *sp = (unsigned char *)&slop;
1225 /* Check if a previous read had more than one char */
1227 c = sp[sizeof(slop) - count];
1229 /* Or if FIFO is empty */
1230 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1232 * If RX packing buffer has less than a word, force stale to
1233 * push contents into RX FIFO
1235 count = msm_read(port, UARTDM_RXFS);
1236 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1238 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1239 slop = msm_read(port, UARTDM_RF);
1242 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1243 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1244 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1249 /* FIFO has a word */
1251 slop = msm_read(port, UARTDM_RF);
1253 count = sizeof(slop) - 1;
1259 static int msm_poll_get_char(struct uart_port *port)
1263 struct msm_port *msm_port = UART_TO_MSM(port);
1265 /* Disable all interrupts */
1266 imr = msm_read(port, UART_IMR);
1267 msm_write(port, 0, UART_IMR);
1269 if (msm_port->is_uartdm)
1270 c = msm_poll_get_char_dm(port);
1272 c = msm_poll_get_char_single(port);
1274 /* Enable interrupts */
1275 msm_write(port, imr, UART_IMR);
1280 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1283 struct msm_port *msm_port = UART_TO_MSM(port);
1285 /* Disable all interrupts */
1286 imr = msm_read(port, UART_IMR);
1287 msm_write(port, 0, UART_IMR);
1289 if (msm_port->is_uartdm)
1290 msm_reset_dm_count(port, 1);
1292 /* Wait until FIFO is empty */
1293 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1296 /* Write a character */
1297 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1299 /* Wait until FIFO is empty */
1300 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1303 /* Enable interrupts */
1304 msm_write(port, imr, UART_IMR);
1308 static struct uart_ops msm_uart_pops = {
1309 .tx_empty = msm_tx_empty,
1310 .set_mctrl = msm_set_mctrl,
1311 .get_mctrl = msm_get_mctrl,
1312 .stop_tx = msm_stop_tx,
1313 .start_tx = msm_start_tx,
1314 .stop_rx = msm_stop_rx,
1315 .enable_ms = msm_enable_ms,
1316 .break_ctl = msm_break_ctl,
1317 .startup = msm_startup,
1318 .shutdown = msm_shutdown,
1319 .set_termios = msm_set_termios,
1321 .release_port = msm_release_port,
1322 .request_port = msm_request_port,
1323 .config_port = msm_config_port,
1324 .verify_port = msm_verify_port,
1326 #ifdef CONFIG_CONSOLE_POLL
1327 .poll_get_char = msm_poll_get_char,
1328 .poll_put_char = msm_poll_put_char,
1332 static struct msm_port msm_uart_ports[] = {
1336 .ops = &msm_uart_pops,
1337 .flags = UPF_BOOT_AUTOCONF,
1345 .ops = &msm_uart_pops,
1346 .flags = UPF_BOOT_AUTOCONF,
1354 .ops = &msm_uart_pops,
1355 .flags = UPF_BOOT_AUTOCONF,
1362 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1364 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1366 return &msm_uart_ports[line].uart;
1369 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1370 static void __msm_console_write(struct uart_port *port, const char *s,
1371 unsigned int count, bool is_uartdm)
1374 int num_newlines = 0;
1375 bool replaced = false;
1379 tf = port->membase + UARTDM_TF;
1381 tf = port->membase + UART_TF;
1383 /* Account for newlines that will get a carriage return added */
1384 for (i = 0; i < count; i++)
1387 count += num_newlines;
1389 spin_lock(&port->lock);
1391 msm_reset_dm_count(port, count);
1396 unsigned int num_chars;
1397 char buf[4] = { 0 };
1400 num_chars = min(count - i, (unsigned int)sizeof(buf));
1404 for (j = 0; j < num_chars; j++) {
1407 if (c == '\n' && !replaced) {
1412 if (j < num_chars) {
1419 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1422 iowrite32_rep(tf, buf, 1);
1425 spin_unlock(&port->lock);
1428 static void msm_console_write(struct console *co, const char *s,
1431 struct uart_port *port;
1432 struct msm_port *msm_port;
1434 BUG_ON(co->index < 0 || co->index >= UART_NR);
1436 port = msm_get_port_from_line(co->index);
1437 msm_port = UART_TO_MSM(port);
1439 __msm_console_write(port, s, count, msm_port->is_uartdm);
1442 static int __init msm_console_setup(struct console *co, char *options)
1444 struct uart_port *port;
1450 if (unlikely(co->index >= UART_NR || co->index < 0))
1453 port = msm_get_port_from_line(co->index);
1455 if (unlikely(!port->membase))
1458 msm_init_clock(port);
1461 uart_parse_options(options, &baud, &parity, &bits, &flow);
1463 pr_info("msm_serial: console setup on port #%d\n", port->line);
1465 return uart_set_options(port, co, baud, parity, bits, flow);
1469 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1471 struct earlycon_device *dev = con->data;
1473 __msm_console_write(&dev->port, s, n, false);
1477 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1479 if (!device->port.membase)
1482 device->con->write = msm_serial_early_write;
1485 EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup);
1486 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1487 msm_serial_early_console_setup);
1490 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1492 struct earlycon_device *dev = con->data;
1494 __msm_console_write(&dev->port, s, n, true);
1498 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1501 if (!device->port.membase)
1504 device->con->write = msm_serial_early_write_dm;
1507 EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm);
1508 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1509 msm_serial_early_console_setup_dm);
1511 static struct uart_driver msm_uart_driver;
1513 static struct console msm_console = {
1515 .write = msm_console_write,
1516 .device = uart_console_device,
1517 .setup = msm_console_setup,
1518 .flags = CON_PRINTBUFFER,
1520 .data = &msm_uart_driver,
1523 #define MSM_CONSOLE (&msm_console)
1526 #define MSM_CONSOLE NULL
1529 static struct uart_driver msm_uart_driver = {
1530 .owner = THIS_MODULE,
1531 .driver_name = "msm_serial",
1532 .dev_name = "ttyMSM",
1534 .cons = MSM_CONSOLE,
1537 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1539 static const struct of_device_id msm_uartdm_table[] = {
1540 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1541 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1542 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1543 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1547 static int msm_serial_probe(struct platform_device *pdev)
1549 struct msm_port *msm_port;
1550 struct resource *resource;
1551 struct uart_port *port;
1552 const struct of_device_id *id;
1555 if (pdev->dev.of_node)
1556 line = of_alias_get_id(pdev->dev.of_node, "serial");
1561 line = atomic_inc_return(&msm_uart_next_id) - 1;
1563 if (unlikely(line < 0 || line >= UART_NR))
1566 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1568 port = msm_get_port_from_line(line);
1569 port->dev = &pdev->dev;
1570 msm_port = UART_TO_MSM(port);
1572 id = of_match_device(msm_uartdm_table, &pdev->dev);
1574 msm_port->is_uartdm = (unsigned long)id->data;
1576 msm_port->is_uartdm = 0;
1578 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1579 if (IS_ERR(msm_port->clk))
1580 return PTR_ERR(msm_port->clk);
1582 if (msm_port->is_uartdm) {
1583 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1584 if (IS_ERR(msm_port->pclk))
1585 return PTR_ERR(msm_port->pclk);
1587 clk_set_rate(msm_port->clk, 1843200);
1590 port->uartclk = clk_get_rate(msm_port->clk);
1591 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1593 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1594 if (unlikely(!resource))
1596 port->mapbase = resource->start;
1598 irq = platform_get_irq(pdev, 0);
1599 if (unlikely(irq < 0))
1603 platform_set_drvdata(pdev, port);
1605 return uart_add_one_port(&msm_uart_driver, port);
1608 static int msm_serial_remove(struct platform_device *pdev)
1610 struct uart_port *port = platform_get_drvdata(pdev);
1612 uart_remove_one_port(&msm_uart_driver, port);
1617 static const struct of_device_id msm_match_table[] = {
1618 { .compatible = "qcom,msm-uart" },
1619 { .compatible = "qcom,msm-uartdm" },
1623 static struct platform_driver msm_platform_driver = {
1624 .remove = msm_serial_remove,
1625 .probe = msm_serial_probe,
1627 .name = "msm_serial",
1628 .of_match_table = msm_match_table,
1632 static int __init msm_serial_init(void)
1636 ret = uart_register_driver(&msm_uart_driver);
1640 ret = platform_driver_register(&msm_platform_driver);
1642 uart_unregister_driver(&msm_uart_driver);
1644 pr_info("msm_serial: driver initialized\n");
1649 static void __exit msm_serial_exit(void)
1651 platform_driver_unregister(&msm_platform_driver);
1652 uart_unregister_driver(&msm_uart_driver);
1655 module_init(msm_serial_init);
1656 module_exit(msm_serial_exit);
1658 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1659 MODULE_DESCRIPTION("Driver for msm7x serial device");
1660 MODULE_LICENSE("GPL");