2 * Application UART driver for:
3 * Freescale STMP37XX/STMP378X
6 * Author: dmitry pervushin <dimka@embeddedalley.com>
8 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
9 * Provide Alphascale ASM9260 support.
10 * Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
13 * The code contained herein is licensed under the GNU General Public
14 * License. You may obtain a copy of the GNU General Public License
15 * Version 2 or later at the following locations:
18 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/kernel.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/console.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
29 #include <linux/wait.h>
30 #include <linux/tty.h>
31 #include <linux/tty_driver.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_core.h>
35 #include <linux/platform_device.h>
36 #include <linux/device.h>
37 #include <linux/clk.h>
38 #include <linux/delay.h>
40 #include <linux/of_device.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/dmaengine.h>
44 #include <asm/cacheflush.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include "serial_mctrl_gpio.h"
52 #define MXS_AUART_PORTS 5
53 #define MXS_AUART_FIFO_SIZE 16
59 #define AUART_CTRL0 0x00000000
60 #define AUART_CTRL1 0x00000010
61 #define AUART_CTRL2 0x00000020
62 #define AUART_LINECTRL 0x00000030
63 #define AUART_LINECTRL2 0x00000040
64 #define AUART_INTR 0x00000050
65 #define AUART_DATA 0x00000060
66 #define AUART_STAT 0x00000070
67 #define AUART_DEBUG 0x00000080
68 #define AUART_VERSION 0x00000090
69 #define AUART_AUTOBAUD 0x000000a0
71 #define AUART_CTRL0_SFTRST (1 << 31)
72 #define AUART_CTRL0_CLKGATE (1 << 30)
73 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
74 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
75 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
77 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
79 #define AUART_CTRL2_DMAONERR (1 << 26)
80 #define AUART_CTRL2_TXDMAE (1 << 25)
81 #define AUART_CTRL2_RXDMAE (1 << 24)
83 #define AUART_CTRL2_CTSEN (1 << 15)
84 #define AUART_CTRL2_RTSEN (1 << 14)
85 #define AUART_CTRL2_RTS (1 << 11)
86 #define AUART_CTRL2_RXE (1 << 9)
87 #define AUART_CTRL2_TXE (1 << 8)
88 #define AUART_CTRL2_UARTEN (1 << 0)
90 #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
91 #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
92 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
93 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
94 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
95 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
96 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
97 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
98 #define AUART_LINECTRL_SPS (1 << 7)
99 #define AUART_LINECTRL_WLEN_MASK 0x00000060
100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
101 #define AUART_LINECTRL_FEN (1 << 4)
102 #define AUART_LINECTRL_STP2 (1 << 3)
103 #define AUART_LINECTRL_EPS (1 << 2)
104 #define AUART_LINECTRL_PEN (1 << 1)
105 #define AUART_LINECTRL_BRK (1 << 0)
107 #define AUART_INTR_RTIEN (1 << 22)
108 #define AUART_INTR_TXIEN (1 << 21)
109 #define AUART_INTR_RXIEN (1 << 20)
110 #define AUART_INTR_CTSMIEN (1 << 17)
111 #define AUART_INTR_RTIS (1 << 6)
112 #define AUART_INTR_TXIS (1 << 5)
113 #define AUART_INTR_RXIS (1 << 4)
114 #define AUART_INTR_CTSMIS (1 << 1)
116 #define AUART_STAT_BUSY (1 << 29)
117 #define AUART_STAT_CTS (1 << 28)
118 #define AUART_STAT_TXFE (1 << 27)
119 #define AUART_STAT_TXFF (1 << 25)
120 #define AUART_STAT_RXFE (1 << 24)
121 #define AUART_STAT_OERR (1 << 19)
122 #define AUART_STAT_BERR (1 << 18)
123 #define AUART_STAT_PERR (1 << 17)
124 #define AUART_STAT_FERR (1 << 16)
125 #define AUART_STAT_RXCOUNT_MASK 0xffff
128 * Start of Alphascale asm9260 defines
129 * This list contains only differences of existing bits
130 * between imx2x and asm9260
132 #define ASM9260_HW_CTRL0 0x0000
134 * RW. Tell the UART to execute the RX DMA Command. The
135 * UART will clear this bit at the end of receive execution.
137 #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
138 /* RW. 0 use FIFO for status register; 1 use DMA */
139 #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
141 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
142 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
143 * operation. If this bit is set to 1, a receive timeout will cause the receive
144 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
146 #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
148 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
149 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
150 * input is idle, then the watchdog counter will decrement each bit-time. Note
151 * 7-bit-time is added to the programmed value, so a value of zero will set
152 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
153 * note that the counter is reloaded at the end of each frame, so if the frame
154 * is 10 bits long and the timeout counter value is zero, then timeout will
155 * occur (when FIFO is not empty) even if the RX input is not idle. The default
156 * value is 0x3 (31 bit-time).
158 #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
159 /* TIMEOUT = (100*7+1)*(1/BAUD) */
160 #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
162 /* TX ctrl register */
163 #define ASM9260_HW_CTRL1 0x0010
165 * RW. Tell the UART to execute the TX DMA Command. The
166 * UART will clear this bit at the end of transmit execution.
168 #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
170 #define ASM9260_HW_CTRL2 0x0020
172 * RW. Receive Interrupt FIFO Level Select.
173 * The trigger points for the receive interrupt are as follows:
174 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
175 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
176 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
177 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
178 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
180 #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
181 #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
182 /* RW. Same as RXIFLSEL */
183 #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
184 #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
185 /* RW. Set DTR. When this bit is 1, the output is 0. */
186 #define ASM9260_BM_CTRL2_DTR BIT(10)
187 /* RW. Loop Back Enable */
188 #define ASM9260_BM_CTRL2_LBE BIT(7)
189 #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
191 #define ASM9260_HW_LINECTRL 0x0030
193 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
194 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
195 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
196 * bit is cleared stick parity is disabled.
198 #define ASM9260_BM_LCTRL_SPS BIT(7)
199 /* RW. Word length */
200 #define ASM9260_BM_LCTRL_WLEN (3 << 5)
201 #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
202 #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
203 #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
204 #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
207 * Interrupt register.
208 * contains the interrupt enables and the interrupt status bits
210 #define ASM9260_HW_INTR 0x0040
211 /* Tx FIFO EMPTY Raw Interrupt enable */
212 #define ASM9260_BM_INTR_TFEIEN BIT(27)
213 /* Overrun Error Interrupt Enable. */
214 #define ASM9260_BM_INTR_OEIEN BIT(26)
215 /* Break Error Interrupt Enable. */
216 #define ASM9260_BM_INTR_BEIEN BIT(25)
217 /* Parity Error Interrupt Enable. */
218 #define ASM9260_BM_INTR_PEIEN BIT(24)
219 /* Framing Error Interrupt Enable. */
220 #define ASM9260_BM_INTR_FEIEN BIT(23)
222 /* nUARTDSR Modem Interrupt Enable. */
223 #define ASM9260_BM_INTR_DSRMIEN BIT(19)
224 /* nUARTDCD Modem Interrupt Enable. */
225 #define ASM9260_BM_INTR_DCDMIEN BIT(18)
226 /* nUARTRI Modem Interrupt Enable. */
227 #define ASM9260_BM_INTR_RIMIEN BIT(16)
228 /* Auto-Boud Timeout */
229 #define ASM9260_BM_INTR_ABTO BIT(13)
230 #define ASM9260_BM_INTR_ABEO BIT(12)
231 /* Tx FIFO EMPTY Raw Interrupt state */
232 #define ASM9260_BM_INTR_TFEIS BIT(11)
234 #define ASM9260_BM_INTR_OEIS BIT(10)
236 #define ASM9260_BM_INTR_BEIS BIT(9)
238 #define ASM9260_BM_INTR_PEIS BIT(8)
240 #define ASM9260_BM_INTR_FEIS BIT(7)
241 #define ASM9260_BM_INTR_DSRMIS BIT(3)
242 #define ASM9260_BM_INTR_DCDMIS BIT(2)
243 #define ASM9260_BM_INTR_RIMIS BIT(0)
246 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
247 * time. In PIO mode, only one character can be accessed at a time. The status
248 * register contains the receive data flags and valid bits.
250 #define ASM9260_HW_DATA 0x0050
252 #define ASM9260_HW_STAT 0x0060
253 /* RO. If 1, UARTAPP is present in this product. */
254 #define ASM9260_BM_STAT_PRESENT BIT(31)
255 /* RO. If 1, HISPEED is present in this product. */
256 #define ASM9260_BM_STAT_HISPEED BIT(30)
257 /* RO. Receive FIFO Full. */
258 #define ASM9260_BM_STAT_RXFULL BIT(26)
260 /* RO. The UART Debug Register contains the state of the DMA signals. */
261 #define ASM9260_HW_DEBUG 0x0070
262 /* DMA Command Run Status */
263 #define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
264 #define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
265 /* DMA Command End Status */
266 #define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
267 #define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
268 /* DMA Request Status */
269 #define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
270 #define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
272 #define ASM9260_HW_ILPR 0x0080
274 #define ASM9260_HW_RS485CTRL 0x0090
276 * RW. This bit reverses the polarity of the direction control signal on the RTS
278 * If 0, The direction control pin will be driven to logic ‘0’ when the
279 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
280 * last bit of data has been transmitted.
282 #define ASM9260_BM_RS485CTRL_ONIV BIT(5)
283 /* RW. Enable Auto Direction Control. */
284 #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
286 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
287 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
289 #define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
290 /* RW. Enable Auto Address Detect (AAD). */
291 #define ASM9260_BM_RS485CTRL_AADEN BIT(2)
292 /* RW. Disable receiver. */
293 #define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
294 /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
295 #define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
297 #define ASM9260_HW_RS485ADRMATCH 0x00a0
298 /* Contains the address match value. */
299 #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
301 #define ASM9260_HW_RS485DLY 0x00b0
303 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
304 * is in periods of the baud clock.
306 #define ASM9260_BM_RS485DLY_MASK (0xff << 0)
308 #define ASM9260_HW_AUTOBAUD 0x00c0
309 /* WO. Auto-baud time-out interrupt clear bit. */
310 #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
311 /* WO. End of auto-baud interrupt clear bit. */
312 #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
313 /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
314 #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
315 /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
316 #define ASM9260_BM_AUTOBAUD_MODE BIT(1)
318 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
319 * automatically cleared after auto-baud completion.
321 #define ASM9260_BM_AUTOBAUD_START BIT(0)
323 #define ASM9260_HW_CTRL3 0x00d0
324 #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
326 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
329 #define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
330 /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
331 #define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
332 /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
333 #define ASM9260_BM_CTRL3_MSBF BIT(2)
334 /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
335 #define ASM9260_BM_CTRL3_BAUD8 BIT(1)
336 /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
337 #define ASM9260_BM_CTRL3_9BIT BIT(0)
339 #define ASM9260_HW_ISO7816_CTRL 0x00e0
340 /* RW. Enable High Speed mode. */
341 #define ASM9260_BM_ISO7816CTRL_HS BIT(12)
342 /* Disable Successive Receive NACK */
343 #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
344 #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
345 /* Receive NACK Inhibit */
346 #define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
347 #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
348 /* RW. 1 - ISO7816 mode; 0 - USART mode */
349 #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
351 #define ASM9260_HW_ISO7816_ERRCNT 0x00f0
352 /* Parity error counter. Will be cleared after reading */
353 #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
355 #define ASM9260_HW_ISO7816_STATUS 0x0100
356 /* Max number of Repetitions Reached */
357 #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
359 /* End of Alphascale asm9260 defines */
361 static struct uart_driver auart_driver;
363 enum mxs_auart_type {
370 const u16 *reg_offset;
386 /* The size of the array - must be last */
390 static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
391 [REG_CTRL0] = ASM9260_HW_CTRL0,
392 [REG_CTRL1] = ASM9260_HW_CTRL1,
393 [REG_CTRL2] = ASM9260_HW_CTRL2,
394 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
395 [REG_INTR] = ASM9260_HW_INTR,
396 [REG_DATA] = ASM9260_HW_DATA,
397 [REG_STAT] = ASM9260_HW_STAT,
398 [REG_DEBUG] = ASM9260_HW_DEBUG,
399 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
402 static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
403 [REG_CTRL0] = AUART_CTRL0,
404 [REG_CTRL1] = AUART_CTRL1,
405 [REG_CTRL2] = AUART_CTRL2,
406 [REG_LINECTRL] = AUART_LINECTRL,
407 [REG_LINECTRL2] = AUART_LINECTRL2,
408 [REG_INTR] = AUART_INTR,
409 [REG_DATA] = AUART_DATA,
410 [REG_STAT] = AUART_STAT,
411 [REG_DEBUG] = AUART_DEBUG,
412 [REG_VERSION] = AUART_VERSION,
413 [REG_AUTOBAUD] = AUART_AUTOBAUD,
416 static const struct vendor_data vendor_alphascale_asm9260 = {
417 .reg_offset = mxs_asm9260_offsets,
420 static const struct vendor_data vendor_freescale_stmp37xx = {
421 .reg_offset = mxs_stmp37xx_offsets,
424 struct mxs_auart_port {
425 struct uart_port port;
427 #define MXS_AUART_DMA_ENABLED 0x2
428 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
429 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
430 #define MXS_AUART_RTSCTS 4 /* bit 4 */
432 unsigned int mctrl_prev;
433 enum mxs_auart_type devtype;
434 const struct vendor_data *vendor;
441 struct scatterlist tx_sgl;
442 struct dma_chan *tx_dma_chan;
445 struct scatterlist rx_sgl;
446 struct dma_chan *rx_dma_chan;
449 struct mctrl_gpios *gpios;
450 int gpio_irq[UART_GPIO_MAX];
454 static const struct platform_device_id mxs_auart_devtype[] = {
455 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
456 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
457 { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART },
460 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
462 static const struct of_device_id mxs_auart_dt_ids[] = {
464 .compatible = "fsl,imx28-auart",
465 .data = &mxs_auart_devtype[IMX28_AUART]
467 .compatible = "fsl,imx23-auart",
468 .data = &mxs_auart_devtype[IMX23_AUART]
470 .compatible = "alphascale,asm9260-auart",
471 .data = &mxs_auart_devtype[ASM9260_AUART]
472 }, { /* sentinel */ }
474 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
476 static inline int is_imx28_auart(struct mxs_auart_port *s)
478 return s->devtype == IMX28_AUART;
481 static inline int is_asm9260_auart(struct mxs_auart_port *s)
483 return s->devtype == ASM9260_AUART;
486 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
488 return s->flags & MXS_AUART_DMA_ENABLED;
491 static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
494 return uap->vendor->reg_offset[reg];
497 static unsigned int mxs_read(const struct mxs_auart_port *uap,
500 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
502 return readl_relaxed(addr);
505 static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
508 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
510 writel_relaxed(val, addr);
513 static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
516 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
518 writel_relaxed(val, addr + SET_REG);
521 static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
524 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
526 writel_relaxed(val, addr + CLR_REG);
529 static void mxs_auart_stop_tx(struct uart_port *u);
531 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
533 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
535 static void dma_tx_callback(void *param)
537 struct mxs_auart_port *s = param;
538 struct circ_buf *xmit = &s->port.state->xmit;
540 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
542 /* clear the bit used to serialize the DMA tx. */
543 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
544 smp_mb__after_atomic();
546 /* wake up the possible processes. */
547 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
548 uart_write_wakeup(&s->port);
550 mxs_auart_tx_chars(s);
553 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
555 struct dma_async_tx_descriptor *desc;
556 struct scatterlist *sgl = &s->tx_sgl;
557 struct dma_chan *channel = s->tx_dma_chan;
560 /* [1] : send PIO. Note, the first pio word is CTRL1. */
561 pio = AUART_CTRL1_XFER_COUNT(size);
562 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
563 1, DMA_TRANS_NONE, 0);
565 dev_err(s->dev, "step 1 error\n");
569 /* [2] : set DMA buffer. */
570 sg_init_one(sgl, s->tx_dma_buf, size);
571 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
572 desc = dmaengine_prep_slave_sg(channel, sgl,
573 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
575 dev_err(s->dev, "step 2 error\n");
579 /* [3] : submit the DMA */
580 desc->callback = dma_tx_callback;
581 desc->callback_param = s;
582 dmaengine_submit(desc);
583 dma_async_issue_pending(channel);
587 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
589 struct circ_buf *xmit = &s->port.state->xmit;
591 if (auart_dma_enabled(s)) {
594 void *buffer = s->tx_dma_buf;
596 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
599 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
600 size = min_t(u32, UART_XMIT_SIZE - i,
601 CIRC_CNT_TO_END(xmit->head,
604 memcpy(buffer + i, xmit->buf + xmit->tail, size);
605 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
608 if (i >= UART_XMIT_SIZE)
612 if (uart_tx_stopped(&s->port))
613 mxs_auart_stop_tx(&s->port);
616 mxs_auart_dma_tx(s, i);
618 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
619 smp_mb__after_atomic();
625 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
626 if (s->port.x_char) {
628 mxs_write(s->port.x_char, s, REG_DATA);
632 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
634 mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
635 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
639 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
640 uart_write_wakeup(&s->port);
642 if (uart_circ_empty(&(s->port.state->xmit)))
643 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
645 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
647 if (uart_tx_stopped(&s->port))
648 mxs_auart_stop_tx(&s->port);
651 static void mxs_auart_rx_char(struct mxs_auart_port *s)
657 c = mxs_read(s, REG_DATA);
658 stat = mxs_read(s, REG_STAT);
663 if (stat & AUART_STAT_BERR) {
664 s->port.icount.brk++;
665 if (uart_handle_break(&s->port))
667 } else if (stat & AUART_STAT_PERR) {
668 s->port.icount.parity++;
669 } else if (stat & AUART_STAT_FERR) {
670 s->port.icount.frame++;
674 * Mask off conditions which should be ingored.
676 stat &= s->port.read_status_mask;
678 if (stat & AUART_STAT_BERR) {
680 } else if (stat & AUART_STAT_PERR)
682 else if (stat & AUART_STAT_FERR)
685 if (stat & AUART_STAT_OERR)
686 s->port.icount.overrun++;
688 if (uart_handle_sysrq_char(&s->port, c))
691 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
693 mxs_write(stat, s, REG_STAT);
696 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
701 stat = mxs_read(s, REG_STAT);
702 if (stat & AUART_STAT_RXFE)
704 mxs_auart_rx_char(s);
707 mxs_write(stat, s, REG_STAT);
708 tty_flip_buffer_push(&s->port.state->port);
711 static int mxs_auart_request_port(struct uart_port *u)
716 static int mxs_auart_verify_port(struct uart_port *u,
717 struct serial_struct *ser)
719 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
724 static void mxs_auart_config_port(struct uart_port *u, int flags)
728 static const char *mxs_auart_type(struct uart_port *u)
730 struct mxs_auart_port *s = to_auart_port(u);
732 return dev_name(s->dev);
735 static void mxs_auart_release_port(struct uart_port *u)
739 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
741 struct mxs_auart_port *s = to_auart_port(u);
743 u32 ctrl = mxs_read(s, REG_CTRL2);
745 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
746 if (mctrl & TIOCM_RTS) {
747 if (uart_cts_enabled(u))
748 ctrl |= AUART_CTRL2_RTSEN;
750 ctrl |= AUART_CTRL2_RTS;
753 mxs_write(ctrl, s, REG_CTRL2);
755 mctrl_gpio_set(s->gpios, mctrl);
758 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
759 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
763 mctrl_diff = mctrl ^ s->mctrl_prev;
764 s->mctrl_prev = mctrl;
765 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
766 s->port.state != NULL) {
767 if (mctrl_diff & TIOCM_RI)
768 s->port.icount.rng++;
769 if (mctrl_diff & TIOCM_DSR)
770 s->port.icount.dsr++;
771 if (mctrl_diff & TIOCM_CD)
772 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
773 if (mctrl_diff & TIOCM_CTS)
774 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
776 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
781 static u32 mxs_auart_get_mctrl(struct uart_port *u)
783 struct mxs_auart_port *s = to_auart_port(u);
784 u32 stat = mxs_read(s, REG_STAT);
787 if (stat & AUART_STAT_CTS)
790 return mctrl_gpio_get(s->gpios, &mctrl);
794 * Enable modem status interrupts
796 static void mxs_auart_enable_ms(struct uart_port *port)
798 struct mxs_auart_port *s = to_auart_port(port);
801 * Interrupt should not be enabled twice
803 if (s->ms_irq_enabled)
806 s->ms_irq_enabled = true;
808 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
809 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
810 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
812 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
813 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
815 if (s->gpio_irq[UART_GPIO_RI] >= 0)
816 enable_irq(s->gpio_irq[UART_GPIO_RI]);
818 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
819 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
823 * Disable modem status interrupts
825 static void mxs_auart_disable_ms(struct uart_port *port)
827 struct mxs_auart_port *s = to_auart_port(port);
830 * Interrupt should not be disabled twice
832 if (!s->ms_irq_enabled)
835 s->ms_irq_enabled = false;
837 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
838 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
839 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
841 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
842 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
844 if (s->gpio_irq[UART_GPIO_RI] >= 0)
845 disable_irq(s->gpio_irq[UART_GPIO_RI]);
847 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
848 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
851 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
852 static void dma_rx_callback(void *arg)
854 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
855 struct tty_port *port = &s->port.state->port;
859 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
861 stat = mxs_read(s, REG_STAT);
862 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
863 AUART_STAT_PERR | AUART_STAT_FERR);
865 count = stat & AUART_STAT_RXCOUNT_MASK;
866 tty_insert_flip_string(port, s->rx_dma_buf, count);
868 mxs_write(stat, s, REG_STAT);
869 tty_flip_buffer_push(port);
871 /* start the next DMA for RX. */
872 mxs_auart_dma_prep_rx(s);
875 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
877 struct dma_async_tx_descriptor *desc;
878 struct scatterlist *sgl = &s->rx_sgl;
879 struct dma_chan *channel = s->rx_dma_chan;
883 pio[0] = AUART_CTRL0_RXTO_ENABLE
884 | AUART_CTRL0_RXTIMEOUT(0x80)
885 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
886 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
887 1, DMA_TRANS_NONE, 0);
889 dev_err(s->dev, "step 1 error\n");
893 /* [2] : send DMA request */
894 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
895 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
896 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
897 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
899 dev_err(s->dev, "step 2 error\n");
903 /* [3] : submit the DMA, but do not issue it. */
904 desc->callback = dma_rx_callback;
905 desc->callback_param = s;
906 dmaengine_submit(desc);
907 dma_async_issue_pending(channel);
911 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
913 if (s->tx_dma_chan) {
914 dma_release_channel(s->tx_dma_chan);
915 s->tx_dma_chan = NULL;
917 if (s->rx_dma_chan) {
918 dma_release_channel(s->rx_dma_chan);
919 s->rx_dma_chan = NULL;
922 kfree(s->tx_dma_buf);
923 kfree(s->rx_dma_buf);
924 s->tx_dma_buf = NULL;
925 s->rx_dma_buf = NULL;
928 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
931 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
934 mxs_auart_dma_exit_channel(s);
935 s->flags &= ~MXS_AUART_DMA_ENABLED;
936 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
937 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
940 static int mxs_auart_dma_init(struct mxs_auart_port *s)
942 if (auart_dma_enabled(s))
946 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
949 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
954 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
957 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
962 s->flags |= MXS_AUART_DMA_ENABLED;
963 dev_dbg(s->dev, "enabled the DMA support.");
965 /* The DMA buffer is now the FIFO the TTY subsystem can use */
966 s->port.fifosize = UART_XMIT_SIZE;
971 mxs_auart_dma_exit_channel(s);
976 #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
978 #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
980 static void mxs_auart_settermios(struct uart_port *u,
981 struct ktermios *termios,
982 struct ktermios *old)
984 struct mxs_auart_port *s = to_auart_port(u);
985 u32 bm, ctrl, ctrl2, div;
986 unsigned int cflag, baud, baud_min, baud_max;
988 cflag = termios->c_cflag;
990 ctrl = AUART_LINECTRL_FEN;
991 ctrl2 = mxs_read(s, REG_CTRL2);
994 switch (cflag & CSIZE) {
1011 ctrl |= AUART_LINECTRL_WLEN(bm);
1014 if (cflag & PARENB) {
1015 ctrl |= AUART_LINECTRL_PEN;
1016 if ((cflag & PARODD) == 0)
1017 ctrl |= AUART_LINECTRL_EPS;
1019 ctrl |= AUART_LINECTRL_SPS;
1022 u->read_status_mask = AUART_STAT_OERR;
1024 if (termios->c_iflag & INPCK)
1025 u->read_status_mask |= AUART_STAT_PERR;
1026 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1027 u->read_status_mask |= AUART_STAT_BERR;
1030 * Characters to ignore
1032 u->ignore_status_mask = 0;
1033 if (termios->c_iflag & IGNPAR)
1034 u->ignore_status_mask |= AUART_STAT_PERR;
1035 if (termios->c_iflag & IGNBRK) {
1036 u->ignore_status_mask |= AUART_STAT_BERR;
1038 * If we're ignoring parity and break indicators,
1039 * ignore overruns too (for real raw support).
1041 if (termios->c_iflag & IGNPAR)
1042 u->ignore_status_mask |= AUART_STAT_OERR;
1046 * ignore all characters if CREAD is not set
1049 ctrl2 |= AUART_CTRL2_RXE;
1051 ctrl2 &= ~AUART_CTRL2_RXE;
1053 /* figure out the stop bits requested */
1055 ctrl |= AUART_LINECTRL_STP2;
1057 /* figure out the hardware flow control settings */
1058 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1059 if (cflag & CRTSCTS) {
1061 * The DMA has a bug(see errata:2836) in mx23.
1062 * So we can not implement the DMA for auart in mx23,
1063 * we can only implement the DMA support for auart
1066 if (is_imx28_auart(s)
1067 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1068 if (!mxs_auart_dma_init(s))
1069 /* enable DMA tranfer */
1070 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1071 | AUART_CTRL2_DMAONERR;
1073 /* Even if RTS is GPIO line RTSEN can be enabled because
1074 * the pinctrl configuration decides about RTS pin function */
1075 ctrl2 |= AUART_CTRL2_RTSEN;
1077 ctrl2 |= AUART_CTRL2_CTSEN;
1081 if (is_asm9260_auart(s)) {
1082 baud = uart_get_baud_rate(u, termios, old,
1083 u->uartclk * 4 / 0x3FFFFF,
1085 div = u->uartclk * 4 / baud;
1087 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1088 AUART_LINECTRL_BAUD_DIV_MAX);
1089 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1090 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1091 div = u->uartclk * 32 / baud;
1094 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1095 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1096 mxs_write(ctrl, s, REG_LINECTRL);
1098 mxs_write(ctrl2, s, REG_CTRL2);
1100 uart_update_timeout(u, termios->c_cflag, baud);
1102 /* prepare for the DMA RX. */
1103 if (auart_dma_enabled(s) &&
1104 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1105 if (!mxs_auart_dma_prep_rx(s)) {
1106 /* Disable the normal RX interrupt. */
1107 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1110 mxs_auart_dma_exit(s);
1111 dev_err(s->dev, "We can not start up the DMA.\n");
1115 /* CTS flow-control and modem-status interrupts */
1116 if (UART_ENABLE_MS(u, termios->c_cflag))
1117 mxs_auart_enable_ms(u);
1119 mxs_auart_disable_ms(u);
1122 static void mxs_auart_set_ldisc(struct uart_port *port,
1123 struct ktermios *termios)
1125 if (termios->c_line == N_PPS) {
1126 port->flags |= UPF_HARDPPS_CD;
1127 mxs_auart_enable_ms(port);
1129 port->flags &= ~UPF_HARDPPS_CD;
1133 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1136 struct mxs_auart_port *s = context;
1137 u32 mctrl_temp = s->mctrl_prev;
1138 u32 stat = mxs_read(s, REG_STAT);
1140 istat = mxs_read(s, REG_INTR);
1143 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1144 | AUART_INTR_CTSMIS), s, REG_INTR);
1147 * Dealing with GPIO interrupt
1149 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1150 irq == s->gpio_irq[UART_GPIO_DCD] ||
1151 irq == s->gpio_irq[UART_GPIO_DSR] ||
1152 irq == s->gpio_irq[UART_GPIO_RI])
1153 mxs_auart_modem_status(s,
1154 mctrl_gpio_get(s->gpios, &mctrl_temp));
1156 if (istat & AUART_INTR_CTSMIS) {
1157 if (CTS_AT_AUART() && s->ms_irq_enabled)
1158 uart_handle_cts_change(&s->port,
1159 stat & AUART_STAT_CTS);
1160 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1161 istat &= ~AUART_INTR_CTSMIS;
1164 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1165 if (!auart_dma_enabled(s))
1166 mxs_auart_rx_chars(s);
1167 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1170 if (istat & AUART_INTR_TXIS) {
1171 mxs_auart_tx_chars(s);
1172 istat &= ~AUART_INTR_TXIS;
1178 static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1183 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1185 for (i = 0; i < 10000; i++) {
1186 reg = mxs_read(s, REG_CTRL0);
1187 if (!(reg & AUART_CTRL0_SFTRST))
1191 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1194 static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1199 reg = mxs_read(s, REG_CTRL0);
1200 /* if already in reset state, keep it untouched */
1201 if (reg & AUART_CTRL0_SFTRST)
1204 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1205 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1207 for (i = 0; i < 1000; i++) {
1208 reg = mxs_read(s, REG_CTRL0);
1209 /* reset is finished when the clock is gated */
1210 if (reg & AUART_CTRL0_CLKGATE)
1215 dev_err(s->dev, "Failed to reset the unit.");
1218 static int mxs_auart_startup(struct uart_port *u)
1221 struct mxs_auart_port *s = to_auart_port(u);
1223 ret = clk_prepare_enable(s->clk);
1227 if (uart_console(u)) {
1228 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1230 /* reset the unit to a well known state */
1231 mxs_auart_reset_assert(s);
1232 mxs_auart_reset_deassert(s);
1235 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1237 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1240 /* Reset FIFO size (it could have changed if DMA was enabled) */
1241 u->fifosize = MXS_AUART_FIFO_SIZE;
1244 * Enable fifo so all four bytes of a DMA word are written to
1245 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1247 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1249 /* get initial status of modem lines */
1250 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1252 s->ms_irq_enabled = false;
1256 static void mxs_auart_shutdown(struct uart_port *u)
1258 struct mxs_auart_port *s = to_auart_port(u);
1260 mxs_auart_disable_ms(u);
1262 if (auart_dma_enabled(s))
1263 mxs_auart_dma_exit(s);
1265 if (uart_console(u)) {
1266 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1268 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1269 AUART_INTR_CTSMIEN, s, REG_INTR);
1270 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1272 mxs_auart_reset_assert(s);
1275 clk_disable_unprepare(s->clk);
1278 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1280 struct mxs_auart_port *s = to_auart_port(u);
1282 if ((mxs_read(s, REG_STAT) &
1283 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1284 return TIOCSER_TEMT;
1289 static void mxs_auart_start_tx(struct uart_port *u)
1291 struct mxs_auart_port *s = to_auart_port(u);
1293 /* enable transmitter */
1294 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1296 mxs_auart_tx_chars(s);
1299 static void mxs_auart_stop_tx(struct uart_port *u)
1301 struct mxs_auart_port *s = to_auart_port(u);
1303 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1306 static void mxs_auart_stop_rx(struct uart_port *u)
1308 struct mxs_auart_port *s = to_auart_port(u);
1310 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1313 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1315 struct mxs_auart_port *s = to_auart_port(u);
1318 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1320 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1323 static const struct uart_ops mxs_auart_ops = {
1324 .tx_empty = mxs_auart_tx_empty,
1325 .start_tx = mxs_auart_start_tx,
1326 .stop_tx = mxs_auart_stop_tx,
1327 .stop_rx = mxs_auart_stop_rx,
1328 .enable_ms = mxs_auart_enable_ms,
1329 .break_ctl = mxs_auart_break_ctl,
1330 .set_mctrl = mxs_auart_set_mctrl,
1331 .get_mctrl = mxs_auart_get_mctrl,
1332 .startup = mxs_auart_startup,
1333 .shutdown = mxs_auart_shutdown,
1334 .set_termios = mxs_auart_settermios,
1335 .set_ldisc = mxs_auart_set_ldisc,
1336 .type = mxs_auart_type,
1337 .release_port = mxs_auart_release_port,
1338 .request_port = mxs_auart_request_port,
1339 .config_port = mxs_auart_config_port,
1340 .verify_port = mxs_auart_verify_port,
1343 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1345 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1346 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1348 struct mxs_auart_port *s = to_auart_port(port);
1349 unsigned int to = 1000;
1351 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1357 mxs_write(ch, s, REG_DATA);
1361 auart_console_write(struct console *co, const char *str, unsigned int count)
1363 struct mxs_auart_port *s;
1364 struct uart_port *port;
1365 unsigned int old_ctrl0, old_ctrl2;
1366 unsigned int to = 20000;
1368 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1371 s = auart_port[co->index];
1376 /* First save the CR then disable the interrupts */
1377 old_ctrl2 = mxs_read(s, REG_CTRL2);
1378 old_ctrl0 = mxs_read(s, REG_CTRL0);
1380 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1381 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1383 uart_console_write(port, str, count, mxs_auart_console_putchar);
1385 /* Finally, wait for transmitter to become empty ... */
1386 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1393 * ... and restore the TCR if we waited long enough for the transmitter
1394 * to be idle. This might keep the transmitter enabled although it is
1395 * unused, but that is better than to disable it while it is still
1398 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1399 mxs_write(old_ctrl0, s, REG_CTRL0);
1400 mxs_write(old_ctrl2, s, REG_CTRL2);
1403 clk_disable(s->clk);
1407 auart_console_get_options(struct mxs_auart_port *s, int *baud,
1408 int *parity, int *bits)
1410 struct uart_port *port = &s->port;
1411 unsigned int lcr_h, quot;
1413 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1416 lcr_h = mxs_read(s, REG_LINECTRL);
1419 if (lcr_h & AUART_LINECTRL_PEN) {
1420 if (lcr_h & AUART_LINECTRL_EPS)
1426 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1431 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1432 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1433 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1434 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1438 *baud = (port->uartclk << 2) / quot;
1442 auart_console_setup(struct console *co, char *options)
1444 struct mxs_auart_port *s;
1452 * Check whether an invalid uart number has been specified, and
1453 * if so, search for the first available port that does have
1456 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1458 s = auart_port[co->index];
1462 ret = clk_prepare_enable(s->clk);
1467 uart_parse_options(options, &baud, &parity, &bits, &flow);
1469 auart_console_get_options(s, &baud, &parity, &bits);
1471 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1473 clk_disable_unprepare(s->clk);
1478 static struct console auart_console = {
1480 .write = auart_console_write,
1481 .device = uart_console_device,
1482 .setup = auart_console_setup,
1483 .flags = CON_PRINTBUFFER,
1485 .data = &auart_driver,
1489 static struct uart_driver auart_driver = {
1490 .owner = THIS_MODULE,
1491 .driver_name = "ttyAPP",
1492 .dev_name = "ttyAPP",
1495 .nr = MXS_AUART_PORTS,
1496 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1497 .cons = &auart_console,
1501 static void mxs_init_regs(struct mxs_auart_port *s)
1503 if (is_asm9260_auart(s))
1504 s->vendor = &vendor_alphascale_asm9260;
1506 s->vendor = &vendor_freescale_stmp37xx;
1509 static int mxs_get_clks(struct mxs_auart_port *s,
1510 struct platform_device *pdev)
1514 if (!is_asm9260_auart(s)) {
1515 s->clk = devm_clk_get(&pdev->dev, NULL);
1516 return PTR_ERR_OR_ZERO(s->clk);
1519 s->clk = devm_clk_get(s->dev, "mod");
1520 if (IS_ERR(s->clk)) {
1521 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1522 return PTR_ERR(s->clk);
1525 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1526 if (IS_ERR(s->clk_ahb)) {
1527 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1528 return PTR_ERR(s->clk_ahb);
1531 err = clk_prepare_enable(s->clk_ahb);
1533 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1537 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1539 dev_err(s->dev, "Failed to set rate!\n");
1540 goto disable_clk_ahb;
1543 err = clk_prepare_enable(s->clk);
1545 dev_err(s->dev, "Failed to enable clk!\n");
1546 goto disable_clk_ahb;
1552 clk_disable_unprepare(s->clk_ahb);
1557 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1558 * could successfully get all information from dt or a negative errno.
1560 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1561 struct platform_device *pdev)
1563 struct device_node *np = pdev->dev.of_node;
1567 /* no device tree device */
1570 ret = of_alias_get_id(np, "serial");
1572 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1577 if (of_get_property(np, "uart-has-rtscts", NULL) ||
1578 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1579 set_bit(MXS_AUART_RTSCTS, &s->flags);
1584 static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1586 enum mctrl_gpio_idx i;
1587 struct gpio_desc *gpiod;
1589 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1590 if (IS_ERR(s->gpios))
1591 return PTR_ERR(s->gpios);
1593 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1594 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1595 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1597 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1598 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1601 for (i = 0; i < UART_GPIO_MAX; i++) {
1602 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1603 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
1604 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1606 s->gpio_irq[i] = -EINVAL;
1612 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1614 enum mctrl_gpio_idx i;
1616 for (i = 0; i < UART_GPIO_MAX; i++)
1617 if (s->gpio_irq[i] >= 0)
1618 free_irq(s->gpio_irq[i], s);
1621 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1623 int *irq = s->gpio_irq;
1624 enum mctrl_gpio_idx i;
1627 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1631 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1632 err = request_irq(irq[i], mxs_auart_irq_handle,
1633 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1635 dev_err(s->dev, "%s - Can't get %d irq\n",
1640 * If something went wrong, rollback.
1642 while (err && (--i >= 0))
1644 free_irq(irq[i], s);
1649 static int mxs_auart_probe(struct platform_device *pdev)
1651 const struct of_device_id *of_id =
1652 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1653 struct mxs_auart_port *s;
1658 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1662 s->port.dev = &pdev->dev;
1663 s->dev = &pdev->dev;
1665 ret = serial_mxs_probe_dt(s, pdev);
1667 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1672 pdev->id_entry = of_id->data;
1673 s->devtype = pdev->id_entry->driver_data;
1676 ret = mxs_get_clks(s, pdev);
1680 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1684 s->port.mapbase = r->start;
1685 s->port.membase = ioremap(r->start, resource_size(r));
1686 s->port.ops = &mxs_auart_ops;
1687 s->port.iotype = UPIO_MEM;
1688 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1689 s->port.uartclk = clk_get_rate(s->clk);
1690 s->port.type = PORT_IMX;
1696 irq = platform_get_irq(pdev, 0);
1701 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1702 dev_name(&pdev->dev), s);
1706 platform_set_drvdata(pdev, s);
1708 ret = mxs_auart_init_gpios(s, &pdev->dev);
1710 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1715 * Get the GPIO lines IRQ
1717 ret = mxs_auart_request_gpio_irq(s);
1721 auart_port[s->port.line] = s;
1723 mxs_auart_reset_deassert(s);
1725 ret = uart_add_one_port(&auart_driver, &s->port);
1727 goto out_free_gpio_irq;
1729 /* ASM9260 don't have version reg */
1730 if (is_asm9260_auart(s)) {
1731 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1733 version = mxs_read(s, REG_VERSION);
1734 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1735 (version >> 24) & 0xff,
1736 (version >> 16) & 0xff, version & 0xffff);
1742 mxs_auart_free_gpio_irq(s);
1743 auart_port[pdev->id] = NULL;
1747 static int mxs_auart_remove(struct platform_device *pdev)
1749 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1751 uart_remove_one_port(&auart_driver, &s->port);
1752 auart_port[pdev->id] = NULL;
1753 mxs_auart_free_gpio_irq(s);
1758 static struct platform_driver mxs_auart_driver = {
1759 .probe = mxs_auart_probe,
1760 .remove = mxs_auart_remove,
1762 .name = "mxs-auart",
1763 .of_match_table = mxs_auart_dt_ids,
1767 static int __init mxs_auart_init(void)
1771 r = uart_register_driver(&auart_driver);
1775 r = platform_driver_register(&mxs_auart_driver);
1781 uart_unregister_driver(&auart_driver);
1786 static void __exit mxs_auart_exit(void)
1788 platform_driver_unregister(&mxs_auart_driver);
1789 uart_unregister_driver(&auart_driver);
1792 module_init(mxs_auart_init);
1793 module_exit(mxs_auart_exit);
1794 MODULE_LICENSE("GPL");
1795 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1796 MODULE_ALIAS("platform:mxs-auart");