2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/of_irq.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45 #include <linux/platform_data/serial-omap.h>
47 #include <dt-bindings/gpio/gpio.h>
49 #define OMAP_MAX_HSUART_PORTS 6
51 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
53 #define OMAP_UART_REV_42 0x0402
54 #define OMAP_UART_REV_46 0x0406
55 #define OMAP_UART_REV_52 0x0502
56 #define OMAP_UART_REV_63 0x0603
58 #define OMAP_UART_TX_WAKEUP_EN BIT(7)
61 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
63 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
64 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
68 /* SCR register bitmasks */
69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
71 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
73 /* FCR register bitmasks */
74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
77 /* MVR register bitmasks */
78 #define OMAP_UART_MVR_SCHEME_SHIFT 30
80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
82 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
84 #define OMAP_UART_MVR_MAJ_MASK 0x700
85 #define OMAP_UART_MVR_MAJ_SHIFT 8
86 #define OMAP_UART_MVR_MIN_MASK 0x3f
88 #define OMAP_UART_DMA_CH_FREE -1
90 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
91 #define OMAP_MODE13X_SPEED 230400
94 * Enable module level wakeup in WER reg
96 #define OMAP_UART_WER_MOD_WKUP 0X7F
98 /* Enable XON/XOFF flow control on output */
99 #define OMAP_UART_SW_TX 0x08
101 /* Enable XON/XOFF flow control on input */
102 #define OMAP_UART_SW_RX 0x02
104 #define OMAP_UART_SW_CLR 0xF0
106 #define OMAP_UART_TCR_TRIG 0x0F
108 struct uart_omap_dma {
113 dma_addr_t rx_buf_dma_phys;
114 dma_addr_t tx_buf_dma_phys;
115 unsigned int uart_base;
117 * Buffer for rx dma.It is not required for tx because the buffer
118 * comes from port structure.
120 unsigned char *rx_buf;
121 unsigned int prev_rx_dma_pos;
127 /* timer to poll activity on rx dma */
128 struct timer_list rx_timer;
129 unsigned int rx_buf_size;
130 unsigned int rx_poll_rate;
131 unsigned int rx_timeout;
134 struct uart_omap_port {
135 struct uart_port port;
136 struct uart_omap_dma uart_dma;
153 * Some bits in registers are cleared on a read, so they must
154 * be saved whenever the register is read but the bits will not
155 * be immediately processed.
157 unsigned int lsr_break_flag;
158 unsigned char msr_saved_flags;
160 unsigned long port_activity;
161 int context_loss_cnt;
170 struct serial_rs485 rs485;
173 struct pm_qos_request pm_qos_request;
176 struct work_struct qos_work;
180 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
182 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
184 /* Forward declaration of functions */
185 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
187 static struct workqueue_struct *serial_omap_uart_wq;
189 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
191 offset <<= up->port.regshift;
192 return readw(up->port.membase + offset);
195 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
197 offset <<= up->port.regshift;
198 writew(value, up->port.membase + offset);
201 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
203 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
204 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
205 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
206 serial_out(up, UART_FCR, 0);
209 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
211 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
213 if (!pdata || !pdata->get_context_loss_count)
216 return pdata->get_context_loss_count(up->dev);
219 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
226 enable_irq(up->wakeirq);
228 disable_irq(up->wakeirq);
231 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
233 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
235 serial_omap_enable_wakeirq(up, enable);
236 if (!pdata || !pdata->enable_wakeup)
239 pdata->enable_wakeup(up->dev, enable);
243 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
244 * @port: uart port info
245 * @baud: baudrate for which mode needs to be determined
247 * Returns true if baud rate is MODE16X and false if MODE13X
248 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
249 * and Error Rates" determines modes not for all common baud rates.
250 * E.g. for 1000000 baud rate mode must be 16x, but according to that
251 * table it's determined as 13x.
254 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
256 unsigned int n13 = port->uartclk / (13 * baud);
257 unsigned int n16 = port->uartclk / (16 * baud);
258 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
259 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
260 if (baudAbsDiff13 < 0)
261 baudAbsDiff13 = -baudAbsDiff13;
262 if (baudAbsDiff16 < 0)
263 baudAbsDiff16 = -baudAbsDiff16;
265 return (baudAbsDiff13 >= baudAbsDiff16);
269 * serial_omap_get_divisor - calculate divisor value
270 * @port: uart port info
271 * @baud: baudrate for which divisor needs to be calculated.
274 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
278 if (!serial_omap_baud_is_mode16(port, baud))
282 return port->uartclk/(mode * baud);
285 static void serial_omap_enable_ms(struct uart_port *port)
287 struct uart_omap_port *up = to_uart_omap_port(port);
289 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
291 pm_runtime_get_sync(up->dev);
292 up->ier |= UART_IER_MSI;
293 serial_out(up, UART_IER, up->ier);
294 pm_runtime_mark_last_busy(up->dev);
295 pm_runtime_put_autosuspend(up->dev);
298 static void serial_omap_stop_tx(struct uart_port *port)
300 struct uart_omap_port *up = to_uart_omap_port(port);
303 pm_runtime_get_sync(up->dev);
306 if (up->rs485.flags & SER_RS485_ENABLED) {
307 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
308 /* THR interrupt is fired when both TX FIFO and TX
309 * shift register are empty. This means there's nothing
310 * left to transmit now, so make sure the THR interrupt
311 * is fired when TX FIFO is below the trigger level,
312 * disable THR interrupts and toggle the RS-485 GPIO
313 * data direction pin if needed.
315 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
316 serial_out(up, UART_OMAP_SCR, up->scr);
317 res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
318 if (gpio_get_value(up->rts_gpio) != res) {
319 if (up->rs485.delay_rts_after_send > 0)
320 mdelay(up->rs485.delay_rts_after_send);
321 gpio_set_value(up->rts_gpio, res);
324 /* We're asked to stop, but there's still stuff in the
325 * UART FIFO, so make sure the THR interrupt is fired
326 * when both TX FIFO and TX shift register are empty.
327 * The next THR interrupt (if no transmission is started
328 * in the meantime) will indicate the end of a
329 * transmission. Therefore we _don't_ disable THR
330 * interrupts in this situation.
332 up->scr |= OMAP_UART_SCR_TX_EMPTY;
333 serial_out(up, UART_OMAP_SCR, up->scr);
338 if (up->ier & UART_IER_THRI) {
339 up->ier &= ~UART_IER_THRI;
340 serial_out(up, UART_IER, up->ier);
343 if ((up->rs485.flags & SER_RS485_ENABLED) &&
344 !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
346 * Empty the RX FIFO, we are not interested in anything
347 * received during the half-duplex transmission.
349 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
350 /* Re-enable RX interrupts */
351 up->ier |= UART_IER_RLSI | UART_IER_RDI;
352 up->port.read_status_mask |= UART_LSR_DR;
353 serial_out(up, UART_IER, up->ier);
356 pm_runtime_mark_last_busy(up->dev);
357 pm_runtime_put_autosuspend(up->dev);
360 static void serial_omap_stop_rx(struct uart_port *port)
362 struct uart_omap_port *up = to_uart_omap_port(port);
364 pm_runtime_get_sync(up->dev);
365 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
366 up->port.read_status_mask &= ~UART_LSR_DR;
367 serial_out(up, UART_IER, up->ier);
368 pm_runtime_mark_last_busy(up->dev);
369 pm_runtime_put_autosuspend(up->dev);
372 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
374 struct circ_buf *xmit = &up->port.state->xmit;
377 if (up->port.x_char) {
378 serial_out(up, UART_TX, up->port.x_char);
379 up->port.icount.tx++;
383 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
384 serial_omap_stop_tx(&up->port);
387 count = up->port.fifosize / 4;
389 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
390 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
391 up->port.icount.tx++;
392 if (uart_circ_empty(xmit))
394 } while (--count > 0);
396 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
397 spin_unlock(&up->port.lock);
398 uart_write_wakeup(&up->port);
399 spin_lock(&up->port.lock);
402 if (uart_circ_empty(xmit))
403 serial_omap_stop_tx(&up->port);
406 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
408 if (!(up->ier & UART_IER_THRI)) {
409 up->ier |= UART_IER_THRI;
410 serial_out(up, UART_IER, up->ier);
414 static void serial_omap_start_tx(struct uart_port *port)
416 struct uart_omap_port *up = to_uart_omap_port(port);
419 pm_runtime_get_sync(up->dev);
422 if (up->rs485.flags & SER_RS485_ENABLED) {
423 /* Fire THR interrupts when FIFO is below trigger level */
424 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
425 serial_out(up, UART_OMAP_SCR, up->scr);
427 /* if rts not already enabled */
428 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
429 if (gpio_get_value(up->rts_gpio) != res) {
430 gpio_set_value(up->rts_gpio, res);
431 if (up->rs485.delay_rts_before_send > 0)
432 mdelay(up->rs485.delay_rts_before_send);
436 if ((up->rs485.flags & SER_RS485_ENABLED) &&
437 !(up->rs485.flags & SER_RS485_RX_DURING_TX))
438 serial_omap_stop_rx(port);
440 serial_omap_enable_ier_thri(up);
441 pm_runtime_mark_last_busy(up->dev);
442 pm_runtime_put_autosuspend(up->dev);
445 static void serial_omap_throttle(struct uart_port *port)
447 struct uart_omap_port *up = to_uart_omap_port(port);
450 pm_runtime_get_sync(up->dev);
451 spin_lock_irqsave(&up->port.lock, flags);
452 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
453 serial_out(up, UART_IER, up->ier);
454 spin_unlock_irqrestore(&up->port.lock, flags);
455 pm_runtime_mark_last_busy(up->dev);
456 pm_runtime_put_autosuspend(up->dev);
459 static void serial_omap_unthrottle(struct uart_port *port)
461 struct uart_omap_port *up = to_uart_omap_port(port);
464 pm_runtime_get_sync(up->dev);
465 spin_lock_irqsave(&up->port.lock, flags);
466 up->ier |= UART_IER_RLSI | UART_IER_RDI;
467 serial_out(up, UART_IER, up->ier);
468 spin_unlock_irqrestore(&up->port.lock, flags);
469 pm_runtime_mark_last_busy(up->dev);
470 pm_runtime_put_autosuspend(up->dev);
473 static unsigned int check_modem_status(struct uart_omap_port *up)
477 status = serial_in(up, UART_MSR);
478 status |= up->msr_saved_flags;
479 up->msr_saved_flags = 0;
480 if ((status & UART_MSR_ANY_DELTA) == 0)
483 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
484 up->port.state != NULL) {
485 if (status & UART_MSR_TERI)
486 up->port.icount.rng++;
487 if (status & UART_MSR_DDSR)
488 up->port.icount.dsr++;
489 if (status & UART_MSR_DDCD)
490 uart_handle_dcd_change
491 (&up->port, status & UART_MSR_DCD);
492 if (status & UART_MSR_DCTS)
493 uart_handle_cts_change
494 (&up->port, status & UART_MSR_CTS);
495 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
501 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
504 unsigned char ch = 0;
506 if (likely(lsr & UART_LSR_DR))
507 ch = serial_in(up, UART_RX);
509 up->port.icount.rx++;
512 if (lsr & UART_LSR_BI) {
514 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
515 up->port.icount.brk++;
517 * We do the SysRQ and SAK checking
518 * here because otherwise the break
519 * may get masked by ignore_status_mask
520 * or read_status_mask.
522 if (uart_handle_break(&up->port))
527 if (lsr & UART_LSR_PE) {
529 up->port.icount.parity++;
532 if (lsr & UART_LSR_FE) {
534 up->port.icount.frame++;
537 if (lsr & UART_LSR_OE)
538 up->port.icount.overrun++;
540 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
541 if (up->port.line == up->port.cons->index) {
542 /* Recover the break flag from console xmit */
543 lsr |= up->lsr_break_flag;
546 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
549 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
551 unsigned char ch = 0;
554 if (!(lsr & UART_LSR_DR))
557 ch = serial_in(up, UART_RX);
559 up->port.icount.rx++;
561 if (uart_handle_sysrq_char(&up->port, ch))
564 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
568 * serial_omap_irq() - This handles the interrupt from one port
569 * @irq: uart port irq number
570 * @dev_id: uart port info
572 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
574 struct uart_omap_port *up = dev_id;
575 unsigned int iir, lsr;
577 irqreturn_t ret = IRQ_NONE;
580 spin_lock(&up->port.lock);
581 pm_runtime_get_sync(up->dev);
584 iir = serial_in(up, UART_IIR);
585 if (iir & UART_IIR_NO_INT)
589 lsr = serial_in(up, UART_LSR);
591 /* extract IRQ type from IIR register */
596 check_modem_status(up);
599 transmit_chars(up, lsr);
601 case UART_IIR_RX_TIMEOUT:
604 serial_omap_rdi(up, lsr);
607 serial_omap_rlsi(up, lsr);
609 case UART_IIR_CTS_RTS_DSR:
610 /* simply try again */
617 } while (!(iir & UART_IIR_NO_INT) && max_count--);
619 spin_unlock(&up->port.lock);
621 tty_flip_buffer_push(&up->port.state->port);
623 pm_runtime_mark_last_busy(up->dev);
624 pm_runtime_put_autosuspend(up->dev);
625 up->port_activity = jiffies;
630 static unsigned int serial_omap_tx_empty(struct uart_port *port)
632 struct uart_omap_port *up = to_uart_omap_port(port);
633 unsigned long flags = 0;
634 unsigned int ret = 0;
636 pm_runtime_get_sync(up->dev);
637 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
638 spin_lock_irqsave(&up->port.lock, flags);
639 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
640 spin_unlock_irqrestore(&up->port.lock, flags);
641 pm_runtime_mark_last_busy(up->dev);
642 pm_runtime_put_autosuspend(up->dev);
646 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
648 struct uart_omap_port *up = to_uart_omap_port(port);
650 unsigned int ret = 0;
652 pm_runtime_get_sync(up->dev);
653 status = check_modem_status(up);
654 pm_runtime_mark_last_busy(up->dev);
655 pm_runtime_put_autosuspend(up->dev);
657 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
659 if (status & UART_MSR_DCD)
661 if (status & UART_MSR_RI)
663 if (status & UART_MSR_DSR)
665 if (status & UART_MSR_CTS)
670 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
672 struct uart_omap_port *up = to_uart_omap_port(port);
673 unsigned char mcr = 0, old_mcr;
675 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
676 if (mctrl & TIOCM_RTS)
678 if (mctrl & TIOCM_DTR)
680 if (mctrl & TIOCM_OUT1)
681 mcr |= UART_MCR_OUT1;
682 if (mctrl & TIOCM_OUT2)
683 mcr |= UART_MCR_OUT2;
684 if (mctrl & TIOCM_LOOP)
685 mcr |= UART_MCR_LOOP;
687 pm_runtime_get_sync(up->dev);
688 old_mcr = serial_in(up, UART_MCR);
689 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
690 UART_MCR_DTR | UART_MCR_RTS);
691 up->mcr = old_mcr | mcr;
692 serial_out(up, UART_MCR, up->mcr);
693 pm_runtime_mark_last_busy(up->dev);
694 pm_runtime_put_autosuspend(up->dev);
696 if (gpio_is_valid(up->DTR_gpio) &&
697 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
698 up->DTR_active = !up->DTR_active;
699 if (gpio_cansleep(up->DTR_gpio))
700 schedule_work(&up->qos_work);
702 gpio_set_value(up->DTR_gpio,
703 up->DTR_active != up->DTR_inverted);
707 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
709 struct uart_omap_port *up = to_uart_omap_port(port);
710 unsigned long flags = 0;
712 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
713 pm_runtime_get_sync(up->dev);
714 spin_lock_irqsave(&up->port.lock, flags);
715 if (break_state == -1)
716 up->lcr |= UART_LCR_SBC;
718 up->lcr &= ~UART_LCR_SBC;
719 serial_out(up, UART_LCR, up->lcr);
720 spin_unlock_irqrestore(&up->port.lock, flags);
721 pm_runtime_mark_last_busy(up->dev);
722 pm_runtime_put_autosuspend(up->dev);
725 static int serial_omap_startup(struct uart_port *port)
727 struct uart_omap_port *up = to_uart_omap_port(port);
728 unsigned long flags = 0;
734 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
739 /* Optional wake-up IRQ */
741 retval = request_irq(up->wakeirq, serial_omap_irq,
742 up->port.irqflags, up->name, up);
744 free_irq(up->port.irq, up);
747 disable_irq(up->wakeirq);
750 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
752 pm_runtime_get_sync(up->dev);
754 * Clear the FIFO buffers and disable them.
755 * (they will be reenabled in set_termios())
757 serial_omap_clear_fifos(up);
758 /* For Hardware flow control */
759 serial_out(up, UART_MCR, UART_MCR_RTS);
762 * Clear the interrupt registers.
764 (void) serial_in(up, UART_LSR);
765 if (serial_in(up, UART_LSR) & UART_LSR_DR)
766 (void) serial_in(up, UART_RX);
767 (void) serial_in(up, UART_IIR);
768 (void) serial_in(up, UART_MSR);
771 * Now, initialize the UART
773 serial_out(up, UART_LCR, UART_LCR_WLEN8);
774 spin_lock_irqsave(&up->port.lock, flags);
776 * Most PC uarts need OUT2 raised to enable interrupts.
778 up->port.mctrl |= TIOCM_OUT2;
779 serial_omap_set_mctrl(&up->port, up->port.mctrl);
780 spin_unlock_irqrestore(&up->port.lock, flags);
782 up->msr_saved_flags = 0;
784 * Finally, enable interrupts. Note: Modem status interrupts
785 * are set via set_termios(), which will be occurring imminently
786 * anyway, so we don't enable them here.
788 up->ier = UART_IER_RLSI | UART_IER_RDI;
789 serial_out(up, UART_IER, up->ier);
791 /* Enable module level wake up */
792 up->wer = OMAP_UART_WER_MOD_WKUP;
793 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
794 up->wer |= OMAP_UART_TX_WAKEUP_EN;
796 serial_out(up, UART_OMAP_WER, up->wer);
798 pm_runtime_mark_last_busy(up->dev);
799 pm_runtime_put_autosuspend(up->dev);
800 up->port_activity = jiffies;
804 static void serial_omap_shutdown(struct uart_port *port)
806 struct uart_omap_port *up = to_uart_omap_port(port);
807 unsigned long flags = 0;
809 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
811 pm_runtime_get_sync(up->dev);
813 * Disable interrupts from this port
816 serial_out(up, UART_IER, 0);
818 spin_lock_irqsave(&up->port.lock, flags);
819 up->port.mctrl &= ~TIOCM_OUT2;
820 serial_omap_set_mctrl(&up->port, up->port.mctrl);
821 spin_unlock_irqrestore(&up->port.lock, flags);
824 * Disable break condition and FIFOs
826 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
827 serial_omap_clear_fifos(up);
830 * Read data port to reset things, and then free the irq
832 if (serial_in(up, UART_LSR) & UART_LSR_DR)
833 (void) serial_in(up, UART_RX);
835 pm_runtime_mark_last_busy(up->dev);
836 pm_runtime_put_autosuspend(up->dev);
837 free_irq(up->port.irq, up);
839 free_irq(up->wakeirq, up);
842 static void serial_omap_uart_qos_work(struct work_struct *work)
844 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
847 pm_qos_update_request(&up->pm_qos_request, up->latency);
848 if (gpio_is_valid(up->DTR_gpio))
849 gpio_set_value_cansleep(up->DTR_gpio,
850 up->DTR_active != up->DTR_inverted);
854 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
855 struct ktermios *old)
857 struct uart_omap_port *up = to_uart_omap_port(port);
858 unsigned char cval = 0;
859 unsigned long flags = 0;
860 unsigned int baud, quot;
862 switch (termios->c_cflag & CSIZE) {
864 cval = UART_LCR_WLEN5;
867 cval = UART_LCR_WLEN6;
870 cval = UART_LCR_WLEN7;
874 cval = UART_LCR_WLEN8;
878 if (termios->c_cflag & CSTOPB)
879 cval |= UART_LCR_STOP;
880 if (termios->c_cflag & PARENB)
881 cval |= UART_LCR_PARITY;
882 if (!(termios->c_cflag & PARODD))
883 cval |= UART_LCR_EPAR;
884 if (termios->c_cflag & CMSPAR)
885 cval |= UART_LCR_SPAR;
888 * Ask the core to calculate the divisor for us.
891 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
892 quot = serial_omap_get_divisor(port, baud);
894 /* calculate wakeup latency constraint */
895 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
896 up->latency = up->calc_latency;
897 schedule_work(&up->qos_work);
899 up->dll = quot & 0xff;
901 up->mdr1 = UART_OMAP_MDR1_DISABLE;
903 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
904 UART_FCR_ENABLE_FIFO;
907 * Ok, we're now changing the port state. Do it with
908 * interrupts disabled.
910 pm_runtime_get_sync(up->dev);
911 spin_lock_irqsave(&up->port.lock, flags);
914 * Update the per-port timeout.
916 uart_update_timeout(port, termios->c_cflag, baud);
918 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
919 if (termios->c_iflag & INPCK)
920 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
921 if (termios->c_iflag & (BRKINT | PARMRK))
922 up->port.read_status_mask |= UART_LSR_BI;
925 * Characters to ignore
927 up->port.ignore_status_mask = 0;
928 if (termios->c_iflag & IGNPAR)
929 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
930 if (termios->c_iflag & IGNBRK) {
931 up->port.ignore_status_mask |= UART_LSR_BI;
933 * If we're ignoring parity and break indicators,
934 * ignore overruns too (for real raw support).
936 if (termios->c_iflag & IGNPAR)
937 up->port.ignore_status_mask |= UART_LSR_OE;
941 * ignore all characters if CREAD is not set
943 if ((termios->c_cflag & CREAD) == 0)
944 up->port.ignore_status_mask |= UART_LSR_DR;
947 * Modem status interrupts
949 up->ier &= ~UART_IER_MSI;
950 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
951 up->ier |= UART_IER_MSI;
952 serial_out(up, UART_IER, up->ier);
953 serial_out(up, UART_LCR, cval); /* reset DLAB */
957 /* FIFOs and DMA Settings */
959 /* FCR can be changed only when the
960 * baud clock is not running
961 * DLL_REG and DLH_REG set to 0.
963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
964 serial_out(up, UART_DLL, 0);
965 serial_out(up, UART_DLM, 0);
966 serial_out(up, UART_LCR, 0);
968 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
970 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
971 up->efr &= ~UART_EFR_SCD;
972 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
974 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
975 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
976 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
977 /* FIFO ENABLE, DMA MODE */
979 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
981 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
982 * sets Enables the granularity of 1 for TRIGGER RX
983 * level. Along with setting RX FIFO trigger level
984 * to 1 (as noted below, 16 characters) and TLR[3:0]
985 * to zero this will result RX FIFO threshold level
986 * to 1 character, instead of 16 as noted in comment
990 /* Set receive FIFO threshold to 16 characters and
991 * transmit FIFO threshold to 32 spaces
993 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
994 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
995 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
996 UART_FCR_ENABLE_FIFO;
998 serial_out(up, UART_FCR, up->fcr);
999 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1001 serial_out(up, UART_OMAP_SCR, up->scr);
1003 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1004 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1005 serial_out(up, UART_MCR, up->mcr);
1006 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007 serial_out(up, UART_EFR, up->efr);
1008 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1010 /* Protocol, Baud Rate, and Interrupt Settings */
1012 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1013 serial_omap_mdr1_errataset(up, up->mdr1);
1015 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1017 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1018 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1020 serial_out(up, UART_LCR, 0);
1021 serial_out(up, UART_IER, 0);
1022 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1024 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1025 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1027 serial_out(up, UART_LCR, 0);
1028 serial_out(up, UART_IER, up->ier);
1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1031 serial_out(up, UART_EFR, up->efr);
1032 serial_out(up, UART_LCR, cval);
1034 if (!serial_omap_baud_is_mode16(port, baud))
1035 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1037 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1039 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1040 serial_omap_mdr1_errataset(up, up->mdr1);
1042 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1044 /* Configure flow control */
1045 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1047 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1048 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1049 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1051 /* Enable access to TCR/TLR */
1052 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1053 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1054 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1056 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1058 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1059 /* Enable AUTORTS and AUTOCTS */
1060 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1062 /* Ensure MCR RTS is asserted */
1063 up->mcr |= UART_MCR_RTS;
1065 /* Disable AUTORTS and AUTOCTS */
1066 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1069 if (up->port.flags & UPF_SOFT_FLOW) {
1070 /* clear SW control mode bits */
1071 up->efr &= OMAP_UART_SW_CLR;
1075 * Enable XON/XOFF flow control on input.
1076 * Receiver compares XON1, XOFF1.
1078 if (termios->c_iflag & IXON)
1079 up->efr |= OMAP_UART_SW_RX;
1083 * Enable XON/XOFF flow control on output.
1084 * Transmit XON1, XOFF1
1086 if (termios->c_iflag & IXOFF)
1087 up->efr |= OMAP_UART_SW_TX;
1091 * Enable any character to restart output.
1092 * Operation resumes after receiving any
1093 * character after recognition of the XOFF character
1095 if (termios->c_iflag & IXANY)
1096 up->mcr |= UART_MCR_XONANY;
1098 up->mcr &= ~UART_MCR_XONANY;
1100 serial_out(up, UART_MCR, up->mcr);
1101 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1102 serial_out(up, UART_EFR, up->efr);
1103 serial_out(up, UART_LCR, up->lcr);
1105 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1107 spin_unlock_irqrestore(&up->port.lock, flags);
1108 pm_runtime_mark_last_busy(up->dev);
1109 pm_runtime_put_autosuspend(up->dev);
1110 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1114 serial_omap_pm(struct uart_port *port, unsigned int state,
1115 unsigned int oldstate)
1117 struct uart_omap_port *up = to_uart_omap_port(port);
1120 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1122 pm_runtime_get_sync(up->dev);
1123 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1124 efr = serial_in(up, UART_EFR);
1125 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1126 serial_out(up, UART_LCR, 0);
1128 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1129 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1130 serial_out(up, UART_EFR, efr);
1131 serial_out(up, UART_LCR, 0);
1133 if (!device_may_wakeup(up->dev)) {
1135 pm_runtime_forbid(up->dev);
1137 pm_runtime_allow(up->dev);
1140 pm_runtime_mark_last_busy(up->dev);
1141 pm_runtime_put_autosuspend(up->dev);
1144 static void serial_omap_release_port(struct uart_port *port)
1146 dev_dbg(port->dev, "serial_omap_release_port+\n");
1149 static int serial_omap_request_port(struct uart_port *port)
1151 dev_dbg(port->dev, "serial_omap_request_port+\n");
1155 static void serial_omap_config_port(struct uart_port *port, int flags)
1157 struct uart_omap_port *up = to_uart_omap_port(port);
1159 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1161 up->port.type = PORT_OMAP;
1162 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1166 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1168 /* we don't want the core code to modify any port params */
1169 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1174 serial_omap_type(struct uart_port *port)
1176 struct uart_omap_port *up = to_uart_omap_port(port);
1178 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1182 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1184 static inline void wait_for_xmitr(struct uart_omap_port *up)
1186 unsigned int status, tmout = 10000;
1188 /* Wait up to 10ms for the character(s) to be sent. */
1190 status = serial_in(up, UART_LSR);
1192 if (status & UART_LSR_BI)
1193 up->lsr_break_flag = UART_LSR_BI;
1198 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1200 /* Wait up to 1s for flow control if necessary */
1201 if (up->port.flags & UPF_CONS_FLOW) {
1203 for (tmout = 1000000; tmout; tmout--) {
1204 unsigned int msr = serial_in(up, UART_MSR);
1206 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1207 if (msr & UART_MSR_CTS)
1215 #ifdef CONFIG_CONSOLE_POLL
1217 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1219 struct uart_omap_port *up = to_uart_omap_port(port);
1221 pm_runtime_get_sync(up->dev);
1223 serial_out(up, UART_TX, ch);
1224 pm_runtime_mark_last_busy(up->dev);
1225 pm_runtime_put_autosuspend(up->dev);
1228 static int serial_omap_poll_get_char(struct uart_port *port)
1230 struct uart_omap_port *up = to_uart_omap_port(port);
1231 unsigned int status;
1233 pm_runtime_get_sync(up->dev);
1234 status = serial_in(up, UART_LSR);
1235 if (!(status & UART_LSR_DR)) {
1236 status = NO_POLL_CHAR;
1240 status = serial_in(up, UART_RX);
1243 pm_runtime_mark_last_busy(up->dev);
1244 pm_runtime_put_autosuspend(up->dev);
1249 #endif /* CONFIG_CONSOLE_POLL */
1251 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1253 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1255 static struct uart_driver serial_omap_reg;
1257 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1259 struct uart_omap_port *up = to_uart_omap_port(port);
1262 serial_out(up, UART_TX, ch);
1266 serial_omap_console_write(struct console *co, const char *s,
1269 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1270 unsigned long flags;
1274 pm_runtime_get_sync(up->dev);
1276 local_irq_save(flags);
1279 else if (oops_in_progress)
1280 locked = spin_trylock(&up->port.lock);
1282 spin_lock(&up->port.lock);
1285 * First save the IER then disable the interrupts
1287 ier = serial_in(up, UART_IER);
1288 serial_out(up, UART_IER, 0);
1290 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1293 * Finally, wait for transmitter to become empty
1294 * and restore the IER
1297 serial_out(up, UART_IER, ier);
1299 * The receive handling will happen properly because the
1300 * receive ready bit will still be set; it is not cleared
1301 * on read. However, modem control will not, we must
1302 * call it if we have saved something in the saved flags
1303 * while processing with interrupts off.
1305 if (up->msr_saved_flags)
1306 check_modem_status(up);
1308 pm_runtime_mark_last_busy(up->dev);
1309 pm_runtime_put_autosuspend(up->dev);
1311 spin_unlock(&up->port.lock);
1312 local_irq_restore(flags);
1316 serial_omap_console_setup(struct console *co, char *options)
1318 struct uart_omap_port *up;
1324 if (serial_omap_console_ports[co->index] == NULL)
1326 up = serial_omap_console_ports[co->index];
1329 uart_parse_options(options, &baud, &parity, &bits, &flow);
1331 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1334 static struct console serial_omap_console = {
1335 .name = OMAP_SERIAL_NAME,
1336 .write = serial_omap_console_write,
1337 .device = uart_console_device,
1338 .setup = serial_omap_console_setup,
1339 .flags = CON_PRINTBUFFER,
1341 .data = &serial_omap_reg,
1344 static void serial_omap_add_console_port(struct uart_omap_port *up)
1346 serial_omap_console_ports[up->port.line] = up;
1349 #define OMAP_CONSOLE (&serial_omap_console)
1353 #define OMAP_CONSOLE NULL
1355 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1360 /* Enable or disable the rs485 support */
1362 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1364 struct uart_omap_port *up = to_uart_omap_port(port);
1365 unsigned long flags;
1369 pm_runtime_get_sync(up->dev);
1370 spin_lock_irqsave(&up->port.lock, flags);
1372 /* Disable interrupts from this port */
1375 serial_out(up, UART_IER, 0);
1377 /* store new config */
1378 up->rs485 = *rs485conf;
1381 * Just as a precaution, only allow rs485
1382 * to be enabled if the gpio pin is valid
1384 if (gpio_is_valid(up->rts_gpio)) {
1385 /* enable / disable rts */
1386 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1387 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1388 val = (up->rs485.flags & val) ? 1 : 0;
1389 gpio_set_value(up->rts_gpio, val);
1391 up->rs485.flags &= ~SER_RS485_ENABLED;
1393 /* Enable interrupts */
1395 serial_out(up, UART_IER, up->ier);
1397 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1398 * TX FIFO is below the trigger level.
1400 if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1401 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1402 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1403 serial_out(up, UART_OMAP_SCR, up->scr);
1406 spin_unlock_irqrestore(&up->port.lock, flags);
1407 pm_runtime_mark_last_busy(up->dev);
1408 pm_runtime_put_autosuspend(up->dev);
1412 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1414 struct serial_rs485 rs485conf;
1418 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1422 serial_omap_config_rs485(port, &rs485conf);
1426 if (copy_to_user((struct serial_rs485 *) arg,
1427 &(to_uart_omap_port(port)->rs485),
1433 return -ENOIOCTLCMD;
1439 static struct uart_ops serial_omap_pops = {
1440 .tx_empty = serial_omap_tx_empty,
1441 .set_mctrl = serial_omap_set_mctrl,
1442 .get_mctrl = serial_omap_get_mctrl,
1443 .stop_tx = serial_omap_stop_tx,
1444 .start_tx = serial_omap_start_tx,
1445 .throttle = serial_omap_throttle,
1446 .unthrottle = serial_omap_unthrottle,
1447 .stop_rx = serial_omap_stop_rx,
1448 .enable_ms = serial_omap_enable_ms,
1449 .break_ctl = serial_omap_break_ctl,
1450 .startup = serial_omap_startup,
1451 .shutdown = serial_omap_shutdown,
1452 .set_termios = serial_omap_set_termios,
1453 .pm = serial_omap_pm,
1454 .type = serial_omap_type,
1455 .release_port = serial_omap_release_port,
1456 .request_port = serial_omap_request_port,
1457 .config_port = serial_omap_config_port,
1458 .verify_port = serial_omap_verify_port,
1459 .ioctl = serial_omap_ioctl,
1460 #ifdef CONFIG_CONSOLE_POLL
1461 .poll_put_char = serial_omap_poll_put_char,
1462 .poll_get_char = serial_omap_poll_get_char,
1466 static struct uart_driver serial_omap_reg = {
1467 .owner = THIS_MODULE,
1468 .driver_name = "OMAP-SERIAL",
1469 .dev_name = OMAP_SERIAL_NAME,
1470 .nr = OMAP_MAX_HSUART_PORTS,
1471 .cons = OMAP_CONSOLE,
1474 #ifdef CONFIG_PM_SLEEP
1475 static int serial_omap_prepare(struct device *dev)
1477 struct uart_omap_port *up = dev_get_drvdata(dev);
1479 up->is_suspending = true;
1484 static void serial_omap_complete(struct device *dev)
1486 struct uart_omap_port *up = dev_get_drvdata(dev);
1488 up->is_suspending = false;
1491 static int serial_omap_suspend(struct device *dev)
1493 struct uart_omap_port *up = dev_get_drvdata(dev);
1495 uart_suspend_port(&serial_omap_reg, &up->port);
1496 flush_work(&up->qos_work);
1501 static int serial_omap_resume(struct device *dev)
1503 struct uart_omap_port *up = dev_get_drvdata(dev);
1505 uart_resume_port(&serial_omap_reg, &up->port);
1510 #define serial_omap_prepare NULL
1511 #define serial_omap_complete NULL
1512 #endif /* CONFIG_PM_SLEEP */
1514 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1517 u16 revision, major, minor;
1519 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1521 /* Check revision register scheme */
1522 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1525 case 0: /* Legacy Scheme: OMAP2/3 */
1526 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1527 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1528 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1529 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1532 /* New Scheme: OMAP4+ */
1533 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1534 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1535 OMAP_UART_MVR_MAJ_SHIFT;
1536 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1540 "Unknown %s revision, defaulting to highest\n",
1542 /* highest possible revision */
1547 /* normalize revision for the driver */
1548 revision = UART_BUILD_REVISION(major, minor);
1551 case OMAP_UART_REV_46:
1552 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1553 UART_ERRATA_i291_DMA_FORCEIDLE);
1555 case OMAP_UART_REV_52:
1556 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1557 UART_ERRATA_i291_DMA_FORCEIDLE);
1558 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1560 case OMAP_UART_REV_63:
1561 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1562 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1569 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1571 struct omap_uart_port_info *omap_up_info;
1573 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1575 return NULL; /* out of memory */
1577 of_property_read_u32(dev->of_node, "clock-frequency",
1578 &omap_up_info->uartclk);
1579 return omap_up_info;
1582 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1583 struct device_node *np)
1585 struct serial_rs485 *rs485conf = &up->rs485;
1587 enum of_gpio_flags flags;
1590 rs485conf->flags = 0;
1591 up->rts_gpio = -EINVAL;
1596 if (of_property_read_bool(np, "rs485-rts-active-high"))
1597 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1599 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1601 /* check for tx enable gpio */
1602 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1603 if (gpio_is_valid(up->rts_gpio)) {
1604 ret = gpio_request(up->rts_gpio, "omap-serial");
1607 ret = gpio_direction_output(up->rts_gpio,
1608 flags & SER_RS485_RTS_AFTER_SEND);
1611 } else if (up->rts_gpio == -EPROBE_DEFER) {
1612 return -EPROBE_DEFER;
1614 up->rts_gpio = -EINVAL;
1617 if (of_property_read_u32_array(np, "rs485-rts-delay",
1618 rs485_delay, 2) == 0) {
1619 rs485conf->delay_rts_before_send = rs485_delay[0];
1620 rs485conf->delay_rts_after_send = rs485_delay[1];
1623 if (of_property_read_bool(np, "rs485-rx-during-tx"))
1624 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1626 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1627 rs485conf->flags |= SER_RS485_ENABLED;
1632 static int serial_omap_probe(struct platform_device *pdev)
1634 struct uart_omap_port *up;
1635 struct resource *mem, *irq;
1636 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1637 int ret, uartirq = 0, wakeirq = 0;
1639 /* The optional wakeirq may be specified in the board dts file */
1640 if (pdev->dev.of_node) {
1641 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1643 return -EPROBE_DEFER;
1644 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1645 omap_up_info = of_get_uart_port_info(&pdev->dev);
1646 pdev->dev.platform_data = omap_up_info;
1648 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1650 dev_err(&pdev->dev, "no irq resource?\n");
1653 uartirq = irq->start;
1656 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1658 dev_err(&pdev->dev, "no mem resource?\n");
1662 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1663 pdev->dev.driver->name)) {
1664 dev_err(&pdev->dev, "memory region already claimed\n");
1668 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1669 omap_up_info->DTR_present) {
1670 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1673 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1674 omap_up_info->DTR_inverted);
1679 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1683 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1684 omap_up_info->DTR_present) {
1685 up->DTR_gpio = omap_up_info->DTR_gpio;
1686 up->DTR_inverted = omap_up_info->DTR_inverted;
1688 up->DTR_gpio = -EINVAL;
1691 up->dev = &pdev->dev;
1692 up->port.dev = &pdev->dev;
1693 up->port.type = PORT_OMAP;
1694 up->port.iotype = UPIO_MEM;
1695 up->port.irq = uartirq;
1696 up->wakeirq = wakeirq;
1698 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1701 up->port.regshift = 2;
1702 up->port.fifosize = 64;
1703 up->port.ops = &serial_omap_pops;
1705 if (pdev->dev.of_node)
1706 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1708 up->port.line = pdev->id;
1710 if (up->port.line < 0) {
1711 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1717 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1721 sprintf(up->name, "OMAP UART%d", up->port.line);
1722 up->port.mapbase = mem->start;
1723 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1724 resource_size(mem));
1725 if (!up->port.membase) {
1726 dev_err(&pdev->dev, "can't ioremap UART\n");
1731 up->port.flags = omap_up_info->flags;
1732 up->port.uartclk = omap_up_info->uartclk;
1733 if (!up->port.uartclk) {
1734 up->port.uartclk = DEFAULT_CLK_SPEED;
1735 dev_warn(&pdev->dev,
1736 "No clock speed specified: using default: %d\n",
1740 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1741 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1742 pm_qos_add_request(&up->pm_qos_request,
1743 PM_QOS_CPU_DMA_LATENCY, up->latency);
1744 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1745 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1747 platform_set_drvdata(pdev, up);
1748 if (omap_up_info->autosuspend_timeout == 0)
1749 omap_up_info->autosuspend_timeout = -1;
1750 device_init_wakeup(up->dev, true);
1751 pm_runtime_use_autosuspend(&pdev->dev);
1752 pm_runtime_set_autosuspend_delay(&pdev->dev,
1753 omap_up_info->autosuspend_timeout);
1755 pm_runtime_irq_safe(&pdev->dev);
1756 pm_runtime_enable(&pdev->dev);
1758 pm_runtime_get_sync(&pdev->dev);
1760 omap_serial_fill_features_erratas(up);
1762 ui[up->port.line] = up;
1763 serial_omap_add_console_port(up);
1765 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1769 pm_runtime_mark_last_busy(up->dev);
1770 pm_runtime_put_autosuspend(up->dev);
1774 pm_runtime_put(&pdev->dev);
1775 pm_runtime_disable(&pdev->dev);
1779 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1780 pdev->id, __func__, ret);
1784 static int serial_omap_remove(struct platform_device *dev)
1786 struct uart_omap_port *up = platform_get_drvdata(dev);
1788 pm_runtime_put_sync(up->dev);
1789 pm_runtime_disable(up->dev);
1790 uart_remove_one_port(&serial_omap_reg, &up->port);
1791 pm_qos_remove_request(&up->pm_qos_request);
1797 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1798 * The access to uart register after MDR1 Access
1799 * causes UART to corrupt data.
1802 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1803 * give 10 times as much
1805 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1809 serial_out(up, UART_OMAP_MDR1, mdr1);
1811 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1812 UART_FCR_CLEAR_RCVR);
1814 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1815 * TX_FIFO_E bit is 1.
1817 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1818 (UART_LSR_THRE | UART_LSR_DR))) {
1821 /* Should *never* happen. we warn and carry on */
1822 dev_crit(up->dev, "Errata i202: timedout %x\n",
1823 serial_in(up, UART_LSR));
1830 #ifdef CONFIG_PM_RUNTIME
1831 static void serial_omap_restore_context(struct uart_omap_port *up)
1833 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1834 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1836 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1839 serial_out(up, UART_EFR, UART_EFR_ECB);
1840 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1841 serial_out(up, UART_IER, 0x0);
1842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1843 serial_out(up, UART_DLL, up->dll);
1844 serial_out(up, UART_DLM, up->dlh);
1845 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1846 serial_out(up, UART_IER, up->ier);
1847 serial_out(up, UART_FCR, up->fcr);
1848 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1849 serial_out(up, UART_MCR, up->mcr);
1850 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1851 serial_out(up, UART_OMAP_SCR, up->scr);
1852 serial_out(up, UART_EFR, up->efr);
1853 serial_out(up, UART_LCR, up->lcr);
1854 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1855 serial_omap_mdr1_errataset(up, up->mdr1);
1857 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1858 serial_out(up, UART_OMAP_WER, up->wer);
1861 static int serial_omap_runtime_suspend(struct device *dev)
1863 struct uart_omap_port *up = dev_get_drvdata(dev);
1869 * When using 'no_console_suspend', the console UART must not be
1870 * suspended. Since driver suspend is managed by runtime suspend,
1871 * preventing runtime suspend (by returning error) will keep device
1872 * active during suspend.
1874 if (up->is_suspending && !console_suspend_enabled &&
1875 uart_console(&up->port))
1878 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1880 if (device_may_wakeup(dev)) {
1881 if (!up->wakeups_enabled) {
1882 serial_omap_enable_wakeup(up, true);
1883 up->wakeups_enabled = true;
1886 if (up->wakeups_enabled) {
1887 serial_omap_enable_wakeup(up, false);
1888 up->wakeups_enabled = false;
1892 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1893 schedule_work(&up->qos_work);
1898 static int serial_omap_runtime_resume(struct device *dev)
1900 struct uart_omap_port *up = dev_get_drvdata(dev);
1902 int loss_cnt = serial_omap_get_context_loss_count(up);
1905 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1907 serial_omap_restore_context(up);
1908 } else if (up->context_loss_cnt != loss_cnt) {
1909 serial_omap_restore_context(up);
1911 up->latency = up->calc_latency;
1912 schedule_work(&up->qos_work);
1918 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1919 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1920 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1921 serial_omap_runtime_resume, NULL)
1922 .prepare = serial_omap_prepare,
1923 .complete = serial_omap_complete,
1926 #if defined(CONFIG_OF)
1927 static const struct of_device_id omap_serial_of_match[] = {
1928 { .compatible = "ti,omap2-uart" },
1929 { .compatible = "ti,omap3-uart" },
1930 { .compatible = "ti,omap4-uart" },
1933 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1936 static struct platform_driver serial_omap_driver = {
1937 .probe = serial_omap_probe,
1938 .remove = serial_omap_remove,
1940 .name = DRIVER_NAME,
1941 .pm = &serial_omap_dev_pm_ops,
1942 .of_match_table = of_match_ptr(omap_serial_of_match),
1946 static int __init serial_omap_init(void)
1950 ret = uart_register_driver(&serial_omap_reg);
1953 ret = platform_driver_register(&serial_omap_driver);
1955 uart_unregister_driver(&serial_omap_reg);
1959 static void __exit serial_omap_exit(void)
1961 platform_driver_unregister(&serial_omap_driver);
1962 uart_unregister_driver(&serial_omap_reg);
1965 module_init(serial_omap_init);
1966 module_exit(serial_omap_exit);
1968 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1969 MODULE_LICENSE("GPL");
1970 MODULE_AUTHOR("Texas Instruments Inc");