drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43
  44 #include <plat/omap-serial.h>
  45
  46 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  47
  48 #define OMAP_UART_REV_42 0x0402
  49 #define OMAP_UART_REV_46 0x0406
  50 #define OMAP_UART_REV_52 0x0502
  51 #define OMAP_UART_REV_63 0x0603
  52
  53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  54
  55 /* SCR register bitmasks */
  56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  57
  58 /* FCR register bitmasks */
  59 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  60 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  61
  62 /* MVR register bitmasks */
  63 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  64
  65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  67 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  68
  69 #define OMAP_UART_MVR_MAJ_MASK          0x700
  70 #define OMAP_UART_MVR_MAJ_SHIFT         8
  71 #define OMAP_UART_MVR_MIN_MASK          0x3f
  72
  73 struct uart_omap_port {
  74         struct uart_port        port;
  75         struct uart_omap_dma    uart_dma;
  76         struct device           *dev;
  77
  78         unsigned char           ier;
  79         unsigned char           lcr;
  80         unsigned char           mcr;
  81         unsigned char           fcr;
  82         unsigned char           efr;
  83         unsigned char           dll;
  84         unsigned char           dlh;
  85         unsigned char           mdr1;
  86         unsigned char           scr;
  87
  88         int                     use_dma;
  89         /*
  90          * Some bits in registers are cleared on a read, so they must
  91          * be saved whenever the register is read but the bits will not
  92          * be immediately processed.
  93          */
  94         unsigned int            lsr_break_flag;
  95         unsigned char           msr_saved_flags;
  96         char                    name[20];
  97         unsigned long           port_activity;
  98         u32                     context_loss_cnt;
  99         u32                     errata;
 100         u8                      wakeups_enabled;
 101         unsigned int            irq_pending:1;
 102
 103         struct pm_qos_request   pm_qos_request;
 104         u32                     latency;
 105         u32                     calc_latency;
 106         struct work_struct      qos_work;
 107 };
 108
 109 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 110
 111 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 112
 113 /* Forward declaration of functions */
 114 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 115
 116 static struct workqueue_struct *serial_omap_uart_wq;
 117
 118 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 119 {
 120         offset <<= up->port.regshift;
 121         return readw(up->port.membase + offset);
 122 }
 123
 124 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 125 {
 126         offset <<= up->port.regshift;
 127         writew(value, up->port.membase + offset);
 128 }
 129
 130 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 131 {
 132         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 133         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 134                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 135         serial_out(up, UART_FCR, 0);
 136 }
 137
 138 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 139 {
 140         struct omap_uart_port_info *pdata = up->dev->platform_data;
 141
 142         if (!pdata->get_context_loss_count)
 143                 return 0;
 144
 145         return pdata->get_context_loss_count(up->dev);
 146 }
 147
 148 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 149 {
 150         struct omap_uart_port_info *pdata = up->dev->platform_data;
 151
 152         if (pdata->set_forceidle)
 153                 pdata->set_forceidle(up->dev);
 154 }
 155
 156 static void serial_omap_set_noidle(struct uart_omap_port *up)
 157 {
 158         struct omap_uart_port_info *pdata = up->dev->platform_data;
 159
 160         if (pdata->set_noidle)
 161                 pdata->set_noidle(up->dev);
 162 }
 163
 164 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 165 {
 166         struct omap_uart_port_info *pdata = up->dev->platform_data;
 167
 168         if (pdata->enable_wakeup)
 169                 pdata->enable_wakeup(up->dev, enable);
 170 }
 171
 172 /*
 173  * serial_omap_get_divisor - calculate divisor value
 174  * @port: uart port info
 175  * @baud: baudrate for which divisor needs to be calculated.
 176  *
 177  * We have written our own function to get the divisor so as to support
 178  * 13x mode. 3Mbps Baudrate as an different divisor.
 179  * Reference OMAP TRM Chapter 17:
 180  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 181  * referring to oversampling - divisor value
 182  * baudrate 460,800 to 3,686,400 all have divisor 13
 183  * except 3,000,000 which has divisor value 16
 184  */
 185 static unsigned int
 186 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 187 {
 188         unsigned int divisor;
 189
 190         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 191                 divisor = 13;
 192         else
 193                 divisor = 16;
 194         return port->uartclk/(baud * divisor);
 195 }
 196
 197 static void serial_omap_enable_ms(struct uart_port *port)
 198 {
 199         struct uart_omap_port *up = to_uart_omap_port(port);
 200
 201         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 202
 203         pm_runtime_get_sync(up->dev);
 204         up->ier |= UART_IER_MSI;
 205         serial_out(up, UART_IER, up->ier);
 206         pm_runtime_mark_last_busy(up->dev);
 207         pm_runtime_put_autosuspend(up->dev);
 208 }
 209
 210 static void serial_omap_stop_tx(struct uart_port *port)
 211 {
 212         struct uart_omap_port *up = to_uart_omap_port(port);
 213
 214         pm_runtime_get_sync(up->dev);
 215         if (up->ier & UART_IER_THRI) {
 216                 up->ier &= ~UART_IER_THRI;
 217                 serial_out(up, UART_IER, up->ier);
 218         }
 219
 220         serial_omap_set_forceidle(up);
 221
 222         pm_runtime_mark_last_busy(up->dev);
 223         pm_runtime_put_autosuspend(up->dev);
 224 }
 225
 226 static void serial_omap_stop_rx(struct uart_port *port)
 227 {
 228         struct uart_omap_port *up = to_uart_omap_port(port);
 229
 230         pm_runtime_get_sync(up->dev);
 231         up->ier &= ~UART_IER_RLSI;
 232         up->port.read_status_mask &= ~UART_LSR_DR;
 233         serial_out(up, UART_IER, up->ier);
 234         pm_runtime_mark_last_busy(up->dev);
 235         pm_runtime_put_autosuspend(up->dev);
 236 }
 237
 238 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 239 {
 240         struct circ_buf *xmit = &up->port.state->xmit;
 241         int count;
 242
 243         if (!(lsr & UART_LSR_THRE))
 244                 return;
 245
 246         if (up->port.x_char) {
 247                 serial_out(up, UART_TX, up->port.x_char);
 248                 up->port.icount.tx++;
 249                 up->port.x_char = 0;
 250                 return;
 251         }
 252         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 253                 serial_omap_stop_tx(&up->port);
 254                 return;
 255         }
 256         count = up->port.fifosize / 4;
 257         do {
 258                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 259                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 260                 up->port.icount.tx++;
 261                 if (uart_circ_empty(xmit))
 262                         break;
 263         } while (--count > 0);
 264
 265         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 266                 spin_unlock(&up->port.lock);
 267                 uart_write_wakeup(&up->port);
 268                 spin_lock(&up->port.lock);
 269         }
 270
 271         if (uart_circ_empty(xmit))
 272                 serial_omap_stop_tx(&up->port);
 273 }
 274
 275 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 276 {
 277         if (!(up->ier & UART_IER_THRI)) {
 278                 up->ier |= UART_IER_THRI;
 279                 serial_out(up, UART_IER, up->ier);
 280         }
 281 }
 282
 283 static void serial_omap_start_tx(struct uart_port *port)
 284 {
 285         struct uart_omap_port *up = to_uart_omap_port(port);
 286
 287         pm_runtime_get_sync(up->dev);
 288         serial_omap_enable_ier_thri(up);
 289         serial_omap_set_noidle(up);
 290         pm_runtime_mark_last_busy(up->dev);
 291         pm_runtime_put_autosuspend(up->dev);
 292 }
 293
 294 static unsigned int check_modem_status(struct uart_omap_port *up)
 295 {
 296         unsigned int status;
 297
 298         status = serial_in(up, UART_MSR);
 299         status |= up->msr_saved_flags;
 300         up->msr_saved_flags = 0;
 301         if ((status & UART_MSR_ANY_DELTA) == 0)
 302                 return status;
 303
 304         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 305             up->port.state != NULL) {
 306                 if (status & UART_MSR_TERI)
 307                         up->port.icount.rng++;
 308                 if (status & UART_MSR_DDSR)
 309                         up->port.icount.dsr++;
 310                 if (status & UART_MSR_DDCD)
 311                         uart_handle_dcd_change
 312                                 (&up->port, status & UART_MSR_DCD);
 313                 if (status & UART_MSR_DCTS)
 314                         uart_handle_cts_change
 315                                 (&up->port, status & UART_MSR_CTS);
 316                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 317         }
 318
 319         return status;
 320 }
 321
 322 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 323 {
 324         unsigned int flag;
 325
 326         up->port.icount.rx++;
 327         flag = TTY_NORMAL;
 328
 329         if (lsr & UART_LSR_BI) {
 330                 flag = TTY_BREAK;
 331                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 332                 up->port.icount.brk++;
 333                 /*
 334                  * We do the SysRQ and SAK checking
 335                  * here because otherwise the break
 336                  * may get masked by ignore_status_mask
 337                  * or read_status_mask.
 338                  */
 339                 if (uart_handle_break(&up->port))
 340                         return;
 341
 342         }
 343
 344         if (lsr & UART_LSR_PE) {
 345                 flag = TTY_PARITY;
 346                 up->port.icount.parity++;
 347         }
 348
 349         if (lsr & UART_LSR_FE) {
 350                 flag = TTY_FRAME;
 351                 up->port.icount.frame++;
 352         }
 353
 354         if (lsr & UART_LSR_OE)
 355                 up->port.icount.overrun++;
 356
 357 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 358         if (up->port.line == up->port.cons->index) {
 359                 /* Recover the break flag from console xmit */
 360                 lsr |= up->lsr_break_flag;
 361         }
 362 #endif
 363         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 364 }
 365
 366 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 367 {
 368         unsigned char ch = 0;
 369         unsigned int flag;
 370
 371         if (!(lsr & UART_LSR_DR))
 372                 return;
 373
 374         ch = serial_in(up, UART_RX);
 375         flag = TTY_NORMAL;
 376         up->port.icount.rx++;
 377
 378         if (uart_handle_sysrq_char(&up->port, ch))
 379                 return;
 380
 381         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 382 }
 383
 384 /**
 385  * serial_omap_irq() - This handles the interrupt from one port
 386  * @irq: uart port irq number
 387  * @dev_id: uart port info
 388  */
 389 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 390 {
 391         struct uart_omap_port *up = dev_id;
 392         struct tty_struct *tty = up->port.state->port.tty;
 393         unsigned int iir, lsr;
 394         unsigned int type;
 395         irqreturn_t ret = IRQ_NONE;
 396         int max_count = 256;
 397
 398         spin_lock(&up->port.lock);
 399         pm_runtime_get_sync(up->dev);
 400
 401         do {
 402                 iir = serial_in(up, UART_IIR);
 403                 if (iir & UART_IIR_NO_INT)
 404                         break;
 405
 406                 ret = IRQ_HANDLED;
 407                 lsr = serial_in(up, UART_LSR);
 408
 409                 /* extract IRQ type from IIR register */
 410                 type = iir & 0x3e;
 411
 412                 switch (type) {
 413                 case UART_IIR_MSI:
 414                         check_modem_status(up);
 415                         break;
 416                 case UART_IIR_THRI:
 417                         transmit_chars(up, lsr);
 418                         break;
 419                 case UART_IIR_RX_TIMEOUT:
 420                         /* FALLTHROUGH */
 421                 case UART_IIR_RDI:
 422                         serial_omap_rdi(up, lsr);
 423                         break;
 424                 case UART_IIR_RLSI:
 425                         serial_omap_rlsi(up, lsr);
 426                         break;
 427                 case UART_IIR_CTS_RTS_DSR:
 428                         /* simply try again */
 429                         break;
 430                 case UART_IIR_XOFF:
 431                         /* FALLTHROUGH */
 432                 default:
 433                         break;
 434                 }
 435         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 436
 437         spin_unlock(&up->port.lock);
 438
 439         tty_flip_buffer_push(tty);
 440
 441         pm_runtime_mark_last_busy(up->dev);
 442         pm_runtime_put_autosuspend(up->dev);
 443         up->port_activity = jiffies;
 444
 445         return ret;
 446 }
 447
 448 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 449 {
 450         struct uart_omap_port *up = to_uart_omap_port(port);
 451         unsigned long flags = 0;
 452         unsigned int ret = 0;
 453
 454         pm_runtime_get_sync(up->dev);
 455         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 456         spin_lock_irqsave(&up->port.lock, flags);
 457         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 458         spin_unlock_irqrestore(&up->port.lock, flags);
 459         pm_runtime_mark_last_busy(up->dev);
 460         pm_runtime_put_autosuspend(up->dev);
 461         return ret;
 462 }
 463
 464 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 465 {
 466         struct uart_omap_port *up = to_uart_omap_port(port);
 467         unsigned int status;
 468         unsigned int ret = 0;
 469
 470         pm_runtime_get_sync(up->dev);
 471         status = check_modem_status(up);
 472         pm_runtime_mark_last_busy(up->dev);
 473         pm_runtime_put_autosuspend(up->dev);
 474
 475         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 476
 477         if (status & UART_MSR_DCD)
 478                 ret |= TIOCM_CAR;
 479         if (status & UART_MSR_RI)
 480                 ret |= TIOCM_RNG;
 481         if (status & UART_MSR_DSR)
 482                 ret |= TIOCM_DSR;
 483         if (status & UART_MSR_CTS)
 484                 ret |= TIOCM_CTS;
 485         return ret;
 486 }
 487
 488 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 489 {
 490         struct uart_omap_port *up = to_uart_omap_port(port);
 491         unsigned char mcr = 0;
 492
 493         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 494         if (mctrl & TIOCM_RTS)
 495                 mcr |= UART_MCR_RTS;
 496         if (mctrl & TIOCM_DTR)
 497                 mcr |= UART_MCR_DTR;
 498         if (mctrl & TIOCM_OUT1)
 499                 mcr |= UART_MCR_OUT1;
 500         if (mctrl & TIOCM_OUT2)
 501                 mcr |= UART_MCR_OUT2;
 502         if (mctrl & TIOCM_LOOP)
 503                 mcr |= UART_MCR_LOOP;
 504
 505         pm_runtime_get_sync(up->dev);
 506         up->mcr = serial_in(up, UART_MCR);
 507         up->mcr |= mcr;
 508         serial_out(up, UART_MCR, up->mcr);
 509         pm_runtime_mark_last_busy(up->dev);
 510         pm_runtime_put_autosuspend(up->dev);
 511
 512         if (gpio_is_valid(up->DTR_gpio) &&
 513             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 514                 up->DTR_active = !up->DTR_active;
 515                 if (gpio_cansleep(up->DTR_gpio))
 516                         schedule_work(&up->qos_work);
 517                 else
 518                         gpio_set_value(up->DTR_gpio,
 519                                        up->DTR_active != up->DTR_inverted);
 520         }
 521 }
 522
 523 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 524 {
 525         struct uart_omap_port *up = to_uart_omap_port(port);
 526         unsigned long flags = 0;
 527
 528         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 529         pm_runtime_get_sync(up->dev);
 530         spin_lock_irqsave(&up->port.lock, flags);
 531         if (break_state == -1)
 532                 up->lcr |= UART_LCR_SBC;
 533         else
 534                 up->lcr &= ~UART_LCR_SBC;
 535         serial_out(up, UART_LCR, up->lcr);
 536         spin_unlock_irqrestore(&up->port.lock, flags);
 537         pm_runtime_mark_last_busy(up->dev);
 538         pm_runtime_put_autosuspend(up->dev);
 539 }
 540
 541 static int serial_omap_startup(struct uart_port *port)
 542 {
 543         struct uart_omap_port *up = to_uart_omap_port(port);
 544         unsigned long flags = 0;
 545         int retval;
 546
 547         /*
 548          * Allocate the IRQ
 549          */
 550         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 551                                 up->name, up);
 552         if (retval)
 553                 return retval;
 554
 555         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 556
 557         pm_runtime_get_sync(up->dev);
 558         /*
 559          * Clear the FIFO buffers and disable them.
 560          * (they will be reenabled in set_termios())
 561          */
 562         serial_omap_clear_fifos(up);
 563         /* For Hardware flow control */
 564         serial_out(up, UART_MCR, UART_MCR_RTS);
 565
 566         /*
 567          * Clear the interrupt registers.
 568          */
 569         (void) serial_in(up, UART_LSR);
 570         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 571                 (void) serial_in(up, UART_RX);
 572         (void) serial_in(up, UART_IIR);
 573         (void) serial_in(up, UART_MSR);
 574
 575         /*
 576          * Now, initialize the UART
 577          */
 578         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 579         spin_lock_irqsave(&up->port.lock, flags);
 580         /*
 581          * Most PC uarts need OUT2 raised to enable interrupts.
 582          */
 583         up->port.mctrl |= TIOCM_OUT2;
 584         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 585         spin_unlock_irqrestore(&up->port.lock, flags);
 586
 587         up->msr_saved_flags = 0;
 588         /*
 589          * Finally, enable interrupts. Note: Modem status interrupts
 590          * are set via set_termios(), which will be occurring imminently
 591          * anyway, so we don't enable them here.
 592          */
 593         up->ier = UART_IER_RLSI | UART_IER_RDI;
 594         serial_out(up, UART_IER, up->ier);
 595
 596         /* Enable module level wake up */
 597         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 598
 599         pm_runtime_mark_last_busy(up->dev);
 600         pm_runtime_put_autosuspend(up->dev);
 601         up->port_activity = jiffies;
 602         return 0;
 603 }
 604
 605 static void serial_omap_shutdown(struct uart_port *port)
 606 {
 607         struct uart_omap_port *up = to_uart_omap_port(port);
 608         unsigned long flags = 0;
 609
 610         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 611
 612         pm_runtime_get_sync(up->dev);
 613         /*
 614          * Disable interrupts from this port
 615          */
 616         up->ier = 0;
 617         serial_out(up, UART_IER, 0);
 618
 619         spin_lock_irqsave(&up->port.lock, flags);
 620         up->port.mctrl &= ~TIOCM_OUT2;
 621         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 622         spin_unlock_irqrestore(&up->port.lock, flags);
 623
 624         /*
 625          * Disable break condition and FIFOs
 626          */
 627         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 628         serial_omap_clear_fifos(up);
 629
 630         /*
 631          * Read data port to reset things, and then free the irq
 632          */
 633         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 634                 (void) serial_in(up, UART_RX);
 635
 636         pm_runtime_mark_last_busy(up->dev);
 637         pm_runtime_put_autosuspend(up->dev);
 638         free_irq(up->port.irq, up);
 639 }
 640
 641 static inline void
 642 serial_omap_configure_xonxoff
 643                 (struct uart_omap_port *up, struct ktermios *termios)
 644 {
 645         up->lcr = serial_in(up, UART_LCR);
 646         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 647         up->efr = serial_in(up, UART_EFR);
 648         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 649
 650         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 651         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 652
 653         /* clear SW control mode bits */
 654         up->efr &= OMAP_UART_SW_CLR;
 655
 656         /*
 657          * IXON Flag:
 658          * Flow control for OMAP.TX
 659          * OMAP.RX should listen for XON/XOFF
 660          */
 661         if (termios->c_iflag & IXON)
 662                 up->efr |= OMAP_UART_SW_RX;
 663
 664         /*
 665          * IXOFF Flag:
 666          * Flow control for OMAP.RX
 667          * OMAP.TX should send XON/XOFF
 668          */
 669         if (termios->c_iflag & IXOFF)
 670                 up->efr |= OMAP_UART_SW_TX;
 671
 672         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 673         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 674
 675         up->mcr = serial_in(up, UART_MCR);
 676
 677         /*
 678          * IXANY Flag:
 679          * Enable any character to restart output.
 680          * Operation resumes after receiving any
 681          * character after recognition of the XOFF character
 682          */
 683         if (termios->c_iflag & IXANY)
 684                 up->mcr |= UART_MCR_XONANY;
 685
 686         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 687         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 688         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 689         /* Enable special char function UARTi.EFR_REG[5] and
 690          * load the new software flow control mode IXON or IXOFF
 691          * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
 692          */
 693         serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
 694         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 695
 696         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 697         serial_out(up, UART_LCR, up->lcr);
 698 }
 699
 700 static void serial_omap_uart_qos_work(struct work_struct *work)
 701 {
 702         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 703                                                 qos_work);
 704
 705         pm_qos_update_request(&up->pm_qos_request, up->latency);
 706         if (gpio_is_valid(up->DTR_gpio))
 707                 gpio_set_value_cansleep(up->DTR_gpio,
 708                                         up->DTR_active != up->DTR_inverted);
 709 }
 710
 711 static void
 712 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 713                         struct ktermios *old)
 714 {
 715         struct uart_omap_port *up = to_uart_omap_port(port);
 716         unsigned char cval = 0;
 717         unsigned char efr = 0;
 718         unsigned long flags = 0;
 719         unsigned int baud, quot;
 720
 721         switch (termios->c_cflag & CSIZE) {
 722         case CS5:
 723                 cval = UART_LCR_WLEN5;
 724                 break;
 725         case CS6:
 726                 cval = UART_LCR_WLEN6;
 727                 break;
 728         case CS7:
 729                 cval = UART_LCR_WLEN7;
 730                 break;
 731         default:
 732         case CS8:
 733                 cval = UART_LCR_WLEN8;
 734                 break;
 735         }
 736
 737         if (termios->c_cflag & CSTOPB)
 738                 cval |= UART_LCR_STOP;
 739         if (termios->c_cflag & PARENB)
 740                 cval |= UART_LCR_PARITY;
 741         if (!(termios->c_cflag & PARODD))
 742                 cval |= UART_LCR_EPAR;
 743
 744         /*
 745          * Ask the core to calculate the divisor for us.
 746          */
 747
 748         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 749         quot = serial_omap_get_divisor(port, baud);
 750
 751         /* calculate wakeup latency constraint */
 752         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 753         up->latency = up->calc_latency;
 754         schedule_work(&up->qos_work);
 755
 756         up->dll = quot & 0xff;
 757         up->dlh = quot >> 8;
 758         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 759
 760         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 761                         UART_FCR_ENABLE_FIFO;
 762
 763         /*
 764          * Ok, we're now changing the port state. Do it with
 765          * interrupts disabled.
 766          */
 767         pm_runtime_get_sync(up->dev);
 768         spin_lock_irqsave(&up->port.lock, flags);
 769
 770         /*
 771          * Update the per-port timeout.
 772          */
 773         uart_update_timeout(port, termios->c_cflag, baud);
 774
 775         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 776         if (termios->c_iflag & INPCK)
 777                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 778         if (termios->c_iflag & (BRKINT | PARMRK))
 779                 up->port.read_status_mask |= UART_LSR_BI;
 780
 781         /*
 782          * Characters to ignore
 783          */
 784         up->port.ignore_status_mask = 0;
 785         if (termios->c_iflag & IGNPAR)
 786                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 787         if (termios->c_iflag & IGNBRK) {
 788                 up->port.ignore_status_mask |= UART_LSR_BI;
 789                 /*
 790                  * If we're ignoring parity and break indicators,
 791                  * ignore overruns too (for real raw support).
 792                  */
 793                 if (termios->c_iflag & IGNPAR)
 794                         up->port.ignore_status_mask |= UART_LSR_OE;
 795         }
 796
 797         /*
 798          * ignore all characters if CREAD is not set
 799          */
 800         if ((termios->c_cflag & CREAD) == 0)
 801                 up->port.ignore_status_mask |= UART_LSR_DR;
 802
 803         /*
 804          * Modem status interrupts
 805          */
 806         up->ier &= ~UART_IER_MSI;
 807         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 808                 up->ier |= UART_IER_MSI;
 809         serial_out(up, UART_IER, up->ier);
 810         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 811         up->lcr = cval;
 812         up->scr = OMAP_UART_SCR_TX_EMPTY;
 813
 814         /* FIFOs and DMA Settings */
 815
 816         /* FCR can be changed only when the
 817          * baud clock is not running
 818          * DLL_REG and DLH_REG set to 0.
 819          */
 820         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 821         serial_out(up, UART_DLL, 0);
 822         serial_out(up, UART_DLM, 0);
 823         serial_out(up, UART_LCR, 0);
 824
 825         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 826
 827         up->efr = serial_in(up, UART_EFR);
 828         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 829
 830         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 831         up->mcr = serial_in(up, UART_MCR);
 832         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 833         /* FIFO ENABLE, DMA MODE */
 834
 835         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 836
 837         /* Set receive FIFO threshold to 16 characters and
 838          * transmit FIFO threshold to 16 spaces
 839          */
 840         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 841         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 842         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 843                 UART_FCR_ENABLE_FIFO;
 844
 845         serial_out(up, UART_FCR, up->fcr);
 846         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 847
 848         serial_out(up, UART_OMAP_SCR, up->scr);
 849
 850         serial_out(up, UART_EFR, up->efr);
 851         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 852         serial_out(up, UART_MCR, up->mcr);
 853
 854         /* Protocol, Baud Rate, and Interrupt Settings */
 855
 856         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 857                 serial_omap_mdr1_errataset(up, up->mdr1);
 858         else
 859                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 860
 861         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 862
 863         up->efr = serial_in(up, UART_EFR);
 864         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 865
 866         serial_out(up, UART_LCR, 0);
 867         serial_out(up, UART_IER, 0);
 868         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 869
 870         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 871         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 872
 873         serial_out(up, UART_LCR, 0);
 874         serial_out(up, UART_IER, up->ier);
 875         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 876
 877         serial_out(up, UART_EFR, up->efr);
 878         serial_out(up, UART_LCR, cval);
 879
 880         if (baud > 230400 && baud != 3000000)
 881                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 882         else
 883                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 884
 885         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 886                 serial_omap_mdr1_errataset(up, up->mdr1);
 887         else
 888                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 889
 890         /* Hardware Flow Control Configuration */
 891
 892         if (termios->c_cflag & CRTSCTS) {
 893                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
 894                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 895
 896                 up->mcr = serial_in(up, UART_MCR);
 897                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 898
 899                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 900                 up->efr = serial_in(up, UART_EFR);
 901                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 902
 903                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 904                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
 905                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 906                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 907                 serial_out(up, UART_LCR, cval);
 908         }
 909
 910         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 911         /* Software Flow Control Configuration */
 912         serial_omap_configure_xonxoff(up, termios);
 913
 914         spin_unlock_irqrestore(&up->port.lock, flags);
 915         pm_runtime_mark_last_busy(up->dev);
 916         pm_runtime_put_autosuspend(up->dev);
 917         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 918 }
 919
 920 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 921 {
 922         struct uart_omap_port *up = to_uart_omap_port(port);
 923
 924         serial_omap_enable_wakeup(up, state);
 925
 926         return 0;
 927 }
 928
 929 static void
 930 serial_omap_pm(struct uart_port *port, unsigned int state,
 931                unsigned int oldstate)
 932 {
 933         struct uart_omap_port *up = to_uart_omap_port(port);
 934         unsigned char efr;
 935
 936         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 937
 938         pm_runtime_get_sync(up->dev);
 939         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 940         efr = serial_in(up, UART_EFR);
 941         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 942         serial_out(up, UART_LCR, 0);
 943
 944         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 945         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 946         serial_out(up, UART_EFR, efr);
 947         serial_out(up, UART_LCR, 0);
 948
 949         if (!device_may_wakeup(up->dev)) {
 950                 if (!state)
 951                         pm_runtime_forbid(up->dev);
 952                 else
 953                         pm_runtime_allow(up->dev);
 954         }
 955
 956         pm_runtime_mark_last_busy(up->dev);
 957         pm_runtime_put_autosuspend(up->dev);
 958 }
 959
 960 static void serial_omap_release_port(struct uart_port *port)
 961 {
 962         dev_dbg(port->dev, "serial_omap_release_port+\n");
 963 }
 964
 965 static int serial_omap_request_port(struct uart_port *port)
 966 {
 967         dev_dbg(port->dev, "serial_omap_request_port+\n");
 968         return 0;
 969 }
 970
 971 static void serial_omap_config_port(struct uart_port *port, int flags)
 972 {
 973         struct uart_omap_port *up = to_uart_omap_port(port);
 974
 975         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 976                                                         up->port.line);
 977         up->port.type = PORT_OMAP;
 978 }
 979
 980 static int
 981 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 982 {
 983         /* we don't want the core code to modify any port params */
 984         dev_dbg(port->dev, "serial_omap_verify_port+\n");
 985         return -EINVAL;
 986 }
 987
 988 static const char *
 989 serial_omap_type(struct uart_port *port)
 990 {
 991         struct uart_omap_port *up = to_uart_omap_port(port);
 992
 993         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 994         return up->name;
 995 }
 996
 997 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 998
 999 static inline void wait_for_xmitr(struct uart_omap_port *up)
1000 {
1001         unsigned int status, tmout = 10000;
1002
1003         /* Wait up to 10ms for the character(s) to be sent. */
1004         do {
1005                 status = serial_in(up, UART_LSR);
1006
1007                 if (status & UART_LSR_BI)
1008                         up->lsr_break_flag = UART_LSR_BI;
1009
1010                 if (--tmout == 0)
1011                         break;
1012                 udelay(1);
1013         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1014
1015         /* Wait up to 1s for flow control if necessary */
1016         if (up->port.flags & UPF_CONS_FLOW) {
1017                 tmout = 1000000;
1018                 for (tmout = 1000000; tmout; tmout--) {
1019                         unsigned int msr = serial_in(up, UART_MSR);
1020
1021                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1022                         if (msr & UART_MSR_CTS)
1023                                 break;
1024
1025                         udelay(1);
1026                 }
1027         }
1028 }
1029
1030 #ifdef CONFIG_CONSOLE_POLL
1031
1032 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1033 {
1034         struct uart_omap_port *up = to_uart_omap_port(port);
1035
1036         pm_runtime_get_sync(up->dev);
1037         wait_for_xmitr(up);
1038         serial_out(up, UART_TX, ch);
1039         pm_runtime_mark_last_busy(up->dev);
1040         pm_runtime_put_autosuspend(up->dev);
1041 }
1042
1043 static int serial_omap_poll_get_char(struct uart_port *port)
1044 {
1045         struct uart_omap_port *up = to_uart_omap_port(port);
1046         unsigned int status;
1047
1048         pm_runtime_get_sync(up->dev);
1049         status = serial_in(up, UART_LSR);
1050         if (!(status & UART_LSR_DR)) {
1051                 status = NO_POLL_CHAR;
1052                 goto out;
1053         }
1054
1055         status = serial_in(up, UART_RX);
1056
1057 out:
1058         pm_runtime_mark_last_busy(up->dev);
1059         pm_runtime_put_autosuspend(up->dev);
1060
1061         return status;
1062 }
1063
1064 #endif /* CONFIG_CONSOLE_POLL */
1065
1066 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1067
1068 static struct uart_omap_port *serial_omap_console_ports[4];
1069
1070 static struct uart_driver serial_omap_reg;
1071
1072 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1073 {
1074         struct uart_omap_port *up = to_uart_omap_port(port);
1075
1076         wait_for_xmitr(up);
1077         serial_out(up, UART_TX, ch);
1078 }
1079
1080 static void
1081 serial_omap_console_write(struct console *co, const char *s,
1082                 unsigned int count)
1083 {
1084         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1085         unsigned long flags;
1086         unsigned int ier;
1087         int locked = 1;
1088
1089         pm_runtime_get_sync(up->dev);
1090
1091         local_irq_save(flags);
1092         if (up->port.sysrq)
1093                 locked = 0;
1094         else if (oops_in_progress)
1095                 locked = spin_trylock(&up->port.lock);
1096         else
1097                 spin_lock(&up->port.lock);
1098
1099         /*
1100          * First save the IER then disable the interrupts
1101          */
1102         ier = serial_in(up, UART_IER);
1103         serial_out(up, UART_IER, 0);
1104
1105         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1106
1107         /*
1108          * Finally, wait for transmitter to become empty
1109          * and restore the IER
1110          */
1111         wait_for_xmitr(up);
1112         serial_out(up, UART_IER, ier);
1113         /*
1114          * The receive handling will happen properly because the
1115          * receive ready bit will still be set; it is not cleared
1116          * on read.  However, modem control will not, we must
1117          * call it if we have saved something in the saved flags
1118          * while processing with interrupts off.
1119          */
1120         if (up->msr_saved_flags)
1121                 check_modem_status(up);
1122
1123         pm_runtime_mark_last_busy(up->dev);
1124         pm_runtime_put_autosuspend(up->dev);
1125         if (locked)
1126                 spin_unlock(&up->port.lock);
1127         local_irq_restore(flags);
1128 }
1129
1130 static int __init
1131 serial_omap_console_setup(struct console *co, char *options)
1132 {
1133         struct uart_omap_port *up;
1134         int baud = 115200;
1135         int bits = 8;
1136         int parity = 'n';
1137         int flow = 'n';
1138
1139         if (serial_omap_console_ports[co->index] == NULL)
1140                 return -ENODEV;
1141         up = serial_omap_console_ports[co->index];
1142
1143         if (options)
1144                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1145
1146         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1147 }
1148
1149 static struct console serial_omap_console = {
1150         .name           = OMAP_SERIAL_NAME,
1151         .write          = serial_omap_console_write,
1152         .device         = uart_console_device,
1153         .setup          = serial_omap_console_setup,
1154         .flags          = CON_PRINTBUFFER,
1155         .index          = -1,
1156         .data           = &serial_omap_reg,
1157 };
1158
1159 static void serial_omap_add_console_port(struct uart_omap_port *up)
1160 {
1161         serial_omap_console_ports[up->port.line] = up;
1162 }
1163
1164 #define OMAP_CONSOLE    (&serial_omap_console)
1165
1166 #else
1167
1168 #define OMAP_CONSOLE    NULL
1169
1170 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1171 {}
1172
1173 #endif
1174
1175 static struct uart_ops serial_omap_pops = {
1176         .tx_empty       = serial_omap_tx_empty,
1177         .set_mctrl      = serial_omap_set_mctrl,
1178         .get_mctrl      = serial_omap_get_mctrl,
1179         .stop_tx        = serial_omap_stop_tx,
1180         .start_tx       = serial_omap_start_tx,
1181         .stop_rx        = serial_omap_stop_rx,
1182         .enable_ms      = serial_omap_enable_ms,
1183         .break_ctl      = serial_omap_break_ctl,
1184         .startup        = serial_omap_startup,
1185         .shutdown       = serial_omap_shutdown,
1186         .set_termios    = serial_omap_set_termios,
1187         .pm             = serial_omap_pm,
1188         .set_wake       = serial_omap_set_wake,
1189         .type           = serial_omap_type,
1190         .release_port   = serial_omap_release_port,
1191         .request_port   = serial_omap_request_port,
1192         .config_port    = serial_omap_config_port,
1193         .verify_port    = serial_omap_verify_port,
1194 #ifdef CONFIG_CONSOLE_POLL
1195         .poll_put_char  = serial_omap_poll_put_char,
1196         .poll_get_char  = serial_omap_poll_get_char,
1197 #endif
1198 };
1199
1200 static struct uart_driver serial_omap_reg = {
1201         .owner          = THIS_MODULE,
1202         .driver_name    = "OMAP-SERIAL",
1203         .dev_name       = OMAP_SERIAL_NAME,
1204         .nr             = OMAP_MAX_HSUART_PORTS,
1205         .cons           = OMAP_CONSOLE,
1206 };
1207
1208 #ifdef CONFIG_PM_SLEEP
1209 static int serial_omap_suspend(struct device *dev)
1210 {
1211         struct uart_omap_port *up = dev_get_drvdata(dev);
1212
1213         if (up) {
1214                 uart_suspend_port(&serial_omap_reg, &up->port);
1215                 flush_work_sync(&up->qos_work);
1216         }
1217
1218         return 0;
1219 }
1220
1221 static int serial_omap_resume(struct device *dev)
1222 {
1223         struct uart_omap_port *up = dev_get_drvdata(dev);
1224
1225         if (up)
1226                 uart_resume_port(&serial_omap_reg, &up->port);
1227         return 0;
1228 }
1229 #endif
1230
1231 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1232 {
1233         u32 mvr, scheme;
1234         u16 revision, major, minor;
1235
1236         mvr = serial_in(up, UART_OMAP_MVER);
1237
1238         /* Check revision register scheme */
1239         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1240
1241         switch (scheme) {
1242         case 0: /* Legacy Scheme: OMAP2/3 */
1243                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1244                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1245                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1246                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1247                 break;
1248         case 1:
1249                 /* New Scheme: OMAP4+ */
1250                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1251                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1252                                         OMAP_UART_MVR_MAJ_SHIFT;
1253                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1254                 break;
1255         default:
1256                 dev_warn(up->dev,
1257                         "Unknown %s revision, defaulting to highest\n",
1258                         up->name);
1259                 /* highest possible revision */
1260                 major = 0xff;
1261                 minor = 0xff;
1262         }
1263
1264         /* normalize revision for the driver */
1265         revision = UART_BUILD_REVISION(major, minor);
1266
1267         switch (revision) {
1268         case OMAP_UART_REV_46:
1269                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1270                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1271                 break;
1272         case OMAP_UART_REV_52:
1273                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1274                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1275                 break;
1276         case OMAP_UART_REV_63:
1277                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1278                 break;
1279         default:
1280                 break;
1281         }
1282 }
1283
1284 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1285 {
1286         struct omap_uart_port_info *omap_up_info;
1287
1288         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1289         if (!omap_up_info)
1290                 return NULL; /* out of memory */
1291
1292         of_property_read_u32(dev->of_node, "clock-frequency",
1293                                          &omap_up_info->uartclk);
1294         return omap_up_info;
1295 }
1296
1297 static int __devinit serial_omap_probe(struct platform_device *pdev)
1298 {
1299         struct uart_omap_port   *up;
1300         struct resource         *mem, *irq;
1301         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1302         int ret;
1303
1304         if (pdev->dev.of_node)
1305                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1306
1307         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1308         if (!mem) {
1309                 dev_err(&pdev->dev, "no mem resource?\n");
1310                 return -ENODEV;
1311         }
1312
1313         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1314         if (!irq) {
1315                 dev_err(&pdev->dev, "no irq resource?\n");
1316                 return -ENODEV;
1317         }
1318
1319         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1320                                 pdev->dev.driver->name)) {
1321                 dev_err(&pdev->dev, "memory region already claimed\n");
1322                 return -EBUSY;
1323         }
1324
1325         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1326             omap_up_info->DTR_present) {
1327                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1328                 if (ret < 0)
1329                         return ret;
1330                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1331                                             omap_up_info->DTR_inverted);
1332                 if (ret < 0)
1333                         return ret;
1334         }
1335
1336         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1337         if (!up)
1338                 return -ENOMEM;
1339
1340         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1341             omap_up_info->DTR_present) {
1342                 up->DTR_gpio = omap_up_info->DTR_gpio;
1343                 up->DTR_inverted = omap_up_info->DTR_inverted;
1344         } else
1345                 up->DTR_gpio = -EINVAL;
1346         up->DTR_active = 0;
1347
1348         up->dev = &pdev->dev;
1349         up->port.dev = &pdev->dev;
1350         up->port.type = PORT_OMAP;
1351         up->port.iotype = UPIO_MEM;
1352         up->port.irq = irq->start;
1353
1354         up->port.regshift = 2;
1355         up->port.fifosize = 64;
1356         up->port.ops = &serial_omap_pops;
1357
1358         if (pdev->dev.of_node)
1359                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1360         else
1361                 up->port.line = pdev->id;
1362
1363         if (up->port.line < 0) {
1364                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1365                                                                 up->port.line);
1366                 ret = -ENODEV;
1367                 goto err_port_line;
1368         }
1369
1370         sprintf(up->name, "OMAP UART%d", up->port.line);
1371         up->port.mapbase = mem->start;
1372         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1373                                                 resource_size(mem));
1374         if (!up->port.membase) {
1375                 dev_err(&pdev->dev, "can't ioremap UART\n");
1376                 ret = -ENOMEM;
1377                 goto err_ioremap;
1378         }
1379
1380         up->port.flags = omap_up_info->flags;
1381         up->port.uartclk = omap_up_info->uartclk;
1382         if (!up->port.uartclk) {
1383                 up->port.uartclk = DEFAULT_CLK_SPEED;
1384                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1385                                                 "%d\n", DEFAULT_CLK_SPEED);
1386         }
1387
1388         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1389         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1390         pm_qos_add_request(&up->pm_qos_request,
1391                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1392         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1393         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1394
1395         platform_set_drvdata(pdev, up);
1396         pm_runtime_enable(&pdev->dev);
1397         pm_runtime_use_autosuspend(&pdev->dev);
1398         pm_runtime_set_autosuspend_delay(&pdev->dev,
1399                         omap_up_info->autosuspend_timeout);
1400
1401         pm_runtime_irq_safe(&pdev->dev);
1402         pm_runtime_get_sync(&pdev->dev);
1403
1404         omap_serial_fill_features_erratas(up);
1405
1406         ui[up->port.line] = up;
1407         serial_omap_add_console_port(up);
1408
1409         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1410         if (ret != 0)
1411                 goto err_add_port;
1412
1413         pm_runtime_mark_last_busy(up->dev);
1414         pm_runtime_put_autosuspend(up->dev);
1415         return 0;
1416
1417 err_add_port:
1418         pm_runtime_put(&pdev->dev);
1419         pm_runtime_disable(&pdev->dev);
1420 err_ioremap:
1421 err_port_line:
1422         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1423                                 pdev->id, __func__, ret);
1424         return ret;
1425 }
1426
1427 static int __devexit serial_omap_remove(struct platform_device *dev)
1428 {
1429         struct uart_omap_port *up = platform_get_drvdata(dev);
1430
1431         pm_runtime_put_sync(up->dev);
1432         pm_runtime_disable(up->dev);
1433         uart_remove_one_port(&serial_omap_reg, &up->port);
1434         pm_qos_remove_request(&up->pm_qos_request);
1435
1436         return 0;
1437 }
1438
1439 /*
1440  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1441  * The access to uart register after MDR1 Access
1442  * causes UART to corrupt data.
1443  *
1444  * Need a delay =
1445  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1446  * give 10 times as much
1447  */
1448 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1449 {
1450         u8 timeout = 255;
1451
1452         serial_out(up, UART_OMAP_MDR1, mdr1);
1453         udelay(2);
1454         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1455                         UART_FCR_CLEAR_RCVR);
1456         /*
1457          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1458          * TX_FIFO_E bit is 1.
1459          */
1460         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1461                                 (UART_LSR_THRE | UART_LSR_DR))) {
1462                 timeout--;
1463                 if (!timeout) {
1464                         /* Should *never* happen. we warn and carry on */
1465                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1466                                                 serial_in(up, UART_LSR));
1467                         break;
1468                 }
1469                 udelay(1);
1470         }
1471 }
1472
1473 #ifdef CONFIG_PM_RUNTIME
1474 static void serial_omap_restore_context(struct uart_omap_port *up)
1475 {
1476         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1477                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1478         else
1479                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1480
1481         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1482         serial_out(up, UART_EFR, UART_EFR_ECB);
1483         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1484         serial_out(up, UART_IER, 0x0);
1485         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1486         serial_out(up, UART_DLL, up->dll);
1487         serial_out(up, UART_DLM, up->dlh);
1488         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1489         serial_out(up, UART_IER, up->ier);
1490         serial_out(up, UART_FCR, up->fcr);
1491         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1492         serial_out(up, UART_MCR, up->mcr);
1493         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1494         serial_out(up, UART_OMAP_SCR, up->scr);
1495         serial_out(up, UART_EFR, up->efr);
1496         serial_out(up, UART_LCR, up->lcr);
1497         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1498                 serial_omap_mdr1_errataset(up, up->mdr1);
1499         else
1500                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1501 }
1502
1503 static int serial_omap_runtime_suspend(struct device *dev)
1504 {
1505         struct uart_omap_port *up = dev_get_drvdata(dev);
1506         struct omap_uart_port_info *pdata = dev->platform_data;
1507
1508         if (!up)
1509                 return -EINVAL;
1510
1511         if (!pdata)
1512                 return 0;
1513
1514         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1515
1516         if (device_may_wakeup(dev)) {
1517                 if (!up->wakeups_enabled) {
1518                         serial_omap_enable_wakeup(up, true);
1519                         up->wakeups_enabled = true;
1520                 }
1521         } else {
1522                 if (up->wakeups_enabled) {
1523                         serial_omap_enable_wakeup(up, false);
1524                         up->wakeups_enabled = false;
1525                 }
1526         }
1527
1528         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1529         schedule_work(&up->qos_work);
1530
1531         return 0;
1532 }
1533
1534 static int serial_omap_runtime_resume(struct device *dev)
1535 {
1536         struct uart_omap_port *up = dev_get_drvdata(dev);
1537         struct omap_uart_port_info *pdata = dev->platform_data;
1538
1539         if (up && pdata) {
1540                         u32 loss_cnt = serial_omap_get_context_loss_count(up);
1541
1542                         if (up->context_loss_cnt != loss_cnt)
1543                                 serial_omap_restore_context(up);
1544
1545                 up->latency = up->calc_latency;
1546                 schedule_work(&up->qos_work);
1547         }
1548
1549         return 0;
1550 }
1551 #endif
1552
1553 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1554         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1555         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1556                                 serial_omap_runtime_resume, NULL)
1557 };
1558
1559 #if defined(CONFIG_OF)
1560 static const struct of_device_id omap_serial_of_match[] = {
1561         { .compatible = "ti,omap2-uart" },
1562         { .compatible = "ti,omap3-uart" },
1563         { .compatible = "ti,omap4-uart" },
1564         {},
1565 };
1566 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1567 #endif
1568
1569 static struct platform_driver serial_omap_driver = {
1570         .probe          = serial_omap_probe,
1571         .remove         = __devexit_p(serial_omap_remove),
1572         .driver         = {
1573                 .name   = DRIVER_NAME,
1574                 .pm     = &serial_omap_dev_pm_ops,
1575                 .of_match_table = of_match_ptr(omap_serial_of_match),
1576         },
1577 };
1578
1579 static int __init serial_omap_init(void)
1580 {
1581         int ret;
1582
1583         ret = uart_register_driver(&serial_omap_reg);
1584         if (ret != 0)
1585                 return ret;
1586         ret = platform_driver_register(&serial_omap_driver);
1587         if (ret != 0)
1588                 uart_unregister_driver(&serial_omap_reg);
1589         return ret;
1590 }
1591
1592 static void __exit serial_omap_exit(void)
1593 {
1594         platform_driver_unregister(&serial_omap_driver);
1595         uart_unregister_driver(&serial_omap_reg);
1596 }
1597
1598 module_init(serial_omap_init);
1599 module_exit(serial_omap_exit);
1600
1601 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1602 MODULE_LICENSE("GPL");
1603 MODULE_AUTHOR("Texas Instruments Inc");