2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/clk.h>
37 #include <linux/serial_core.h>
38 #include <linux/irq.h>
39 #include <linux/pm_runtime.h>
41 #include <linux/gpio.h>
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
46 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
48 #define OMAP_UART_REV_42 0x0402
49 #define OMAP_UART_REV_46 0x0406
50 #define OMAP_UART_REV_52 0x0502
51 #define OMAP_UART_REV_63 0x0603
53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
55 /* SCR register bitmasks */
56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
58 /* FCR register bitmasks */
59 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
62 /* MVR register bitmasks */
63 #define OMAP_UART_MVR_SCHEME_SHIFT 30
65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
67 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
69 #define OMAP_UART_MVR_MAJ_MASK 0x700
70 #define OMAP_UART_MVR_MAJ_SHIFT 8
71 #define OMAP_UART_MVR_MIN_MASK 0x3f
73 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
75 /* Forward declaration of functions */
76 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
78 static struct workqueue_struct *serial_omap_uart_wq;
80 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
82 offset <<= up->port.regshift;
83 return readw(up->port.membase + offset);
86 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
88 offset <<= up->port.regshift;
89 writew(value, up->port.membase + offset);
92 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
94 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
95 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
96 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
97 serial_out(up, UART_FCR, 0);
100 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
102 struct omap_uart_port_info *pdata = up->dev->platform_data;
104 if (!pdata->get_context_loss_count)
107 return pdata->get_context_loss_count(up->dev);
110 static void serial_omap_set_forceidle(struct uart_omap_port *up)
112 struct omap_uart_port_info *pdata = up->dev->platform_data;
114 if (pdata->set_forceidle)
115 pdata->set_forceidle(up->dev);
118 static void serial_omap_set_noidle(struct uart_omap_port *up)
120 struct omap_uart_port_info *pdata = up->dev->platform_data;
122 if (pdata->set_noidle)
123 pdata->set_noidle(up->dev);
126 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
128 struct omap_uart_port_info *pdata = up->dev->platform_data;
130 if (pdata->enable_wakeup)
131 pdata->enable_wakeup(up->dev, enable);
135 * serial_omap_get_divisor - calculate divisor value
136 * @port: uart port info
137 * @baud: baudrate for which divisor needs to be calculated.
139 * We have written our own function to get the divisor so as to support
140 * 13x mode. 3Mbps Baudrate as an different divisor.
141 * Reference OMAP TRM Chapter 17:
142 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
143 * referring to oversampling - divisor value
144 * baudrate 460,800 to 3,686,400 all have divisor 13
145 * except 3,000,000 which has divisor value 16
148 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
150 unsigned int divisor;
152 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
156 return port->uartclk/(baud * divisor);
159 static void serial_omap_enable_ms(struct uart_port *port)
161 struct uart_omap_port *up = to_uart_omap_port(port);
163 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
165 pm_runtime_get_sync(up->dev);
166 up->ier |= UART_IER_MSI;
167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_mark_last_busy(up->dev);
169 pm_runtime_put_autosuspend(up->dev);
172 static void serial_omap_stop_tx(struct uart_port *port)
174 struct uart_omap_port *up = to_uart_omap_port(port);
176 pm_runtime_get_sync(up->dev);
177 if (up->ier & UART_IER_THRI) {
178 up->ier &= ~UART_IER_THRI;
179 serial_out(up, UART_IER, up->ier);
182 serial_omap_set_forceidle(up);
184 pm_runtime_mark_last_busy(up->dev);
185 pm_runtime_put_autosuspend(up->dev);
188 static void serial_omap_stop_rx(struct uart_port *port)
190 struct uart_omap_port *up = to_uart_omap_port(port);
192 pm_runtime_get_sync(up->dev);
193 up->ier &= ~UART_IER_RLSI;
194 up->port.read_status_mask &= ~UART_LSR_DR;
195 serial_out(up, UART_IER, up->ier);
196 pm_runtime_mark_last_busy(up->dev);
197 pm_runtime_put_autosuspend(up->dev);
200 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
202 struct circ_buf *xmit = &up->port.state->xmit;
205 if (!(lsr & UART_LSR_THRE))
208 if (up->port.x_char) {
209 serial_out(up, UART_TX, up->port.x_char);
210 up->port.icount.tx++;
214 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
215 serial_omap_stop_tx(&up->port);
218 count = up->port.fifosize / 4;
220 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
221 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
222 up->port.icount.tx++;
223 if (uart_circ_empty(xmit))
225 } while (--count > 0);
227 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
228 uart_write_wakeup(&up->port);
230 if (uart_circ_empty(xmit))
231 serial_omap_stop_tx(&up->port);
234 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
236 if (!(up->ier & UART_IER_THRI)) {
237 up->ier |= UART_IER_THRI;
238 serial_out(up, UART_IER, up->ier);
242 static void serial_omap_start_tx(struct uart_port *port)
244 struct uart_omap_port *up = to_uart_omap_port(port);
246 pm_runtime_get_sync(up->dev);
247 serial_omap_enable_ier_thri(up);
248 serial_omap_set_noidle(up);
249 pm_runtime_mark_last_busy(up->dev);
250 pm_runtime_put_autosuspend(up->dev);
253 static unsigned int check_modem_status(struct uart_omap_port *up)
257 status = serial_in(up, UART_MSR);
258 status |= up->msr_saved_flags;
259 up->msr_saved_flags = 0;
260 if ((status & UART_MSR_ANY_DELTA) == 0)
263 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
264 up->port.state != NULL) {
265 if (status & UART_MSR_TERI)
266 up->port.icount.rng++;
267 if (status & UART_MSR_DDSR)
268 up->port.icount.dsr++;
269 if (status & UART_MSR_DDCD)
270 uart_handle_dcd_change
271 (&up->port, status & UART_MSR_DCD);
272 if (status & UART_MSR_DCTS)
273 uart_handle_cts_change
274 (&up->port, status & UART_MSR_CTS);
275 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
281 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
285 up->port.icount.rx++;
288 if (lsr & UART_LSR_BI) {
290 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
291 up->port.icount.brk++;
293 * We do the SysRQ and SAK checking
294 * here because otherwise the break
295 * may get masked by ignore_status_mask
296 * or read_status_mask.
298 if (uart_handle_break(&up->port))
303 if (lsr & UART_LSR_PE) {
305 up->port.icount.parity++;
308 if (lsr & UART_LSR_FE) {
310 up->port.icount.frame++;
313 if (lsr & UART_LSR_OE)
314 up->port.icount.overrun++;
316 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
317 if (up->port.line == up->port.cons->index) {
318 /* Recover the break flag from console xmit */
319 lsr |= up->lsr_break_flag;
322 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
325 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
327 unsigned char ch = 0;
330 if (!(lsr & UART_LSR_DR))
333 ch = serial_in(up, UART_RX);
335 up->port.icount.rx++;
337 if (uart_handle_sysrq_char(&up->port, ch))
340 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
344 * serial_omap_irq() - This handles the interrupt from one port
345 * @irq: uart port irq number
346 * @dev_id: uart port info
348 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
350 struct uart_omap_port *up = dev_id;
351 struct tty_struct *tty = up->port.state->port.tty;
352 unsigned int iir, lsr;
355 irqreturn_t ret = IRQ_NONE;
358 spin_lock_irqsave(&up->port.lock, flags);
359 pm_runtime_get_sync(up->dev);
362 iir = serial_in(up, UART_IIR);
363 if (iir & UART_IIR_NO_INT)
367 lsr = serial_in(up, UART_LSR);
369 /* extract IRQ type from IIR register */
374 check_modem_status(up);
377 transmit_chars(up, lsr);
379 case UART_IIR_RX_TIMEOUT:
382 serial_omap_rdi(up, lsr);
385 serial_omap_rlsi(up, lsr);
387 case UART_IIR_CTS_RTS_DSR:
388 /* simply try again */
395 } while (!(iir & UART_IIR_NO_INT) && max_count--);
397 spin_unlock_irqrestore(&up->port.lock, flags);
399 tty_flip_buffer_push(tty);
401 pm_runtime_mark_last_busy(up->dev);
402 pm_runtime_put_autosuspend(up->dev);
403 up->port_activity = jiffies;
408 static unsigned int serial_omap_tx_empty(struct uart_port *port)
410 struct uart_omap_port *up = to_uart_omap_port(port);
411 unsigned long flags = 0;
412 unsigned int ret = 0;
414 pm_runtime_get_sync(up->dev);
415 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
416 spin_lock_irqsave(&up->port.lock, flags);
417 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
418 spin_unlock_irqrestore(&up->port.lock, flags);
419 pm_runtime_mark_last_busy(up->dev);
420 pm_runtime_put_autosuspend(up->dev);
424 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
426 struct uart_omap_port *up = to_uart_omap_port(port);
428 unsigned int ret = 0;
430 pm_runtime_get_sync(up->dev);
431 status = check_modem_status(up);
432 pm_runtime_mark_last_busy(up->dev);
433 pm_runtime_put_autosuspend(up->dev);
435 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
437 if (status & UART_MSR_DCD)
439 if (status & UART_MSR_RI)
441 if (status & UART_MSR_DSR)
443 if (status & UART_MSR_CTS)
448 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
450 struct uart_omap_port *up = to_uart_omap_port(port);
451 unsigned char mcr = 0;
453 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
454 if (mctrl & TIOCM_RTS)
456 if (mctrl & TIOCM_DTR)
458 if (mctrl & TIOCM_OUT1)
459 mcr |= UART_MCR_OUT1;
460 if (mctrl & TIOCM_OUT2)
461 mcr |= UART_MCR_OUT2;
462 if (mctrl & TIOCM_LOOP)
463 mcr |= UART_MCR_LOOP;
465 pm_runtime_get_sync(up->dev);
466 up->mcr = serial_in(up, UART_MCR);
468 serial_out(up, UART_MCR, up->mcr);
469 pm_runtime_mark_last_busy(up->dev);
470 pm_runtime_put_autosuspend(up->dev);
472 if (gpio_is_valid(up->DTR_gpio) &&
473 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
474 up->DTR_active = !up->DTR_active;
475 if (gpio_cansleep(up->DTR_gpio))
476 schedule_work(&up->qos_work);
478 gpio_set_value(up->DTR_gpio,
479 up->DTR_active != up->DTR_inverted);
483 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
485 struct uart_omap_port *up = to_uart_omap_port(port);
486 unsigned long flags = 0;
488 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
489 pm_runtime_get_sync(up->dev);
490 spin_lock_irqsave(&up->port.lock, flags);
491 if (break_state == -1)
492 up->lcr |= UART_LCR_SBC;
494 up->lcr &= ~UART_LCR_SBC;
495 serial_out(up, UART_LCR, up->lcr);
496 spin_unlock_irqrestore(&up->port.lock, flags);
497 pm_runtime_mark_last_busy(up->dev);
498 pm_runtime_put_autosuspend(up->dev);
501 static int serial_omap_startup(struct uart_port *port)
503 struct uart_omap_port *up = to_uart_omap_port(port);
504 unsigned long flags = 0;
510 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
515 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
517 pm_runtime_get_sync(up->dev);
519 * Clear the FIFO buffers and disable them.
520 * (they will be reenabled in set_termios())
522 serial_omap_clear_fifos(up);
523 /* For Hardware flow control */
524 serial_out(up, UART_MCR, UART_MCR_RTS);
527 * Clear the interrupt registers.
529 (void) serial_in(up, UART_LSR);
530 if (serial_in(up, UART_LSR) & UART_LSR_DR)
531 (void) serial_in(up, UART_RX);
532 (void) serial_in(up, UART_IIR);
533 (void) serial_in(up, UART_MSR);
536 * Now, initialize the UART
538 serial_out(up, UART_LCR, UART_LCR_WLEN8);
539 spin_lock_irqsave(&up->port.lock, flags);
541 * Most PC uarts need OUT2 raised to enable interrupts.
543 up->port.mctrl |= TIOCM_OUT2;
544 serial_omap_set_mctrl(&up->port, up->port.mctrl);
545 spin_unlock_irqrestore(&up->port.lock, flags);
547 up->msr_saved_flags = 0;
549 * Finally, enable interrupts. Note: Modem status interrupts
550 * are set via set_termios(), which will be occurring imminently
551 * anyway, so we don't enable them here.
553 up->ier = UART_IER_RLSI | UART_IER_RDI;
554 serial_out(up, UART_IER, up->ier);
556 /* Enable module level wake up */
557 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
559 pm_runtime_mark_last_busy(up->dev);
560 pm_runtime_put_autosuspend(up->dev);
561 up->port_activity = jiffies;
565 static void serial_omap_shutdown(struct uart_port *port)
567 struct uart_omap_port *up = to_uart_omap_port(port);
568 unsigned long flags = 0;
570 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
572 pm_runtime_get_sync(up->dev);
574 * Disable interrupts from this port
577 serial_out(up, UART_IER, 0);
579 spin_lock_irqsave(&up->port.lock, flags);
580 up->port.mctrl &= ~TIOCM_OUT2;
581 serial_omap_set_mctrl(&up->port, up->port.mctrl);
582 spin_unlock_irqrestore(&up->port.lock, flags);
585 * Disable break condition and FIFOs
587 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
588 serial_omap_clear_fifos(up);
591 * Read data port to reset things, and then free the irq
593 if (serial_in(up, UART_LSR) & UART_LSR_DR)
594 (void) serial_in(up, UART_RX);
596 pm_runtime_mark_last_busy(up->dev);
597 pm_runtime_put_autosuspend(up->dev);
598 free_irq(up->port.irq, up);
602 serial_omap_configure_xonxoff
603 (struct uart_omap_port *up, struct ktermios *termios)
605 up->lcr = serial_in(up, UART_LCR);
606 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
607 up->efr = serial_in(up, UART_EFR);
608 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
610 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
611 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
613 /* clear SW control mode bits */
614 up->efr &= OMAP_UART_SW_CLR;
618 * Enable XON/XOFF flow control on output.
619 * Transmit XON1, XOFF1
621 if (termios->c_iflag & IXON)
622 up->efr |= OMAP_UART_SW_TX;
626 * Enable XON/XOFF flow control on input.
627 * Receiver compares XON1, XOFF1.
629 if (termios->c_iflag & IXOFF)
630 up->efr |= OMAP_UART_SW_RX;
632 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
633 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
635 up->mcr = serial_in(up, UART_MCR);
639 * Enable any character to restart output.
640 * Operation resumes after receiving any
641 * character after recognition of the XOFF character
643 if (termios->c_iflag & IXANY)
644 up->mcr |= UART_MCR_XONANY;
646 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
647 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
648 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
649 /* Enable special char function UARTi.EFR_REG[5] and
650 * load the new software flow control mode IXON or IXOFF
651 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
653 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
654 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
656 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
657 serial_out(up, UART_LCR, up->lcr);
660 static void serial_omap_uart_qos_work(struct work_struct *work)
662 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
665 pm_qos_update_request(&up->pm_qos_request, up->latency);
666 if (gpio_is_valid(up->DTR_gpio))
667 gpio_set_value_cansleep(up->DTR_gpio,
668 up->DTR_active != up->DTR_inverted);
672 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
673 struct ktermios *old)
675 struct uart_omap_port *up = to_uart_omap_port(port);
676 unsigned char cval = 0;
677 unsigned char efr = 0;
678 unsigned long flags = 0;
679 unsigned int baud, quot;
681 switch (termios->c_cflag & CSIZE) {
683 cval = UART_LCR_WLEN5;
686 cval = UART_LCR_WLEN6;
689 cval = UART_LCR_WLEN7;
693 cval = UART_LCR_WLEN8;
697 if (termios->c_cflag & CSTOPB)
698 cval |= UART_LCR_STOP;
699 if (termios->c_cflag & PARENB)
700 cval |= UART_LCR_PARITY;
701 if (!(termios->c_cflag & PARODD))
702 cval |= UART_LCR_EPAR;
705 * Ask the core to calculate the divisor for us.
708 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
709 quot = serial_omap_get_divisor(port, baud);
711 /* calculate wakeup latency constraint */
712 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
713 up->latency = up->calc_latency;
714 schedule_work(&up->qos_work);
716 up->dll = quot & 0xff;
718 up->mdr1 = UART_OMAP_MDR1_DISABLE;
720 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
721 UART_FCR_ENABLE_FIFO;
724 * Ok, we're now changing the port state. Do it with
725 * interrupts disabled.
727 pm_runtime_get_sync(up->dev);
728 spin_lock_irqsave(&up->port.lock, flags);
731 * Update the per-port timeout.
733 uart_update_timeout(port, termios->c_cflag, baud);
735 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
736 if (termios->c_iflag & INPCK)
737 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
738 if (termios->c_iflag & (BRKINT | PARMRK))
739 up->port.read_status_mask |= UART_LSR_BI;
742 * Characters to ignore
744 up->port.ignore_status_mask = 0;
745 if (termios->c_iflag & IGNPAR)
746 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
747 if (termios->c_iflag & IGNBRK) {
748 up->port.ignore_status_mask |= UART_LSR_BI;
750 * If we're ignoring parity and break indicators,
751 * ignore overruns too (for real raw support).
753 if (termios->c_iflag & IGNPAR)
754 up->port.ignore_status_mask |= UART_LSR_OE;
758 * ignore all characters if CREAD is not set
760 if ((termios->c_cflag & CREAD) == 0)
761 up->port.ignore_status_mask |= UART_LSR_DR;
764 * Modem status interrupts
766 up->ier &= ~UART_IER_MSI;
767 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
768 up->ier |= UART_IER_MSI;
769 serial_out(up, UART_IER, up->ier);
770 serial_out(up, UART_LCR, cval); /* reset DLAB */
772 up->scr = OMAP_UART_SCR_TX_EMPTY;
774 /* FIFOs and DMA Settings */
776 /* FCR can be changed only when the
777 * baud clock is not running
778 * DLL_REG and DLH_REG set to 0.
780 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
781 serial_out(up, UART_DLL, 0);
782 serial_out(up, UART_DLM, 0);
783 serial_out(up, UART_LCR, 0);
785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
787 up->efr = serial_in(up, UART_EFR);
788 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
790 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
791 up->mcr = serial_in(up, UART_MCR);
792 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
793 /* FIFO ENABLE, DMA MODE */
795 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
797 /* Set receive FIFO threshold to 1 byte */
798 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
799 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
801 serial_out(up, UART_FCR, up->fcr);
802 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
804 serial_out(up, UART_OMAP_SCR, up->scr);
806 serial_out(up, UART_EFR, up->efr);
807 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
808 serial_out(up, UART_MCR, up->mcr);
810 /* Protocol, Baud Rate, and Interrupt Settings */
812 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
813 serial_omap_mdr1_errataset(up, up->mdr1);
815 serial_out(up, UART_OMAP_MDR1, up->mdr1);
817 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
819 up->efr = serial_in(up, UART_EFR);
820 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
822 serial_out(up, UART_LCR, 0);
823 serial_out(up, UART_IER, 0);
824 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
826 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
827 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
829 serial_out(up, UART_LCR, 0);
830 serial_out(up, UART_IER, up->ier);
831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
833 serial_out(up, UART_EFR, up->efr);
834 serial_out(up, UART_LCR, cval);
836 if (baud > 230400 && baud != 3000000)
837 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
839 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
841 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
842 serial_omap_mdr1_errataset(up, up->mdr1);
844 serial_out(up, UART_OMAP_MDR1, up->mdr1);
846 /* Hardware Flow Control Configuration */
848 if (termios->c_cflag & CRTSCTS) {
849 efr |= (UART_EFR_CTS | UART_EFR_RTS);
850 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
852 up->mcr = serial_in(up, UART_MCR);
853 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
855 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
856 up->efr = serial_in(up, UART_EFR);
857 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
859 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
860 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
861 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
862 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
863 serial_out(up, UART_LCR, cval);
866 serial_omap_set_mctrl(&up->port, up->port.mctrl);
867 /* Software Flow Control Configuration */
868 serial_omap_configure_xonxoff(up, termios);
870 spin_unlock_irqrestore(&up->port.lock, flags);
871 pm_runtime_mark_last_busy(up->dev);
872 pm_runtime_put_autosuspend(up->dev);
873 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
877 serial_omap_pm(struct uart_port *port, unsigned int state,
878 unsigned int oldstate)
880 struct uart_omap_port *up = to_uart_omap_port(port);
883 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
885 pm_runtime_get_sync(up->dev);
886 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
887 efr = serial_in(up, UART_EFR);
888 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
889 serial_out(up, UART_LCR, 0);
891 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
892 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
893 serial_out(up, UART_EFR, efr);
894 serial_out(up, UART_LCR, 0);
896 if (!device_may_wakeup(up->dev)) {
898 pm_runtime_forbid(up->dev);
900 pm_runtime_allow(up->dev);
903 pm_runtime_mark_last_busy(up->dev);
904 pm_runtime_put_autosuspend(up->dev);
907 static void serial_omap_release_port(struct uart_port *port)
909 dev_dbg(port->dev, "serial_omap_release_port+\n");
912 static int serial_omap_request_port(struct uart_port *port)
914 dev_dbg(port->dev, "serial_omap_request_port+\n");
918 static void serial_omap_config_port(struct uart_port *port, int flags)
920 struct uart_omap_port *up = to_uart_omap_port(port);
922 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
924 up->port.type = PORT_OMAP;
928 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
930 /* we don't want the core code to modify any port params */
931 dev_dbg(port->dev, "serial_omap_verify_port+\n");
936 serial_omap_type(struct uart_port *port)
938 struct uart_omap_port *up = to_uart_omap_port(port);
940 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
944 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
946 static inline void wait_for_xmitr(struct uart_omap_port *up)
948 unsigned int status, tmout = 10000;
950 /* Wait up to 10ms for the character(s) to be sent. */
952 status = serial_in(up, UART_LSR);
954 if (status & UART_LSR_BI)
955 up->lsr_break_flag = UART_LSR_BI;
960 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
962 /* Wait up to 1s for flow control if necessary */
963 if (up->port.flags & UPF_CONS_FLOW) {
965 for (tmout = 1000000; tmout; tmout--) {
966 unsigned int msr = serial_in(up, UART_MSR);
968 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
969 if (msr & UART_MSR_CTS)
977 #ifdef CONFIG_CONSOLE_POLL
979 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
981 struct uart_omap_port *up = to_uart_omap_port(port);
983 pm_runtime_get_sync(up->dev);
985 serial_out(up, UART_TX, ch);
986 pm_runtime_mark_last_busy(up->dev);
987 pm_runtime_put_autosuspend(up->dev);
990 static int serial_omap_poll_get_char(struct uart_port *port)
992 struct uart_omap_port *up = to_uart_omap_port(port);
995 pm_runtime_get_sync(up->dev);
996 status = serial_in(up, UART_LSR);
997 if (!(status & UART_LSR_DR))
1000 status = serial_in(up, UART_RX);
1001 pm_runtime_mark_last_busy(up->dev);
1002 pm_runtime_put_autosuspend(up->dev);
1006 #endif /* CONFIG_CONSOLE_POLL */
1008 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1010 static struct uart_omap_port *serial_omap_console_ports[4];
1012 static struct uart_driver serial_omap_reg;
1014 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1016 struct uart_omap_port *up = to_uart_omap_port(port);
1019 serial_out(up, UART_TX, ch);
1023 serial_omap_console_write(struct console *co, const char *s,
1026 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1027 unsigned long flags;
1031 pm_runtime_get_sync(up->dev);
1033 local_irq_save(flags);
1036 else if (oops_in_progress)
1037 locked = spin_trylock(&up->port.lock);
1039 spin_lock(&up->port.lock);
1042 * First save the IER then disable the interrupts
1044 ier = serial_in(up, UART_IER);
1045 serial_out(up, UART_IER, 0);
1047 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1050 * Finally, wait for transmitter to become empty
1051 * and restore the IER
1054 serial_out(up, UART_IER, ier);
1056 * The receive handling will happen properly because the
1057 * receive ready bit will still be set; it is not cleared
1058 * on read. However, modem control will not, we must
1059 * call it if we have saved something in the saved flags
1060 * while processing with interrupts off.
1062 if (up->msr_saved_flags)
1063 check_modem_status(up);
1065 pm_runtime_mark_last_busy(up->dev);
1066 pm_runtime_put_autosuspend(up->dev);
1068 spin_unlock(&up->port.lock);
1069 local_irq_restore(flags);
1073 serial_omap_console_setup(struct console *co, char *options)
1075 struct uart_omap_port *up;
1081 if (serial_omap_console_ports[co->index] == NULL)
1083 up = serial_omap_console_ports[co->index];
1086 uart_parse_options(options, &baud, &parity, &bits, &flow);
1088 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1091 static struct console serial_omap_console = {
1092 .name = OMAP_SERIAL_NAME,
1093 .write = serial_omap_console_write,
1094 .device = uart_console_device,
1095 .setup = serial_omap_console_setup,
1096 .flags = CON_PRINTBUFFER,
1098 .data = &serial_omap_reg,
1101 static void serial_omap_add_console_port(struct uart_omap_port *up)
1103 serial_omap_console_ports[up->port.line] = up;
1106 #define OMAP_CONSOLE (&serial_omap_console)
1110 #define OMAP_CONSOLE NULL
1112 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1117 static struct uart_ops serial_omap_pops = {
1118 .tx_empty = serial_omap_tx_empty,
1119 .set_mctrl = serial_omap_set_mctrl,
1120 .get_mctrl = serial_omap_get_mctrl,
1121 .stop_tx = serial_omap_stop_tx,
1122 .start_tx = serial_omap_start_tx,
1123 .stop_rx = serial_omap_stop_rx,
1124 .enable_ms = serial_omap_enable_ms,
1125 .break_ctl = serial_omap_break_ctl,
1126 .startup = serial_omap_startup,
1127 .shutdown = serial_omap_shutdown,
1128 .set_termios = serial_omap_set_termios,
1129 .pm = serial_omap_pm,
1130 .type = serial_omap_type,
1131 .release_port = serial_omap_release_port,
1132 .request_port = serial_omap_request_port,
1133 .config_port = serial_omap_config_port,
1134 .verify_port = serial_omap_verify_port,
1135 #ifdef CONFIG_CONSOLE_POLL
1136 .poll_put_char = serial_omap_poll_put_char,
1137 .poll_get_char = serial_omap_poll_get_char,
1141 static struct uart_driver serial_omap_reg = {
1142 .owner = THIS_MODULE,
1143 .driver_name = "OMAP-SERIAL",
1144 .dev_name = OMAP_SERIAL_NAME,
1145 .nr = OMAP_MAX_HSUART_PORTS,
1146 .cons = OMAP_CONSOLE,
1149 #ifdef CONFIG_PM_SLEEP
1150 static int serial_omap_suspend(struct device *dev)
1152 struct uart_omap_port *up = dev_get_drvdata(dev);
1155 uart_suspend_port(&serial_omap_reg, &up->port);
1156 flush_work_sync(&up->qos_work);
1162 static int serial_omap_resume(struct device *dev)
1164 struct uart_omap_port *up = dev_get_drvdata(dev);
1167 uart_resume_port(&serial_omap_reg, &up->port);
1172 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1175 u16 revision, major, minor;
1177 mvr = serial_in(up, UART_OMAP_MVER);
1179 /* Check revision register scheme */
1180 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1183 case 0: /* Legacy Scheme: OMAP2/3 */
1184 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1185 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1186 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1187 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1190 /* New Scheme: OMAP4+ */
1191 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1192 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1193 OMAP_UART_MVR_MAJ_SHIFT;
1194 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1198 "Unknown %s revision, defaulting to highest\n",
1200 /* highest possible revision */
1205 /* normalize revision for the driver */
1206 revision = UART_BUILD_REVISION(major, minor);
1209 case OMAP_UART_REV_46:
1210 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1211 UART_ERRATA_i291_DMA_FORCEIDLE);
1213 case OMAP_UART_REV_52:
1214 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1215 UART_ERRATA_i291_DMA_FORCEIDLE);
1217 case OMAP_UART_REV_63:
1218 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1225 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1227 struct omap_uart_port_info *omap_up_info;
1229 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1231 return NULL; /* out of memory */
1233 of_property_read_u32(dev->of_node, "clock-frequency",
1234 &omap_up_info->uartclk);
1235 return omap_up_info;
1238 static int serial_omap_probe(struct platform_device *pdev)
1240 struct uart_omap_port *up;
1241 struct resource *mem, *irq;
1242 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1245 if (pdev->dev.of_node)
1246 omap_up_info = of_get_uart_port_info(&pdev->dev);
1248 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 dev_err(&pdev->dev, "no mem resource?\n");
1254 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1256 dev_err(&pdev->dev, "no irq resource?\n");
1260 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1261 pdev->dev.driver->name)) {
1262 dev_err(&pdev->dev, "memory region already claimed\n");
1266 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1267 omap_up_info->DTR_present) {
1268 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1271 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1272 omap_up_info->DTR_inverted);
1277 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1281 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1282 omap_up_info->DTR_present) {
1283 up->DTR_gpio = omap_up_info->DTR_gpio;
1284 up->DTR_inverted = omap_up_info->DTR_inverted;
1286 up->DTR_gpio = -EINVAL;
1289 up->dev = &pdev->dev;
1290 up->port.dev = &pdev->dev;
1291 up->port.type = PORT_OMAP;
1292 up->port.iotype = UPIO_MEM;
1293 up->port.irq = irq->start;
1295 up->port.regshift = 2;
1296 up->port.fifosize = 64;
1297 up->port.ops = &serial_omap_pops;
1299 if (pdev->dev.of_node)
1300 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1302 up->port.line = pdev->id;
1304 if (up->port.line < 0) {
1305 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1311 sprintf(up->name, "OMAP UART%d", up->port.line);
1312 up->port.mapbase = mem->start;
1313 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1314 resource_size(mem));
1315 if (!up->port.membase) {
1316 dev_err(&pdev->dev, "can't ioremap UART\n");
1321 up->port.flags = omap_up_info->flags;
1322 up->port.uartclk = omap_up_info->uartclk;
1323 if (!up->port.uartclk) {
1324 up->port.uartclk = DEFAULT_CLK_SPEED;
1325 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1326 "%d\n", DEFAULT_CLK_SPEED);
1329 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1330 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1331 pm_qos_add_request(&up->pm_qos_request,
1332 PM_QOS_CPU_DMA_LATENCY, up->latency);
1333 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1334 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1336 platform_set_drvdata(pdev, up);
1337 pm_runtime_use_autosuspend(&pdev->dev);
1338 pm_runtime_set_autosuspend_delay(&pdev->dev,
1339 omap_up_info->autosuspend_timeout);
1341 pm_runtime_irq_safe(&pdev->dev);
1342 pm_runtime_enable(&pdev->dev);
1343 pm_runtime_get_sync(&pdev->dev);
1345 omap_serial_fill_features_erratas(up);
1347 ui[up->port.line] = up;
1348 serial_omap_add_console_port(up);
1350 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1354 pm_runtime_mark_last_busy(up->dev);
1355 pm_runtime_put_autosuspend(up->dev);
1359 pm_runtime_put(&pdev->dev);
1360 pm_runtime_disable(&pdev->dev);
1363 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1364 pdev->id, __func__, ret);
1368 static int serial_omap_remove(struct platform_device *dev)
1370 struct uart_omap_port *up = platform_get_drvdata(dev);
1372 pm_runtime_put_sync(up->dev);
1373 pm_runtime_disable(up->dev);
1374 uart_remove_one_port(&serial_omap_reg, &up->port);
1375 pm_qos_remove_request(&up->pm_qos_request);
1381 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1382 * The access to uart register after MDR1 Access
1383 * causes UART to corrupt data.
1386 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1387 * give 10 times as much
1389 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1393 serial_out(up, UART_OMAP_MDR1, mdr1);
1395 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1396 UART_FCR_CLEAR_RCVR);
1398 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1399 * TX_FIFO_E bit is 1.
1401 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1402 (UART_LSR_THRE | UART_LSR_DR))) {
1405 /* Should *never* happen. we warn and carry on */
1406 dev_crit(up->dev, "Errata i202: timedout %x\n",
1407 serial_in(up, UART_LSR));
1414 #ifdef CONFIG_PM_RUNTIME
1415 static void serial_omap_restore_context(struct uart_omap_port *up)
1417 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1418 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1420 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1422 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1423 serial_out(up, UART_EFR, UART_EFR_ECB);
1424 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1425 serial_out(up, UART_IER, 0x0);
1426 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1427 serial_out(up, UART_DLL, up->dll);
1428 serial_out(up, UART_DLM, up->dlh);
1429 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1430 serial_out(up, UART_IER, up->ier);
1431 serial_out(up, UART_FCR, up->fcr);
1432 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1433 serial_out(up, UART_MCR, up->mcr);
1434 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1435 serial_out(up, UART_OMAP_SCR, up->scr);
1436 serial_out(up, UART_EFR, up->efr);
1437 serial_out(up, UART_LCR, up->lcr);
1438 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1439 serial_omap_mdr1_errataset(up, up->mdr1);
1441 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1444 static int serial_omap_runtime_suspend(struct device *dev)
1446 struct uart_omap_port *up = dev_get_drvdata(dev);
1447 struct omap_uart_port_info *pdata = dev->platform_data;
1455 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1457 if (device_may_wakeup(dev)) {
1458 if (!up->wakeups_enabled) {
1459 serial_omap_enable_wakeup(up, true);
1460 up->wakeups_enabled = true;
1463 if (up->wakeups_enabled) {
1464 serial_omap_enable_wakeup(up, false);
1465 up->wakeups_enabled = false;
1469 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1470 schedule_work(&up->qos_work);
1475 static int serial_omap_runtime_resume(struct device *dev)
1477 struct uart_omap_port *up = dev_get_drvdata(dev);
1478 struct omap_uart_port_info *pdata = dev->platform_data;
1481 u32 loss_cnt = serial_omap_get_context_loss_count(up);
1483 if (up->context_loss_cnt != loss_cnt)
1484 serial_omap_restore_context(up);
1486 up->latency = up->calc_latency;
1487 schedule_work(&up->qos_work);
1494 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1495 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1496 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1497 serial_omap_runtime_resume, NULL)
1500 #if defined(CONFIG_OF)
1501 static const struct of_device_id omap_serial_of_match[] = {
1502 { .compatible = "ti,omap2-uart" },
1503 { .compatible = "ti,omap3-uart" },
1504 { .compatible = "ti,omap4-uart" },
1507 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1510 static struct platform_driver serial_omap_driver = {
1511 .probe = serial_omap_probe,
1512 .remove = serial_omap_remove,
1514 .name = DRIVER_NAME,
1515 .pm = &serial_omap_dev_pm_ops,
1516 .of_match_table = of_match_ptr(omap_serial_of_match),
1520 static int __init serial_omap_init(void)
1524 ret = uart_register_driver(&serial_omap_reg);
1527 ret = platform_driver_register(&serial_omap_driver);
1529 uart_unregister_driver(&serial_omap_reg);
1533 static void __exit serial_omap_exit(void)
1535 platform_driver_unregister(&serial_omap_driver);
1536 uart_unregister_driver(&serial_omap_reg);
1539 module_init(serial_omap_init);
1540 module_exit(serial_omap_exit);
1542 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1543 MODULE_LICENSE("GPL");
1544 MODULE_AUTHOR("Texas Instruments Inc");