drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43
  44 #include <plat/omap-serial.h>
  45
  46 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  47
  48 #define OMAP_UART_REV_42 0x0402
  49 #define OMAP_UART_REV_46 0x0406
  50 #define OMAP_UART_REV_52 0x0502
  51 #define OMAP_UART_REV_63 0x0603
  52
  53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  54
  55 /* SCR register bitmasks */
  56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  57
  58 /* FCR register bitmasks */
  59 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  60 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  61
  62 /* MVR register bitmasks */
  63 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  64
  65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  67 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  68
  69 #define OMAP_UART_MVR_MAJ_MASK          0x700
  70 #define OMAP_UART_MVR_MAJ_SHIFT         8
  71 #define OMAP_UART_MVR_MIN_MASK          0x3f
  72
  73 struct uart_omap_port {
  74         struct uart_port        port;
  75         struct uart_omap_dma    uart_dma;
  76         struct device           *dev;
  77
  78         unsigned char           ier;
  79         unsigned char           lcr;
  80         unsigned char           mcr;
  81         unsigned char           fcr;
  82         unsigned char           efr;
  83         unsigned char           dll;
  84         unsigned char           dlh;
  85         unsigned char           mdr1;
  86         unsigned char           scr;
  87
  88         int                     use_dma;
  89         /*
  90          * Some bits in registers are cleared on a read, so they must
  91          * be saved whenever the register is read but the bits will not
  92          * be immediately processed.
  93          */
  94         unsigned int            lsr_break_flag;
  95         unsigned char           msr_saved_flags;
  96         char                    name[20];
  97         unsigned long           port_activity;
  98         u32                     context_loss_cnt;
  99         u32                     errata;
 100         u8                      wakeups_enabled;
 101         unsigned int            irq_pending:1;
 102
 103         int                     DTR_gpio;
 104         int                     DTR_inverted;
 105         int                     DTR_active;
 106
 107         struct pm_qos_request   pm_qos_request;
 108         u32                     latency;
 109         u32                     calc_latency;
 110         struct work_struct      qos_work;
 111 };
 112
 113 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 114
 115 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 116
 117 /* Forward declaration of functions */
 118 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 119
 120 static struct workqueue_struct *serial_omap_uart_wq;
 121
 122 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 123 {
 124         offset <<= up->port.regshift;
 125         return readw(up->port.membase + offset);
 126 }
 127
 128 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 129 {
 130         offset <<= up->port.regshift;
 131         writew(value, up->port.membase + offset);
 132 }
 133
 134 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 135 {
 136         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 137         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 138                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 139         serial_out(up, UART_FCR, 0);
 140 }
 141
 142 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 143 {
 144         struct omap_uart_port_info *pdata = up->dev->platform_data;
 145
 146         if (!pdata->get_context_loss_count)
 147                 return 0;
 148
 149         return pdata->get_context_loss_count(up->dev);
 150 }
 151
 152 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 153 {
 154         struct omap_uart_port_info *pdata = up->dev->platform_data;
 155
 156         if (pdata->set_forceidle)
 157                 pdata->set_forceidle(up->dev);
 158 }
 159
 160 static void serial_omap_set_noidle(struct uart_omap_port *up)
 161 {
 162         struct omap_uart_port_info *pdata = up->dev->platform_data;
 163
 164         if (pdata->set_noidle)
 165                 pdata->set_noidle(up->dev);
 166 }
 167
 168 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 169 {
 170         struct omap_uart_port_info *pdata = up->dev->platform_data;
 171
 172         if (pdata->enable_wakeup)
 173                 pdata->enable_wakeup(up->dev, enable);
 174 }
 175
 176 /*
 177  * serial_omap_get_divisor - calculate divisor value
 178  * @port: uart port info
 179  * @baud: baudrate for which divisor needs to be calculated.
 180  *
 181  * We have written our own function to get the divisor so as to support
 182  * 13x mode. 3Mbps Baudrate as an different divisor.
 183  * Reference OMAP TRM Chapter 17:
 184  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 185  * referring to oversampling - divisor value
 186  * baudrate 460,800 to 3,686,400 all have divisor 13
 187  * except 3,000,000 which has divisor value 16
 188  */
 189 static unsigned int
 190 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 191 {
 192         unsigned int divisor;
 193
 194         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 195                 divisor = 13;
 196         else
 197                 divisor = 16;
 198         return port->uartclk/(baud * divisor);
 199 }
 200
 201 static void serial_omap_enable_ms(struct uart_port *port)
 202 {
 203         struct uart_omap_port *up = to_uart_omap_port(port);
 204
 205         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 206
 207         pm_runtime_get_sync(up->dev);
 208         up->ier |= UART_IER_MSI;
 209         serial_out(up, UART_IER, up->ier);
 210         pm_runtime_mark_last_busy(up->dev);
 211         pm_runtime_put_autosuspend(up->dev);
 212 }
 213
 214 static void serial_omap_stop_tx(struct uart_port *port)
 215 {
 216         struct uart_omap_port *up = to_uart_omap_port(port);
 217
 218         pm_runtime_get_sync(up->dev);
 219         if (up->ier & UART_IER_THRI) {
 220                 up->ier &= ~UART_IER_THRI;
 221                 serial_out(up, UART_IER, up->ier);
 222         }
 223
 224         serial_omap_set_forceidle(up);
 225
 226         pm_runtime_mark_last_busy(up->dev);
 227         pm_runtime_put_autosuspend(up->dev);
 228 }
 229
 230 static void serial_omap_stop_rx(struct uart_port *port)
 231 {
 232         struct uart_omap_port *up = to_uart_omap_port(port);
 233
 234         pm_runtime_get_sync(up->dev);
 235         up->ier &= ~UART_IER_RLSI;
 236         up->port.read_status_mask &= ~UART_LSR_DR;
 237         serial_out(up, UART_IER, up->ier);
 238         pm_runtime_mark_last_busy(up->dev);
 239         pm_runtime_put_autosuspend(up->dev);
 240 }
 241
 242 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 243 {
 244         struct circ_buf *xmit = &up->port.state->xmit;
 245         int count;
 246
 247         if (!(lsr & UART_LSR_THRE))
 248                 return;
 249
 250         if (up->port.x_char) {
 251                 serial_out(up, UART_TX, up->port.x_char);
 252                 up->port.icount.tx++;
 253                 up->port.x_char = 0;
 254                 return;
 255         }
 256         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 257                 serial_omap_stop_tx(&up->port);
 258                 return;
 259         }
 260         count = up->port.fifosize / 4;
 261         do {
 262                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 263                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 264                 up->port.icount.tx++;
 265                 if (uart_circ_empty(xmit))
 266                         break;
 267         } while (--count > 0);
 268
 269         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 270                 spin_unlock(&up->port.lock);
 271                 uart_write_wakeup(&up->port);
 272                 spin_lock(&up->port.lock);
 273         }
 274
 275         if (uart_circ_empty(xmit))
 276                 serial_omap_stop_tx(&up->port);
 277 }
 278
 279 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 280 {
 281         if (!(up->ier & UART_IER_THRI)) {
 282                 up->ier |= UART_IER_THRI;
 283                 serial_out(up, UART_IER, up->ier);
 284         }
 285 }
 286
 287 static void serial_omap_start_tx(struct uart_port *port)
 288 {
 289         struct uart_omap_port *up = to_uart_omap_port(port);
 290
 291         pm_runtime_get_sync(up->dev);
 292         serial_omap_enable_ier_thri(up);
 293         serial_omap_set_noidle(up);
 294         pm_runtime_mark_last_busy(up->dev);
 295         pm_runtime_put_autosuspend(up->dev);
 296 }
 297
 298 static unsigned int check_modem_status(struct uart_omap_port *up)
 299 {
 300         unsigned int status;
 301
 302         status = serial_in(up, UART_MSR);
 303         status |= up->msr_saved_flags;
 304         up->msr_saved_flags = 0;
 305         if ((status & UART_MSR_ANY_DELTA) == 0)
 306                 return status;
 307
 308         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 309             up->port.state != NULL) {
 310                 if (status & UART_MSR_TERI)
 311                         up->port.icount.rng++;
 312                 if (status & UART_MSR_DDSR)
 313                         up->port.icount.dsr++;
 314                 if (status & UART_MSR_DDCD)
 315                         uart_handle_dcd_change
 316                                 (&up->port, status & UART_MSR_DCD);
 317                 if (status & UART_MSR_DCTS)
 318                         uart_handle_cts_change
 319                                 (&up->port, status & UART_MSR_CTS);
 320                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 321         }
 322
 323         return status;
 324 }
 325
 326 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 327 {
 328         unsigned int flag;
 329
 330         up->port.icount.rx++;
 331         flag = TTY_NORMAL;
 332
 333         if (lsr & UART_LSR_BI) {
 334                 flag = TTY_BREAK;
 335                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 336                 up->port.icount.brk++;
 337                 /*
 338                  * We do the SysRQ and SAK checking
 339                  * here because otherwise the break
 340                  * may get masked by ignore_status_mask
 341                  * or read_status_mask.
 342                  */
 343                 if (uart_handle_break(&up->port))
 344                         return;
 345
 346         }
 347
 348         if (lsr & UART_LSR_PE) {
 349                 flag = TTY_PARITY;
 350                 up->port.icount.parity++;
 351         }
 352
 353         if (lsr & UART_LSR_FE) {
 354                 flag = TTY_FRAME;
 355                 up->port.icount.frame++;
 356         }
 357
 358         if (lsr & UART_LSR_OE)
 359                 up->port.icount.overrun++;
 360
 361 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 362         if (up->port.line == up->port.cons->index) {
 363                 /* Recover the break flag from console xmit */
 364                 lsr |= up->lsr_break_flag;
 365         }
 366 #endif
 367         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 368 }
 369
 370 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 371 {
 372         unsigned char ch = 0;
 373         unsigned int flag;
 374
 375         if (!(lsr & UART_LSR_DR))
 376                 return;
 377
 378         ch = serial_in(up, UART_RX);
 379         flag = TTY_NORMAL;
 380         up->port.icount.rx++;
 381
 382         if (uart_handle_sysrq_char(&up->port, ch))
 383                 return;
 384
 385         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 386 }
 387
 388 /**
 389  * serial_omap_irq() - This handles the interrupt from one port
 390  * @irq: uart port irq number
 391  * @dev_id: uart port info
 392  */
 393 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 394 {
 395         struct uart_omap_port *up = dev_id;
 396         struct tty_struct *tty = up->port.state->port.tty;
 397         unsigned int iir, lsr;
 398         unsigned int type;
 399         irqreturn_t ret = IRQ_NONE;
 400         int max_count = 256;
 401
 402         spin_lock(&up->port.lock);
 403         pm_runtime_get_sync(up->dev);
 404
 405         do {
 406                 iir = serial_in(up, UART_IIR);
 407                 if (iir & UART_IIR_NO_INT)
 408                         break;
 409
 410                 ret = IRQ_HANDLED;
 411                 lsr = serial_in(up, UART_LSR);
 412
 413                 /* extract IRQ type from IIR register */
 414                 type = iir & 0x3e;
 415
 416                 switch (type) {
 417                 case UART_IIR_MSI:
 418                         check_modem_status(up);
 419                         break;
 420                 case UART_IIR_THRI:
 421                         transmit_chars(up, lsr);
 422                         break;
 423                 case UART_IIR_RX_TIMEOUT:
 424                         /* FALLTHROUGH */
 425                 case UART_IIR_RDI:
 426                         serial_omap_rdi(up, lsr);
 427                         break;
 428                 case UART_IIR_RLSI:
 429                         serial_omap_rlsi(up, lsr);
 430                         break;
 431                 case UART_IIR_CTS_RTS_DSR:
 432                         /* simply try again */
 433                         break;
 434                 case UART_IIR_XOFF:
 435                         /* FALLTHROUGH */
 436                 default:
 437                         break;
 438                 }
 439         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 440
 441         spin_unlock(&up->port.lock);
 442
 443         tty_flip_buffer_push(tty);
 444
 445         pm_runtime_mark_last_busy(up->dev);
 446         pm_runtime_put_autosuspend(up->dev);
 447         up->port_activity = jiffies;
 448
 449         return ret;
 450 }
 451
 452 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 453 {
 454         struct uart_omap_port *up = to_uart_omap_port(port);
 455         unsigned long flags = 0;
 456         unsigned int ret = 0;
 457
 458         pm_runtime_get_sync(up->dev);
 459         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 460         spin_lock_irqsave(&up->port.lock, flags);
 461         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 462         spin_unlock_irqrestore(&up->port.lock, flags);
 463         pm_runtime_mark_last_busy(up->dev);
 464         pm_runtime_put_autosuspend(up->dev);
 465         return ret;
 466 }
 467
 468 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 469 {
 470         struct uart_omap_port *up = to_uart_omap_port(port);
 471         unsigned int status;
 472         unsigned int ret = 0;
 473
 474         pm_runtime_get_sync(up->dev);
 475         status = check_modem_status(up);
 476         pm_runtime_mark_last_busy(up->dev);
 477         pm_runtime_put_autosuspend(up->dev);
 478
 479         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 480
 481         if (status & UART_MSR_DCD)
 482                 ret |= TIOCM_CAR;
 483         if (status & UART_MSR_RI)
 484                 ret |= TIOCM_RNG;
 485         if (status & UART_MSR_DSR)
 486                 ret |= TIOCM_DSR;
 487         if (status & UART_MSR_CTS)
 488                 ret |= TIOCM_CTS;
 489         return ret;
 490 }
 491
 492 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 493 {
 494         struct uart_omap_port *up = to_uart_omap_port(port);
 495         unsigned char mcr = 0;
 496
 497         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 498         if (mctrl & TIOCM_RTS)
 499                 mcr |= UART_MCR_RTS;
 500         if (mctrl & TIOCM_DTR)
 501                 mcr |= UART_MCR_DTR;
 502         if (mctrl & TIOCM_OUT1)
 503                 mcr |= UART_MCR_OUT1;
 504         if (mctrl & TIOCM_OUT2)
 505                 mcr |= UART_MCR_OUT2;
 506         if (mctrl & TIOCM_LOOP)
 507                 mcr |= UART_MCR_LOOP;
 508
 509         pm_runtime_get_sync(up->dev);
 510         up->mcr = serial_in(up, UART_MCR);
 511         up->mcr |= mcr;
 512         serial_out(up, UART_MCR, up->mcr);
 513         pm_runtime_mark_last_busy(up->dev);
 514         pm_runtime_put_autosuspend(up->dev);
 515
 516         if (gpio_is_valid(up->DTR_gpio) &&
 517             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 518                 up->DTR_active = !up->DTR_active;
 519                 if (gpio_cansleep(up->DTR_gpio))
 520                         schedule_work(&up->qos_work);
 521                 else
 522                         gpio_set_value(up->DTR_gpio,
 523                                        up->DTR_active != up->DTR_inverted);
 524         }
 525 }
 526
 527 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 528 {
 529         struct uart_omap_port *up = to_uart_omap_port(port);
 530         unsigned long flags = 0;
 531
 532         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 533         pm_runtime_get_sync(up->dev);
 534         spin_lock_irqsave(&up->port.lock, flags);
 535         if (break_state == -1)
 536                 up->lcr |= UART_LCR_SBC;
 537         else
 538                 up->lcr &= ~UART_LCR_SBC;
 539         serial_out(up, UART_LCR, up->lcr);
 540         spin_unlock_irqrestore(&up->port.lock, flags);
 541         pm_runtime_mark_last_busy(up->dev);
 542         pm_runtime_put_autosuspend(up->dev);
 543 }
 544
 545 static int serial_omap_startup(struct uart_port *port)
 546 {
 547         struct uart_omap_port *up = to_uart_omap_port(port);
 548         unsigned long flags = 0;
 549         int retval;
 550
 551         /*
 552          * Allocate the IRQ
 553          */
 554         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 555                                 up->name, up);
 556         if (retval)
 557                 return retval;
 558
 559         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 560
 561         pm_runtime_get_sync(up->dev);
 562         /*
 563          * Clear the FIFO buffers and disable them.
 564          * (they will be reenabled in set_termios())
 565          */
 566         serial_omap_clear_fifos(up);
 567         /* For Hardware flow control */
 568         serial_out(up, UART_MCR, UART_MCR_RTS);
 569
 570         /*
 571          * Clear the interrupt registers.
 572          */
 573         (void) serial_in(up, UART_LSR);
 574         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 575                 (void) serial_in(up, UART_RX);
 576         (void) serial_in(up, UART_IIR);
 577         (void) serial_in(up, UART_MSR);
 578
 579         /*
 580          * Now, initialize the UART
 581          */
 582         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 583         spin_lock_irqsave(&up->port.lock, flags);
 584         /*
 585          * Most PC uarts need OUT2 raised to enable interrupts.
 586          */
 587         up->port.mctrl |= TIOCM_OUT2;
 588         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 589         spin_unlock_irqrestore(&up->port.lock, flags);
 590
 591         up->msr_saved_flags = 0;
 592         /*
 593          * Finally, enable interrupts. Note: Modem status interrupts
 594          * are set via set_termios(), which will be occurring imminently
 595          * anyway, so we don't enable them here.
 596          */
 597         up->ier = UART_IER_RLSI | UART_IER_RDI;
 598         serial_out(up, UART_IER, up->ier);
 599
 600         /* Enable module level wake up */
 601         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 602
 603         pm_runtime_mark_last_busy(up->dev);
 604         pm_runtime_put_autosuspend(up->dev);
 605         up->port_activity = jiffies;
 606         return 0;
 607 }
 608
 609 static void serial_omap_shutdown(struct uart_port *port)
 610 {
 611         struct uart_omap_port *up = to_uart_omap_port(port);
 612         unsigned long flags = 0;
 613
 614         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 615
 616         pm_runtime_get_sync(up->dev);
 617         /*
 618          * Disable interrupts from this port
 619          */
 620         up->ier = 0;
 621         serial_out(up, UART_IER, 0);
 622
 623         spin_lock_irqsave(&up->port.lock, flags);
 624         up->port.mctrl &= ~TIOCM_OUT2;
 625         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 626         spin_unlock_irqrestore(&up->port.lock, flags);
 627
 628         /*
 629          * Disable break condition and FIFOs
 630          */
 631         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 632         serial_omap_clear_fifos(up);
 633
 634         /*
 635          * Read data port to reset things, and then free the irq
 636          */
 637         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 638                 (void) serial_in(up, UART_RX);
 639
 640         pm_runtime_mark_last_busy(up->dev);
 641         pm_runtime_put_autosuspend(up->dev);
 642         free_irq(up->port.irq, up);
 643 }
 644
 645 static inline void
 646 serial_omap_configure_xonxoff
 647                 (struct uart_omap_port *up, struct ktermios *termios)
 648 {
 649         up->lcr = serial_in(up, UART_LCR);
 650         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 651         up->efr = serial_in(up, UART_EFR);
 652         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 653
 654         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 655         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 656
 657         /* clear SW control mode bits */
 658         up->efr &= OMAP_UART_SW_CLR;
 659
 660         /*
 661          * IXON Flag:
 662          * Flow control for OMAP.TX
 663          * OMAP.RX should listen for XON/XOFF
 664          */
 665         if (termios->c_iflag & IXON)
 666                 up->efr |= OMAP_UART_SW_RX;
 667
 668         /*
 669          * IXOFF Flag:
 670          * Flow control for OMAP.RX
 671          * OMAP.TX should send XON/XOFF
 672          */
 673         if (termios->c_iflag & IXOFF)
 674                 up->efr |= OMAP_UART_SW_TX;
 675
 676         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 677         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 678
 679         up->mcr = serial_in(up, UART_MCR);
 680
 681         /*
 682          * IXANY Flag:
 683          * Enable any character to restart output.
 684          * Operation resumes after receiving any
 685          * character after recognition of the XOFF character
 686          */
 687         if (termios->c_iflag & IXANY)
 688                 up->mcr |= UART_MCR_XONANY;
 689
 690         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 691         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 692         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 693         /* Enable special char function UARTi.EFR_REG[5] and
 694          * load the new software flow control mode IXON or IXOFF
 695          * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
 696          */
 697         serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
 698         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 699
 700         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 701         serial_out(up, UART_LCR, up->lcr);
 702 }
 703
 704 static void serial_omap_uart_qos_work(struct work_struct *work)
 705 {
 706         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 707                                                 qos_work);
 708
 709         pm_qos_update_request(&up->pm_qos_request, up->latency);
 710         if (gpio_is_valid(up->DTR_gpio))
 711                 gpio_set_value_cansleep(up->DTR_gpio,
 712                                         up->DTR_active != up->DTR_inverted);
 713 }
 714
 715 static void
 716 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 717                         struct ktermios *old)
 718 {
 719         struct uart_omap_port *up = to_uart_omap_port(port);
 720         unsigned char cval = 0;
 721         unsigned char efr = 0;
 722         unsigned long flags = 0;
 723         unsigned int baud, quot;
 724
 725         switch (termios->c_cflag & CSIZE) {
 726         case CS5:
 727                 cval = UART_LCR_WLEN5;
 728                 break;
 729         case CS6:
 730                 cval = UART_LCR_WLEN6;
 731                 break;
 732         case CS7:
 733                 cval = UART_LCR_WLEN7;
 734                 break;
 735         default:
 736         case CS8:
 737                 cval = UART_LCR_WLEN8;
 738                 break;
 739         }
 740
 741         if (termios->c_cflag & CSTOPB)
 742                 cval |= UART_LCR_STOP;
 743         if (termios->c_cflag & PARENB)
 744                 cval |= UART_LCR_PARITY;
 745         if (!(termios->c_cflag & PARODD))
 746                 cval |= UART_LCR_EPAR;
 747
 748         /*
 749          * Ask the core to calculate the divisor for us.
 750          */
 751
 752         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 753         quot = serial_omap_get_divisor(port, baud);
 754
 755         /* calculate wakeup latency constraint */
 756         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 757         up->latency = up->calc_latency;
 758         schedule_work(&up->qos_work);
 759
 760         up->dll = quot & 0xff;
 761         up->dlh = quot >> 8;
 762         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 763
 764         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 765                         UART_FCR_ENABLE_FIFO;
 766
 767         /*
 768          * Ok, we're now changing the port state. Do it with
 769          * interrupts disabled.
 770          */
 771         pm_runtime_get_sync(up->dev);
 772         spin_lock_irqsave(&up->port.lock, flags);
 773
 774         /*
 775          * Update the per-port timeout.
 776          */
 777         uart_update_timeout(port, termios->c_cflag, baud);
 778
 779         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 780         if (termios->c_iflag & INPCK)
 781                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 782         if (termios->c_iflag & (BRKINT | PARMRK))
 783                 up->port.read_status_mask |= UART_LSR_BI;
 784
 785         /*
 786          * Characters to ignore
 787          */
 788         up->port.ignore_status_mask = 0;
 789         if (termios->c_iflag & IGNPAR)
 790                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 791         if (termios->c_iflag & IGNBRK) {
 792                 up->port.ignore_status_mask |= UART_LSR_BI;
 793                 /*
 794                  * If we're ignoring parity and break indicators,
 795                  * ignore overruns too (for real raw support).
 796                  */
 797                 if (termios->c_iflag & IGNPAR)
 798                         up->port.ignore_status_mask |= UART_LSR_OE;
 799         }
 800
 801         /*
 802          * ignore all characters if CREAD is not set
 803          */
 804         if ((termios->c_cflag & CREAD) == 0)
 805                 up->port.ignore_status_mask |= UART_LSR_DR;
 806
 807         /*
 808          * Modem status interrupts
 809          */
 810         up->ier &= ~UART_IER_MSI;
 811         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 812                 up->ier |= UART_IER_MSI;
 813         serial_out(up, UART_IER, up->ier);
 814         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 815         up->lcr = cval;
 816         up->scr = OMAP_UART_SCR_TX_EMPTY;
 817
 818         /* FIFOs and DMA Settings */
 819
 820         /* FCR can be changed only when the
 821          * baud clock is not running
 822          * DLL_REG and DLH_REG set to 0.
 823          */
 824         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 825         serial_out(up, UART_DLL, 0);
 826         serial_out(up, UART_DLM, 0);
 827         serial_out(up, UART_LCR, 0);
 828
 829         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 830
 831         up->efr = serial_in(up, UART_EFR);
 832         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 833
 834         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 835         up->mcr = serial_in(up, UART_MCR);
 836         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 837         /* FIFO ENABLE, DMA MODE */
 838
 839         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 840
 841         /* Set receive FIFO threshold to 16 characters and
 842          * transmit FIFO threshold to 16 spaces
 843          */
 844         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 845         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 846         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 847                 UART_FCR_ENABLE_FIFO;
 848
 849         serial_out(up, UART_FCR, up->fcr);
 850         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 851
 852         serial_out(up, UART_OMAP_SCR, up->scr);
 853
 854         serial_out(up, UART_EFR, up->efr);
 855         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 856         serial_out(up, UART_MCR, up->mcr);
 857
 858         /* Protocol, Baud Rate, and Interrupt Settings */
 859
 860         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 861                 serial_omap_mdr1_errataset(up, up->mdr1);
 862         else
 863                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 864
 865         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 866
 867         up->efr = serial_in(up, UART_EFR);
 868         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 869
 870         serial_out(up, UART_LCR, 0);
 871         serial_out(up, UART_IER, 0);
 872         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 873
 874         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 875         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 876
 877         serial_out(up, UART_LCR, 0);
 878         serial_out(up, UART_IER, up->ier);
 879         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 880
 881         serial_out(up, UART_EFR, up->efr);
 882         serial_out(up, UART_LCR, cval);
 883
 884         if (baud > 230400 && baud != 3000000)
 885                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 886         else
 887                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 888
 889         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 890                 serial_omap_mdr1_errataset(up, up->mdr1);
 891         else
 892                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 893
 894         /* Hardware Flow Control Configuration */
 895
 896         if (termios->c_cflag & CRTSCTS) {
 897                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
 898                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 899
 900                 up->mcr = serial_in(up, UART_MCR);
 901                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 902
 903                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 904                 up->efr = serial_in(up, UART_EFR);
 905                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 906
 907                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 908                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
 909                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 910                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 911                 serial_out(up, UART_LCR, cval);
 912         }
 913
 914         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 915         /* Software Flow Control Configuration */
 916         serial_omap_configure_xonxoff(up, termios);
 917
 918         spin_unlock_irqrestore(&up->port.lock, flags);
 919         pm_runtime_mark_last_busy(up->dev);
 920         pm_runtime_put_autosuspend(up->dev);
 921         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 922 }
 923
 924 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 925 {
 926         struct uart_omap_port *up = to_uart_omap_port(port);
 927
 928         serial_omap_enable_wakeup(up, state);
 929
 930         return 0;
 931 }
 932
 933 static void
 934 serial_omap_pm(struct uart_port *port, unsigned int state,
 935                unsigned int oldstate)
 936 {
 937         struct uart_omap_port *up = to_uart_omap_port(port);
 938         unsigned char efr;
 939
 940         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 941
 942         pm_runtime_get_sync(up->dev);
 943         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 944         efr = serial_in(up, UART_EFR);
 945         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 946         serial_out(up, UART_LCR, 0);
 947
 948         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 949         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 950         serial_out(up, UART_EFR, efr);
 951         serial_out(up, UART_LCR, 0);
 952
 953         if (!device_may_wakeup(up->dev)) {
 954                 if (!state)
 955                         pm_runtime_forbid(up->dev);
 956                 else
 957                         pm_runtime_allow(up->dev);
 958         }
 959
 960         pm_runtime_mark_last_busy(up->dev);
 961         pm_runtime_put_autosuspend(up->dev);
 962 }
 963
 964 static void serial_omap_release_port(struct uart_port *port)
 965 {
 966         dev_dbg(port->dev, "serial_omap_release_port+\n");
 967 }
 968
 969 static int serial_omap_request_port(struct uart_port *port)
 970 {
 971         dev_dbg(port->dev, "serial_omap_request_port+\n");
 972         return 0;
 973 }
 974
 975 static void serial_omap_config_port(struct uart_port *port, int flags)
 976 {
 977         struct uart_omap_port *up = to_uart_omap_port(port);
 978
 979         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 980                                                         up->port.line);
 981         up->port.type = PORT_OMAP;
 982 }
 983
 984 static int
 985 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 986 {
 987         /* we don't want the core code to modify any port params */
 988         dev_dbg(port->dev, "serial_omap_verify_port+\n");
 989         return -EINVAL;
 990 }
 991
 992 static const char *
 993 serial_omap_type(struct uart_port *port)
 994 {
 995         struct uart_omap_port *up = to_uart_omap_port(port);
 996
 997         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 998         return up->name;
 999 }
1000
1001 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1002
1003 static inline void wait_for_xmitr(struct uart_omap_port *up)
1004 {
1005         unsigned int status, tmout = 10000;
1006
1007         /* Wait up to 10ms for the character(s) to be sent. */
1008         do {
1009                 status = serial_in(up, UART_LSR);
1010
1011                 if (status & UART_LSR_BI)
1012                         up->lsr_break_flag = UART_LSR_BI;
1013
1014                 if (--tmout == 0)
1015                         break;
1016                 udelay(1);
1017         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1018
1019         /* Wait up to 1s for flow control if necessary */
1020         if (up->port.flags & UPF_CONS_FLOW) {
1021                 tmout = 1000000;
1022                 for (tmout = 1000000; tmout; tmout--) {
1023                         unsigned int msr = serial_in(up, UART_MSR);
1024
1025                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1026                         if (msr & UART_MSR_CTS)
1027                                 break;
1028
1029                         udelay(1);
1030                 }
1031         }
1032 }
1033
1034 #ifdef CONFIG_CONSOLE_POLL
1035
1036 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1037 {
1038         struct uart_omap_port *up = to_uart_omap_port(port);
1039
1040         pm_runtime_get_sync(up->dev);
1041         wait_for_xmitr(up);
1042         serial_out(up, UART_TX, ch);
1043         pm_runtime_mark_last_busy(up->dev);
1044         pm_runtime_put_autosuspend(up->dev);
1045 }
1046
1047 static int serial_omap_poll_get_char(struct uart_port *port)
1048 {
1049         struct uart_omap_port *up = to_uart_omap_port(port);
1050         unsigned int status;
1051
1052         pm_runtime_get_sync(up->dev);
1053         status = serial_in(up, UART_LSR);
1054         if (!(status & UART_LSR_DR)) {
1055                 status = NO_POLL_CHAR;
1056                 goto out;
1057         }
1058
1059         status = serial_in(up, UART_RX);
1060
1061 out:
1062         pm_runtime_mark_last_busy(up->dev);
1063         pm_runtime_put_autosuspend(up->dev);
1064
1065         return status;
1066 }
1067
1068 #endif /* CONFIG_CONSOLE_POLL */
1069
1070 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1071
1072 static struct uart_omap_port *serial_omap_console_ports[4];
1073
1074 static struct uart_driver serial_omap_reg;
1075
1076 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1077 {
1078         struct uart_omap_port *up = to_uart_omap_port(port);
1079
1080         wait_for_xmitr(up);
1081         serial_out(up, UART_TX, ch);
1082 }
1083
1084 static void
1085 serial_omap_console_write(struct console *co, const char *s,
1086                 unsigned int count)
1087 {
1088         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1089         unsigned long flags;
1090         unsigned int ier;
1091         int locked = 1;
1092
1093         pm_runtime_get_sync(up->dev);
1094
1095         local_irq_save(flags);
1096         if (up->port.sysrq)
1097                 locked = 0;
1098         else if (oops_in_progress)
1099                 locked = spin_trylock(&up->port.lock);
1100         else
1101                 spin_lock(&up->port.lock);
1102
1103         /*
1104          * First save the IER then disable the interrupts
1105          */
1106         ier = serial_in(up, UART_IER);
1107         serial_out(up, UART_IER, 0);
1108
1109         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1110
1111         /*
1112          * Finally, wait for transmitter to become empty
1113          * and restore the IER
1114          */
1115         wait_for_xmitr(up);
1116         serial_out(up, UART_IER, ier);
1117         /*
1118          * The receive handling will happen properly because the
1119          * receive ready bit will still be set; it is not cleared
1120          * on read.  However, modem control will not, we must
1121          * call it if we have saved something in the saved flags
1122          * while processing with interrupts off.
1123          */
1124         if (up->msr_saved_flags)
1125                 check_modem_status(up);
1126
1127         pm_runtime_mark_last_busy(up->dev);
1128         pm_runtime_put_autosuspend(up->dev);
1129         if (locked)
1130                 spin_unlock(&up->port.lock);
1131         local_irq_restore(flags);
1132 }
1133
1134 static int __init
1135 serial_omap_console_setup(struct console *co, char *options)
1136 {
1137         struct uart_omap_port *up;
1138         int baud = 115200;
1139         int bits = 8;
1140         int parity = 'n';
1141         int flow = 'n';
1142
1143         if (serial_omap_console_ports[co->index] == NULL)
1144                 return -ENODEV;
1145         up = serial_omap_console_ports[co->index];
1146
1147         if (options)
1148                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1149
1150         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1151 }
1152
1153 static struct console serial_omap_console = {
1154         .name           = OMAP_SERIAL_NAME,
1155         .write          = serial_omap_console_write,
1156         .device         = uart_console_device,
1157         .setup          = serial_omap_console_setup,
1158         .flags          = CON_PRINTBUFFER,
1159         .index          = -1,
1160         .data           = &serial_omap_reg,
1161 };
1162
1163 static void serial_omap_add_console_port(struct uart_omap_port *up)
1164 {
1165         serial_omap_console_ports[up->port.line] = up;
1166 }
1167
1168 #define OMAP_CONSOLE    (&serial_omap_console)
1169
1170 #else
1171
1172 #define OMAP_CONSOLE    NULL
1173
1174 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1175 {}
1176
1177 #endif
1178
1179 static struct uart_ops serial_omap_pops = {
1180         .tx_empty       = serial_omap_tx_empty,
1181         .set_mctrl      = serial_omap_set_mctrl,
1182         .get_mctrl      = serial_omap_get_mctrl,
1183         .stop_tx        = serial_omap_stop_tx,
1184         .start_tx       = serial_omap_start_tx,
1185         .stop_rx        = serial_omap_stop_rx,
1186         .enable_ms      = serial_omap_enable_ms,
1187         .break_ctl      = serial_omap_break_ctl,
1188         .startup        = serial_omap_startup,
1189         .shutdown       = serial_omap_shutdown,
1190         .set_termios    = serial_omap_set_termios,
1191         .pm             = serial_omap_pm,
1192         .set_wake       = serial_omap_set_wake,
1193         .type           = serial_omap_type,
1194         .release_port   = serial_omap_release_port,
1195         .request_port   = serial_omap_request_port,
1196         .config_port    = serial_omap_config_port,
1197         .verify_port    = serial_omap_verify_port,
1198 #ifdef CONFIG_CONSOLE_POLL
1199         .poll_put_char  = serial_omap_poll_put_char,
1200         .poll_get_char  = serial_omap_poll_get_char,
1201 #endif
1202 };
1203
1204 static struct uart_driver serial_omap_reg = {
1205         .owner          = THIS_MODULE,
1206         .driver_name    = "OMAP-SERIAL",
1207         .dev_name       = OMAP_SERIAL_NAME,
1208         .nr             = OMAP_MAX_HSUART_PORTS,
1209         .cons           = OMAP_CONSOLE,
1210 };
1211
1212 #ifdef CONFIG_PM_SLEEP
1213 static int serial_omap_suspend(struct device *dev)
1214 {
1215         struct uart_omap_port *up = dev_get_drvdata(dev);
1216
1217         if (up) {
1218                 uart_suspend_port(&serial_omap_reg, &up->port);
1219                 flush_work_sync(&up->qos_work);
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int serial_omap_resume(struct device *dev)
1226 {
1227         struct uart_omap_port *up = dev_get_drvdata(dev);
1228
1229         if (up)
1230                 uart_resume_port(&serial_omap_reg, &up->port);
1231         return 0;
1232 }
1233 #endif
1234
1235 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1236 {
1237         u32 mvr, scheme;
1238         u16 revision, major, minor;
1239
1240         mvr = serial_in(up, UART_OMAP_MVER);
1241
1242         /* Check revision register scheme */
1243         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1244
1245         switch (scheme) {
1246         case 0: /* Legacy Scheme: OMAP2/3 */
1247                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1248                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1249                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1250                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1251                 break;
1252         case 1:
1253                 /* New Scheme: OMAP4+ */
1254                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1255                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1256                                         OMAP_UART_MVR_MAJ_SHIFT;
1257                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1258                 break;
1259         default:
1260                 dev_warn(up->dev,
1261                         "Unknown %s revision, defaulting to highest\n",
1262                         up->name);
1263                 /* highest possible revision */
1264                 major = 0xff;
1265                 minor = 0xff;
1266         }
1267
1268         /* normalize revision for the driver */
1269         revision = UART_BUILD_REVISION(major, minor);
1270
1271         switch (revision) {
1272         case OMAP_UART_REV_46:
1273                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1274                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1275                 break;
1276         case OMAP_UART_REV_52:
1277                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1278                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1279                 break;
1280         case OMAP_UART_REV_63:
1281                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1282                 break;
1283         default:
1284                 break;
1285         }
1286 }
1287
1288 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1289 {
1290         struct omap_uart_port_info *omap_up_info;
1291
1292         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1293         if (!omap_up_info)
1294                 return NULL; /* out of memory */
1295
1296         of_property_read_u32(dev->of_node, "clock-frequency",
1297                                          &omap_up_info->uartclk);
1298         return omap_up_info;
1299 }
1300
1301 static int __devinit serial_omap_probe(struct platform_device *pdev)
1302 {
1303         struct uart_omap_port   *up;
1304         struct resource         *mem, *irq;
1305         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1306         int ret;
1307
1308         if (pdev->dev.of_node)
1309                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1310
1311         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1312         if (!mem) {
1313                 dev_err(&pdev->dev, "no mem resource?\n");
1314                 return -ENODEV;
1315         }
1316
1317         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1318         if (!irq) {
1319                 dev_err(&pdev->dev, "no irq resource?\n");
1320                 return -ENODEV;
1321         }
1322
1323         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1324                                 pdev->dev.driver->name)) {
1325                 dev_err(&pdev->dev, "memory region already claimed\n");
1326                 return -EBUSY;
1327         }
1328
1329         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1330             omap_up_info->DTR_present) {
1331                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1332                 if (ret < 0)
1333                         return ret;
1334                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1335                                             omap_up_info->DTR_inverted);
1336                 if (ret < 0)
1337                         return ret;
1338         }
1339
1340         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1341         if (!up)
1342                 return -ENOMEM;
1343
1344         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1345             omap_up_info->DTR_present) {
1346                 up->DTR_gpio = omap_up_info->DTR_gpio;
1347                 up->DTR_inverted = omap_up_info->DTR_inverted;
1348         } else
1349                 up->DTR_gpio = -EINVAL;
1350         up->DTR_active = 0;
1351
1352         up->dev = &pdev->dev;
1353         up->port.dev = &pdev->dev;
1354         up->port.type = PORT_OMAP;
1355         up->port.iotype = UPIO_MEM;
1356         up->port.irq = irq->start;
1357
1358         up->port.regshift = 2;
1359         up->port.fifosize = 64;
1360         up->port.ops = &serial_omap_pops;
1361
1362         if (pdev->dev.of_node)
1363                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1364         else
1365                 up->port.line = pdev->id;
1366
1367         if (up->port.line < 0) {
1368                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1369                                                                 up->port.line);
1370                 ret = -ENODEV;
1371                 goto err_port_line;
1372         }
1373
1374         sprintf(up->name, "OMAP UART%d", up->port.line);
1375         up->port.mapbase = mem->start;
1376         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1377                                                 resource_size(mem));
1378         if (!up->port.membase) {
1379                 dev_err(&pdev->dev, "can't ioremap UART\n");
1380                 ret = -ENOMEM;
1381                 goto err_ioremap;
1382         }
1383
1384         up->port.flags = omap_up_info->flags;
1385         up->port.uartclk = omap_up_info->uartclk;
1386         if (!up->port.uartclk) {
1387                 up->port.uartclk = DEFAULT_CLK_SPEED;
1388                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1389                                                 "%d\n", DEFAULT_CLK_SPEED);
1390         }
1391
1392         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1393         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1394         pm_qos_add_request(&up->pm_qos_request,
1395                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1396         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1397         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1398
1399         platform_set_drvdata(pdev, up);
1400         pm_runtime_enable(&pdev->dev);
1401         pm_runtime_use_autosuspend(&pdev->dev);
1402         pm_runtime_set_autosuspend_delay(&pdev->dev,
1403                         omap_up_info->autosuspend_timeout);
1404
1405         pm_runtime_irq_safe(&pdev->dev);
1406         pm_runtime_get_sync(&pdev->dev);
1407
1408         omap_serial_fill_features_erratas(up);
1409
1410         ui[up->port.line] = up;
1411         serial_omap_add_console_port(up);
1412
1413         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1414         if (ret != 0)
1415                 goto err_add_port;
1416
1417         pm_runtime_mark_last_busy(up->dev);
1418         pm_runtime_put_autosuspend(up->dev);
1419         return 0;
1420
1421 err_add_port:
1422         pm_runtime_put(&pdev->dev);
1423         pm_runtime_disable(&pdev->dev);
1424 err_ioremap:
1425 err_port_line:
1426         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1427                                 pdev->id, __func__, ret);
1428         return ret;
1429 }
1430
1431 static int __devexit serial_omap_remove(struct platform_device *dev)
1432 {
1433         struct uart_omap_port *up = platform_get_drvdata(dev);
1434
1435         pm_runtime_put_sync(up->dev);
1436         pm_runtime_disable(up->dev);
1437         uart_remove_one_port(&serial_omap_reg, &up->port);
1438         pm_qos_remove_request(&up->pm_qos_request);
1439
1440         return 0;
1441 }
1442
1443 /*
1444  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1445  * The access to uart register after MDR1 Access
1446  * causes UART to corrupt data.
1447  *
1448  * Need a delay =
1449  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1450  * give 10 times as much
1451  */
1452 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1453 {
1454         u8 timeout = 255;
1455
1456         serial_out(up, UART_OMAP_MDR1, mdr1);
1457         udelay(2);
1458         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1459                         UART_FCR_CLEAR_RCVR);
1460         /*
1461          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1462          * TX_FIFO_E bit is 1.
1463          */
1464         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1465                                 (UART_LSR_THRE | UART_LSR_DR))) {
1466                 timeout--;
1467                 if (!timeout) {
1468                         /* Should *never* happen. we warn and carry on */
1469                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1470                                                 serial_in(up, UART_LSR));
1471                         break;
1472                 }
1473                 udelay(1);
1474         }
1475 }
1476
1477 #ifdef CONFIG_PM_RUNTIME
1478 static void serial_omap_restore_context(struct uart_omap_port *up)
1479 {
1480         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1481                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1482         else
1483                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1484
1485         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1486         serial_out(up, UART_EFR, UART_EFR_ECB);
1487         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1488         serial_out(up, UART_IER, 0x0);
1489         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1490         serial_out(up, UART_DLL, up->dll);
1491         serial_out(up, UART_DLM, up->dlh);
1492         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1493         serial_out(up, UART_IER, up->ier);
1494         serial_out(up, UART_FCR, up->fcr);
1495         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1496         serial_out(up, UART_MCR, up->mcr);
1497         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1498         serial_out(up, UART_OMAP_SCR, up->scr);
1499         serial_out(up, UART_EFR, up->efr);
1500         serial_out(up, UART_LCR, up->lcr);
1501         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1502                 serial_omap_mdr1_errataset(up, up->mdr1);
1503         else
1504                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1505 }
1506
1507 static int serial_omap_runtime_suspend(struct device *dev)
1508 {
1509         struct uart_omap_port *up = dev_get_drvdata(dev);
1510         struct omap_uart_port_info *pdata = dev->platform_data;
1511
1512         if (!up)
1513                 return -EINVAL;
1514
1515         if (!pdata)
1516                 return 0;
1517
1518         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1519
1520         if (device_may_wakeup(dev)) {
1521                 if (!up->wakeups_enabled) {
1522                         serial_omap_enable_wakeup(up, true);
1523                         up->wakeups_enabled = true;
1524                 }
1525         } else {
1526                 if (up->wakeups_enabled) {
1527                         serial_omap_enable_wakeup(up, false);
1528                         up->wakeups_enabled = false;
1529                 }
1530         }
1531
1532         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1533         schedule_work(&up->qos_work);
1534
1535         return 0;
1536 }
1537
1538 static int serial_omap_runtime_resume(struct device *dev)
1539 {
1540         struct uart_omap_port *up = dev_get_drvdata(dev);
1541         struct omap_uart_port_info *pdata = dev->platform_data;
1542
1543         if (up && pdata) {
1544                         u32 loss_cnt = serial_omap_get_context_loss_count(up);
1545
1546                         if (up->context_loss_cnt != loss_cnt)
1547                                 serial_omap_restore_context(up);
1548
1549                 up->latency = up->calc_latency;
1550                 schedule_work(&up->qos_work);
1551         }
1552
1553         return 0;
1554 }
1555 #endif
1556
1557 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1558         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1559         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1560                                 serial_omap_runtime_resume, NULL)
1561 };
1562
1563 #if defined(CONFIG_OF)
1564 static const struct of_device_id omap_serial_of_match[] = {
1565         { .compatible = "ti,omap2-uart" },
1566         { .compatible = "ti,omap3-uart" },
1567         { .compatible = "ti,omap4-uart" },
1568         {},
1569 };
1570 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1571 #endif
1572
1573 static struct platform_driver serial_omap_driver = {
1574         .probe          = serial_omap_probe,
1575         .remove         = __devexit_p(serial_omap_remove),
1576         .driver         = {
1577                 .name   = DRIVER_NAME,
1578                 .pm     = &serial_omap_dev_pm_ops,
1579                 .of_match_table = of_match_ptr(omap_serial_of_match),
1580         },
1581 };
1582
1583 static int __init serial_omap_init(void)
1584 {
1585         int ret;
1586
1587         ret = uart_register_driver(&serial_omap_reg);
1588         if (ret != 0)
1589                 return ret;
1590         ret = platform_driver_register(&serial_omap_driver);
1591         if (ret != 0)
1592                 uart_unregister_driver(&serial_omap_reg);
1593         return ret;
1594 }
1595
1596 static void __exit serial_omap_exit(void)
1597 {
1598         platform_driver_unregister(&serial_omap_driver);
1599         uart_unregister_driver(&serial_omap_reg);
1600 }
1601
1602 module_init(serial_omap_init);
1603 module_exit(serial_omap_exit);
1604
1605 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1606 MODULE_LICENSE("GPL");
1607 MODULE_AUTHOR("Texas Instruments Inc");