2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
36 #include <linux/debugfs.h>
37 #include <linux/dmaengine.h>
38 #include <linux/pch_dma.h>
41 PCH_UART_HANDLED_RX_INT_SHIFT,
42 PCH_UART_HANDLED_TX_INT_SHIFT,
43 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
44 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
45 PCH_UART_HANDLED_MS_INT_SHIFT,
46 PCH_UART_HANDLED_LS_INT_SHIFT,
54 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
56 /* Set the max number of UART port
57 * Intel EG20T PCH: 4 port
58 * LAPIS Semiconductor ML7213 IOH: 3 port
59 * LAPIS Semiconductor ML7223 IOH: 2 port
63 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
65 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
66 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
67 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
68 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
69 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
71 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
73 #define PCH_UART_RBR 0x00
74 #define PCH_UART_THR 0x00
76 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
77 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
78 #define PCH_UART_IER_ERBFI 0x00000001
79 #define PCH_UART_IER_ETBEI 0x00000002
80 #define PCH_UART_IER_ELSI 0x00000004
81 #define PCH_UART_IER_EDSSI 0x00000008
83 #define PCH_UART_IIR_IP 0x00000001
84 #define PCH_UART_IIR_IID 0x00000006
85 #define PCH_UART_IIR_MSI 0x00000000
86 #define PCH_UART_IIR_TRI 0x00000002
87 #define PCH_UART_IIR_RRI 0x00000004
88 #define PCH_UART_IIR_REI 0x00000006
89 #define PCH_UART_IIR_TOI 0x00000008
90 #define PCH_UART_IIR_FIFO256 0x00000020
91 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
92 #define PCH_UART_IIR_FE 0x000000C0
94 #define PCH_UART_FCR_FIFOE 0x00000001
95 #define PCH_UART_FCR_RFR 0x00000002
96 #define PCH_UART_FCR_TFR 0x00000004
97 #define PCH_UART_FCR_DMS 0x00000008
98 #define PCH_UART_FCR_FIFO256 0x00000020
99 #define PCH_UART_FCR_RFTL 0x000000C0
101 #define PCH_UART_FCR_RFTL1 0x00000000
102 #define PCH_UART_FCR_RFTL64 0x00000040
103 #define PCH_UART_FCR_RFTL128 0x00000080
104 #define PCH_UART_FCR_RFTL224 0x000000C0
105 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
106 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
107 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
108 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
109 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
110 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
111 #define PCH_UART_FCR_RFTL_SHIFT 6
113 #define PCH_UART_LCR_WLS 0x00000003
114 #define PCH_UART_LCR_STB 0x00000004
115 #define PCH_UART_LCR_PEN 0x00000008
116 #define PCH_UART_LCR_EPS 0x00000010
117 #define PCH_UART_LCR_SP 0x00000020
118 #define PCH_UART_LCR_SB 0x00000040
119 #define PCH_UART_LCR_DLAB 0x00000080
120 #define PCH_UART_LCR_NP 0x00000000
121 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
122 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
123 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
124 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
127 #define PCH_UART_LCR_5BIT 0x00000000
128 #define PCH_UART_LCR_6BIT 0x00000001
129 #define PCH_UART_LCR_7BIT 0x00000002
130 #define PCH_UART_LCR_8BIT 0x00000003
132 #define PCH_UART_MCR_DTR 0x00000001
133 #define PCH_UART_MCR_RTS 0x00000002
134 #define PCH_UART_MCR_OUT 0x0000000C
135 #define PCH_UART_MCR_LOOP 0x00000010
136 #define PCH_UART_MCR_AFE 0x00000020
138 #define PCH_UART_LSR_DR 0x00000001
139 #define PCH_UART_LSR_ERR (1<<7)
141 #define PCH_UART_MSR_DCTS 0x00000001
142 #define PCH_UART_MSR_DDSR 0x00000002
143 #define PCH_UART_MSR_TERI 0x00000004
144 #define PCH_UART_MSR_DDCD 0x00000008
145 #define PCH_UART_MSR_CTS 0x00000010
146 #define PCH_UART_MSR_DSR 0x00000020
147 #define PCH_UART_MSR_RI 0x00000040
148 #define PCH_UART_MSR_DCD 0x00000080
149 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
150 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
152 #define PCH_UART_DLL 0x00
153 #define PCH_UART_DLM 0x01
155 #define PCH_UART_BRCSR 0x0E
157 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
158 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
159 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
160 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
161 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
163 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
164 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
165 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
166 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
167 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
168 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
169 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
170 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
171 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
172 #define PCH_UART_HAL_STB1 0
173 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
175 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
176 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
177 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
178 PCH_UART_HAL_CLR_RX_FIFO)
180 #define PCH_UART_HAL_DMA_MODE0 0
181 #define PCH_UART_HAL_FIFO_DIS 0
182 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
183 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
184 PCH_UART_FCR_FIFO256)
185 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
186 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
187 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
188 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
189 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
190 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
191 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
192 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
193 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
194 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
195 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
196 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
197 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
198 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
200 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
201 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
202 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
203 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
204 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
206 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
207 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
208 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
209 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
210 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
212 #define PCI_VENDOR_ID_ROHM 0x10DB
214 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
216 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
217 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
218 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
219 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
220 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
221 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
223 struct pch_uart_buffer {
229 struct uart_port port;
231 void __iomem *membase;
232 resource_size_t mapbase;
234 struct pci_dev *pdev;
236 unsigned int uartclk;
242 struct pch_uart_buffer rxbuf;
246 unsigned int use_dma;
247 struct dma_async_tx_descriptor *desc_tx;
248 struct dma_async_tx_descriptor *desc_rx;
249 struct pch_dma_slave param_tx;
250 struct pch_dma_slave param_rx;
251 struct dma_chan *chan_tx;
252 struct dma_chan *chan_rx;
253 struct scatterlist *sg_tx_p;
255 struct scatterlist sg_rx;
258 dma_addr_t rx_buf_dma;
260 struct dentry *debugfs;
261 #define IRQ_NAME_SIZE 17
262 char irq_name[IRQ_NAME_SIZE];
264 /* protect the eg20t_port private structure and io access to membase */
269 * struct pch_uart_driver_data - private data structure for UART-DMA
270 * @port_type: The number of DMA channel
271 * @line_no: UART port line number (0, 1, 2...)
273 struct pch_uart_driver_data {
278 enum pch_uart_num_t {
292 static struct pch_uart_driver_data drv_dat[] = {
293 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
294 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
295 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
296 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
297 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
298 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
299 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
300 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
301 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
302 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
303 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
306 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
307 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
309 static unsigned int default_baud = 9600;
310 static unsigned int user_uartclk = 0;
311 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
312 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
313 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
314 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
316 #ifdef CONFIG_DEBUG_FS
318 #define PCH_REGS_BUFSIZE 1024
321 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
322 size_t count, loff_t *ppos)
324 struct eg20t_port *priv = file->private_data;
330 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "PCH EG20T port[%d] regs:\n", priv->port.line);
337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
338 "=================================\n");
339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
340 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
341 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
343 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
344 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
345 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
346 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
347 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
348 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
349 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
350 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
351 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
353 ioread8(priv->membase + PCH_UART_BRCSR));
355 lcr = ioread8(priv->membase + UART_LCR);
356 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
357 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
358 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
359 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
360 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
361 iowrite8(lcr, priv->membase + UART_LCR);
363 if (len > PCH_REGS_BUFSIZE)
364 len = PCH_REGS_BUFSIZE;
366 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
371 static const struct file_operations port_regs_ops = {
372 .owner = THIS_MODULE,
374 .read = port_show_regs,
375 .llseek = default_llseek,
377 #endif /* CONFIG_DEBUG_FS */
379 static struct dmi_system_id pch_uart_dmi_table[] = {
383 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
385 (void *)CMITC_UARTCLK,
390 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
392 (void *)FRI2_64_UARTCLK,
395 .ident = "Fish River Island II",
397 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
399 (void *)FRI2_48_UARTCLK,
404 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
406 (void *)NTC1_UARTCLK,
409 .ident = "nanoETXexpress-TT",
411 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
413 (void *)NTC1_UARTCLK,
416 .ident = "MinnowBoard",
418 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
420 (void *)MINNOW_UARTCLK,
425 /* Return UART clock, checking for board specific clocks. */
426 static unsigned int pch_uart_get_uartclk(void)
428 const struct dmi_system_id *d;
433 d = dmi_first_match(pch_uart_dmi_table);
435 return (unsigned long)d->driver_data;
437 return DEFAULT_UARTCLK;
440 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
443 u8 ier = ioread8(priv->membase + UART_IER);
444 ier |= flag & PCH_UART_IER_MASK;
445 iowrite8(ier, priv->membase + UART_IER);
448 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
451 u8 ier = ioread8(priv->membase + UART_IER);
452 ier &= ~(flag & PCH_UART_IER_MASK);
453 iowrite8(ier, priv->membase + UART_IER);
456 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
457 unsigned int parity, unsigned int bits,
460 unsigned int dll, dlm, lcr;
463 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
464 if (div < 0 || USHRT_MAX <= div) {
465 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
469 dll = (unsigned int)div & 0x00FFU;
470 dlm = ((unsigned int)div >> 8) & 0x00FFU;
472 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
473 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
477 if (bits & ~PCH_UART_LCR_WLS) {
478 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
482 if (stb & ~PCH_UART_LCR_STB) {
483 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
491 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
492 __func__, baud, div, lcr, jiffies);
493 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
494 iowrite8(dll, priv->membase + PCH_UART_DLL);
495 iowrite8(dlm, priv->membase + PCH_UART_DLM);
496 iowrite8(lcr, priv->membase + UART_LCR);
501 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
504 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
505 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
510 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
511 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
512 priv->membase + UART_FCR);
513 iowrite8(priv->fcr, priv->membase + UART_FCR);
518 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
519 unsigned int dmamode,
520 unsigned int fifo_size, unsigned int trigger)
524 if (dmamode & ~PCH_UART_FCR_DMS) {
525 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
530 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
531 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
532 __func__, fifo_size);
536 if (trigger & ~PCH_UART_FCR_RFTL) {
537 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
542 switch (priv->fifo_size) {
544 priv->trigger_level =
545 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
548 priv->trigger_level =
549 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
552 priv->trigger_level =
553 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
556 priv->trigger_level =
557 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
561 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
562 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
563 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
564 priv->membase + UART_FCR);
565 iowrite8(fcr, priv->membase + UART_FCR);
571 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
573 unsigned int msr = ioread8(priv->membase + UART_MSR);
574 priv->dmsr = msr & PCH_UART_MSR_DELTA;
578 static void pch_uart_hal_write(struct eg20t_port *priv,
579 const unsigned char *buf, int tx_size)
584 for (i = 0; i < tx_size;) {
586 iowrite8(thr, priv->membase + PCH_UART_THR);
590 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
595 struct uart_port *port = &priv->port;
597 lsr = ioread8(priv->membase + UART_LSR);
598 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
599 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
600 lsr = ioread8(priv->membase + UART_LSR)) {
601 rbr = ioread8(priv->membase + PCH_UART_RBR);
603 if (lsr & UART_LSR_BI) {
605 if (uart_handle_break(port))
610 if (uart_handle_sysrq_char(port, rbr))
620 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
622 return ioread8(priv->membase + UART_IIR) &\
623 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
626 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
628 return ioread8(priv->membase + UART_LSR);
631 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
635 lcr = ioread8(priv->membase + UART_LCR);
637 lcr |= PCH_UART_LCR_SB;
639 lcr &= ~PCH_UART_LCR_SB;
641 iowrite8(lcr, priv->membase + UART_LCR);
644 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
647 struct uart_port *port = &priv->port;
648 struct tty_port *tport = &port->state->port;
650 tty_insert_flip_string(tport, buf, size);
651 tty_flip_buffer_push(tport);
656 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
659 struct uart_port *port = &priv->port;
662 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
663 __func__, port->x_char, jiffies);
664 buf[0] = port->x_char;
672 static int dma_push_rx(struct eg20t_port *priv, int size)
675 struct uart_port *port = &priv->port;
676 struct tty_port *tport = &port->state->port;
678 room = tty_buffer_request_room(tport, size);
681 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
686 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
688 port->icount.rx += room;
693 static void pch_free_dma(struct uart_port *port)
695 struct eg20t_port *priv;
696 priv = container_of(port, struct eg20t_port, port);
699 dma_release_channel(priv->chan_tx);
700 priv->chan_tx = NULL;
703 dma_release_channel(priv->chan_rx);
704 priv->chan_rx = NULL;
707 if (priv->rx_buf_dma) {
708 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
710 priv->rx_buf_virt = NULL;
711 priv->rx_buf_dma = 0;
717 static bool filter(struct dma_chan *chan, void *slave)
719 struct pch_dma_slave *param = slave;
721 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
722 chan->device->dev)) {
723 chan->private = param;
730 static void pch_request_dma(struct uart_port *port)
733 struct dma_chan *chan;
734 struct pci_dev *dma_dev;
735 struct pch_dma_slave *param;
736 struct eg20t_port *priv =
737 container_of(port, struct eg20t_port, port);
739 dma_cap_set(DMA_SLAVE, mask);
741 /* Get DMA's dev information */
742 dma_dev = pci_get_slot(priv->pdev->bus,
743 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
746 param = &priv->param_tx;
747 param->dma_dev = &dma_dev->dev;
748 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
750 param->tx_reg = port->mapbase + UART_TX;
751 chan = dma_request_channel(mask, filter, param);
753 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
757 priv->chan_tx = chan;
760 param = &priv->param_rx;
761 param->dma_dev = &dma_dev->dev;
762 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
764 param->rx_reg = port->mapbase + UART_RX;
765 chan = dma_request_channel(mask, filter, param);
767 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
769 dma_release_channel(priv->chan_tx);
770 priv->chan_tx = NULL;
774 /* Get Consistent memory for DMA */
775 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
776 &priv->rx_buf_dma, GFP_KERNEL);
777 priv->chan_rx = chan;
780 static void pch_dma_rx_complete(void *arg)
782 struct eg20t_port *priv = arg;
783 struct uart_port *port = &priv->port;
786 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
787 count = dma_push_rx(priv, priv->trigger_level);
789 tty_flip_buffer_push(&port->state->port);
790 async_tx_ack(priv->desc_rx);
791 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
792 PCH_UART_HAL_RX_ERR_INT);
795 static void pch_dma_tx_complete(void *arg)
797 struct eg20t_port *priv = arg;
798 struct uart_port *port = &priv->port;
799 struct circ_buf *xmit = &port->state->xmit;
800 struct scatterlist *sg = priv->sg_tx_p;
803 for (i = 0; i < priv->nent; i++, sg++) {
804 xmit->tail += sg_dma_len(sg);
805 port->icount.tx += sg_dma_len(sg);
807 xmit->tail &= UART_XMIT_SIZE - 1;
808 async_tx_ack(priv->desc_tx);
809 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
810 priv->tx_dma_use = 0;
812 kfree(priv->sg_tx_p);
813 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
816 static int pop_tx(struct eg20t_port *priv, int size)
819 struct uart_port *port = &priv->port;
820 struct circ_buf *xmit = &port->state->xmit;
822 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
827 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
828 int sz = min(size - count, cnt_to_end);
829 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
830 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
832 } while (!uart_circ_empty(xmit) && count < size);
835 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
836 count, size - count, jiffies);
841 static int handle_rx_to(struct eg20t_port *priv)
843 struct pch_uart_buffer *buf;
846 if (!priv->start_rx) {
847 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
848 PCH_UART_HAL_RX_ERR_INT);
853 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
854 ret = push_rx(priv, buf->buf, rx_size);
857 } while (rx_size == buf->size);
859 return PCH_UART_HANDLED_RX_INT;
862 static int handle_rx(struct eg20t_port *priv)
864 return handle_rx_to(priv);
867 static int dma_handle_rx(struct eg20t_port *priv)
869 struct uart_port *port = &priv->port;
870 struct dma_async_tx_descriptor *desc;
871 struct scatterlist *sg;
873 priv = container_of(port, struct eg20t_port, port);
876 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
878 sg_dma_len(sg) = priv->trigger_level;
880 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
881 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
884 sg_dma_address(sg) = priv->rx_buf_dma;
886 desc = dmaengine_prep_slave_sg(priv->chan_rx,
887 sg, 1, DMA_DEV_TO_MEM,
888 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
893 priv->desc_rx = desc;
894 desc->callback = pch_dma_rx_complete;
895 desc->callback_param = priv;
896 desc->tx_submit(desc);
897 dma_async_issue_pending(priv->chan_rx);
899 return PCH_UART_HANDLED_RX_INT;
902 static unsigned int handle_tx(struct eg20t_port *priv)
904 struct uart_port *port = &priv->port;
905 struct circ_buf *xmit = &port->state->xmit;
911 if (!priv->start_tx) {
912 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
914 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
919 fifo_size = max(priv->fifo_size, 1);
921 if (pop_tx_x(priv, xmit->buf)) {
922 pch_uart_hal_write(priv, xmit->buf, 1);
927 size = min(xmit->head - xmit->tail, fifo_size);
931 tx_size = pop_tx(priv, size);
933 port->icount.tx += tx_size;
937 priv->tx_empty = tx_empty;
940 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
941 uart_write_wakeup(port);
944 return PCH_UART_HANDLED_TX_INT;
947 static unsigned int dma_handle_tx(struct eg20t_port *priv)
949 struct uart_port *port = &priv->port;
950 struct circ_buf *xmit = &port->state->xmit;
951 struct scatterlist *sg;
955 struct dma_async_tx_descriptor *desc;
962 if (!priv->start_tx) {
963 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
965 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
970 if (priv->tx_dma_use) {
971 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
973 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
978 fifo_size = max(priv->fifo_size, 1);
980 if (pop_tx_x(priv, xmit->buf)) {
981 pch_uart_hal_write(priv, xmit->buf, 1);
987 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
988 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
989 xmit->tail, UART_XMIT_SIZE));
991 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
992 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
993 uart_write_wakeup(port);
997 if (bytes > fifo_size) {
998 num = bytes / fifo_size + 1;
1000 rem = bytes % fifo_size;
1007 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1008 __func__, num, size, rem);
1010 priv->tx_dma_use = 1;
1012 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1013 if (!priv->sg_tx_p) {
1014 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1018 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1021 for (i = 0; i < num; i++, sg++) {
1023 sg_set_page(sg, virt_to_page(xmit->buf),
1024 rem, fifo_size * i);
1026 sg_set_page(sg, virt_to_page(xmit->buf),
1027 size, fifo_size * i);
1031 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1033 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1038 for (i = 0; i < nent; i++, sg++) {
1039 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1041 sg_dma_address(sg) = (sg_dma_address(sg) &
1042 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1043 if (i == (nent - 1))
1044 sg_dma_len(sg) = rem;
1046 sg_dma_len(sg) = size;
1049 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1050 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1051 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1053 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1057 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1058 priv->desc_tx = desc;
1059 desc->callback = pch_dma_tx_complete;
1060 desc->callback_param = priv;
1062 desc->tx_submit(desc);
1064 dma_async_issue_pending(priv->chan_tx);
1066 return PCH_UART_HANDLED_TX_INT;
1069 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1071 struct uart_port *port = &priv->port;
1072 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1073 char *error_msg[5] = {};
1076 if (lsr & PCH_UART_LSR_ERR)
1077 error_msg[i++] = "Error data in FIFO\n";
1079 if (lsr & UART_LSR_FE) {
1080 port->icount.frame++;
1081 error_msg[i++] = " Framing Error\n";
1084 if (lsr & UART_LSR_PE) {
1085 port->icount.parity++;
1086 error_msg[i++] = " Parity Error\n";
1089 if (lsr & UART_LSR_OE) {
1090 port->icount.overrun++;
1091 error_msg[i++] = " Overrun Error\n";
1095 for (i = 0; error_msg[i] != NULL; i++)
1096 dev_err(&priv->pdev->dev, error_msg[i]);
1102 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1104 struct eg20t_port *priv = dev_id;
1105 unsigned int handled;
1109 unsigned long flags;
1113 spin_lock_irqsave(&priv->lock, flags);
1116 iid = pch_uart_hal_get_iid(priv);
1117 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1120 case PCH_UART_IID_RLS: /* Receiver Line Status */
1121 lsr = pch_uart_hal_get_line_status(priv);
1122 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1123 UART_LSR_PE | UART_LSR_OE)) {
1124 pch_uart_err_ir(priv, lsr);
1125 ret = PCH_UART_HANDLED_RX_ERR_INT;
1127 ret = PCH_UART_HANDLED_LS_INT;
1130 case PCH_UART_IID_RDR: /* Received Data Ready */
1131 if (priv->use_dma) {
1132 pch_uart_hal_disable_interrupt(priv,
1133 PCH_UART_HAL_RX_INT |
1134 PCH_UART_HAL_RX_ERR_INT);
1135 ret = dma_handle_rx(priv);
1137 pch_uart_hal_enable_interrupt(priv,
1138 PCH_UART_HAL_RX_INT |
1139 PCH_UART_HAL_RX_ERR_INT);
1141 ret = handle_rx(priv);
1144 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1146 ret = handle_rx_to(priv);
1148 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1151 ret = dma_handle_tx(priv);
1153 ret = handle_tx(priv);
1155 case PCH_UART_IID_MS: /* Modem Status */
1156 msr = pch_uart_hal_get_modem(priv);
1157 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1158 means final interrupt */
1159 if ((msr & UART_MSR_ANY_DELTA) == 0)
1161 ret |= PCH_UART_HANDLED_MS_INT;
1163 default: /* Never junp to this label */
1164 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1170 handled |= (unsigned int)ret;
1173 spin_unlock_irqrestore(&priv->lock, flags);
1174 return IRQ_RETVAL(handled);
1177 /* This function tests whether the transmitter fifo and shifter for the port
1178 described by 'port' is empty. */
1179 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1181 struct eg20t_port *priv;
1183 priv = container_of(port, struct eg20t_port, port);
1185 return TIOCSER_TEMT;
1190 /* Returns the current state of modem control inputs. */
1191 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1193 struct eg20t_port *priv;
1195 unsigned int ret = 0;
1197 priv = container_of(port, struct eg20t_port, port);
1198 modem = pch_uart_hal_get_modem(priv);
1200 if (modem & UART_MSR_DCD)
1203 if (modem & UART_MSR_RI)
1206 if (modem & UART_MSR_DSR)
1209 if (modem & UART_MSR_CTS)
1215 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1218 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1220 if (mctrl & TIOCM_DTR)
1221 mcr |= UART_MCR_DTR;
1222 if (mctrl & TIOCM_RTS)
1223 mcr |= UART_MCR_RTS;
1224 if (mctrl & TIOCM_LOOP)
1225 mcr |= UART_MCR_LOOP;
1227 if (priv->mcr & UART_MCR_AFE)
1228 mcr |= UART_MCR_AFE;
1231 iowrite8(mcr, priv->membase + UART_MCR);
1234 static void pch_uart_stop_tx(struct uart_port *port)
1236 struct eg20t_port *priv;
1237 priv = container_of(port, struct eg20t_port, port);
1239 priv->tx_dma_use = 0;
1242 static void pch_uart_start_tx(struct uart_port *port)
1244 struct eg20t_port *priv;
1246 priv = container_of(port, struct eg20t_port, port);
1248 if (priv->use_dma) {
1249 if (priv->tx_dma_use) {
1250 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1257 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1260 static void pch_uart_stop_rx(struct uart_port *port)
1262 struct eg20t_port *priv;
1263 priv = container_of(port, struct eg20t_port, port);
1265 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1266 PCH_UART_HAL_RX_ERR_INT);
1269 /* Enable the modem status interrupts. */
1270 static void pch_uart_enable_ms(struct uart_port *port)
1272 struct eg20t_port *priv;
1273 priv = container_of(port, struct eg20t_port, port);
1274 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1277 /* Control the transmission of a break signal. */
1278 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1280 struct eg20t_port *priv;
1281 unsigned long flags;
1283 priv = container_of(port, struct eg20t_port, port);
1284 spin_lock_irqsave(&priv->lock, flags);
1285 pch_uart_hal_set_break(priv, ctl);
1286 spin_unlock_irqrestore(&priv->lock, flags);
1289 /* Grab any interrupt resources and initialise any low level driver state. */
1290 static int pch_uart_startup(struct uart_port *port)
1292 struct eg20t_port *priv;
1297 priv = container_of(port, struct eg20t_port, port);
1301 priv->uartclk = port->uartclk;
1303 port->uartclk = priv->uartclk;
1305 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1306 ret = pch_uart_hal_set_line(priv, default_baud,
1307 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1312 switch (priv->fifo_size) {
1314 fifo_size = PCH_UART_HAL_FIFO256;
1317 fifo_size = PCH_UART_HAL_FIFO64;
1320 fifo_size = PCH_UART_HAL_FIFO16;
1324 fifo_size = PCH_UART_HAL_FIFO_DIS;
1328 switch (priv->trigger) {
1329 case PCH_UART_HAL_TRIGGER1:
1332 case PCH_UART_HAL_TRIGGER_L:
1333 trigger_level = priv->fifo_size / 4;
1335 case PCH_UART_HAL_TRIGGER_M:
1336 trigger_level = priv->fifo_size / 2;
1338 case PCH_UART_HAL_TRIGGER_H:
1340 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1344 priv->trigger_level = trigger_level;
1345 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1346 fifo_size, priv->trigger);
1350 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1351 priv->irq_name, priv);
1356 pch_request_dma(port);
1359 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1360 PCH_UART_HAL_RX_ERR_INT);
1361 uart_update_timeout(port, CS8, default_baud);
1366 static void pch_uart_shutdown(struct uart_port *port)
1368 struct eg20t_port *priv;
1371 priv = container_of(port, struct eg20t_port, port);
1372 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1373 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1374 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1375 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1377 dev_err(priv->port.dev,
1378 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1382 free_irq(priv->port.irq, priv);
1385 /* Change the port parameters, including word length, parity, stop
1386 *bits. Update read_status_mask and ignore_status_mask to indicate
1387 *the types of events we are interested in receiving. */
1388 static void pch_uart_set_termios(struct uart_port *port,
1389 struct ktermios *termios, struct ktermios *old)
1392 unsigned int baud, parity, bits, stb;
1393 struct eg20t_port *priv;
1394 unsigned long flags;
1396 priv = container_of(port, struct eg20t_port, port);
1397 switch (termios->c_cflag & CSIZE) {
1399 bits = PCH_UART_HAL_5BIT;
1402 bits = PCH_UART_HAL_6BIT;
1405 bits = PCH_UART_HAL_7BIT;
1408 bits = PCH_UART_HAL_8BIT;
1411 if (termios->c_cflag & CSTOPB)
1412 stb = PCH_UART_HAL_STB2;
1414 stb = PCH_UART_HAL_STB1;
1416 if (termios->c_cflag & PARENB) {
1417 if (termios->c_cflag & PARODD)
1418 parity = PCH_UART_HAL_PARITY_ODD;
1420 parity = PCH_UART_HAL_PARITY_EVEN;
1423 parity = PCH_UART_HAL_PARITY_NONE;
1425 /* Only UART0 has auto hardware flow function */
1426 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1427 priv->mcr |= UART_MCR_AFE;
1429 priv->mcr &= ~UART_MCR_AFE;
1431 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1433 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1435 spin_lock_irqsave(&priv->lock, flags);
1436 spin_lock(&port->lock);
1438 uart_update_timeout(port, termios->c_cflag, baud);
1439 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1443 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1444 /* Don't rewrite B0 */
1445 if (tty_termios_baud_rate(termios))
1446 tty_termios_encode_baud_rate(termios, baud, baud);
1449 spin_unlock(&port->lock);
1450 spin_unlock_irqrestore(&priv->lock, flags);
1453 static const char *pch_uart_type(struct uart_port *port)
1455 return KBUILD_MODNAME;
1458 static void pch_uart_release_port(struct uart_port *port)
1460 struct eg20t_port *priv;
1462 priv = container_of(port, struct eg20t_port, port);
1463 pci_iounmap(priv->pdev, priv->membase);
1464 pci_release_regions(priv->pdev);
1467 static int pch_uart_request_port(struct uart_port *port)
1469 struct eg20t_port *priv;
1471 void __iomem *membase;
1473 priv = container_of(port, struct eg20t_port, port);
1474 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1478 membase = pci_iomap(priv->pdev, 1, 0);
1480 pci_release_regions(priv->pdev);
1483 priv->membase = port->membase = membase;
1488 static void pch_uart_config_port(struct uart_port *port, int type)
1490 struct eg20t_port *priv;
1492 priv = container_of(port, struct eg20t_port, port);
1493 if (type & UART_CONFIG_TYPE) {
1494 port->type = priv->port_type;
1495 pch_uart_request_port(port);
1499 static int pch_uart_verify_port(struct uart_port *port,
1500 struct serial_struct *serinfo)
1502 struct eg20t_port *priv;
1504 priv = container_of(port, struct eg20t_port, port);
1505 if (serinfo->flags & UPF_LOW_LATENCY) {
1506 dev_info(priv->port.dev,
1507 "PCH UART : Use PIO Mode (without DMA)\n");
1509 serinfo->flags &= ~UPF_LOW_LATENCY;
1511 #ifndef CONFIG_PCH_DMA
1512 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1516 if (!priv->use_dma) {
1517 pch_request_dma(port);
1521 dev_info(priv->port.dev, "PCH UART: %s\n",
1523 "Use DMA Mode" : "No DMA");
1529 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1531 * Wait for transmitter & holding register to empty
1533 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1535 unsigned int status, tmout = 10000;
1537 /* Wait up to 10ms for the character(s) to be sent. */
1539 status = ioread8(up->membase + UART_LSR);
1541 if ((status & bits) == bits)
1548 /* Wait up to 1s for flow control if necessary */
1549 if (up->port.flags & UPF_CONS_FLOW) {
1551 for (tmout = 1000000; tmout; tmout--) {
1552 unsigned int msr = ioread8(up->membase + UART_MSR);
1553 if (msr & UART_MSR_CTS)
1556 touch_nmi_watchdog();
1560 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1562 #ifdef CONFIG_CONSOLE_POLL
1564 * Console polling routines for communicate via uart while
1565 * in an interrupt or debug context.
1567 static int pch_uart_get_poll_char(struct uart_port *port)
1569 struct eg20t_port *priv =
1570 container_of(port, struct eg20t_port, port);
1571 u8 lsr = ioread8(priv->membase + UART_LSR);
1573 if (!(lsr & UART_LSR_DR))
1574 return NO_POLL_CHAR;
1576 return ioread8(priv->membase + PCH_UART_RBR);
1580 static void pch_uart_put_poll_char(struct uart_port *port,
1584 struct eg20t_port *priv =
1585 container_of(port, struct eg20t_port, port);
1588 * First save the IER then disable the interrupts
1590 ier = ioread8(priv->membase + UART_IER);
1591 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1593 wait_for_xmitr(priv, UART_LSR_THRE);
1595 * Send the character out.
1597 iowrite8(c, priv->membase + PCH_UART_THR);
1600 * Finally, wait for transmitter to become empty
1601 * and restore the IER
1603 wait_for_xmitr(priv, BOTH_EMPTY);
1604 iowrite8(ier, priv->membase + UART_IER);
1606 #endif /* CONFIG_CONSOLE_POLL */
1608 static const struct uart_ops pch_uart_ops = {
1609 .tx_empty = pch_uart_tx_empty,
1610 .set_mctrl = pch_uart_set_mctrl,
1611 .get_mctrl = pch_uart_get_mctrl,
1612 .stop_tx = pch_uart_stop_tx,
1613 .start_tx = pch_uart_start_tx,
1614 .stop_rx = pch_uart_stop_rx,
1615 .enable_ms = pch_uart_enable_ms,
1616 .break_ctl = pch_uart_break_ctl,
1617 .startup = pch_uart_startup,
1618 .shutdown = pch_uart_shutdown,
1619 .set_termios = pch_uart_set_termios,
1620 /* .pm = pch_uart_pm, Not supported yet */
1621 .type = pch_uart_type,
1622 .release_port = pch_uart_release_port,
1623 .request_port = pch_uart_request_port,
1624 .config_port = pch_uart_config_port,
1625 .verify_port = pch_uart_verify_port,
1626 #ifdef CONFIG_CONSOLE_POLL
1627 .poll_get_char = pch_uart_get_poll_char,
1628 .poll_put_char = pch_uart_put_poll_char,
1632 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1634 static void pch_console_putchar(struct uart_port *port, int ch)
1636 struct eg20t_port *priv =
1637 container_of(port, struct eg20t_port, port);
1639 wait_for_xmitr(priv, UART_LSR_THRE);
1640 iowrite8(ch, priv->membase + PCH_UART_THR);
1644 * Print a string to the serial port trying not to disturb
1645 * any possible real use of the port...
1647 * The console_lock must be held when we get here.
1650 pch_console_write(struct console *co, const char *s, unsigned int count)
1652 struct eg20t_port *priv;
1653 unsigned long flags;
1654 int priv_locked = 1;
1655 int port_locked = 1;
1658 priv = pch_uart_ports[co->index];
1660 touch_nmi_watchdog();
1662 local_irq_save(flags);
1663 if (priv->port.sysrq) {
1664 /* call to uart_handle_sysrq_char already took the priv lock */
1666 /* serial8250_handle_port() already took the port lock */
1668 } else if (oops_in_progress) {
1669 priv_locked = spin_trylock(&priv->lock);
1670 port_locked = spin_trylock(&priv->port.lock);
1672 spin_lock(&priv->lock);
1673 spin_lock(&priv->port.lock);
1677 * First save the IER then disable the interrupts
1679 ier = ioread8(priv->membase + UART_IER);
1681 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1683 uart_console_write(&priv->port, s, count, pch_console_putchar);
1686 * Finally, wait for transmitter to become empty
1687 * and restore the IER
1689 wait_for_xmitr(priv, BOTH_EMPTY);
1690 iowrite8(ier, priv->membase + UART_IER);
1693 spin_unlock(&priv->port.lock);
1695 spin_unlock(&priv->lock);
1696 local_irq_restore(flags);
1699 static int __init pch_console_setup(struct console *co, char *options)
1701 struct uart_port *port;
1702 int baud = default_baud;
1708 * Check whether an invalid uart number has been specified, and
1709 * if so, search for the first available port that does have
1712 if (co->index >= PCH_UART_NR)
1714 port = &pch_uart_ports[co->index]->port;
1716 if (!port || (!port->iobase && !port->membase))
1719 port->uartclk = pch_uart_get_uartclk();
1722 uart_parse_options(options, &baud, &parity, &bits, &flow);
1724 return uart_set_options(port, co, baud, parity, bits, flow);
1727 static struct uart_driver pch_uart_driver;
1729 static struct console pch_console = {
1730 .name = PCH_UART_DRIVER_DEVICE,
1731 .write = pch_console_write,
1732 .device = uart_console_device,
1733 .setup = pch_console_setup,
1734 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1736 .data = &pch_uart_driver,
1739 #define PCH_CONSOLE (&pch_console)
1741 #define PCH_CONSOLE NULL
1742 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1744 static struct uart_driver pch_uart_driver = {
1745 .owner = THIS_MODULE,
1746 .driver_name = KBUILD_MODNAME,
1747 .dev_name = PCH_UART_DRIVER_DEVICE,
1751 .cons = PCH_CONSOLE,
1754 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1755 const struct pci_device_id *id)
1757 struct eg20t_port *priv;
1759 unsigned int iobase;
1760 unsigned int mapbase;
1761 unsigned char *rxbuf;
1764 struct pch_uart_driver_data *board;
1765 #ifdef CONFIG_DEBUG_FS
1766 char name[32]; /* for debugfs file name */
1769 board = &drv_dat[id->driver_data];
1770 port_type = board->port_type;
1772 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1774 goto init_port_alloc_err;
1776 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1778 goto init_port_free_txbuf;
1780 switch (port_type) {
1782 fifosize = 256; /* EG20T/ML7213: UART0 */
1785 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1788 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1789 goto init_port_hal_free;
1792 pci_enable_msi(pdev);
1793 pci_set_master(pdev);
1795 spin_lock_init(&priv->lock);
1797 iobase = pci_resource_start(pdev, 0);
1798 mapbase = pci_resource_start(pdev, 1);
1799 priv->mapbase = mapbase;
1800 priv->iobase = iobase;
1803 priv->rxbuf.buf = rxbuf;
1804 priv->rxbuf.size = PAGE_SIZE;
1806 priv->fifo_size = fifosize;
1807 priv->uartclk = pch_uart_get_uartclk();
1808 priv->port_type = PORT_MAX_8250 + port_type + 1;
1809 priv->port.dev = &pdev->dev;
1810 priv->port.iobase = iobase;
1811 priv->port.membase = NULL;
1812 priv->port.mapbase = mapbase;
1813 priv->port.irq = pdev->irq;
1814 priv->port.iotype = UPIO_PORT;
1815 priv->port.ops = &pch_uart_ops;
1816 priv->port.flags = UPF_BOOT_AUTOCONF;
1817 priv->port.fifosize = fifosize;
1818 priv->port.line = board->line_no;
1819 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1821 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1822 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1825 spin_lock_init(&priv->port.lock);
1827 pci_set_drvdata(pdev, priv);
1828 priv->trigger_level = 1;
1831 if (pdev->dev.of_node)
1832 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1835 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1836 pch_uart_ports[board->line_no] = priv;
1838 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1840 goto init_port_hal_free;
1842 #ifdef CONFIG_DEBUG_FS
1843 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1844 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1845 NULL, priv, &port_regs_ops);
1851 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1852 pch_uart_ports[board->line_no] = NULL;
1854 free_page((unsigned long)rxbuf);
1855 init_port_free_txbuf:
1857 init_port_alloc_err:
1862 static void pch_uart_exit_port(struct eg20t_port *priv)
1865 #ifdef CONFIG_DEBUG_FS
1867 debugfs_remove(priv->debugfs);
1869 uart_remove_one_port(&pch_uart_driver, &priv->port);
1870 free_page((unsigned long)priv->rxbuf.buf);
1873 static void pch_uart_pci_remove(struct pci_dev *pdev)
1875 struct eg20t_port *priv = pci_get_drvdata(pdev);
1877 pci_disable_msi(pdev);
1879 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1880 pch_uart_ports[priv->port.line] = NULL;
1882 pch_uart_exit_port(priv);
1883 pci_disable_device(pdev);
1888 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1890 struct eg20t_port *priv = pci_get_drvdata(pdev);
1892 uart_suspend_port(&pch_uart_driver, &priv->port);
1894 pci_save_state(pdev);
1895 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1899 static int pch_uart_pci_resume(struct pci_dev *pdev)
1901 struct eg20t_port *priv = pci_get_drvdata(pdev);
1904 pci_set_power_state(pdev, PCI_D0);
1905 pci_restore_state(pdev);
1907 ret = pci_enable_device(pdev);
1910 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1914 uart_resume_port(&pch_uart_driver, &priv->port);
1919 #define pch_uart_pci_suspend NULL
1920 #define pch_uart_pci_resume NULL
1923 static const struct pci_device_id pch_uart_pci_id[] = {
1924 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1925 .driver_data = pch_et20t_uart0},
1926 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1927 .driver_data = pch_et20t_uart1},
1928 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1929 .driver_data = pch_et20t_uart2},
1930 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1931 .driver_data = pch_et20t_uart3},
1932 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1933 .driver_data = pch_ml7213_uart0},
1934 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1935 .driver_data = pch_ml7213_uart1},
1936 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1937 .driver_data = pch_ml7213_uart2},
1938 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1939 .driver_data = pch_ml7223_uart0},
1940 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1941 .driver_data = pch_ml7223_uart1},
1942 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1943 .driver_data = pch_ml7831_uart0},
1944 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1945 .driver_data = pch_ml7831_uart1},
1949 static int pch_uart_pci_probe(struct pci_dev *pdev,
1950 const struct pci_device_id *id)
1953 struct eg20t_port *priv;
1955 ret = pci_enable_device(pdev);
1959 priv = pch_uart_init_port(pdev, id);
1962 goto probe_disable_device;
1964 pci_set_drvdata(pdev, priv);
1968 probe_disable_device:
1969 pci_disable_msi(pdev);
1970 pci_disable_device(pdev);
1975 static struct pci_driver pch_uart_pci_driver = {
1977 .id_table = pch_uart_pci_id,
1978 .probe = pch_uart_pci_probe,
1979 .remove = pch_uart_pci_remove,
1980 .suspend = pch_uart_pci_suspend,
1981 .resume = pch_uart_pci_resume,
1984 static int __init pch_uart_module_init(void)
1988 /* register as UART driver */
1989 ret = uart_register_driver(&pch_uart_driver);
1993 /* register as PCI driver */
1994 ret = pci_register_driver(&pch_uart_pci_driver);
1996 uart_unregister_driver(&pch_uart_driver);
2000 module_init(pch_uart_module_init);
2002 static void __exit pch_uart_module_exit(void)
2004 pci_unregister_driver(&pch_uart_pci_driver);
2005 uart_unregister_driver(&pch_uart_driver);
2007 module_exit(pch_uart_module_exit);
2009 MODULE_LICENSE("GPL v2");
2010 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2011 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2013 module_param(default_baud, uint, S_IRUGO);
2014 MODULE_PARM_DESC(default_baud,
2015 "Default BAUD for initial driver state and console (default 9600)");
2016 module_param(user_uartclk, uint, S_IRUGO);
2017 MODULE_PARM_DESC(user_uartclk,
2018 "Override UART default or board specific UART clock");