2 * Driver for PowerMac Z85c30 based ESCC cell found in the
3 * "macio" ASICs of various PowerMac models
5 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
8 * and drivers/serial/sunzilog.c by David S. Miller
10 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
11 * adapted special tweaks needed for us. I don't think it's worth
12 * merging back those though. The DMA code still has to get in
13 * and once done, I expect that driver to remain fairly stable in
14 * the long term, unless we change the driver model again...
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
31 * - Enable BREAK interrupt
32 * - Add support for sysreq
34 * TODO: - Add DMA support
35 * - Defer port shutdown to a few seconds after close
36 * - maybe put something right into uap->clk_divisor
41 #undef USE_CTRL_O_SYSRQ
43 #include <linux/module.h>
44 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
51 #include <linux/kernel.h>
52 #include <linux/delay.h>
53 #include <linux/init.h>
54 #include <linux/console.h>
55 #include <linux/adb.h>
56 #include <linux/pmu.h>
57 #include <linux/bitops.h>
58 #include <linux/sysrq.h>
59 #include <linux/mutex.h>
60 #include <asm/sections.h>
64 #ifdef CONFIG_PPC_PMAC
66 #include <asm/machdep.h>
67 #include <asm/pmac_feature.h>
68 #include <asm/dbdma.h>
69 #include <asm/macio.h>
71 #include <linux/platform_device.h>
72 #define of_machine_is_compatible(x) (0)
75 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
79 #include <linux/serial.h>
80 #include <linux/serial_core.h>
82 #include "pmac_zilog.h"
84 /* Not yet implemented */
87 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
88 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
89 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
90 MODULE_LICENSE("GPL");
92 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS
93 #define PMACZILOG_MAJOR TTY_MAJOR
94 #define PMACZILOG_MINOR 64
95 #define PMACZILOG_NAME "ttyS"
97 #define PMACZILOG_MAJOR 204
98 #define PMACZILOG_MINOR 192
99 #define PMACZILOG_NAME "ttyPZ"
104 * For the sake of early serial console, we can do a pre-probe
105 * (optional) of the ports at rather early boot time.
107 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
108 static int pmz_ports_count;
109 static DEFINE_MUTEX(pmz_irq_mutex);
111 static struct uart_driver pmz_uart_reg = {
112 .owner = THIS_MODULE,
113 .driver_name = PMACZILOG_NAME,
114 .dev_name = PMACZILOG_NAME,
115 .major = PMACZILOG_MAJOR,
116 .minor = PMACZILOG_MINOR,
121 * Load all registers to reprogram the port
122 * This function must only be called when the TX is not busy. The UART
123 * port lock must be held and local interrupts disabled.
125 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
129 if (ZS_IS_ASLEEP(uap))
132 /* Let pending transmits finish. */
133 for (i = 0; i < 1000; i++) {
134 unsigned char stat = read_zsreg(uap, R1);
146 /* Disable all interrupts. */
148 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
150 /* Set parity, sync config, stop bits, and clock divisor. */
151 write_zsreg(uap, R4, regs[R4]);
153 /* Set misc. TX/RX control bits. */
154 write_zsreg(uap, R10, regs[R10]);
156 /* Set TX/RX controls sans the enable bits. */
157 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
158 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
160 /* now set R7 "prime" on ESCC */
161 write_zsreg(uap, R15, regs[R15] | EN85C30);
162 write_zsreg(uap, R7, regs[R7P]);
164 /* make sure we use R7 "non-prime" on ESCC */
165 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
167 /* Synchronous mode config. */
168 write_zsreg(uap, R6, regs[R6]);
169 write_zsreg(uap, R7, regs[R7]);
171 /* Disable baud generator. */
172 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
174 /* Clock mode control. */
175 write_zsreg(uap, R11, regs[R11]);
177 /* Lower and upper byte of baud rate generator divisor. */
178 write_zsreg(uap, R12, regs[R12]);
179 write_zsreg(uap, R13, regs[R13]);
181 /* Now rewrite R14, with BRENAB (if set). */
182 write_zsreg(uap, R14, regs[R14]);
184 /* Reset external status interrupts. */
185 write_zsreg(uap, R0, RES_EXT_INT);
186 write_zsreg(uap, R0, RES_EXT_INT);
188 /* Rewrite R3/R5, this time without enables masked. */
189 write_zsreg(uap, R3, regs[R3]);
190 write_zsreg(uap, R5, regs[R5]);
192 /* Rewrite R1, this time without IRQ enabled masked. */
193 write_zsreg(uap, R1, regs[R1]);
195 /* Enable interrupts */
196 write_zsreg(uap, R9, regs[R9]);
200 * We do like sunzilog to avoid disrupting pending Tx
201 * Reprogram the Zilog channel HW registers with the copies found in the
202 * software state struct. If the transmitter is busy, we defer this update
203 * until the next TX complete interrupt. Else, we do it right now.
205 * The UART port lock must be held and local interrupts disabled.
207 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
209 if (!ZS_REGS_HELD(uap)) {
210 if (ZS_TX_ACTIVE(uap)) {
211 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
213 pmz_debug("pmz: maybe_update_regs: updating\n");
214 pmz_load_zsregs(uap, uap->curregs);
219 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
222 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
223 if (!ZS_IS_EXTCLK(uap))
224 uap->curregs[1] |= EXT_INT_ENAB;
226 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
228 write_zsreg(uap, R1, uap->curregs[1]);
231 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
233 struct tty_struct *tty = NULL;
234 unsigned char ch, r1, drop, error, flag;
237 /* The interrupt can be enabled when the port isn't open, typically
238 * that happens when using one port is open and the other closed (stale
239 * interrupt) or when one port is used as a console.
241 if (!ZS_IS_OPEN(uap)) {
242 pmz_debug("pmz: draining input\n");
243 /* Port is closed, drain input data */
245 if ((++loops) > 1000)
247 (void)read_zsreg(uap, R1);
248 write_zsreg(uap, R0, ERR_RES);
249 (void)read_zsdata(uap);
250 ch = read_zsreg(uap, R0);
251 if (!(ch & Rx_CH_AV))
257 /* Sanity check, make sure the old bug is no longer happening */
258 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
260 (void)read_zsdata(uap);
263 tty = uap->port.state->port.tty;
269 r1 = read_zsreg(uap, R1);
270 ch = read_zsdata(uap);
272 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
273 write_zsreg(uap, R0, ERR_RES);
277 ch &= uap->parity_mask;
278 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
279 uap->flags &= ~PMACZILOG_FLAG_BREAK;
282 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
283 #ifdef USE_CTRL_O_SYSRQ
284 /* Handle the SysRq ^O Hack */
286 uap->port.sysrq = jiffies + HZ*5;
289 #endif /* USE_CTRL_O_SYSRQ */
290 if (uap->port.sysrq) {
292 spin_unlock(&uap->port.lock);
293 swallow = uart_handle_sysrq_char(&uap->port, ch);
294 spin_lock(&uap->port.lock);
298 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
300 /* A real serial line, record the character and status. */
305 uap->port.icount.rx++;
307 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
310 pmz_debug("pmz: got break !\n");
311 r1 &= ~(PAR_ERR | CRC_ERR);
312 uap->port.icount.brk++;
313 if (uart_handle_break(&uap->port))
316 else if (r1 & PAR_ERR)
317 uap->port.icount.parity++;
318 else if (r1 & CRC_ERR)
319 uap->port.icount.frame++;
321 uap->port.icount.overrun++;
322 r1 &= uap->port.read_status_mask;
325 else if (r1 & PAR_ERR)
327 else if (r1 & CRC_ERR)
331 if (uap->port.ignore_status_mask == 0xff ||
332 (r1 & uap->port.ignore_status_mask) == 0) {
333 tty_insert_flip_char(tty, ch, flag);
336 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
338 /* We can get stuck in an infinite loop getting char 0 when the
339 * line is in a wrong HW state, we break that here.
340 * When that happens, I disable the receive side of the driver.
341 * Note that what I've been experiencing is a real irq loop where
342 * I'm getting flooded regardless of the actual port speed.
343 * Something strange is going on with the HW
345 if ((++loops) > 1000)
347 ch = read_zsreg(uap, R0);
348 if (!(ch & Rx_CH_AV))
354 pmz_interrupt_control(uap, 0);
355 pmz_error("pmz: rx irq flood !\n");
359 static void pmz_status_handle(struct uart_pmac_port *uap)
361 unsigned char status;
363 status = read_zsreg(uap, R0);
364 write_zsreg(uap, R0, RES_EXT_INT);
367 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
368 if (status & SYNC_HUNT)
369 uap->port.icount.dsr++;
371 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
372 * But it does not tell us which bit has changed, we have to keep
373 * track of this ourselves.
374 * The CTS input is inverted for some reason. -- paulus
376 if ((status ^ uap->prev_status) & DCD)
377 uart_handle_dcd_change(&uap->port,
379 if ((status ^ uap->prev_status) & CTS)
380 uart_handle_cts_change(&uap->port,
383 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
386 if (status & BRK_ABRT)
387 uap->flags |= PMACZILOG_FLAG_BREAK;
389 uap->prev_status = status;
392 static void pmz_transmit_chars(struct uart_pmac_port *uap)
394 struct circ_buf *xmit;
396 if (ZS_IS_ASLEEP(uap))
398 if (ZS_IS_CONS(uap)) {
399 unsigned char status = read_zsreg(uap, R0);
401 /* TX still busy? Just wait for the next TX done interrupt.
403 * It can occur because of how we do serial console writes. It would
404 * be nice to transmit console writes just like we normally would for
405 * a TTY line. (ie. buffered and TX interrupt driven). That is not
406 * easy because console writes cannot sleep. One solution might be
407 * to poll on enough port->xmit space becoming free. -DaveM
409 if (!(status & Tx_BUF_EMP))
413 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
415 if (ZS_REGS_HELD(uap)) {
416 pmz_load_zsregs(uap, uap->curregs);
417 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
420 if (ZS_TX_STOPPED(uap)) {
421 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
425 /* Under some circumstances, we see interrupts reported for
426 * a closed channel. The interrupt mask in R1 is clear, but
427 * R3 still signals the interrupts and we see them when taking
428 * an interrupt for the other channel (this could be a qemu
429 * bug but since the ESCC doc doesn't specify precsiely whether
430 * R3 interrup status bits are masked by R1 interrupt enable
431 * bits, better safe than sorry). --BenH.
433 if (!ZS_IS_OPEN(uap))
436 if (uap->port.x_char) {
437 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
438 write_zsdata(uap, uap->port.x_char);
440 uap->port.icount.tx++;
441 uap->port.x_char = 0;
445 if (uap->port.state == NULL)
447 xmit = &uap->port.state->xmit;
448 if (uart_circ_empty(xmit)) {
449 uart_write_wakeup(&uap->port);
452 if (uart_tx_stopped(&uap->port))
455 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
456 write_zsdata(uap, xmit->buf[xmit->tail]);
459 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
460 uap->port.icount.tx++;
462 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
463 uart_write_wakeup(&uap->port);
468 write_zsreg(uap, R0, RES_Tx_P);
472 /* Hrm... we register that twice, fixme later.... */
473 static irqreturn_t pmz_interrupt(int irq, void *dev_id)
475 struct uart_pmac_port *uap = dev_id;
476 struct uart_pmac_port *uap_a;
477 struct uart_pmac_port *uap_b;
479 struct tty_struct *tty;
482 uap_a = pmz_get_port_A(uap);
485 spin_lock(&uap_a->port.lock);
486 r3 = read_zsreg(uap_a, R3);
489 pmz_debug("irq, r3: %x\n", r3);
493 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
494 write_zsreg(uap_a, R0, RES_H_IUS);
497 pmz_status_handle(uap_a);
499 tty = pmz_receive_chars(uap_a);
501 pmz_transmit_chars(uap_a);
504 spin_unlock(&uap_a->port.lock);
506 tty_flip_buffer_push(tty);
508 if (uap_b->node == NULL)
511 spin_lock(&uap_b->port.lock);
513 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
514 write_zsreg(uap_b, R0, RES_H_IUS);
517 pmz_status_handle(uap_b);
519 tty = pmz_receive_chars(uap_b);
521 pmz_transmit_chars(uap_b);
524 spin_unlock(&uap_b->port.lock);
526 tty_flip_buffer_push(tty);
530 pmz_debug("irq done.\n");
536 * Peek the status register, lock not held by caller
538 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
543 spin_lock_irqsave(&uap->port.lock, flags);
544 status = read_zsreg(uap, R0);
545 spin_unlock_irqrestore(&uap->port.lock, flags);
551 * Check if transmitter is empty
552 * The port lock is not held.
554 static unsigned int pmz_tx_empty(struct uart_port *port)
556 struct uart_pmac_port *uap = to_pmz(port);
557 unsigned char status;
559 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
562 status = pmz_peek_status(to_pmz(port));
563 if (status & Tx_BUF_EMP)
569 * Set Modem Control (RTS & DTR) bits
570 * The port lock is held and interrupts are disabled.
571 * Note: Shall we really filter out RTS on external ports or
572 * should that be dealt at higher level only ?
574 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
576 struct uart_pmac_port *uap = to_pmz(port);
577 unsigned char set_bits, clear_bits;
579 /* Do nothing for irda for now... */
582 /* We get called during boot with a port not up yet */
583 if (ZS_IS_ASLEEP(uap) ||
584 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
587 set_bits = clear_bits = 0;
589 if (ZS_IS_INTMODEM(uap)) {
590 if (mctrl & TIOCM_RTS)
595 if (mctrl & TIOCM_DTR)
600 /* NOTE: Not subject to 'transmitter active' rule. */
601 uap->curregs[R5] |= set_bits;
602 uap->curregs[R5] &= ~clear_bits;
603 if (ZS_IS_ASLEEP(uap))
605 write_zsreg(uap, R5, uap->curregs[R5]);
606 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
607 set_bits, clear_bits, uap->curregs[R5]);
612 * Get Modem Control bits (only the input ones, the core will
613 * or that with a cached value of the control ones)
614 * The port lock is held and interrupts are disabled.
616 static unsigned int pmz_get_mctrl(struct uart_port *port)
618 struct uart_pmac_port *uap = to_pmz(port);
619 unsigned char status;
622 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
625 status = read_zsreg(uap, R0);
630 if (status & SYNC_HUNT)
639 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
640 * though for DMA, we will have to do a bit more.
641 * The port lock is held and interrupts are disabled.
643 static void pmz_stop_tx(struct uart_port *port)
645 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
650 * The port lock is held and interrupts are disabled.
652 static void pmz_start_tx(struct uart_port *port)
654 struct uart_pmac_port *uap = to_pmz(port);
655 unsigned char status;
657 pmz_debug("pmz: start_tx()\n");
659 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
660 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
662 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
665 status = read_zsreg(uap, R0);
667 /* TX busy? Just wait for the TX done interrupt. */
668 if (!(status & Tx_BUF_EMP))
671 /* Send the first character to jump-start the TX done
672 * IRQ sending engine.
675 write_zsdata(uap, port->x_char);
680 struct circ_buf *xmit = &port->state->xmit;
682 write_zsdata(uap, xmit->buf[xmit->tail]);
684 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
687 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
688 uart_write_wakeup(&uap->port);
690 pmz_debug("pmz: start_tx() done.\n");
694 * Stop Rx side, basically disable emitting of
695 * Rx interrupts on the port. We don't disable the rx
696 * side of the chip proper though
697 * The port lock is held.
699 static void pmz_stop_rx(struct uart_port *port)
701 struct uart_pmac_port *uap = to_pmz(port);
703 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
706 pmz_debug("pmz: stop_rx()()\n");
708 /* Disable all RX interrupts. */
709 uap->curregs[R1] &= ~RxINT_MASK;
710 pmz_maybe_update_regs(uap);
712 pmz_debug("pmz: stop_rx() done.\n");
716 * Enable modem status change interrupts
717 * The port lock is held.
719 static void pmz_enable_ms(struct uart_port *port)
721 struct uart_pmac_port *uap = to_pmz(port);
722 unsigned char new_reg;
724 if (ZS_IS_IRDA(uap) || uap->node == NULL)
726 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
727 if (new_reg != uap->curregs[R15]) {
728 uap->curregs[R15] = new_reg;
730 if (ZS_IS_ASLEEP(uap))
732 /* NOTE: Not subject to 'transmitter active' rule. */
733 write_zsreg(uap, R15, uap->curregs[R15]);
738 * Control break state emission
739 * The port lock is not held.
741 static void pmz_break_ctl(struct uart_port *port, int break_state)
743 struct uart_pmac_port *uap = to_pmz(port);
744 unsigned char set_bits, clear_bits, new_reg;
747 if (uap->node == NULL)
749 set_bits = clear_bits = 0;
754 clear_bits |= SND_BRK;
756 spin_lock_irqsave(&port->lock, flags);
758 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
759 if (new_reg != uap->curregs[R5]) {
760 uap->curregs[R5] = new_reg;
762 /* NOTE: Not subject to 'transmitter active' rule. */
763 if (ZS_IS_ASLEEP(uap)) {
764 spin_unlock_irqrestore(&port->lock, flags);
767 write_zsreg(uap, R5, uap->curregs[R5]);
770 spin_unlock_irqrestore(&port->lock, flags);
773 #ifdef CONFIG_PPC_PMAC
776 * Turn power on or off to the SCC and associated stuff
777 * (port drivers, modem, IR port, etc.)
778 * Returns the number of milliseconds we should wait before
779 * trying to use the port.
781 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
787 rc = pmac_call_feature(
788 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
789 pmz_debug("port power on result: %d\n", rc);
790 if (ZS_IS_INTMODEM(uap)) {
791 rc = pmac_call_feature(
792 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
793 delay = 2500; /* wait for 2.5s before using */
794 pmz_debug("modem power result: %d\n", rc);
797 /* TODO: Make that depend on a timer, don't power down
800 if (ZS_IS_INTMODEM(uap)) {
801 rc = pmac_call_feature(
802 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
803 pmz_debug("port power off result: %d\n", rc);
805 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
812 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
817 #endif /* !CONFIG_PPC_PMAC */
820 * FixZeroBug....Works around a bug in the SCC receiving channel.
821 * Inspired from Darwin code, 15 Sept. 2000 -DanM
823 * The following sequence prevents a problem that is seen with O'Hare ASICs
824 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
825 * at the input to the receiver becomes 'stuck' and locks up the receiver.
826 * This problem can occur as a result of a zero bit at the receiver input
827 * coincident with any of the following events:
829 * The SCC is initialized (hardware or software).
830 * A framing error is detected.
831 * The clocking option changes from synchronous or X1 asynchronous
832 * clocking to X16, X32, or X64 asynchronous clocking.
833 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
835 * This workaround attempts to recover from the lockup condition by placing
836 * the SCC in synchronous loopback mode with a fast clock before programming
837 * any of the asynchronous modes.
839 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
841 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
844 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
847 write_zsreg(uap, 4, X1CLK | MONSYNC);
848 write_zsreg(uap, 3, Rx8);
849 write_zsreg(uap, 5, Tx8 | RTS);
850 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
851 write_zsreg(uap, 11, RCBR | TCBR);
852 write_zsreg(uap, 12, 0);
853 write_zsreg(uap, 13, 0);
854 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
855 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
856 write_zsreg(uap, 3, Rx8 | RxENABLE);
857 write_zsreg(uap, 0, RES_EXT_INT);
858 write_zsreg(uap, 0, RES_EXT_INT);
859 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
861 /* The channel should be OK now, but it is probably receiving
863 * Switch to asynchronous mode, disable the receiver,
864 * and discard everything in the receive buffer.
866 write_zsreg(uap, 9, NV);
867 write_zsreg(uap, 4, X16CLK | SB_MASK);
868 write_zsreg(uap, 3, Rx8);
870 while (read_zsreg(uap, 0) & Rx_CH_AV) {
871 (void)read_zsreg(uap, 8);
872 write_zsreg(uap, 0, RES_EXT_INT);
873 write_zsreg(uap, 0, ERR_RES);
878 * Real startup routine, powers up the hardware and sets up
879 * the SCC. Returns a delay in ms where you need to wait before
880 * actually using the port, this is typically the internal modem
881 * powerup delay. This routine expect the lock to be taken.
883 static int __pmz_startup(struct uart_pmac_port *uap)
887 memset(&uap->curregs, 0, sizeof(uap->curregs));
889 /* Power up the SCC & underlying hardware (modem/irda) */
890 pwr_delay = pmz_set_scc_power(uap, 1);
892 /* Nice buggy HW ... */
893 pmz_fix_zero_bug_scc(uap);
895 /* Reset the channel */
896 uap->curregs[R9] = 0;
897 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
900 write_zsreg(uap, 9, 0);
903 /* Clear the interrupt registers */
904 write_zsreg(uap, R1, 0);
905 write_zsreg(uap, R0, ERR_RES);
906 write_zsreg(uap, R0, ERR_RES);
907 write_zsreg(uap, R0, RES_H_IUS);
908 write_zsreg(uap, R0, RES_H_IUS);
910 /* Setup some valid baud rate */
911 uap->curregs[R4] = X16CLK | SB1;
912 uap->curregs[R3] = Rx8;
913 uap->curregs[R5] = Tx8 | RTS;
914 if (!ZS_IS_IRDA(uap))
915 uap->curregs[R5] |= DTR;
916 uap->curregs[R12] = 0;
917 uap->curregs[R13] = 0;
918 uap->curregs[R14] = BRENAB;
920 /* Clear handshaking, enable BREAK interrupts */
921 uap->curregs[R15] = BRKIE;
923 /* Master interrupt enable */
924 uap->curregs[R9] |= NV | MIE;
926 pmz_load_zsregs(uap, uap->curregs);
928 /* Enable receiver and transmitter. */
929 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
930 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
932 /* Remember status for DCD/CTS changes */
933 uap->prev_status = read_zsreg(uap, R0);
938 static void pmz_irda_reset(struct uart_pmac_port *uap)
940 uap->curregs[R5] |= DTR;
941 write_zsreg(uap, R5, uap->curregs[R5]);
944 uap->curregs[R5] &= ~DTR;
945 write_zsreg(uap, R5, uap->curregs[R5]);
951 * This is the "normal" startup routine, using the above one
952 * wrapped with the lock and doing a schedule delay
954 static int pmz_startup(struct uart_port *port)
956 struct uart_pmac_port *uap = to_pmz(port);
960 pmz_debug("pmz: startup()\n");
962 if (ZS_IS_ASLEEP(uap))
964 if (uap->node == NULL)
967 mutex_lock(&pmz_irq_mutex);
969 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
971 /* A console is never powered down. Else, power up and
972 * initialize the chip
974 if (!ZS_IS_CONS(uap)) {
975 spin_lock_irqsave(&port->lock, flags);
976 pwr_delay = __pmz_startup(uap);
977 spin_unlock_irqrestore(&port->lock, flags);
980 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
981 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
983 pmz_error("Unable to register zs interrupt handler.\n");
984 pmz_set_scc_power(uap, 0);
985 mutex_unlock(&pmz_irq_mutex);
989 mutex_unlock(&pmz_irq_mutex);
991 /* Right now, we deal with delay by blocking here, I'll be
994 if (pwr_delay != 0) {
995 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
999 /* IrDA reset is done now */
1000 if (ZS_IS_IRDA(uap))
1001 pmz_irda_reset(uap);
1003 /* Enable interrupt requests for the channel */
1004 spin_lock_irqsave(&port->lock, flags);
1005 pmz_interrupt_control(uap, 1);
1006 spin_unlock_irqrestore(&port->lock, flags);
1008 pmz_debug("pmz: startup() done.\n");
1013 static void pmz_shutdown(struct uart_port *port)
1015 struct uart_pmac_port *uap = to_pmz(port);
1016 unsigned long flags;
1018 pmz_debug("pmz: shutdown()\n");
1020 if (uap->node == NULL)
1023 mutex_lock(&pmz_irq_mutex);
1025 spin_lock_irqsave(&port->lock, flags);
1027 if (!ZS_IS_ASLEEP(uap)) {
1028 /* Disable interrupt requests for the channel */
1029 pmz_interrupt_control(uap, 0);
1031 if (!ZS_IS_CONS(uap)) {
1032 /* Disable receiver and transmitter */
1033 uap->curregs[R3] &= ~RxENABLE;
1034 uap->curregs[R5] &= ~TxENABLE;
1036 /* Disable break assertion */
1037 uap->curregs[R5] &= ~SND_BRK;
1038 pmz_maybe_update_regs(uap);
1042 spin_unlock_irqrestore(&port->lock, flags);
1044 /* Release interrupt handler */
1045 free_irq(uap->port.irq, uap);
1047 spin_lock_irqsave(&port->lock, flags);
1049 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1051 if (!ZS_IS_OPEN(uap->mate))
1052 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1054 if (!ZS_IS_ASLEEP(uap) && !ZS_IS_CONS(uap))
1055 pmz_set_scc_power(uap, 0); /* Shut the chip down */
1057 spin_unlock_irqrestore(&port->lock, flags);
1059 mutex_unlock(&pmz_irq_mutex);
1061 pmz_debug("pmz: shutdown() done.\n");
1064 /* Shared by TTY driver and serial console setup. The port lock is held
1065 * and local interrupts are disabled.
1067 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1068 unsigned int iflag, unsigned long baud)
1072 /* Switch to external clocking for IrDA high clock rates. That
1073 * code could be re-used for Midi interfaces with different
1076 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1077 uap->curregs[R4] = X1CLK;
1078 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1079 uap->curregs[R14] = 0; /* BRG off */
1080 uap->curregs[R12] = 0;
1081 uap->curregs[R13] = 0;
1082 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1085 case ZS_CLOCK/16: /* 230400 */
1086 uap->curregs[R4] = X16CLK;
1087 uap->curregs[R11] = 0;
1088 uap->curregs[R14] = 0;
1090 case ZS_CLOCK/32: /* 115200 */
1091 uap->curregs[R4] = X32CLK;
1092 uap->curregs[R11] = 0;
1093 uap->curregs[R14] = 0;
1096 uap->curregs[R4] = X16CLK;
1097 uap->curregs[R11] = TCBR | RCBR;
1098 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1099 uap->curregs[R12] = (brg & 255);
1100 uap->curregs[R13] = ((brg >> 8) & 255);
1101 uap->curregs[R14] = BRENAB;
1103 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1106 /* Character size, stop bits, and parity. */
1107 uap->curregs[3] &= ~RxN_MASK;
1108 uap->curregs[5] &= ~TxN_MASK;
1110 switch (cflag & CSIZE) {
1112 uap->curregs[3] |= Rx5;
1113 uap->curregs[5] |= Tx5;
1114 uap->parity_mask = 0x1f;
1117 uap->curregs[3] |= Rx6;
1118 uap->curregs[5] |= Tx6;
1119 uap->parity_mask = 0x3f;
1122 uap->curregs[3] |= Rx7;
1123 uap->curregs[5] |= Tx7;
1124 uap->parity_mask = 0x7f;
1128 uap->curregs[3] |= Rx8;
1129 uap->curregs[5] |= Tx8;
1130 uap->parity_mask = 0xff;
1133 uap->curregs[4] &= ~(SB_MASK);
1135 uap->curregs[4] |= SB2;
1137 uap->curregs[4] |= SB1;
1139 uap->curregs[4] |= PAR_ENAB;
1141 uap->curregs[4] &= ~PAR_ENAB;
1142 if (!(cflag & PARODD))
1143 uap->curregs[4] |= PAR_EVEN;
1145 uap->curregs[4] &= ~PAR_EVEN;
1147 uap->port.read_status_mask = Rx_OVR;
1149 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1150 if (iflag & (BRKINT | PARMRK))
1151 uap->port.read_status_mask |= BRK_ABRT;
1153 uap->port.ignore_status_mask = 0;
1155 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1156 if (iflag & IGNBRK) {
1157 uap->port.ignore_status_mask |= BRK_ABRT;
1159 uap->port.ignore_status_mask |= Rx_OVR;
1162 if ((cflag & CREAD) == 0)
1163 uap->port.ignore_status_mask = 0xff;
1168 * Set the irda codec on the imac to the specified baud rate.
1170 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1198 /* The FIR modes aren't really supported at this point, how
1199 * do we select the speed ? via the FCR on KeyLargo ?
1213 /* Wait for transmitter to drain */
1215 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1216 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1218 pmz_error("transmitter didn't drain\n");
1224 /* Drain the receiver too */
1226 (void)read_zsdata(uap);
1227 (void)read_zsdata(uap);
1228 (void)read_zsdata(uap);
1230 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1234 pmz_error("receiver didn't drain\n");
1239 /* Switch to command mode */
1240 uap->curregs[R5] |= DTR;
1241 write_zsreg(uap, R5, uap->curregs[R5]);
1245 /* Switch SCC to 19200 */
1246 pmz_convert_to_zs(uap, CS8, 0, 19200);
1247 pmz_load_zsregs(uap, uap->curregs);
1250 /* Write get_version command byte */
1251 write_zsdata(uap, 1);
1253 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1255 pmz_error("irda_setup timed out on get_version byte\n");
1260 version = read_zsdata(uap);
1263 pmz_info("IrDA: dongle version %d not supported\n", version);
1267 /* Send speed mode */
1268 write_zsdata(uap, cmdbyte);
1270 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1272 pmz_error("irda_setup timed out on speed mode byte\n");
1277 t = read_zsdata(uap);
1279 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1281 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1284 (void)read_zsdata(uap);
1285 (void)read_zsdata(uap);
1286 (void)read_zsdata(uap);
1289 /* Switch back to data mode */
1290 uap->curregs[R5] &= ~DTR;
1291 write_zsreg(uap, R5, uap->curregs[R5]);
1294 (void)read_zsdata(uap);
1295 (void)read_zsdata(uap);
1296 (void)read_zsdata(uap);
1300 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1301 struct ktermios *old)
1303 struct uart_pmac_port *uap = to_pmz(port);
1306 pmz_debug("pmz: set_termios()\n");
1308 if (ZS_IS_ASLEEP(uap))
1311 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1313 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1314 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1315 * about the FIR mode and high speed modes. So these are unused. For
1316 * implementing proper support for these, we should probably add some
1317 * DMA as well, at least on the Rx side, which isn't a simple thing
1320 if (ZS_IS_IRDA(uap)) {
1321 /* Calc baud rate */
1322 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1323 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1324 /* Cet the irda codec to the right rate */
1325 pmz_irda_setup(uap, &baud);
1326 /* Set final baud rate */
1327 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1328 pmz_load_zsregs(uap, uap->curregs);
1331 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1332 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1333 /* Make sure modem status interrupts are correctly configured */
1334 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1335 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1336 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1338 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1339 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1342 /* Load registers to the chip */
1343 pmz_maybe_update_regs(uap);
1345 uart_update_timeout(port, termios->c_cflag, baud);
1347 pmz_debug("pmz: set_termios() done.\n");
1350 /* The port lock is not held. */
1351 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1352 struct ktermios *old)
1354 struct uart_pmac_port *uap = to_pmz(port);
1355 unsigned long flags;
1357 spin_lock_irqsave(&port->lock, flags);
1359 /* Disable IRQs on the port */
1360 pmz_interrupt_control(uap, 0);
1362 /* Setup new port configuration */
1363 __pmz_set_termios(port, termios, old);
1365 /* Re-enable IRQs on the port */
1366 if (ZS_IS_OPEN(uap))
1367 pmz_interrupt_control(uap, 1);
1369 spin_unlock_irqrestore(&port->lock, flags);
1372 static const char *pmz_type(struct uart_port *port)
1374 struct uart_pmac_port *uap = to_pmz(port);
1376 if (ZS_IS_IRDA(uap))
1377 return "Z85c30 ESCC - Infrared port";
1378 else if (ZS_IS_INTMODEM(uap))
1379 return "Z85c30 ESCC - Internal modem";
1380 return "Z85c30 ESCC - Serial port";
1383 /* We do not request/release mappings of the registers here, this
1384 * happens at early serial probe time.
1386 static void pmz_release_port(struct uart_port *port)
1390 static int pmz_request_port(struct uart_port *port)
1395 /* These do not need to do anything interesting either. */
1396 static void pmz_config_port(struct uart_port *port, int flags)
1400 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1401 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1406 #ifdef CONFIG_CONSOLE_POLL
1408 static int pmz_poll_get_char(struct uart_port *port)
1410 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1412 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0)
1414 return read_zsdata(uap);
1417 static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1419 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1421 /* Wait for the transmit buffer to empty. */
1422 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1424 write_zsdata(uap, c);
1427 #endif /* CONFIG_CONSOLE_POLL */
1429 static struct uart_ops pmz_pops = {
1430 .tx_empty = pmz_tx_empty,
1431 .set_mctrl = pmz_set_mctrl,
1432 .get_mctrl = pmz_get_mctrl,
1433 .stop_tx = pmz_stop_tx,
1434 .start_tx = pmz_start_tx,
1435 .stop_rx = pmz_stop_rx,
1436 .enable_ms = pmz_enable_ms,
1437 .break_ctl = pmz_break_ctl,
1438 .startup = pmz_startup,
1439 .shutdown = pmz_shutdown,
1440 .set_termios = pmz_set_termios,
1442 .release_port = pmz_release_port,
1443 .request_port = pmz_request_port,
1444 .config_port = pmz_config_port,
1445 .verify_port = pmz_verify_port,
1446 #ifdef CONFIG_CONSOLE_POLL
1447 .poll_get_char = pmz_poll_get_char,
1448 .poll_put_char = pmz_poll_put_char,
1452 #ifdef CONFIG_PPC_PMAC
1455 * Setup one port structure after probing, HW is down at this point,
1456 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1457 * register our console before uart_add_one_port() is called
1459 static int __init pmz_init_port(struct uart_pmac_port *uap)
1461 struct device_node *np = uap->node;
1463 const struct slot_names_prop {
1468 struct resource r_ports, r_rxdma, r_txdma;
1471 * Request & map chip registers
1473 if (of_address_to_resource(np, 0, &r_ports))
1475 uap->port.mapbase = r_ports.start;
1476 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1478 uap->control_reg = uap->port.membase;
1479 uap->data_reg = uap->control_reg + 0x10;
1482 * Request & map DBDMA registers
1485 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1486 of_address_to_resource(np, 2, &r_rxdma) == 0)
1487 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1489 memset(&r_txdma, 0, sizeof(struct resource));
1490 memset(&r_rxdma, 0, sizeof(struct resource));
1492 if (ZS_HAS_DMA(uap)) {
1493 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1494 if (uap->tx_dma_regs == NULL) {
1495 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1498 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1499 if (uap->rx_dma_regs == NULL) {
1500 iounmap(uap->tx_dma_regs);
1501 uap->tx_dma_regs = NULL;
1502 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1505 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1506 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1513 if (of_device_is_compatible(np, "cobalt"))
1514 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1515 conn = of_get_property(np, "AAPL,connector", &len);
1516 if (conn && (strcmp(conn, "infrared") == 0))
1517 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1518 uap->port_type = PMAC_SCC_ASYNC;
1519 /* 1999 Powerbook G3 has slot-names property instead */
1520 slots = of_get_property(np, "slot-names", &len);
1521 if (slots && slots->count > 0) {
1522 if (strcmp(slots->name, "IrDA") == 0)
1523 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1524 else if (strcmp(slots->name, "Modem") == 0)
1525 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1527 if (ZS_IS_IRDA(uap))
1528 uap->port_type = PMAC_SCC_IRDA;
1529 if (ZS_IS_INTMODEM(uap)) {
1530 struct device_node* i2c_modem =
1531 of_find_node_by_name(NULL, "i2c-modem");
1534 of_get_property(i2c_modem, "modem-id", NULL);
1535 if (mid) switch(*mid) {
1542 uap->port_type = PMAC_SCC_I2S1;
1544 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1546 of_node_put(i2c_modem);
1548 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1553 * Init remaining bits of "port" structure
1555 uap->port.iotype = UPIO_MEM;
1556 uap->port.irq = irq_of_parse_and_map(np, 0);
1557 uap->port.uartclk = ZS_CLOCK;
1558 uap->port.fifosize = 1;
1559 uap->port.ops = &pmz_pops;
1560 uap->port.type = PORT_PMAC_ZILOG;
1561 uap->port.flags = 0;
1564 * Fixup for the port on Gatwick for which the device-tree has
1565 * missing interrupts. Normally, the macio_dev would contain
1566 * fixed up interrupt info, but we use the device-tree directly
1567 * here due to early probing so we need the fixup too.
1569 if (uap->port.irq == NO_IRQ &&
1570 np->parent && np->parent->parent &&
1571 of_device_is_compatible(np->parent->parent, "gatwick")) {
1572 /* IRQs on gatwick are offset by 64 */
1573 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1574 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1575 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1578 /* Setup some valid baud rate information in the register
1579 * shadows so we don't write crap there before baud rate is
1580 * first initialized.
1582 pmz_convert_to_zs(uap, CS8, 0, 9600);
1588 * Get rid of a port on module removal
1590 static void pmz_dispose_port(struct uart_pmac_port *uap)
1592 struct device_node *np;
1595 iounmap(uap->rx_dma_regs);
1596 iounmap(uap->tx_dma_regs);
1597 iounmap(uap->control_reg);
1600 memset(uap, 0, sizeof(struct uart_pmac_port));
1604 * Called upon match with an escc node in the device-tree.
1606 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1610 /* Iterate the pmz_ports array to find a matching entry
1612 for (i = 0; i < MAX_ZS_PORTS; i++)
1613 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) {
1614 struct uart_pmac_port *uap = &pmz_ports[i];
1617 dev_set_drvdata(&mdev->ofdev.dev, uap);
1618 if (macio_request_resources(uap->dev, "pmac_zilog"))
1619 printk(KERN_WARNING "%s: Failed to request resource"
1620 ", port still active\n",
1623 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1630 * That one should not be called, macio isn't really a hotswap device,
1631 * we don't expect one of those serial ports to go away...
1633 static int pmz_detach(struct macio_dev *mdev)
1635 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1640 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1641 macio_release_resources(uap->dev);
1642 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1644 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1651 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1653 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1654 struct uart_state *state;
1655 unsigned long flags;
1658 printk("HRM... pmz_suspend with NULL uap\n");
1662 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1665 pmz_debug("suspend, switching to state %d\n", pm_state.event);
1667 state = pmz_uart_reg.state + uap->port.line;
1669 mutex_lock(&pmz_irq_mutex);
1670 mutex_lock(&state->port.mutex);
1672 spin_lock_irqsave(&uap->port.lock, flags);
1674 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1675 /* Disable interrupt requests for the channel */
1676 pmz_interrupt_control(uap, 0);
1678 /* Disable receiver and transmitter */
1679 uap->curregs[R3] &= ~RxENABLE;
1680 uap->curregs[R5] &= ~TxENABLE;
1682 /* Disable break assertion */
1683 uap->curregs[R5] &= ~SND_BRK;
1684 pmz_load_zsregs(uap, uap->curregs);
1686 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1690 spin_unlock_irqrestore(&uap->port.lock, flags);
1692 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1693 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1694 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1695 disable_irq(uap->port.irq);
1698 if (ZS_IS_CONS(uap))
1699 uap->port.cons->flags &= ~CON_ENABLED;
1701 /* Shut the chip down */
1702 pmz_set_scc_power(uap, 0);
1704 mutex_unlock(&state->port.mutex);
1705 mutex_unlock(&pmz_irq_mutex);
1707 pmz_debug("suspend, switching complete\n");
1709 mdev->ofdev.dev.power.power_state = pm_state;
1715 static int pmz_resume(struct macio_dev *mdev)
1717 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1718 struct uart_state *state;
1719 unsigned long flags;
1725 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1728 pmz_debug("resume, switching to state 0\n");
1730 state = pmz_uart_reg.state + uap->port.line;
1732 mutex_lock(&pmz_irq_mutex);
1733 mutex_lock(&state->port.mutex);
1735 spin_lock_irqsave(&uap->port.lock, flags);
1736 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1737 spin_unlock_irqrestore(&uap->port.lock, flags);
1740 pwr_delay = __pmz_startup(uap);
1742 /* Take care of config that may have changed while asleep */
1743 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1745 spin_unlock_irqrestore(&uap->port.lock, flags);
1747 if (ZS_IS_CONS(uap))
1748 uap->port.cons->flags |= CON_ENABLED;
1750 /* Re-enable IRQ on the controller */
1751 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1752 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1753 enable_irq(uap->port.irq);
1756 if (ZS_IS_OPEN(uap)) {
1757 spin_lock_irqsave(&uap->port.lock, flags);
1758 pmz_interrupt_control(uap, 1);
1759 spin_unlock_irqrestore(&uap->port.lock, flags);
1763 mutex_unlock(&state->port.mutex);
1764 mutex_unlock(&pmz_irq_mutex);
1766 /* Right now, we deal with delay by blocking here, I'll be
1769 if (pwr_delay != 0) {
1770 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1774 pmz_debug("resume, switching complete\n");
1776 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1782 * Probe all ports in the system and build the ports array, we register
1783 * with the serial layer at this point, the macio-type probing is only
1784 * used later to "attach" to the sysfs tree so we get power management
1787 static int __init pmz_probe(void)
1789 struct device_node *node_p, *node_a, *node_b, *np;
1794 * Find all escc chips in the system
1796 node_p = of_find_node_by_name(NULL, "escc");
1799 * First get channel A/B node pointers
1801 * TODO: Add routines with proper locking to do that...
1803 node_a = node_b = NULL;
1804 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1805 if (strncmp(np->name, "ch-a", 4) == 0)
1806 node_a = of_node_get(np);
1807 else if (strncmp(np->name, "ch-b", 4) == 0)
1808 node_b = of_node_get(np);
1810 if (!node_a && !node_b) {
1811 of_node_put(node_a);
1812 of_node_put(node_b);
1813 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1814 (!node_a) ? 'a' : 'b', node_p->full_name);
1819 * Fill basic fields in the port structures
1821 pmz_ports[count].mate = &pmz_ports[count+1];
1822 pmz_ports[count+1].mate = &pmz_ports[count];
1823 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1824 pmz_ports[count].node = node_a;
1825 pmz_ports[count+1].node = node_b;
1826 pmz_ports[count].port.line = count;
1827 pmz_ports[count+1].port.line = count+1;
1830 * Setup the ports for real
1832 rc = pmz_init_port(&pmz_ports[count]);
1833 if (rc == 0 && node_b != NULL)
1834 rc = pmz_init_port(&pmz_ports[count+1]);
1836 of_node_put(node_a);
1837 of_node_put(node_b);
1838 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1839 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1844 node_p = of_find_node_by_name(node_p, "escc");
1846 pmz_ports_count = count;
1853 extern struct platform_device scc_a_pdev, scc_b_pdev;
1855 static int __init pmz_init_port(struct uart_pmac_port *uap)
1857 struct resource *r_ports;
1860 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0);
1861 irq = platform_get_irq(uap->node, 0);
1862 if (!r_ports || !irq)
1865 uap->port.mapbase = r_ports->start;
1866 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1867 uap->port.iotype = UPIO_MEM;
1868 uap->port.irq = irq;
1869 uap->port.uartclk = ZS_CLOCK;
1870 uap->port.fifosize = 1;
1871 uap->port.ops = &pmz_pops;
1872 uap->port.type = PORT_PMAC_ZILOG;
1873 uap->port.flags = 0;
1875 uap->control_reg = uap->port.membase;
1876 uap->data_reg = uap->control_reg + 4;
1879 pmz_convert_to_zs(uap, CS8, 0, 9600);
1884 static int __init pmz_probe(void)
1888 pmz_ports_count = 0;
1890 pmz_ports[0].mate = &pmz_ports[1];
1891 pmz_ports[0].port.line = 0;
1892 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1893 pmz_ports[0].node = &scc_a_pdev;
1894 err = pmz_init_port(&pmz_ports[0]);
1899 pmz_ports[1].mate = &pmz_ports[0];
1900 pmz_ports[1].port.line = 1;
1901 pmz_ports[1].flags = 0;
1902 pmz_ports[1].node = &scc_b_pdev;
1903 err = pmz_init_port(&pmz_ports[1]);
1911 static void pmz_dispose_port(struct uart_pmac_port *uap)
1913 memset(uap, 0, sizeof(struct uart_pmac_port));
1916 static int __init pmz_attach(struct platform_device *pdev)
1920 for (i = 0; i < pmz_ports_count; i++)
1921 if (pmz_ports[i].node == pdev)
1926 static int __exit pmz_detach(struct platform_device *pdev)
1931 #endif /* !CONFIG_PPC_PMAC */
1933 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1935 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1936 static int __init pmz_console_setup(struct console *co, char *options);
1938 static struct console pmz_console = {
1939 .name = PMACZILOG_NAME,
1940 .write = pmz_console_write,
1941 .device = uart_console_device,
1942 .setup = pmz_console_setup,
1943 .flags = CON_PRINTBUFFER,
1945 .data = &pmz_uart_reg,
1948 #define PMACZILOG_CONSOLE &pmz_console
1949 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1950 #define PMACZILOG_CONSOLE (NULL)
1951 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1954 * Register the driver, console driver and ports with the serial
1957 static int __init pmz_register(void)
1961 pmz_uart_reg.nr = pmz_ports_count;
1962 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1965 * Register this driver with the serial core
1967 rc = uart_register_driver(&pmz_uart_reg);
1972 * Register each port with the serial core
1974 for (i = 0; i < pmz_ports_count; i++) {
1975 struct uart_pmac_port *uport = &pmz_ports[i];
1976 /* NULL node may happen on wallstreet */
1977 if (uport->node != NULL)
1978 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1986 struct uart_pmac_port *uport = &pmz_ports[i];
1987 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1989 uart_unregister_driver(&pmz_uart_reg);
1993 #ifdef CONFIG_PPC_PMAC
1995 static struct of_device_id pmz_match[] =
2005 MODULE_DEVICE_TABLE (of, pmz_match);
2007 static struct macio_driver pmz_driver = {
2009 .name = "pmac_zilog",
2010 .owner = THIS_MODULE,
2011 .of_match_table = pmz_match,
2013 .probe = pmz_attach,
2014 .remove = pmz_detach,
2015 .suspend = pmz_suspend,
2016 .resume = pmz_resume,
2021 static struct platform_driver pmz_driver = {
2022 .remove = __exit_p(pmz_detach),
2025 .owner = THIS_MODULE,
2029 #endif /* !CONFIG_PPC_PMAC */
2031 static int __init init_pmz(void)
2034 printk(KERN_INFO "%s\n", version);
2037 * First, we need to do a direct OF-based probe pass. We
2038 * do that because we want serial console up before the
2039 * macio stuffs calls us back, and since that makes it
2040 * easier to pass the proper number of channels to
2041 * uart_register_driver()
2043 if (pmz_ports_count == 0)
2047 * Bail early if no port found
2049 if (pmz_ports_count == 0)
2053 * Now we register with the serial layer
2055 rc = pmz_register();
2058 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
2059 "pmac_zilog: Did another serial driver already claim the minors?\n");
2060 /* effectively "pmz_unprobe()" */
2061 for (i=0; i < pmz_ports_count; i++)
2062 pmz_dispose_port(&pmz_ports[i]);
2067 * Then we register the macio driver itself
2069 #ifdef CONFIG_PPC_PMAC
2070 return macio_register_driver(&pmz_driver);
2072 return platform_driver_probe(&pmz_driver, pmz_attach);
2076 static void __exit exit_pmz(void)
2080 #ifdef CONFIG_PPC_PMAC
2081 /* Get rid of macio-driver (detach from macio) */
2082 macio_unregister_driver(&pmz_driver);
2084 platform_driver_unregister(&pmz_driver);
2087 for (i = 0; i < pmz_ports_count; i++) {
2088 struct uart_pmac_port *uport = &pmz_ports[i];
2089 if (uport->node != NULL) {
2090 uart_remove_one_port(&pmz_uart_reg, &uport->port);
2091 pmz_dispose_port(uport);
2094 /* Unregister UART driver */
2095 uart_unregister_driver(&pmz_uart_reg);
2098 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
2100 static void pmz_console_putchar(struct uart_port *port, int ch)
2102 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
2104 /* Wait for the transmit buffer to empty. */
2105 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
2107 write_zsdata(uap, ch);
2111 * Print a string to the serial port trying not to disturb
2112 * any possible real use of the port...
2114 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
2116 struct uart_pmac_port *uap = &pmz_ports[con->index];
2117 unsigned long flags;
2119 if (ZS_IS_ASLEEP(uap))
2121 spin_lock_irqsave(&uap->port.lock, flags);
2123 /* Turn of interrupts and enable the transmitter. */
2124 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
2125 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
2127 uart_console_write(&uap->port, s, count, pmz_console_putchar);
2129 /* Restore the values in the registers. */
2130 write_zsreg(uap, R1, uap->curregs[1]);
2131 /* Don't disable the transmitter. */
2133 spin_unlock_irqrestore(&uap->port.lock, flags);
2137 * Setup the serial console
2139 static int __init pmz_console_setup(struct console *co, char *options)
2141 struct uart_pmac_port *uap;
2142 struct uart_port *port;
2147 unsigned long pwr_delay;
2150 * XServe's default to 57600 bps
2152 if (of_machine_is_compatible("RackMac1,1")
2153 || of_machine_is_compatible("RackMac1,2")
2154 || of_machine_is_compatible("MacRISC4"))
2158 * Check whether an invalid uart number has been specified, and
2159 * if so, search for the first available port that does have
2162 if (co->index >= pmz_ports_count)
2164 uap = &pmz_ports[co->index];
2165 if (uap->node == NULL)
2170 * Mark port as beeing a console
2172 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2175 * Temporary fix for uart layer who didn't setup the spinlock yet
2177 spin_lock_init(&port->lock);
2180 * Enable the hardware
2182 pwr_delay = __pmz_startup(uap);
2187 uart_parse_options(options, &baud, &parity, &bits, &flow);
2189 return uart_set_options(port, co, baud, parity, bits, flow);
2192 static int __init pmz_console_init(void)
2197 /* TODO: Autoprobe console based on OF */
2198 /* pmz_console.index = i; */
2199 register_console(&pmz_console);
2204 console_initcall(pmz_console_init);
2205 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2207 module_init(init_pmz);
2208 module_exit(exit_pmz);