drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 173         else
 174                 disable_irq_nosync(ourport->tx_irq);
 175
 176         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 177                 dmaengine_pause(dma->tx_chan);
 178                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 179                 dmaengine_terminate_all(dma->tx_chan);
 180                 dma_sync_single_for_cpu(ourport->port.dev,
 181                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 182                 async_tx_ack(dma->tx_desc);
 183                 count = dma->tx_bytes_requested - state.residue;
 184                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 185                 port->icount.tx += count;
 186         }
 187
 188         tx_enabled(port) = 0;
 189         ourport->tx_in_progress = 0;
 190
 191         if (port->flags & UPF_CONS_FLOW)
 192                 s3c24xx_serial_rx_enable(port);
 193
 194         ourport->tx_mode = 0;
 195 }
 196
 197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 198
 199 static void s3c24xx_serial_tx_dma_complete(void *args)
 200 {
 201         struct s3c24xx_uart_port *ourport = args;
 202         struct uart_port *port = &ourport->port;
 203         struct circ_buf *xmit = &port->state->xmit;
 204         struct s3c24xx_uart_dma *dma = ourport->dma;
 205         struct dma_tx_state state;
 206         unsigned long flags;
 207         int count;
 208
 209
 210         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 211         count = dma->tx_bytes_requested - state.residue;
 212         async_tx_ack(dma->tx_desc);
 213
 214         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 215                                 dma->tx_size, DMA_TO_DEVICE);
 216
 217         spin_lock_irqsave(&port->lock, flags);
 218
 219         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 220         port->icount.tx += count;
 221         ourport->tx_in_progress = 0;
 222
 223         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 224                 uart_write_wakeup(port);
 225
 226         s3c24xx_serial_start_next_tx(ourport);
 227         spin_unlock_irqrestore(&port->lock, flags);
 228 }
 229
 230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 231 {
 232         struct uart_port *port = &ourport->port;
 233         u32 ucon;
 234
 235         /* Mask Tx interrupt */
 236         if (s3c24xx_serial_has_interrupt_mask(port))
 237                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 238         else
 239                 disable_irq_nosync(ourport->tx_irq);
 240
 241         /* Enable tx dma mode */
 242         ucon = rd_regl(port, S3C2410_UCON);
 243         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 244         ucon |= (dma_get_cache_alignment() >= 16) ?
 245                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 246         ucon |= S3C64XX_UCON_TXMODE_DMA;
 247         wr_regl(port,  S3C2410_UCON, ucon);
 248
 249         ourport->tx_mode = S3C24XX_TX_DMA;
 250 }
 251
 252 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 253 {
 254         struct uart_port *port = &ourport->port;
 255         u32 ucon, ufcon;
 256
 257         /* Set ufcon txtrig */
 258         ourport->tx_in_progress = S3C24XX_TX_PIO;
 259         ufcon = rd_regl(port, S3C2410_UFCON);
 260         wr_regl(port,  S3C2410_UFCON, ufcon);
 261
 262         /* Enable tx pio mode */
 263         ucon = rd_regl(port, S3C2410_UCON);
 264         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 265         ucon |= S3C64XX_UCON_TXMODE_CPU;
 266         wr_regl(port,  S3C2410_UCON, ucon);
 267
 268         /* Unmask Tx interrupt */
 269         if (s3c24xx_serial_has_interrupt_mask(port))
 270                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 271                                   S3C64XX_UINTM);
 272         else
 273                 enable_irq(ourport->tx_irq);
 274
 275         ourport->tx_mode = S3C24XX_TX_PIO;
 276 }
 277
 278 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 279 {
 280         if (ourport->tx_mode != S3C24XX_TX_PIO)
 281                 enable_tx_pio(ourport);
 282 }
 283
 284 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 285                                       unsigned int count)
 286 {
 287         struct uart_port *port = &ourport->port;
 288         struct circ_buf *xmit = &port->state->xmit;
 289         struct s3c24xx_uart_dma *dma = ourport->dma;
 290
 291
 292         if (ourport->tx_mode != S3C24XX_TX_DMA)
 293                 enable_tx_dma(ourport);
 294
 295         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 296         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 297
 298         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 299                                 dma->tx_size, DMA_TO_DEVICE);
 300
 301         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 302                                 dma->tx_transfer_addr, dma->tx_size,
 303                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 304         if (!dma->tx_desc) {
 305                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 306                 return -EIO;
 307         }
 308
 309         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 310         dma->tx_desc->callback_param = ourport;
 311         dma->tx_bytes_requested = dma->tx_size;
 312
 313         ourport->tx_in_progress = S3C24XX_TX_DMA;
 314         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 315         dma_async_issue_pending(dma->tx_chan);
 316         return 0;
 317 }
 318
 319 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 320 {
 321         struct uart_port *port = &ourport->port;
 322         struct circ_buf *xmit = &port->state->xmit;
 323         unsigned long count;
 324
 325         /* Get data size up to the end of buffer */
 326         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 327
 328         if (!count) {
 329                 s3c24xx_serial_stop_tx(port);
 330                 return;
 331         }
 332
 333         if (!ourport->dma || !ourport->dma->tx_chan ||
 334             count < ourport->min_dma_size ||
 335             xmit->tail & (dma_get_cache_alignment() - 1))
 336                 s3c24xx_serial_start_tx_pio(ourport);
 337         else
 338                 s3c24xx_serial_start_tx_dma(ourport, count);
 339 }
 340
 341 static void s3c24xx_serial_start_tx(struct uart_port *port)
 342 {
 343         struct s3c24xx_uart_port *ourport = to_ourport(port);
 344         struct circ_buf *xmit = &port->state->xmit;
 345
 346         if (!tx_enabled(port)) {
 347                 if (port->flags & UPF_CONS_FLOW)
 348                         s3c24xx_serial_rx_disable(port);
 349
 350                 tx_enabled(port) = 1;
 351                 if (!ourport->dma || !ourport->dma->tx_chan)
 352                         s3c24xx_serial_start_tx_pio(ourport);
 353         }
 354
 355         if (ourport->dma && ourport->dma->tx_chan) {
 356                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 357                         s3c24xx_serial_start_next_tx(ourport);
 358         }
 359 }
 360
 361 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 362                 struct tty_port *tty, int count)
 363 {
 364         struct s3c24xx_uart_dma *dma = ourport->dma;
 365         int copied;
 366
 367         if (!count)
 368                 return;
 369
 370         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 371                                 dma->rx_size, DMA_FROM_DEVICE);
 372
 373         ourport->port.icount.rx += count;
 374         if (!tty) {
 375                 dev_err(ourport->port.dev, "No tty port\n");
 376                 return;
 377         }
 378         copied = tty_insert_flip_string(tty,
 379                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 380         if (copied != count) {
 381                 WARN_ON(1);
 382                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 383         }
 384 }
 385
 386 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 387 {
 388         struct s3c24xx_uart_port *ourport = to_ourport(port);
 389         struct s3c24xx_uart_dma *dma = ourport->dma;
 390         struct tty_port *t = &port->state->port;
 391         struct dma_tx_state state;
 392         enum dma_status dma_status;
 393         unsigned int received;
 394
 395         if (rx_enabled(port)) {
 396                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 397                 if (s3c24xx_serial_has_interrupt_mask(port))
 398                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 399                                         S3C64XX_UINTM);
 400                 else
 401                         disable_irq_nosync(ourport->rx_irq);
 402                 rx_enabled(port) = 0;
 403         }
 404         if (dma && dma->rx_chan) {
 405                 dmaengine_pause(dma->tx_chan);
 406                 dma_status = dmaengine_tx_status(dma->rx_chan,
 407                                 dma->rx_cookie, &state);
 408                 if (dma_status == DMA_IN_PROGRESS ||
 409                         dma_status == DMA_PAUSED) {
 410                         received = dma->rx_bytes_requested - state.residue;
 411                         dmaengine_terminate_all(dma->rx_chan);
 412                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 413                 }
 414         }
 415 }
 416
 417 static inline struct s3c24xx_uart_info
 418         *s3c24xx_port_to_info(struct uart_port *port)
 419 {
 420         return to_ourport(port)->info;
 421 }
 422
 423 static inline struct s3c2410_uartcfg
 424         *s3c24xx_port_to_cfg(struct uart_port *port)
 425 {
 426         struct s3c24xx_uart_port *ourport;
 427
 428         if (port->dev == NULL)
 429                 return NULL;
 430
 431         ourport = container_of(port, struct s3c24xx_uart_port, port);
 432         return ourport->cfg;
 433 }
 434
 435 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 436                                      unsigned long ufstat)
 437 {
 438         struct s3c24xx_uart_info *info = ourport->info;
 439
 440         if (ufstat & info->rx_fifofull)
 441                 return ourport->port.fifosize;
 442
 443         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 444 }
 445
 446 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 447 static void s3c24xx_serial_rx_dma_complete(void *args)
 448 {
 449         struct s3c24xx_uart_port *ourport = args;
 450         struct uart_port *port = &ourport->port;
 451
 452         struct s3c24xx_uart_dma *dma = ourport->dma;
 453         struct tty_port *t = &port->state->port;
 454         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 455
 456         struct dma_tx_state state;
 457         unsigned long flags;
 458         int received;
 459
 460         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 461         received  = dma->rx_bytes_requested - state.residue;
 462         async_tx_ack(dma->rx_desc);
 463
 464         spin_lock_irqsave(&port->lock, flags);
 465
 466         if (received)
 467                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 468
 469         if (tty) {
 470                 tty_flip_buffer_push(t);
 471                 tty_kref_put(tty);
 472         }
 473
 474         s3c64xx_start_rx_dma(ourport);
 475
 476         spin_unlock_irqrestore(&port->lock, flags);
 477 }
 478
 479 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 480 {
 481         struct s3c24xx_uart_dma *dma = ourport->dma;
 482
 483         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 484                                 dma->rx_size, DMA_FROM_DEVICE);
 485
 486         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 487                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 488                                 DMA_PREP_INTERRUPT);
 489         if (!dma->rx_desc) {
 490                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 491                 return;
 492         }
 493
 494         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 495         dma->rx_desc->callback_param = ourport;
 496         dma->rx_bytes_requested = dma->rx_size;
 497
 498         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 499         dma_async_issue_pending(dma->rx_chan);
 500 }
 501
 502 /* ? - where has parity gone?? */
 503 #define S3C2410_UERSTAT_PARITY (0x1000)
 504
 505 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 506 {
 507         struct uart_port *port = &ourport->port;
 508         unsigned int ucon;
 509
 510         /* set Rx mode to DMA mode */
 511         ucon = rd_regl(port, S3C2410_UCON);
 512         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 513                         S3C64XX_UCON_TIMEOUT_MASK |
 514                         S3C64XX_UCON_EMPTYINT_EN |
 515                         S3C64XX_UCON_DMASUS_EN |
 516                         S3C64XX_UCON_TIMEOUT_EN |
 517                         S3C64XX_UCON_RXMODE_MASK);
 518         ucon |= S3C64XX_UCON_RXBURST_16 |
 519                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 520                         S3C64XX_UCON_EMPTYINT_EN |
 521                         S3C64XX_UCON_TIMEOUT_EN |
 522                         S3C64XX_UCON_RXMODE_DMA;
 523         wr_regl(port, S3C2410_UCON, ucon);
 524
 525         ourport->rx_mode = S3C24XX_RX_DMA;
 526 }
 527
 528 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 529 {
 530         struct uart_port *port = &ourport->port;
 531         unsigned int ucon;
 532
 533         /* set Rx mode to DMA mode */
 534         ucon = rd_regl(port, S3C2410_UCON);
 535         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 536                         S3C64XX_UCON_EMPTYINT_EN |
 537                         S3C64XX_UCON_DMASUS_EN |
 538                         S3C64XX_UCON_TIMEOUT_EN |
 539                         S3C64XX_UCON_RXMODE_MASK);
 540         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 541                         S3C64XX_UCON_TIMEOUT_EN |
 542                         S3C64XX_UCON_RXMODE_CPU;
 543         wr_regl(port, S3C2410_UCON, ucon);
 544
 545         ourport->rx_mode = S3C24XX_RX_PIO;
 546 }
 547
 548 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 549
 550 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 551 {
 552         unsigned int utrstat, ufstat, received;
 553         struct s3c24xx_uart_port *ourport = dev_id;
 554         struct uart_port *port = &ourport->port;
 555         struct s3c24xx_uart_dma *dma = ourport->dma;
 556         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 557         struct tty_port *t = &port->state->port;
 558         unsigned long flags;
 559         struct dma_tx_state state;
 560
 561         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 562         ufstat = rd_regl(port, S3C2410_UFSTAT);
 563
 564         spin_lock_irqsave(&port->lock, flags);
 565
 566         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 567                 s3c64xx_start_rx_dma(ourport);
 568                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 569                         enable_rx_dma(ourport);
 570                 goto finish;
 571         }
 572
 573         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 574                 dmaengine_pause(dma->rx_chan);
 575                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 576                 dmaengine_terminate_all(dma->rx_chan);
 577                 received = dma->rx_bytes_requested - state.residue;
 578                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 579
 580                 enable_rx_pio(ourport);
 581         }
 582
 583         s3c24xx_serial_rx_drain_fifo(ourport);
 584
 585         if (tty) {
 586                 tty_flip_buffer_push(t);
 587                 tty_kref_put(tty);
 588         }
 589
 590         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 591
 592 finish:
 593         spin_unlock_irqrestore(&port->lock, flags);
 594
 595         return IRQ_HANDLED;
 596 }
 597
 598 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 599 {
 600         struct uart_port *port = &ourport->port;
 601         unsigned int ufcon, ch, flag, ufstat, uerstat;
 602         unsigned int fifocnt = 0;
 603         int max_count = port->fifosize;
 604
 605         while (max_count-- > 0) {
 606                 /*
 607                  * Receive all characters known to be in FIFO
 608                  * before reading FIFO level again
 609                  */
 610                 if (fifocnt == 0) {
 611                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 612                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 613                         if (fifocnt == 0)
 614                                 break;
 615                 }
 616                 fifocnt--;
 617
 618                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 619                 ch = rd_regb(port, S3C2410_URXH);
 620
 621                 if (port->flags & UPF_CONS_FLOW) {
 622                         int txe = s3c24xx_serial_txempty_nofifo(port);
 623
 624                         if (rx_enabled(port)) {
 625                                 if (!txe) {
 626                                         rx_enabled(port) = 0;
 627                                         continue;
 628                                 }
 629                         } else {
 630                                 if (txe) {
 631                                         ufcon = rd_regl(port, S3C2410_UFCON);
 632                                         ufcon |= S3C2410_UFCON_RESETRX;
 633                                         wr_regl(port, S3C2410_UFCON, ufcon);
 634                                         rx_enabled(port) = 1;
 635                                         return;
 636                                 }
 637                                 continue;
 638                         }
 639                 }
 640
 641                 /* insert the character into the buffer */
 642
 643                 flag = TTY_NORMAL;
 644                 port->icount.rx++;
 645
 646                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 647                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 648                             ch, uerstat);
 649
 650                         /* check for break */
 651                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 652                                 dbg("break!\n");
 653                                 port->icount.brk++;
 654                                 if (uart_handle_break(port))
 655                                         continue; /* Ignore character */
 656                         }
 657
 658                         if (uerstat & S3C2410_UERSTAT_FRAME)
 659                                 port->icount.frame++;
 660                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 661                                 port->icount.overrun++;
 662
 663                         uerstat &= port->read_status_mask;
 664
 665                         if (uerstat & S3C2410_UERSTAT_BREAK)
 666                                 flag = TTY_BREAK;
 667                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 668                                 flag = TTY_PARITY;
 669                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 670                                             S3C2410_UERSTAT_OVERRUN))
 671                                 flag = TTY_FRAME;
 672                 }
 673
 674                 if (uart_handle_sysrq_char(port, ch))
 675                         continue; /* Ignore character */
 676
 677                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 678                                  ch, flag);
 679         }
 680
 681         tty_flip_buffer_push(&port->state->port);
 682 }
 683
 684 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 685 {
 686         struct s3c24xx_uart_port *ourport = dev_id;
 687         struct uart_port *port = &ourport->port;
 688         unsigned long flags;
 689
 690         spin_lock_irqsave(&port->lock, flags);
 691         s3c24xx_serial_rx_drain_fifo(ourport);
 692         spin_unlock_irqrestore(&port->lock, flags);
 693
 694         return IRQ_HANDLED;
 695 }
 696
 697
 698 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 699 {
 700         struct s3c24xx_uart_port *ourport = dev_id;
 701
 702         if (ourport->dma && ourport->dma->rx_chan)
 703                 return s3c24xx_serial_rx_chars_dma(dev_id);
 704         return s3c24xx_serial_rx_chars_pio(dev_id);
 705 }
 706
 707 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 708 {
 709         struct s3c24xx_uart_port *ourport = id;
 710         struct uart_port *port = &ourport->port;
 711         struct circ_buf *xmit = &port->state->xmit;
 712         unsigned long flags;
 713         int count, dma_count = 0;
 714
 715         spin_lock_irqsave(&port->lock, flags);
 716
 717         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 718
 719         if (ourport->dma && ourport->dma->tx_chan &&
 720             count >= ourport->min_dma_size) {
 721                 int align = dma_get_cache_alignment() -
 722                         (xmit->tail & (dma_get_cache_alignment() - 1));
 723                 if (count-align >= ourport->min_dma_size) {
 724                         dma_count = count-align;
 725                         count = align;
 726                 }
 727         }
 728
 729         if (port->x_char) {
 730                 wr_regb(port, S3C2410_UTXH, port->x_char);
 731                 port->icount.tx++;
 732                 port->x_char = 0;
 733                 goto out;
 734         }
 735
 736         /* if there isn't anything more to transmit, or the uart is now
 737          * stopped, disable the uart and exit
 738         */
 739
 740         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 741                 s3c24xx_serial_stop_tx(port);
 742                 goto out;
 743         }
 744
 745         /* try and drain the buffer... */
 746
 747         if (count > port->fifosize) {
 748                 count = port->fifosize;
 749                 dma_count = 0;
 750         }
 751
 752         while (!uart_circ_empty(xmit) && count > 0) {
 753                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 754                         break;
 755
 756                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 757                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 758                 port->icount.tx++;
 759                 count--;
 760         }
 761
 762         if (!count && dma_count) {
 763                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 764                 goto out;
 765         }
 766
 767         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 768                 spin_unlock(&port->lock);
 769                 uart_write_wakeup(port);
 770                 spin_lock(&port->lock);
 771         }
 772
 773         if (uart_circ_empty(xmit))
 774                 s3c24xx_serial_stop_tx(port);
 775
 776 out:
 777         spin_unlock_irqrestore(&port->lock, flags);
 778         return IRQ_HANDLED;
 779 }
 780
 781 /* interrupt handler for s3c64xx and later SoC's.*/
 782 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 783 {
 784         struct s3c24xx_uart_port *ourport = id;
 785         struct uart_port *port = &ourport->port;
 786         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 787         irqreturn_t ret = IRQ_HANDLED;
 788
 789         if (pend & S3C64XX_UINTM_RXD_MSK) {
 790                 ret = s3c24xx_serial_rx_chars(irq, id);
 791                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 792         }
 793         if (pend & S3C64XX_UINTM_TXD_MSK) {
 794                 ret = s3c24xx_serial_tx_chars(irq, id);
 795                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 796         }
 797         return ret;
 798 }
 799
 800 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 801 {
 802         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 803         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 804         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 805
 806         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 807                 if ((ufstat & info->tx_fifomask) != 0 ||
 808                     (ufstat & info->tx_fifofull))
 809                         return 0;
 810
 811                 return 1;
 812         }
 813
 814         return s3c24xx_serial_txempty_nofifo(port);
 815 }
 816
 817 /* no modem control lines */
 818 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 819 {
 820         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 821
 822         if (umstat & S3C2410_UMSTAT_CTS)
 823                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 824         else
 825                 return TIOCM_CAR | TIOCM_DSR;
 826 }
 827
 828 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 829 {
 830         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 831
 832         if (mctrl & TIOCM_RTS)
 833                 umcon |= S3C2410_UMCOM_RTS_LOW;
 834         else
 835                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 836
 837         wr_regl(port, S3C2410_UMCON, umcon);
 838 }
 839
 840 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 841 {
 842         unsigned long flags;
 843         unsigned int ucon;
 844
 845         spin_lock_irqsave(&port->lock, flags);
 846
 847         ucon = rd_regl(port, S3C2410_UCON);
 848
 849         if (break_state)
 850                 ucon |= S3C2410_UCON_SBREAK;
 851         else
 852                 ucon &= ~S3C2410_UCON_SBREAK;
 853
 854         wr_regl(port, S3C2410_UCON, ucon);
 855
 856         spin_unlock_irqrestore(&port->lock, flags);
 857 }
 858
 859 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 860 {
 861         struct s3c24xx_uart_dma *dma = p->dma;
 862         unsigned long flags;
 863
 864         /* Default slave configuration parameters */
 865         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 866         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 867         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 868         dma->rx_conf.src_maxburst       = 16;
 869
 870         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 871         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 872         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 873         if (dma_get_cache_alignment() >= 16)
 874                 dma->tx_conf.dst_maxburst = 16;
 875         else
 876                 dma->tx_conf.dst_maxburst = 1;
 877
 878         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 879
 880         if (IS_ERR(dma->rx_chan))
 881                 return PTR_ERR(dma->rx_chan);
 882
 883         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 884
 885         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 886         if (IS_ERR(dma->tx_chan)) {
 887                 dma_release_channel(dma->rx_chan);
 888                 return PTR_ERR(dma->tx_chan);
 889         }
 890
 891         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 892
 893         /* RX buffer */
 894         dma->rx_size = PAGE_SIZE;
 895
 896         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 897
 898         if (!dma->rx_buf) {
 899                 dma_release_channel(dma->rx_chan);
 900                 dma_release_channel(dma->tx_chan);
 901                 return -ENOMEM;
 902         }
 903
 904         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
 905                                 dma->rx_size, DMA_FROM_DEVICE);
 906
 907         spin_lock_irqsave(&p->port.lock, flags);
 908
 909         /* TX buffer */
 910         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
 911                                 p->port.state->xmit.buf,
 912                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 913
 914         spin_unlock_irqrestore(&p->port.lock, flags);
 915
 916         return 0;
 917 }
 918
 919 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 920 {
 921         struct s3c24xx_uart_dma *dma = p->dma;
 922
 923         if (dma->rx_chan) {
 924                 dmaengine_terminate_all(dma->rx_chan);
 925                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
 926                                 dma->rx_size, DMA_FROM_DEVICE);
 927                 kfree(dma->rx_buf);
 928                 dma_release_channel(dma->rx_chan);
 929                 dma->rx_chan = NULL;
 930         }
 931
 932         if (dma->tx_chan) {
 933                 dmaengine_terminate_all(dma->tx_chan);
 934                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
 935                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 936                 dma_release_channel(dma->tx_chan);
 937                 dma->tx_chan = NULL;
 938         }
 939 }
 940
 941 static void s3c24xx_serial_shutdown(struct uart_port *port)
 942 {
 943         struct s3c24xx_uart_port *ourport = to_ourport(port);
 944
 945         if (ourport->tx_claimed) {
 946                 if (!s3c24xx_serial_has_interrupt_mask(port))
 947                         free_irq(ourport->tx_irq, ourport);
 948                 tx_enabled(port) = 0;
 949                 ourport->tx_claimed = 0;
 950                 ourport->tx_mode = 0;
 951         }
 952
 953         if (ourport->rx_claimed) {
 954                 if (!s3c24xx_serial_has_interrupt_mask(port))
 955                         free_irq(ourport->rx_irq, ourport);
 956                 ourport->rx_claimed = 0;
 957                 rx_enabled(port) = 0;
 958         }
 959
 960         /* Clear pending interrupts and mask all interrupts */
 961         if (s3c24xx_serial_has_interrupt_mask(port)) {
 962                 free_irq(port->irq, ourport);
 963
 964                 wr_regl(port, S3C64XX_UINTP, 0xf);
 965                 wr_regl(port, S3C64XX_UINTM, 0xf);
 966         }
 967
 968         if (ourport->dma)
 969                 s3c24xx_serial_release_dma(ourport);
 970
 971         ourport->tx_in_progress = 0;
 972 }
 973
 974 static int s3c24xx_serial_startup(struct uart_port *port)
 975 {
 976         struct s3c24xx_uart_port *ourport = to_ourport(port);
 977         int ret;
 978
 979         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 980             port, (unsigned long long)port->mapbase, port->membase);
 981
 982         rx_enabled(port) = 1;
 983
 984         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 985                           s3c24xx_serial_portname(port), ourport);
 986
 987         if (ret != 0) {
 988                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 989                 return ret;
 990         }
 991
 992         ourport->rx_claimed = 1;
 993
 994         dbg("requesting tx irq...\n");
 995
 996         tx_enabled(port) = 1;
 997
 998         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
 999                           s3c24xx_serial_portname(port), ourport);
1000
1001         if (ret) {
1002                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1003                 goto err;
1004         }
1005
1006         ourport->tx_claimed = 1;
1007
1008         dbg("s3c24xx_serial_startup ok\n");
1009
1010         /* the port reset code should have done the correct
1011          * register setup for the port controls */
1012
1013         return ret;
1014
1015 err:
1016         s3c24xx_serial_shutdown(port);
1017         return ret;
1018 }
1019
1020 static int s3c64xx_serial_startup(struct uart_port *port)
1021 {
1022         struct s3c24xx_uart_port *ourport = to_ourport(port);
1023         unsigned long flags;
1024         unsigned int ufcon;
1025         int ret;
1026
1027         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1028             port, (unsigned long long)port->mapbase, port->membase);
1029
1030         wr_regl(port, S3C64XX_UINTM, 0xf);
1031         if (ourport->dma) {
1032                 ret = s3c24xx_serial_request_dma(ourport);
1033                 if (ret < 0) {
1034                         dev_warn(port->dev, "DMA request failed\n");
1035                         return ret;
1036                 }
1037         }
1038
1039         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1040                           s3c24xx_serial_portname(port), ourport);
1041         if (ret) {
1042                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1043                 return ret;
1044         }
1045
1046         /* For compatibility with s3c24xx Soc's */
1047         rx_enabled(port) = 1;
1048         ourport->rx_claimed = 1;
1049         tx_enabled(port) = 0;
1050         ourport->tx_claimed = 1;
1051
1052         spin_lock_irqsave(&port->lock, flags);
1053
1054         ufcon = rd_regl(port, S3C2410_UFCON);
1055         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1056         if (!uart_console(port))
1057                 ufcon |= S3C2410_UFCON_RESETTX;
1058         wr_regl(port, S3C2410_UFCON, ufcon);
1059
1060         enable_rx_pio(ourport);
1061
1062         spin_unlock_irqrestore(&port->lock, flags);
1063
1064         /* Enable Rx Interrupt */
1065         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1066
1067         dbg("s3c64xx_serial_startup ok\n");
1068         return ret;
1069 }
1070
1071 /* power power management control */
1072
1073 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1074                               unsigned int old)
1075 {
1076         struct s3c24xx_uart_port *ourport = to_ourport(port);
1077         int timeout = 10000;
1078
1079         ourport->pm_level = level;
1080
1081         switch (level) {
1082         case 3:
1083                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1084                         udelay(100);
1085
1086                 if (!IS_ERR(ourport->baudclk))
1087                         clk_disable_unprepare(ourport->baudclk);
1088
1089                 clk_disable_unprepare(ourport->clk);
1090                 break;
1091
1092         case 0:
1093                 clk_prepare_enable(ourport->clk);
1094
1095                 if (!IS_ERR(ourport->baudclk))
1096                         clk_prepare_enable(ourport->baudclk);
1097
1098                 break;
1099         default:
1100                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1101         }
1102 }
1103
1104 /* baud rate calculation
1105  *
1106  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1107  * of different sources, including the peripheral clock ("pclk") and an
1108  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1109  * with a programmable extra divisor.
1110  *
1111  * The following code goes through the clock sources, and calculates the
1112  * baud clocks (and the resultant actual baud rates) and then tries to
1113  * pick the closest one and select that.
1114  *
1115 */
1116
1117 #define MAX_CLK_NAME_LENGTH 15
1118
1119 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1120 {
1121         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1122         unsigned int ucon;
1123
1124         if (info->num_clks == 1)
1125                 return 0;
1126
1127         ucon = rd_regl(port, S3C2410_UCON);
1128         ucon &= info->clksel_mask;
1129         return ucon >> info->clksel_shift;
1130 }
1131
1132 static void s3c24xx_serial_setsource(struct uart_port *port,
1133                         unsigned int clk_sel)
1134 {
1135         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1136         unsigned int ucon;
1137
1138         if (info->num_clks == 1)
1139                 return;
1140
1141         ucon = rd_regl(port, S3C2410_UCON);
1142         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1143                 return;
1144
1145         ucon &= ~info->clksel_mask;
1146         ucon |= clk_sel << info->clksel_shift;
1147         wr_regl(port, S3C2410_UCON, ucon);
1148 }
1149
1150 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1151                         unsigned int req_baud, struct clk **best_clk,
1152                         unsigned int *clk_num)
1153 {
1154         struct s3c24xx_uart_info *info = ourport->info;
1155         struct clk *clk;
1156         unsigned long rate;
1157         unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1158         char clkname[MAX_CLK_NAME_LENGTH];
1159         int calc_deviation, deviation = (1 << 30) - 1;
1160
1161         clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1162                         ourport->info->def_clk_sel;
1163         for (cnt = 0; cnt < info->num_clks; cnt++) {
1164                 if (!(clk_sel & (1 << cnt)))
1165                         continue;
1166
1167                 sprintf(clkname, "clk_uart_baud%d", cnt);
1168                 clk = clk_get(ourport->port.dev, clkname);
1169                 if (IS_ERR(clk))
1170                         continue;
1171
1172                 rate = clk_get_rate(clk);
1173                 if (!rate)
1174                         continue;
1175
1176                 if (ourport->info->has_divslot) {
1177                         unsigned long div = rate / req_baud;
1178
1179                         /* The UDIVSLOT register on the newer UARTs allows us to
1180                          * get a divisor adjustment of 1/16th on the baud clock.
1181                          *
1182                          * We don't keep the UDIVSLOT value (the 16ths we
1183                          * calculated by not multiplying the baud by 16) as it
1184                          * is easy enough to recalculate.
1185                          */
1186
1187                         quot = div / 16;
1188                         baud = rate / div;
1189                 } else {
1190                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1191                         baud = rate / (quot * 16);
1192                 }
1193                 quot--;
1194
1195                 calc_deviation = req_baud - baud;
1196                 if (calc_deviation < 0)
1197                         calc_deviation = -calc_deviation;
1198
1199                 if (calc_deviation < deviation) {
1200                         *best_clk = clk;
1201                         best_quot = quot;
1202                         *clk_num = cnt;
1203                         deviation = calc_deviation;
1204                 }
1205         }
1206
1207         return best_quot;
1208 }
1209
1210 /* udivslot_table[]
1211  *
1212  * This table takes the fractional value of the baud divisor and gives
1213  * the recommended setting for the UDIVSLOT register.
1214  */
1215 static u16 udivslot_table[16] = {
1216         [0] = 0x0000,
1217         [1] = 0x0080,
1218         [2] = 0x0808,
1219         [3] = 0x0888,
1220         [4] = 0x2222,
1221         [5] = 0x4924,
1222         [6] = 0x4A52,
1223         [7] = 0x54AA,
1224         [8] = 0x5555,
1225         [9] = 0xD555,
1226         [10] = 0xD5D5,
1227         [11] = 0xDDD5,
1228         [12] = 0xDDDD,
1229         [13] = 0xDFDD,
1230         [14] = 0xDFDF,
1231         [15] = 0xFFDF,
1232 };
1233
1234 static void s3c24xx_serial_set_termios(struct uart_port *port,
1235                                        struct ktermios *termios,
1236                                        struct ktermios *old)
1237 {
1238         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1239         struct s3c24xx_uart_port *ourport = to_ourport(port);
1240         struct clk *clk = ERR_PTR(-EINVAL);
1241         unsigned long flags;
1242         unsigned int baud, quot, clk_sel = 0;
1243         unsigned int ulcon;
1244         unsigned int umcon;
1245         unsigned int udivslot = 0;
1246
1247         /*
1248          * We don't support modem control lines.
1249          */
1250         termios->c_cflag &= ~(HUPCL | CMSPAR);
1251         termios->c_cflag |= CLOCAL;
1252
1253         /*
1254          * Ask the core to calculate the divisor for us.
1255          */
1256
1257         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1258         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1259         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1260                 quot = port->custom_divisor;
1261         if (IS_ERR(clk))
1262                 return;
1263
1264         /* check to see if we need  to change clock source */
1265
1266         if (ourport->baudclk != clk) {
1267                 clk_prepare_enable(clk);
1268
1269                 s3c24xx_serial_setsource(port, clk_sel);
1270
1271                 if (!IS_ERR(ourport->baudclk)) {
1272                         clk_disable_unprepare(ourport->baudclk);
1273                         ourport->baudclk = ERR_PTR(-EINVAL);
1274                 }
1275
1276                 ourport->baudclk = clk;
1277                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1278         }
1279
1280         if (ourport->info->has_divslot) {
1281                 unsigned int div = ourport->baudclk_rate / baud;
1282
1283                 if (cfg->has_fracval) {
1284                         udivslot = (div & 15);
1285                         dbg("fracval = %04x\n", udivslot);
1286                 } else {
1287                         udivslot = udivslot_table[div & 15];
1288                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1289                 }
1290         }
1291
1292         switch (termios->c_cflag & CSIZE) {
1293         case CS5:
1294                 dbg("config: 5bits/char\n");
1295                 ulcon = S3C2410_LCON_CS5;
1296                 break;
1297         case CS6:
1298                 dbg("config: 6bits/char\n");
1299                 ulcon = S3C2410_LCON_CS6;
1300                 break;
1301         case CS7:
1302                 dbg("config: 7bits/char\n");
1303                 ulcon = S3C2410_LCON_CS7;
1304                 break;
1305         case CS8:
1306         default:
1307                 dbg("config: 8bits/char\n");
1308                 ulcon = S3C2410_LCON_CS8;
1309                 break;
1310         }
1311
1312         /* preserve original lcon IR settings */
1313         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1314
1315         if (termios->c_cflag & CSTOPB)
1316                 ulcon |= S3C2410_LCON_STOPB;
1317
1318         if (termios->c_cflag & PARENB) {
1319                 if (termios->c_cflag & PARODD)
1320                         ulcon |= S3C2410_LCON_PODD;
1321                 else
1322                         ulcon |= S3C2410_LCON_PEVEN;
1323         } else {
1324                 ulcon |= S3C2410_LCON_PNONE;
1325         }
1326
1327         spin_lock_irqsave(&port->lock, flags);
1328
1329         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1330             ulcon, quot, udivslot);
1331
1332         wr_regl(port, S3C2410_ULCON, ulcon);
1333         wr_regl(port, S3C2410_UBRDIV, quot);
1334
1335         umcon = rd_regl(port, S3C2410_UMCON);
1336         if (termios->c_cflag & CRTSCTS) {
1337                 umcon |= S3C2410_UMCOM_AFC;
1338                 /* Disable RTS when RX FIFO contains 63 bytes */
1339                 umcon &= ~S3C2412_UMCON_AFC_8;
1340         } else {
1341                 umcon &= ~S3C2410_UMCOM_AFC;
1342         }
1343         wr_regl(port, S3C2410_UMCON, umcon);
1344
1345         if (ourport->info->has_divslot)
1346                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1347
1348         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1349             rd_regl(port, S3C2410_ULCON),
1350             rd_regl(port, S3C2410_UCON),
1351             rd_regl(port, S3C2410_UFCON));
1352
1353         /*
1354          * Update the per-port timeout.
1355          */
1356         uart_update_timeout(port, termios->c_cflag, baud);
1357
1358         /*
1359          * Which character status flags are we interested in?
1360          */
1361         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1362         if (termios->c_iflag & INPCK)
1363                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1364                         S3C2410_UERSTAT_PARITY;
1365         /*
1366          * Which character status flags should we ignore?
1367          */
1368         port->ignore_status_mask = 0;
1369         if (termios->c_iflag & IGNPAR)
1370                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1371         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1372                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1373
1374         /*
1375          * Ignore all characters if CREAD is not set.
1376          */
1377         if ((termios->c_cflag & CREAD) == 0)
1378                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1379
1380         spin_unlock_irqrestore(&port->lock, flags);
1381 }
1382
1383 static const char *s3c24xx_serial_type(struct uart_port *port)
1384 {
1385         switch (port->type) {
1386         case PORT_S3C2410:
1387                 return "S3C2410";
1388         case PORT_S3C2440:
1389                 return "S3C2440";
1390         case PORT_S3C2412:
1391                 return "S3C2412";
1392         case PORT_S3C6400:
1393                 return "S3C6400/10";
1394         default:
1395                 return NULL;
1396         }
1397 }
1398
1399 #define MAP_SIZE (0x100)
1400
1401 static void s3c24xx_serial_release_port(struct uart_port *port)
1402 {
1403         release_mem_region(port->mapbase, MAP_SIZE);
1404 }
1405
1406 static int s3c24xx_serial_request_port(struct uart_port *port)
1407 {
1408         const char *name = s3c24xx_serial_portname(port);
1409         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1410 }
1411
1412 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1413 {
1414         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1415
1416         if (flags & UART_CONFIG_TYPE &&
1417             s3c24xx_serial_request_port(port) == 0)
1418                 port->type = info->type;
1419 }
1420
1421 /*
1422  * verify the new serial_struct (for TIOCSSERIAL).
1423  */
1424 static int
1425 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1426 {
1427         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1428
1429         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1430                 return -EINVAL;
1431
1432         return 0;
1433 }
1434
1435
1436 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1437
1438 static struct console s3c24xx_serial_console;
1439
1440 static int __init s3c24xx_serial_console_init(void)
1441 {
1442         register_console(&s3c24xx_serial_console);
1443         return 0;
1444 }
1445 console_initcall(s3c24xx_serial_console_init);
1446
1447 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1448 #else
1449 #define S3C24XX_SERIAL_CONSOLE NULL
1450 #endif
1451
1452 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1453 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1454 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1455                          unsigned char c);
1456 #endif
1457
1458 static struct uart_ops s3c24xx_serial_ops = {
1459         .pm             = s3c24xx_serial_pm,
1460         .tx_empty       = s3c24xx_serial_tx_empty,
1461         .get_mctrl      = s3c24xx_serial_get_mctrl,
1462         .set_mctrl      = s3c24xx_serial_set_mctrl,
1463         .stop_tx        = s3c24xx_serial_stop_tx,
1464         .start_tx       = s3c24xx_serial_start_tx,
1465         .stop_rx        = s3c24xx_serial_stop_rx,
1466         .break_ctl      = s3c24xx_serial_break_ctl,
1467         .startup        = s3c24xx_serial_startup,
1468         .shutdown       = s3c24xx_serial_shutdown,
1469         .set_termios    = s3c24xx_serial_set_termios,
1470         .type           = s3c24xx_serial_type,
1471         .release_port   = s3c24xx_serial_release_port,
1472         .request_port   = s3c24xx_serial_request_port,
1473         .config_port    = s3c24xx_serial_config_port,
1474         .verify_port    = s3c24xx_serial_verify_port,
1475 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1476         .poll_get_char = s3c24xx_serial_get_poll_char,
1477         .poll_put_char = s3c24xx_serial_put_poll_char,
1478 #endif
1479 };
1480
1481 static struct uart_driver s3c24xx_uart_drv = {
1482         .owner          = THIS_MODULE,
1483         .driver_name    = "s3c2410_serial",
1484         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1485         .cons           = S3C24XX_SERIAL_CONSOLE,
1486         .dev_name       = S3C24XX_SERIAL_NAME,
1487         .major          = S3C24XX_SERIAL_MAJOR,
1488         .minor          = S3C24XX_SERIAL_MINOR,
1489 };
1490
1491 #define __PORT_LOCK_UNLOCKED(i) \
1492         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1493 static struct s3c24xx_uart_port
1494 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1495         [0] = {
1496                 .port = {
1497                         .lock           = __PORT_LOCK_UNLOCKED(0),
1498                         .iotype         = UPIO_MEM,
1499                         .uartclk        = 0,
1500                         .fifosize       = 16,
1501                         .ops            = &s3c24xx_serial_ops,
1502                         .flags          = UPF_BOOT_AUTOCONF,
1503                         .line           = 0,
1504                 }
1505         },
1506         [1] = {
1507                 .port = {
1508                         .lock           = __PORT_LOCK_UNLOCKED(1),
1509                         .iotype         = UPIO_MEM,
1510                         .uartclk        = 0,
1511                         .fifosize       = 16,
1512                         .ops            = &s3c24xx_serial_ops,
1513                         .flags          = UPF_BOOT_AUTOCONF,
1514                         .line           = 1,
1515                 }
1516         },
1517 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1518
1519         [2] = {
1520                 .port = {
1521                         .lock           = __PORT_LOCK_UNLOCKED(2),
1522                         .iotype         = UPIO_MEM,
1523                         .uartclk        = 0,
1524                         .fifosize       = 16,
1525                         .ops            = &s3c24xx_serial_ops,
1526                         .flags          = UPF_BOOT_AUTOCONF,
1527                         .line           = 2,
1528                 }
1529         },
1530 #endif
1531 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1532         [3] = {
1533                 .port = {
1534                         .lock           = __PORT_LOCK_UNLOCKED(3),
1535                         .iotype         = UPIO_MEM,
1536                         .uartclk        = 0,
1537                         .fifosize       = 16,
1538                         .ops            = &s3c24xx_serial_ops,
1539                         .flags          = UPF_BOOT_AUTOCONF,
1540                         .line           = 3,
1541                 }
1542         }
1543 #endif
1544 };
1545 #undef __PORT_LOCK_UNLOCKED
1546
1547 /* s3c24xx_serial_resetport
1548  *
1549  * reset the fifos and other the settings.
1550 */
1551
1552 static void s3c24xx_serial_resetport(struct uart_port *port,
1553                                    struct s3c2410_uartcfg *cfg)
1554 {
1555         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1556         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1557         unsigned int ucon_mask;
1558
1559         ucon_mask = info->clksel_mask;
1560         if (info->type == PORT_S3C2440)
1561                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1562
1563         ucon &= ucon_mask;
1564         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1565
1566         /* reset both fifos */
1567         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1568         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1569
1570         /* some delay is required after fifo reset */
1571         udelay(1);
1572 }
1573
1574
1575 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1576
1577 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1578                                              unsigned long val, void *data)
1579 {
1580         struct s3c24xx_uart_port *port;
1581         struct uart_port *uport;
1582
1583         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1584         uport = &port->port;
1585
1586         /* check to see if port is enabled */
1587
1588         if (port->pm_level != 0)
1589                 return 0;
1590
1591         /* try and work out if the baudrate is changing, we can detect
1592          * a change in rate, but we do not have support for detecting
1593          * a disturbance in the clock-rate over the change.
1594          */
1595
1596         if (IS_ERR(port->baudclk))
1597                 goto exit;
1598
1599         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1600                 goto exit;
1601
1602         if (val == CPUFREQ_PRECHANGE) {
1603                 /* we should really shut the port down whilst the
1604                  * frequency change is in progress. */
1605
1606         } else if (val == CPUFREQ_POSTCHANGE) {
1607                 struct ktermios *termios;
1608                 struct tty_struct *tty;
1609
1610                 if (uport->state == NULL)
1611                         goto exit;
1612
1613                 tty = uport->state->port.tty;
1614
1615                 if (tty == NULL)
1616                         goto exit;
1617
1618                 termios = &tty->termios;
1619
1620                 if (termios == NULL) {
1621                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1622                         goto exit;
1623                 }
1624
1625                 s3c24xx_serial_set_termios(uport, termios, NULL);
1626         }
1627
1628 exit:
1629         return 0;
1630 }
1631
1632 static inline int
1633 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1634 {
1635         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1636
1637         return cpufreq_register_notifier(&port->freq_transition,
1638                                          CPUFREQ_TRANSITION_NOTIFIER);
1639 }
1640
1641 static inline void
1642 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1643 {
1644         cpufreq_unregister_notifier(&port->freq_transition,
1645                                     CPUFREQ_TRANSITION_NOTIFIER);
1646 }
1647
1648 #else
1649 static inline int
1650 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1651 {
1652         return 0;
1653 }
1654
1655 static inline void
1656 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1657 {
1658 }
1659 #endif
1660
1661 /* s3c24xx_serial_init_port
1662  *
1663  * initialise a single serial port from the platform device given
1664  */
1665
1666 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1667                                     struct platform_device *platdev)
1668 {
1669         struct uart_port *port = &ourport->port;
1670         struct s3c2410_uartcfg *cfg = ourport->cfg;
1671         struct resource *res;
1672         int ret;
1673
1674         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1675
1676         if (platdev == NULL)
1677                 return -ENODEV;
1678
1679         if (port->mapbase != 0)
1680                 return -EINVAL;
1681
1682         /* setup info for port */
1683         port->dev       = &platdev->dev;
1684
1685         /* Startup sequence is different for s3c64xx and higher SoC's */
1686         if (s3c24xx_serial_has_interrupt_mask(port))
1687                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1688
1689         port->uartclk = 1;
1690
1691         if (cfg->uart_flags & UPF_CONS_FLOW) {
1692                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1693                 port->flags |= UPF_CONS_FLOW;
1694         }
1695
1696         /* sort our the physical and virtual addresses for each UART */
1697
1698         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1699         if (res == NULL) {
1700                 dev_err(port->dev, "failed to find memory resource for uart\n");
1701                 return -EINVAL;
1702         }
1703
1704         dbg("resource %pR)\n", res);
1705
1706         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1707         if (!port->membase) {
1708                 dev_err(port->dev, "failed to remap controller address\n");
1709                 return -EBUSY;
1710         }
1711
1712         port->mapbase = res->start;
1713         ret = platform_get_irq(platdev, 0);
1714         if (ret < 0)
1715                 port->irq = 0;
1716         else {
1717                 port->irq = ret;
1718                 ourport->rx_irq = ret;
1719                 ourport->tx_irq = ret + 1;
1720         }
1721
1722         ret = platform_get_irq(platdev, 1);
1723         if (ret > 0)
1724                 ourport->tx_irq = ret;
1725         /*
1726          * DMA is currently supported only on DT platforms, if DMA properties
1727          * are specified.
1728          */
1729         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1730                                                      "dmas", NULL)) {
1731                 ourport->dma = devm_kzalloc(port->dev,
1732                                             sizeof(*ourport->dma),
1733                                             GFP_KERNEL);
1734                 if (!ourport->dma) {
1735                         ret = -ENOMEM;
1736                         goto err;
1737                 }
1738         }
1739
1740         ourport->clk    = clk_get(&platdev->dev, "uart");
1741         if (IS_ERR(ourport->clk)) {
1742                 pr_err("%s: Controller clock not found\n",
1743                                 dev_name(&platdev->dev));
1744                 ret = PTR_ERR(ourport->clk);
1745                 goto err;
1746         }
1747
1748         ret = clk_prepare_enable(ourport->clk);
1749         if (ret) {
1750                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1751                 clk_put(ourport->clk);
1752                 goto err;
1753         }
1754
1755         /* Keep all interrupts masked and cleared */
1756         if (s3c24xx_serial_has_interrupt_mask(port)) {
1757                 wr_regl(port, S3C64XX_UINTM, 0xf);
1758                 wr_regl(port, S3C64XX_UINTP, 0xf);
1759                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1760         }
1761
1762         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1763             &port->mapbase, port->membase, port->irq,
1764             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1765
1766         /* reset the fifos (and setup the uart) */
1767         s3c24xx_serial_resetport(port, cfg);
1768
1769         return 0;
1770
1771 err:
1772         port->mapbase = 0;
1773         return ret;
1774 }
1775
1776 /* Device driver serial port probe */
1777
1778 static const struct of_device_id s3c24xx_uart_dt_match[];
1779 static int probe_index;
1780
1781 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1782                         struct platform_device *pdev)
1783 {
1784 #ifdef CONFIG_OF
1785         if (pdev->dev.of_node) {
1786                 const struct of_device_id *match;
1787                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1788                 return (struct s3c24xx_serial_drv_data *)match->data;
1789         }
1790 #endif
1791         return (struct s3c24xx_serial_drv_data *)
1792                         platform_get_device_id(pdev)->driver_data;
1793 }
1794
1795 static int s3c24xx_serial_probe(struct platform_device *pdev)
1796 {
1797         struct device_node *np = pdev->dev.of_node;
1798         struct s3c24xx_uart_port *ourport;
1799         int index = probe_index;
1800         int ret;
1801
1802         if (np) {
1803                 ret = of_alias_get_id(np, "serial");
1804                 if (ret >= 0)
1805                         index = ret;
1806         }
1807
1808         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1809
1810         ourport = &s3c24xx_serial_ports[index];
1811
1812         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1813         if (!ourport->drv_data) {
1814                 dev_err(&pdev->dev, "could not find driver data\n");
1815                 return -ENODEV;
1816         }
1817
1818         ourport->baudclk = ERR_PTR(-EINVAL);
1819         ourport->info = ourport->drv_data->info;
1820         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1821                         dev_get_platdata(&pdev->dev) :
1822                         ourport->drv_data->def_cfg;
1823
1824         if (np)
1825                 of_property_read_u32(np,
1826                         "samsung,uart-fifosize", &ourport->port.fifosize);
1827
1828         if (ourport->drv_data->fifosize[index])
1829                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1830         else if (ourport->info->fifosize)
1831                 ourport->port.fifosize = ourport->info->fifosize;
1832
1833         /*
1834          * DMA transfers must be aligned at least to cache line size,
1835          * so find minimal transfer size suitable for DMA mode
1836          */
1837         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1838                                     dma_get_cache_alignment());
1839
1840         dbg("%s: initialising port %p...\n", __func__, ourport);
1841
1842         ret = s3c24xx_serial_init_port(ourport, pdev);
1843         if (ret < 0)
1844                 return ret;
1845
1846         if (!s3c24xx_uart_drv.state) {
1847                 ret = uart_register_driver(&s3c24xx_uart_drv);
1848                 if (ret < 0) {
1849                         pr_err("Failed to register Samsung UART driver\n");
1850                         return ret;
1851                 }
1852         }
1853
1854         dbg("%s: adding port\n", __func__);
1855         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1856         platform_set_drvdata(pdev, &ourport->port);
1857
1858         /*
1859          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1860          * so that a potential re-enablement through the pm-callback overlaps
1861          * and keeps the clock enabled in this case.
1862          */
1863         clk_disable_unprepare(ourport->clk);
1864
1865         ret = s3c24xx_serial_cpufreq_register(ourport);
1866         if (ret < 0)
1867                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1868
1869         probe_index++;
1870
1871         return 0;
1872 }
1873
1874 static int s3c24xx_serial_remove(struct platform_device *dev)
1875 {
1876         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1877
1878         if (port) {
1879                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1880                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1881         }
1882
1883         uart_unregister_driver(&s3c24xx_uart_drv);
1884
1885         return 0;
1886 }
1887
1888 /* UART power management code */
1889 #ifdef CONFIG_PM_SLEEP
1890 static int s3c24xx_serial_suspend(struct device *dev)
1891 {
1892         struct uart_port *port = s3c24xx_dev_to_port(dev);
1893
1894         if (port)
1895                 uart_suspend_port(&s3c24xx_uart_drv, port);
1896
1897         return 0;
1898 }
1899
1900 static int s3c24xx_serial_resume(struct device *dev)
1901 {
1902         struct uart_port *port = s3c24xx_dev_to_port(dev);
1903         struct s3c24xx_uart_port *ourport = to_ourport(port);
1904
1905         if (port) {
1906                 clk_prepare_enable(ourport->clk);
1907                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1908                 clk_disable_unprepare(ourport->clk);
1909
1910                 uart_resume_port(&s3c24xx_uart_drv, port);
1911         }
1912
1913         return 0;
1914 }
1915
1916 static int s3c24xx_serial_resume_noirq(struct device *dev)
1917 {
1918         struct uart_port *port = s3c24xx_dev_to_port(dev);
1919         struct s3c24xx_uart_port *ourport = to_ourport(port);
1920
1921         if (port) {
1922                 /* restore IRQ mask */
1923                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1924                         unsigned int uintm = 0xf;
1925                         if (tx_enabled(port))
1926                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1927                         if (rx_enabled(port))
1928                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1929                         clk_prepare_enable(ourport->clk);
1930                         wr_regl(port, S3C64XX_UINTM, uintm);
1931                         clk_disable_unprepare(ourport->clk);
1932                 }
1933         }
1934
1935         return 0;
1936 }
1937
1938 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1939         .suspend = s3c24xx_serial_suspend,
1940         .resume = s3c24xx_serial_resume,
1941         .resume_noirq = s3c24xx_serial_resume_noirq,
1942 };
1943 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1944
1945 #else /* !CONFIG_PM_SLEEP */
1946
1947 #define SERIAL_SAMSUNG_PM_OPS   NULL
1948 #endif /* CONFIG_PM_SLEEP */
1949
1950 /* Console code */
1951
1952 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1953
1954 static struct uart_port *cons_uart;
1955
1956 static int
1957 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1958 {
1959         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1960         unsigned long ufstat, utrstat;
1961
1962         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1963                 /* fifo mode - check amount of data in fifo registers... */
1964
1965                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1966                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1967         }
1968
1969         /* in non-fifo mode, we go and use the tx buffer empty */
1970
1971         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1972         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1973 }
1974
1975 static bool
1976 s3c24xx_port_configured(unsigned int ucon)
1977 {
1978         /* consider the serial port configured if the tx/rx mode set */
1979         return (ucon & 0xf) != 0;
1980 }
1981
1982 #ifdef CONFIG_CONSOLE_POLL
1983 /*
1984  * Console polling routines for writing and reading from the uart while
1985  * in an interrupt or debug context.
1986  */
1987
1988 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1989 {
1990         struct s3c24xx_uart_port *ourport = to_ourport(port);
1991         unsigned int ufstat;
1992
1993         ufstat = rd_regl(port, S3C2410_UFSTAT);
1994         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1995                 return NO_POLL_CHAR;
1996
1997         return rd_regb(port, S3C2410_URXH);
1998 }
1999
2000 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2001                 unsigned char c)
2002 {
2003         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2004         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2005
2006         /* not possible to xmit on unconfigured port */
2007         if (!s3c24xx_port_configured(ucon))
2008                 return;
2009
2010         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2011                 cpu_relax();
2012         wr_regb(port, S3C2410_UTXH, c);
2013 }
2014
2015 #endif /* CONFIG_CONSOLE_POLL */
2016
2017 static void
2018 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2019 {
2020         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2021
2022         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2023                 cpu_relax();
2024         wr_regb(port, S3C2410_UTXH, ch);
2025 }
2026
2027 static void
2028 s3c24xx_serial_console_write(struct console *co, const char *s,
2029                              unsigned int count)
2030 {
2031         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2032
2033         /* not possible to xmit on unconfigured port */
2034         if (!s3c24xx_port_configured(ucon))
2035                 return;
2036
2037         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2038 }
2039
2040 static void __init
2041 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2042                            int *parity, int *bits)
2043 {
2044         struct clk *clk;
2045         unsigned int ulcon;
2046         unsigned int ucon;
2047         unsigned int ubrdiv;
2048         unsigned long rate;
2049         unsigned int clk_sel;
2050         char clk_name[MAX_CLK_NAME_LENGTH];
2051
2052         ulcon  = rd_regl(port, S3C2410_ULCON);
2053         ucon   = rd_regl(port, S3C2410_UCON);
2054         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2055
2056         dbg("s3c24xx_serial_get_options: port=%p\n"
2057             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2058             port, ulcon, ucon, ubrdiv);
2059
2060         if (s3c24xx_port_configured(ucon)) {
2061                 switch (ulcon & S3C2410_LCON_CSMASK) {
2062                 case S3C2410_LCON_CS5:
2063                         *bits = 5;
2064                         break;
2065                 case S3C2410_LCON_CS6:
2066                         *bits = 6;
2067                         break;
2068                 case S3C2410_LCON_CS7:
2069                         *bits = 7;
2070                         break;
2071                 case S3C2410_LCON_CS8:
2072                 default:
2073                         *bits = 8;
2074                         break;
2075                 }
2076
2077                 switch (ulcon & S3C2410_LCON_PMASK) {
2078                 case S3C2410_LCON_PEVEN:
2079                         *parity = 'e';
2080                         break;
2081
2082                 case S3C2410_LCON_PODD:
2083                         *parity = 'o';
2084                         break;
2085
2086                 case S3C2410_LCON_PNONE:
2087                 default:
2088                         *parity = 'n';
2089                 }
2090
2091                 /* now calculate the baud rate */
2092
2093                 clk_sel = s3c24xx_serial_getsource(port);
2094                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2095
2096                 clk = clk_get(port->dev, clk_name);
2097                 if (!IS_ERR(clk))
2098                         rate = clk_get_rate(clk);
2099                 else
2100                         rate = 1;
2101
2102                 *baud = rate / (16 * (ubrdiv + 1));
2103                 dbg("calculated baud %d\n", *baud);
2104         }
2105
2106 }
2107
2108 static int __init
2109 s3c24xx_serial_console_setup(struct console *co, char *options)
2110 {
2111         struct uart_port *port;
2112         int baud = 9600;
2113         int bits = 8;
2114         int parity = 'n';
2115         int flow = 'n';
2116
2117         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2118             co, co->index, options);
2119
2120         /* is this a valid port */
2121
2122         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2123                 co->index = 0;
2124
2125         port = &s3c24xx_serial_ports[co->index].port;
2126
2127         /* is the port configured? */
2128
2129         if (port->mapbase == 0x0)
2130                 return -ENODEV;
2131
2132         cons_uart = port;
2133
2134         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2135
2136         /*
2137          * Check whether an invalid uart number has been specified, and
2138          * if so, search for the first available port that does have
2139          * console support.
2140          */
2141         if (options)
2142                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2143         else
2144                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2145
2146         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2147
2148         return uart_set_options(port, co, baud, parity, bits, flow);
2149 }
2150
2151 static struct console s3c24xx_serial_console = {
2152         .name           = S3C24XX_SERIAL_NAME,
2153         .device         = uart_console_device,
2154         .flags          = CON_PRINTBUFFER,
2155         .index          = -1,
2156         .write          = s3c24xx_serial_console_write,
2157         .setup          = s3c24xx_serial_console_setup,
2158         .data           = &s3c24xx_uart_drv,
2159 };
2160 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2161
2162 #ifdef CONFIG_CPU_S3C2410
2163 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2164         .info = &(struct s3c24xx_uart_info) {
2165                 .name           = "Samsung S3C2410 UART",
2166                 .type           = PORT_S3C2410,
2167                 .fifosize       = 16,
2168                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2169                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2170                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2171                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2172                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2173                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2174                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2175                 .num_clks       = 2,
2176                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2177                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2178         },
2179         .def_cfg = &(struct s3c2410_uartcfg) {
2180                 .ucon           = S3C2410_UCON_DEFAULT,
2181                 .ufcon          = S3C2410_UFCON_DEFAULT,
2182         },
2183 };
2184 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2185 #else
2186 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2187 #endif
2188
2189 #ifdef CONFIG_CPU_S3C2412
2190 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2191         .info = &(struct s3c24xx_uart_info) {
2192                 .name           = "Samsung S3C2412 UART",
2193                 .type           = PORT_S3C2412,
2194                 .fifosize       = 64,
2195                 .has_divslot    = 1,
2196                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2197                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2198                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2199                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2200                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2201                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2202                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2203                 .num_clks       = 4,
2204                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2205                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2206         },
2207         .def_cfg = &(struct s3c2410_uartcfg) {
2208                 .ucon           = S3C2410_UCON_DEFAULT,
2209                 .ufcon          = S3C2410_UFCON_DEFAULT,
2210         },
2211 };
2212 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2213 #else
2214 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2215 #endif
2216
2217 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2218         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2219 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2220         .info = &(struct s3c24xx_uart_info) {
2221                 .name           = "Samsung S3C2440 UART",
2222                 .type           = PORT_S3C2440,
2223                 .fifosize       = 64,
2224                 .has_divslot    = 1,
2225                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2226                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2227                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2228                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2229                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2230                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2231                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2232                 .num_clks       = 4,
2233                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2234                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2235         },
2236         .def_cfg = &(struct s3c2410_uartcfg) {
2237                 .ucon           = S3C2410_UCON_DEFAULT,
2238                 .ufcon          = S3C2410_UFCON_DEFAULT,
2239         },
2240 };
2241 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2242 #else
2243 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2244 #endif
2245
2246 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2247 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2248         .info = &(struct s3c24xx_uart_info) {
2249                 .name           = "Samsung S3C6400 UART",
2250                 .type           = PORT_S3C6400,
2251                 .fifosize       = 64,
2252                 .has_divslot    = 1,
2253                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2254                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2255                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2256                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2257                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2258                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2259                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2260                 .num_clks       = 4,
2261                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2262                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2263         },
2264         .def_cfg = &(struct s3c2410_uartcfg) {
2265                 .ucon           = S3C2410_UCON_DEFAULT,
2266                 .ufcon          = S3C2410_UFCON_DEFAULT,
2267         },
2268 };
2269 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2270 #else
2271 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2272 #endif
2273
2274 #ifdef CONFIG_CPU_S5PV210
2275 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2276         .info = &(struct s3c24xx_uart_info) {
2277                 .name           = "Samsung S5PV210 UART",
2278                 .type           = PORT_S3C6400,
2279                 .has_divslot    = 1,
2280                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2281                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2282                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2283                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2284                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2285                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2286                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2287                 .num_clks       = 2,
2288                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2289                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2290         },
2291         .def_cfg = &(struct s3c2410_uartcfg) {
2292                 .ucon           = S5PV210_UCON_DEFAULT,
2293                 .ufcon          = S5PV210_UFCON_DEFAULT,
2294         },
2295         .fifosize = { 256, 64, 16, 16 },
2296 };
2297 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2298 #else
2299 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2300 #endif
2301
2302 #if defined(CONFIG_ARCH_EXYNOS)
2303 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2304         .info = &(struct s3c24xx_uart_info) {                   \
2305                 .name           = "Samsung Exynos UART",        \
2306                 .type           = PORT_S3C6400,                 \
2307                 .has_divslot    = 1,                            \
2308                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2309                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2310                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2311                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2312                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2313                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2314                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2315                 .num_clks       = 1,                            \
2316                 .clksel_mask    = 0,                            \
2317                 .clksel_shift   = 0,                            \
2318         },                                                      \
2319         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2320                 .ucon           = S5PV210_UCON_DEFAULT,         \
2321                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2322                 .has_fracval    = 1,                            \
2323         }                                                       \
2324
2325 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2326         EXYNOS_COMMON_SERIAL_DRV_DATA,
2327         .fifosize = { 256, 64, 16, 16 },
2328 };
2329
2330 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2331         EXYNOS_COMMON_SERIAL_DRV_DATA,
2332         .fifosize = { 64, 256, 16, 256 },
2333 };
2334
2335 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2336 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2337 #else
2338 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2339 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2340 #endif
2341
2342 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2343         {
2344                 .name           = "s3c2410-uart",
2345                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2346         }, {
2347                 .name           = "s3c2412-uart",
2348                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2349         }, {
2350                 .name           = "s3c2440-uart",
2351                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2352         }, {
2353                 .name           = "s3c6400-uart",
2354                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2355         }, {
2356                 .name           = "s5pv210-uart",
2357                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2358         }, {
2359                 .name           = "exynos4210-uart",
2360                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2361         }, {
2362                 .name           = "exynos5433-uart",
2363                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2364         },
2365         { },
2366 };
2367 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2368
2369 #ifdef CONFIG_OF
2370 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2371         { .compatible = "samsung,s3c2410-uart",
2372                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2373         { .compatible = "samsung,s3c2412-uart",
2374                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2375         { .compatible = "samsung,s3c2440-uart",
2376                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2377         { .compatible = "samsung,s3c6400-uart",
2378                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2379         { .compatible = "samsung,s5pv210-uart",
2380                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2381         { .compatible = "samsung,exynos4210-uart",
2382                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2383         { .compatible = "samsung,exynos5433-uart",
2384                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2385         {},
2386 };
2387 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2388 #endif
2389
2390 static struct platform_driver samsung_serial_driver = {
2391         .probe          = s3c24xx_serial_probe,
2392         .remove         = s3c24xx_serial_remove,
2393         .id_table       = s3c24xx_serial_driver_ids,
2394         .driver         = {
2395                 .name   = "samsung-uart",
2396                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2397                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2398         },
2399 };
2400
2401 module_platform_driver(samsung_serial_driver);
2402
2403 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2404 /*
2405  * Early console.
2406  */
2407
2408 struct samsung_early_console_data {
2409         u32 txfull_mask;
2410 };
2411
2412 static void samsung_early_busyuart(struct uart_port *port)
2413 {
2414         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2415                 ;
2416 }
2417
2418 static void samsung_early_busyuart_fifo(struct uart_port *port)
2419 {
2420         struct samsung_early_console_data *data = port->private_data;
2421
2422         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2423                 ;
2424 }
2425
2426 static void samsung_early_putc(struct uart_port *port, int c)
2427 {
2428         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2429                 samsung_early_busyuart_fifo(port);
2430         else
2431                 samsung_early_busyuart(port);
2432
2433         writeb(c, port->membase + S3C2410_UTXH);
2434 }
2435
2436 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2437 {
2438         struct earlycon_device *dev = con->data;
2439
2440         uart_console_write(&dev->port, s, n, samsung_early_putc);
2441 }
2442
2443 static int __init samsung_early_console_setup(struct earlycon_device *device,
2444                                               const char *opt)
2445 {
2446         if (!device->port.membase)
2447                 return -ENODEV;
2448
2449         device->con->write = samsung_early_write;
2450         return 0;
2451 }
2452
2453 /* S3C2410 */
2454 static struct samsung_early_console_data s3c2410_early_console_data = {
2455         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2456 };
2457
2458 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2459                                               const char *opt)
2460 {
2461         device->port.private_data = &s3c2410_early_console_data;
2462         return samsung_early_console_setup(device, opt);
2463 }
2464 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2465                         s3c2410_early_console_setup);
2466
2467 /* S3C2412, S3C2440, S3C64xx */
2468 static struct samsung_early_console_data s3c2440_early_console_data = {
2469         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2470 };
2471
2472 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2473                                               const char *opt)
2474 {
2475         device->port.private_data = &s3c2440_early_console_data;
2476         return samsung_early_console_setup(device, opt);
2477 }
2478 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2479                         s3c2440_early_console_setup);
2480 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2481                         s3c2440_early_console_setup);
2482 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2483                         s3c2440_early_console_setup);
2484
2485 /* S5PV210, EXYNOS */
2486 static struct samsung_early_console_data s5pv210_early_console_data = {
2487         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2488 };
2489
2490 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2491                                               const char *opt)
2492 {
2493         device->port.private_data = &s5pv210_early_console_data;
2494         return samsung_early_console_setup(device, opt);
2495 }
2496 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2497                         s5pv210_early_console_setup);
2498 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2499                         s5pv210_early_console_setup);
2500 #endif
2501
2502 MODULE_ALIAS("platform:samsung-uart");
2503 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2504 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2505 MODULE_LICENSE("GPL v2");