2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
56 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
57 defined(CONFIG_DEBUG_LL) && \
60 extern void printascii(const char *);
63 static void dbg(const char *fmt, ...)
69 vscnprintf(buff, sizeof(buff), fmt, va);
76 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
79 /* UART name and device definitions */
81 #define S3C24XX_SERIAL_NAME "ttySAC"
82 #define S3C24XX_SERIAL_MAJOR 204
83 #define S3C24XX_SERIAL_MINOR 64
85 /* macros to change one thing to another */
87 #define tx_enabled(port) ((port)->unused[0])
88 #define rx_enabled(port) ((port)->unused[1])
90 /* flag to ignore all characters coming in */
91 #define RXSTAT_DUMMY_READ (0x10000000)
93 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
95 return container_of(port, struct s3c24xx_uart_port, port);
98 /* translate a port to the device name */
100 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
102 return to_platform_device(port->dev)->name;
105 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
107 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
111 * s3c64xx and later SoC's include the interrupt mask and status registers in
112 * the controller itself, unlike the s3c24xx SoC's which have these registers
113 * in the interrupt controller. Check if the port type is s3c64xx or higher.
115 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
117 return to_ourport(port)->info->type == PORT_S3C6400;
120 static void s3c24xx_serial_rx_enable(struct uart_port *port)
123 unsigned int ucon, ufcon;
126 spin_lock_irqsave(&port->lock, flags);
128 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 ufcon = rd_regl(port, S3C2410_UFCON);
132 ufcon |= S3C2410_UFCON_RESETRX;
133 wr_regl(port, S3C2410_UFCON, ufcon);
135 ucon = rd_regl(port, S3C2410_UCON);
136 ucon |= S3C2410_UCON_RXIRQMODE;
137 wr_regl(port, S3C2410_UCON, ucon);
139 rx_enabled(port) = 1;
140 spin_unlock_irqrestore(&port->lock, flags);
143 static void s3c24xx_serial_rx_disable(struct uart_port *port)
148 spin_lock_irqsave(&port->lock, flags);
150 ucon = rd_regl(port, S3C2410_UCON);
151 ucon &= ~S3C2410_UCON_RXIRQMODE;
152 wr_regl(port, S3C2410_UCON, ucon);
154 rx_enabled(port) = 0;
155 spin_unlock_irqrestore(&port->lock, flags);
158 static void s3c24xx_serial_stop_tx(struct uart_port *port)
160 struct s3c24xx_uart_port *ourport = to_ourport(port);
162 if (tx_enabled(port)) {
163 if (s3c24xx_serial_has_interrupt_mask(port))
164 __set_bit(S3C64XX_UINTM_TXD,
165 portaddrl(port, S3C64XX_UINTM));
167 disable_irq_nosync(ourport->tx_irq);
168 tx_enabled(port) = 0;
169 if (port->flags & UPF_CONS_FLOW)
170 s3c24xx_serial_rx_enable(port);
174 static void s3c24xx_serial_start_tx(struct uart_port *port)
176 struct s3c24xx_uart_port *ourport = to_ourport(port);
178 if (!tx_enabled(port)) {
179 if (port->flags & UPF_CONS_FLOW)
180 s3c24xx_serial_rx_disable(port);
182 if (s3c24xx_serial_has_interrupt_mask(port))
183 __clear_bit(S3C64XX_UINTM_TXD,
184 portaddrl(port, S3C64XX_UINTM));
186 enable_irq(ourport->tx_irq);
187 tx_enabled(port) = 1;
191 static void s3c24xx_serial_stop_rx(struct uart_port *port)
193 struct s3c24xx_uart_port *ourport = to_ourport(port);
195 if (rx_enabled(port)) {
196 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
197 if (s3c24xx_serial_has_interrupt_mask(port))
198 __set_bit(S3C64XX_UINTM_RXD,
199 portaddrl(port, S3C64XX_UINTM));
201 disable_irq_nosync(ourport->rx_irq);
202 rx_enabled(port) = 0;
206 static void s3c24xx_serial_enable_ms(struct uart_port *port)
210 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
212 return to_ourport(port)->info;
215 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
217 struct s3c24xx_uart_port *ourport;
219 if (port->dev == NULL)
222 ourport = container_of(port, struct s3c24xx_uart_port, port);
226 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
227 unsigned long ufstat)
229 struct s3c24xx_uart_info *info = ourport->info;
231 if (ufstat & info->rx_fifofull)
232 return ourport->port.fifosize;
234 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
238 /* ? - where has parity gone?? */
239 #define S3C2410_UERSTAT_PARITY (0x1000)
242 s3c24xx_serial_rx_chars(int irq, void *dev_id)
244 struct s3c24xx_uart_port *ourport = dev_id;
245 struct uart_port *port = &ourport->port;
246 unsigned int ufcon, ch, flag, ufstat, uerstat;
250 spin_lock_irqsave(&port->lock, flags);
252 while (max_count-- > 0) {
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufstat = rd_regl(port, S3C2410_UFSTAT);
256 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
259 uerstat = rd_regl(port, S3C2410_UERSTAT);
260 ch = rd_regb(port, S3C2410_URXH);
262 if (port->flags & UPF_CONS_FLOW) {
263 int txe = s3c24xx_serial_txempty_nofifo(port);
265 if (rx_enabled(port)) {
267 rx_enabled(port) = 0;
272 ufcon |= S3C2410_UFCON_RESETRX;
273 wr_regl(port, S3C2410_UFCON, ufcon);
274 rx_enabled(port) = 1;
275 spin_unlock_irqrestore(&port->lock,
283 /* insert the character into the buffer */
288 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
289 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
292 /* check for break */
293 if (uerstat & S3C2410_UERSTAT_BREAK) {
296 if (uart_handle_break(port))
300 if (uerstat & S3C2410_UERSTAT_FRAME)
301 port->icount.frame++;
302 if (uerstat & S3C2410_UERSTAT_OVERRUN)
303 port->icount.overrun++;
305 uerstat &= port->read_status_mask;
307 if (uerstat & S3C2410_UERSTAT_BREAK)
309 else if (uerstat & S3C2410_UERSTAT_PARITY)
311 else if (uerstat & (S3C2410_UERSTAT_FRAME |
312 S3C2410_UERSTAT_OVERRUN))
316 if (uart_handle_sysrq_char(port, ch))
319 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
326 spin_unlock_irqrestore(&port->lock, flags);
327 tty_flip_buffer_push(&port->state->port);
333 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
335 struct s3c24xx_uart_port *ourport = id;
336 struct uart_port *port = &ourport->port;
337 struct circ_buf *xmit = &port->state->xmit;
341 spin_lock_irqsave(&port->lock, flags);
344 wr_regb(port, S3C2410_UTXH, port->x_char);
350 /* if there isn't anything more to transmit, or the uart is now
351 * stopped, disable the uart and exit
354 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
355 s3c24xx_serial_stop_tx(port);
359 /* try and drain the buffer... */
361 while (!uart_circ_empty(xmit) && count-- > 0) {
362 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
365 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
366 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
370 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
371 spin_unlock(&port->lock);
372 uart_write_wakeup(port);
373 spin_lock(&port->lock);
376 if (uart_circ_empty(xmit))
377 s3c24xx_serial_stop_tx(port);
380 spin_unlock_irqrestore(&port->lock, flags);
384 /* interrupt handler for s3c64xx and later SoC's.*/
385 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
387 struct s3c24xx_uart_port *ourport = id;
388 struct uart_port *port = &ourport->port;
389 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
390 irqreturn_t ret = IRQ_HANDLED;
392 if (pend & S3C64XX_UINTM_RXD_MSK) {
393 ret = s3c24xx_serial_rx_chars(irq, id);
394 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
396 if (pend & S3C64XX_UINTM_TXD_MSK) {
397 ret = s3c24xx_serial_tx_chars(irq, id);
398 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
403 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
405 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
406 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
407 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
409 if (ufcon & S3C2410_UFCON_FIFOMODE) {
410 if ((ufstat & info->tx_fifomask) != 0 ||
411 (ufstat & info->tx_fifofull))
417 return s3c24xx_serial_txempty_nofifo(port);
420 /* no modem control lines */
421 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
423 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
425 if (umstat & S3C2410_UMSTAT_CTS)
426 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
428 return TIOCM_CAR | TIOCM_DSR;
431 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
433 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
435 if (mctrl & TIOCM_RTS)
436 umcon |= S3C2410_UMCOM_RTS_LOW;
438 umcon &= ~S3C2410_UMCOM_RTS_LOW;
440 wr_regl(port, S3C2410_UMCON, umcon);
443 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
448 spin_lock_irqsave(&port->lock, flags);
450 ucon = rd_regl(port, S3C2410_UCON);
453 ucon |= S3C2410_UCON_SBREAK;
455 ucon &= ~S3C2410_UCON_SBREAK;
457 wr_regl(port, S3C2410_UCON, ucon);
459 spin_unlock_irqrestore(&port->lock, flags);
462 static void s3c24xx_serial_shutdown(struct uart_port *port)
464 struct s3c24xx_uart_port *ourport = to_ourport(port);
466 if (ourport->tx_claimed) {
467 if (!s3c24xx_serial_has_interrupt_mask(port))
468 free_irq(ourport->tx_irq, ourport);
469 tx_enabled(port) = 0;
470 ourport->tx_claimed = 0;
473 if (ourport->rx_claimed) {
474 if (!s3c24xx_serial_has_interrupt_mask(port))
475 free_irq(ourport->rx_irq, ourport);
476 ourport->rx_claimed = 0;
477 rx_enabled(port) = 0;
480 /* Clear pending interrupts and mask all interrupts */
481 if (s3c24xx_serial_has_interrupt_mask(port)) {
482 free_irq(port->irq, ourport);
484 wr_regl(port, S3C64XX_UINTP, 0xf);
485 wr_regl(port, S3C64XX_UINTM, 0xf);
489 static int s3c24xx_serial_startup(struct uart_port *port)
491 struct s3c24xx_uart_port *ourport = to_ourport(port);
494 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
495 port, (unsigned long long)port->mapbase, port->membase);
497 rx_enabled(port) = 1;
499 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
500 s3c24xx_serial_portname(port), ourport);
503 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
507 ourport->rx_claimed = 1;
509 dbg("requesting tx irq...\n");
511 tx_enabled(port) = 1;
513 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
514 s3c24xx_serial_portname(port), ourport);
517 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
521 ourport->tx_claimed = 1;
523 dbg("s3c24xx_serial_startup ok\n");
525 /* the port reset code should have done the correct
526 * register setup for the port controls */
531 s3c24xx_serial_shutdown(port);
535 static int s3c64xx_serial_startup(struct uart_port *port)
537 struct s3c24xx_uart_port *ourport = to_ourport(port);
540 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
541 port, (unsigned long long)port->mapbase, port->membase);
543 wr_regl(port, S3C64XX_UINTM, 0xf);
545 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
546 s3c24xx_serial_portname(port), ourport);
548 dev_err(port->dev, "cannot get irq %d\n", port->irq);
552 /* For compatibility with s3c24xx Soc's */
553 rx_enabled(port) = 1;
554 ourport->rx_claimed = 1;
555 tx_enabled(port) = 0;
556 ourport->tx_claimed = 1;
558 /* Enable Rx Interrupt */
559 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
560 dbg("s3c64xx_serial_startup ok\n");
564 /* power power management control */
566 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
569 struct s3c24xx_uart_port *ourport = to_ourport(port);
571 ourport->pm_level = level;
575 if (!IS_ERR(ourport->baudclk))
576 clk_disable_unprepare(ourport->baudclk);
578 clk_disable_unprepare(ourport->clk);
582 clk_prepare_enable(ourport->clk);
584 if (!IS_ERR(ourport->baudclk))
585 clk_prepare_enable(ourport->baudclk);
589 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
593 /* baud rate calculation
595 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
596 * of different sources, including the peripheral clock ("pclk") and an
597 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
598 * with a programmable extra divisor.
600 * The following code goes through the clock sources, and calculates the
601 * baud clocks (and the resultant actual baud rates) and then tries to
602 * pick the closest one and select that.
606 #define MAX_CLK_NAME_LENGTH 15
608 static inline int s3c24xx_serial_getsource(struct uart_port *port)
610 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
613 if (info->num_clks == 1)
616 ucon = rd_regl(port, S3C2410_UCON);
617 ucon &= info->clksel_mask;
618 return ucon >> info->clksel_shift;
621 static void s3c24xx_serial_setsource(struct uart_port *port,
622 unsigned int clk_sel)
624 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
627 if (info->num_clks == 1)
630 ucon = rd_regl(port, S3C2410_UCON);
631 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
634 ucon &= ~info->clksel_mask;
635 ucon |= clk_sel << info->clksel_shift;
636 wr_regl(port, S3C2410_UCON, ucon);
639 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
640 unsigned int req_baud, struct clk **best_clk,
641 unsigned int *clk_num)
643 struct s3c24xx_uart_info *info = ourport->info;
646 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
647 char clkname[MAX_CLK_NAME_LENGTH];
648 int calc_deviation, deviation = (1 << 30) - 1;
650 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
651 ourport->info->def_clk_sel;
652 for (cnt = 0; cnt < info->num_clks; cnt++) {
653 if (!(clk_sel & (1 << cnt)))
656 sprintf(clkname, "clk_uart_baud%d", cnt);
657 clk = clk_get(ourport->port.dev, clkname);
661 rate = clk_get_rate(clk);
665 if (ourport->info->has_divslot) {
666 unsigned long div = rate / req_baud;
668 /* The UDIVSLOT register on the newer UARTs allows us to
669 * get a divisor adjustment of 1/16th on the baud clock.
671 * We don't keep the UDIVSLOT value (the 16ths we
672 * calculated by not multiplying the baud by 16) as it
673 * is easy enough to recalculate.
679 quot = (rate + (8 * req_baud)) / (16 * req_baud);
680 baud = rate / (quot * 16);
684 calc_deviation = req_baud - baud;
685 if (calc_deviation < 0)
686 calc_deviation = -calc_deviation;
688 if (calc_deviation < deviation) {
692 deviation = calc_deviation;
701 * This table takes the fractional value of the baud divisor and gives
702 * the recommended setting for the UDIVSLOT register.
704 static u16 udivslot_table[16] = {
723 static void s3c24xx_serial_set_termios(struct uart_port *port,
724 struct ktermios *termios,
725 struct ktermios *old)
727 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
728 struct s3c24xx_uart_port *ourport = to_ourport(port);
729 struct clk *clk = ERR_PTR(-EINVAL);
731 unsigned int baud, quot, clk_sel = 0;
734 unsigned int udivslot = 0;
737 * We don't support modem control lines.
739 termios->c_cflag &= ~(HUPCL | CMSPAR);
740 termios->c_cflag |= CLOCAL;
743 * Ask the core to calculate the divisor for us.
746 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
747 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
748 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
749 quot = port->custom_divisor;
753 /* check to see if we need to change clock source */
755 if (ourport->baudclk != clk) {
756 s3c24xx_serial_setsource(port, clk_sel);
758 if (!IS_ERR(ourport->baudclk)) {
759 clk_disable_unprepare(ourport->baudclk);
760 ourport->baudclk = ERR_PTR(-EINVAL);
763 clk_prepare_enable(clk);
765 ourport->baudclk = clk;
766 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
769 if (ourport->info->has_divslot) {
770 unsigned int div = ourport->baudclk_rate / baud;
772 if (cfg->has_fracval) {
773 udivslot = (div & 15);
774 dbg("fracval = %04x\n", udivslot);
776 udivslot = udivslot_table[div & 15];
777 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
781 switch (termios->c_cflag & CSIZE) {
783 dbg("config: 5bits/char\n");
784 ulcon = S3C2410_LCON_CS5;
787 dbg("config: 6bits/char\n");
788 ulcon = S3C2410_LCON_CS6;
791 dbg("config: 7bits/char\n");
792 ulcon = S3C2410_LCON_CS7;
796 dbg("config: 8bits/char\n");
797 ulcon = S3C2410_LCON_CS8;
801 /* preserve original lcon IR settings */
802 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
804 if (termios->c_cflag & CSTOPB)
805 ulcon |= S3C2410_LCON_STOPB;
807 if (termios->c_cflag & PARENB) {
808 if (termios->c_cflag & PARODD)
809 ulcon |= S3C2410_LCON_PODD;
811 ulcon |= S3C2410_LCON_PEVEN;
813 ulcon |= S3C2410_LCON_PNONE;
816 spin_lock_irqsave(&port->lock, flags);
818 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
819 ulcon, quot, udivslot);
821 wr_regl(port, S3C2410_ULCON, ulcon);
822 wr_regl(port, S3C2410_UBRDIV, quot);
824 umcon = rd_regl(port, S3C2410_UMCON);
825 if (termios->c_cflag & CRTSCTS) {
826 umcon |= S3C2410_UMCOM_AFC;
827 /* Disable RTS when RX FIFO contains 63 bytes */
828 umcon &= ~S3C2412_UMCON_AFC_8;
830 umcon &= ~S3C2410_UMCOM_AFC;
832 wr_regl(port, S3C2410_UMCON, umcon);
834 if (ourport->info->has_divslot)
835 wr_regl(port, S3C2443_DIVSLOT, udivslot);
837 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
838 rd_regl(port, S3C2410_ULCON),
839 rd_regl(port, S3C2410_UCON),
840 rd_regl(port, S3C2410_UFCON));
843 * Update the per-port timeout.
845 uart_update_timeout(port, termios->c_cflag, baud);
848 * Which character status flags are we interested in?
850 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
851 if (termios->c_iflag & INPCK)
852 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
855 * Which character status flags should we ignore?
857 port->ignore_status_mask = 0;
858 if (termios->c_iflag & IGNPAR)
859 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
860 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
861 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
864 * Ignore all characters if CREAD is not set.
866 if ((termios->c_cflag & CREAD) == 0)
867 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
869 spin_unlock_irqrestore(&port->lock, flags);
872 static const char *s3c24xx_serial_type(struct uart_port *port)
874 switch (port->type) {
888 #define MAP_SIZE (0x100)
890 static void s3c24xx_serial_release_port(struct uart_port *port)
892 release_mem_region(port->mapbase, MAP_SIZE);
895 static int s3c24xx_serial_request_port(struct uart_port *port)
897 const char *name = s3c24xx_serial_portname(port);
898 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
901 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
903 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
905 if (flags & UART_CONFIG_TYPE &&
906 s3c24xx_serial_request_port(port) == 0)
907 port->type = info->type;
911 * verify the new serial_struct (for TIOCSSERIAL).
914 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
916 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
918 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
925 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
927 static struct console s3c24xx_serial_console;
929 static int __init s3c24xx_serial_console_init(void)
931 register_console(&s3c24xx_serial_console);
934 console_initcall(s3c24xx_serial_console_init);
936 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
938 #define S3C24XX_SERIAL_CONSOLE NULL
941 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
942 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
943 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
947 static struct uart_ops s3c24xx_serial_ops = {
948 .pm = s3c24xx_serial_pm,
949 .tx_empty = s3c24xx_serial_tx_empty,
950 .get_mctrl = s3c24xx_serial_get_mctrl,
951 .set_mctrl = s3c24xx_serial_set_mctrl,
952 .stop_tx = s3c24xx_serial_stop_tx,
953 .start_tx = s3c24xx_serial_start_tx,
954 .stop_rx = s3c24xx_serial_stop_rx,
955 .enable_ms = s3c24xx_serial_enable_ms,
956 .break_ctl = s3c24xx_serial_break_ctl,
957 .startup = s3c24xx_serial_startup,
958 .shutdown = s3c24xx_serial_shutdown,
959 .set_termios = s3c24xx_serial_set_termios,
960 .type = s3c24xx_serial_type,
961 .release_port = s3c24xx_serial_release_port,
962 .request_port = s3c24xx_serial_request_port,
963 .config_port = s3c24xx_serial_config_port,
964 .verify_port = s3c24xx_serial_verify_port,
965 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
966 .poll_get_char = s3c24xx_serial_get_poll_char,
967 .poll_put_char = s3c24xx_serial_put_poll_char,
971 static struct uart_driver s3c24xx_uart_drv = {
972 .owner = THIS_MODULE,
973 .driver_name = "s3c2410_serial",
974 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
975 .cons = S3C24XX_SERIAL_CONSOLE,
976 .dev_name = S3C24XX_SERIAL_NAME,
977 .major = S3C24XX_SERIAL_MAJOR,
978 .minor = S3C24XX_SERIAL_MINOR,
981 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
984 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
988 .ops = &s3c24xx_serial_ops,
989 .flags = UPF_BOOT_AUTOCONF,
995 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
999 .ops = &s3c24xx_serial_ops,
1000 .flags = UPF_BOOT_AUTOCONF,
1004 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1008 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1012 .ops = &s3c24xx_serial_ops,
1013 .flags = UPF_BOOT_AUTOCONF,
1018 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1021 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1025 .ops = &s3c24xx_serial_ops,
1026 .flags = UPF_BOOT_AUTOCONF,
1033 /* s3c24xx_serial_resetport
1035 * reset the fifos and other the settings.
1038 static void s3c24xx_serial_resetport(struct uart_port *port,
1039 struct s3c2410_uartcfg *cfg)
1041 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1042 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1043 unsigned int ucon_mask;
1045 ucon_mask = info->clksel_mask;
1046 if (info->type == PORT_S3C2440)
1047 ucon_mask |= S3C2440_UCON0_DIVMASK;
1050 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1052 /* reset both fifos */
1053 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1054 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1056 /* some delay is required after fifo reset */
1061 #ifdef CONFIG_CPU_FREQ
1063 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1064 unsigned long val, void *data)
1066 struct s3c24xx_uart_port *port;
1067 struct uart_port *uport;
1069 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1070 uport = &port->port;
1072 /* check to see if port is enabled */
1074 if (port->pm_level != 0)
1077 /* try and work out if the baudrate is changing, we can detect
1078 * a change in rate, but we do not have support for detecting
1079 * a disturbance in the clock-rate over the change.
1082 if (IS_ERR(port->baudclk))
1085 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1088 if (val == CPUFREQ_PRECHANGE) {
1089 /* we should really shut the port down whilst the
1090 * frequency change is in progress. */
1092 } else if (val == CPUFREQ_POSTCHANGE) {
1093 struct ktermios *termios;
1094 struct tty_struct *tty;
1096 if (uport->state == NULL)
1099 tty = uport->state->port.tty;
1104 termios = &tty->termios;
1106 if (termios == NULL) {
1107 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1111 s3c24xx_serial_set_termios(uport, termios, NULL);
1118 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1120 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1122 return cpufreq_register_notifier(&port->freq_transition,
1123 CPUFREQ_TRANSITION_NOTIFIER);
1126 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1128 cpufreq_unregister_notifier(&port->freq_transition,
1129 CPUFREQ_TRANSITION_NOTIFIER);
1133 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1138 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1143 /* s3c24xx_serial_init_port
1145 * initialise a single serial port from the platform device given
1148 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1149 struct platform_device *platdev)
1151 struct uart_port *port = &ourport->port;
1152 struct s3c2410_uartcfg *cfg = ourport->cfg;
1153 struct resource *res;
1156 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1158 if (platdev == NULL)
1161 if (port->mapbase != 0)
1164 /* setup info for port */
1165 port->dev = &platdev->dev;
1167 /* Startup sequence is different for s3c64xx and higher SoC's */
1168 if (s3c24xx_serial_has_interrupt_mask(port))
1169 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1173 if (cfg->uart_flags & UPF_CONS_FLOW) {
1174 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1175 port->flags |= UPF_CONS_FLOW;
1178 /* sort our the physical and virtual addresses for each UART */
1180 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1182 dev_err(port->dev, "failed to find memory resource for uart\n");
1186 dbg("resource %pR)\n", res);
1188 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1189 if (!port->membase) {
1190 dev_err(port->dev, "failed to remap controller address\n");
1194 port->mapbase = res->start;
1195 ret = platform_get_irq(platdev, 0);
1200 ourport->rx_irq = ret;
1201 ourport->tx_irq = ret + 1;
1204 ret = platform_get_irq(platdev, 1);
1206 ourport->tx_irq = ret;
1208 ourport->clk = clk_get(&platdev->dev, "uart");
1209 if (IS_ERR(ourport->clk)) {
1210 pr_err("%s: Controller clock not found\n",
1211 dev_name(&platdev->dev));
1212 return PTR_ERR(ourport->clk);
1215 ret = clk_prepare_enable(ourport->clk);
1217 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1218 clk_put(ourport->clk);
1222 /* Keep all interrupts masked and cleared */
1223 if (s3c24xx_serial_has_interrupt_mask(port)) {
1224 wr_regl(port, S3C64XX_UINTM, 0xf);
1225 wr_regl(port, S3C64XX_UINTP, 0xf);
1226 wr_regl(port, S3C64XX_UINTSP, 0xf);
1229 dbg("port: map=%08x, mem=%p, irq=%d (%d,%d), clock=%u\n",
1230 port->mapbase, port->membase, port->irq,
1231 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1233 /* reset the fifos (and setup the uart) */
1234 s3c24xx_serial_resetport(port, cfg);
1238 #ifdef CONFIG_SAMSUNG_CLOCK
1239 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1240 struct device_attribute *attr,
1243 struct uart_port *port = s3c24xx_dev_to_port(dev);
1244 struct s3c24xx_uart_port *ourport = to_ourport(port);
1246 if (IS_ERR(ourport->baudclk))
1249 return snprintf(buf, PAGE_SIZE, "* %s\n",
1250 ourport->baudclk->name ?: "(null)");
1253 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1256 /* Device driver serial port probe */
1258 static const struct of_device_id s3c24xx_uart_dt_match[];
1259 static int probe_index;
1261 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1262 struct platform_device *pdev)
1265 if (pdev->dev.of_node) {
1266 const struct of_device_id *match;
1267 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1268 return (struct s3c24xx_serial_drv_data *)match->data;
1271 return (struct s3c24xx_serial_drv_data *)
1272 platform_get_device_id(pdev)->driver_data;
1275 static int s3c24xx_serial_probe(struct platform_device *pdev)
1277 struct s3c24xx_uart_port *ourport;
1280 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1282 ourport = &s3c24xx_serial_ports[probe_index];
1284 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1285 if (!ourport->drv_data) {
1286 dev_err(&pdev->dev, "could not find driver data\n");
1290 ourport->baudclk = ERR_PTR(-EINVAL);
1291 ourport->info = ourport->drv_data->info;
1292 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1293 dev_get_platdata(&pdev->dev) :
1294 ourport->drv_data->def_cfg;
1296 ourport->port.fifosize = (ourport->info->fifosize) ?
1297 ourport->info->fifosize :
1298 ourport->drv_data->fifosize[probe_index];
1302 dbg("%s: initialising port %p...\n", __func__, ourport);
1304 ret = s3c24xx_serial_init_port(ourport, pdev);
1308 if (!s3c24xx_uart_drv.state) {
1309 ret = uart_register_driver(&s3c24xx_uart_drv);
1311 pr_err("Failed to register Samsung UART driver\n");
1316 dbg("%s: adding port\n", __func__);
1317 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1318 platform_set_drvdata(pdev, &ourport->port);
1321 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1322 * so that a potential re-enablement through the pm-callback overlaps
1323 * and keeps the clock enabled in this case.
1325 clk_disable_unprepare(ourport->clk);
1327 #ifdef CONFIG_SAMSUNG_CLOCK
1328 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1330 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1333 ret = s3c24xx_serial_cpufreq_register(ourport);
1335 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1343 static int s3c24xx_serial_remove(struct platform_device *dev)
1345 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1348 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1349 #ifdef CONFIG_SAMSUNG_CLOCK
1350 device_remove_file(&dev->dev, &dev_attr_clock_source);
1352 uart_remove_one_port(&s3c24xx_uart_drv, port);
1355 uart_unregister_driver(&s3c24xx_uart_drv);
1360 /* UART power management code */
1361 #ifdef CONFIG_PM_SLEEP
1362 static int s3c24xx_serial_suspend(struct device *dev)
1364 struct uart_port *port = s3c24xx_dev_to_port(dev);
1367 uart_suspend_port(&s3c24xx_uart_drv, port);
1372 static int s3c24xx_serial_resume(struct device *dev)
1374 struct uart_port *port = s3c24xx_dev_to_port(dev);
1375 struct s3c24xx_uart_port *ourport = to_ourport(port);
1378 clk_prepare_enable(ourport->clk);
1379 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1380 clk_disable_unprepare(ourport->clk);
1382 uart_resume_port(&s3c24xx_uart_drv, port);
1388 static int s3c24xx_serial_resume_noirq(struct device *dev)
1390 struct uart_port *port = s3c24xx_dev_to_port(dev);
1393 /* restore IRQ mask */
1394 if (s3c24xx_serial_has_interrupt_mask(port)) {
1395 unsigned int uintm = 0xf;
1396 if (tx_enabled(port))
1397 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1398 if (rx_enabled(port))
1399 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1400 wr_regl(port, S3C64XX_UINTM, uintm);
1407 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1408 .suspend = s3c24xx_serial_suspend,
1409 .resume = s3c24xx_serial_resume,
1410 .resume_noirq = s3c24xx_serial_resume_noirq,
1412 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1414 #else /* !CONFIG_PM_SLEEP */
1416 #define SERIAL_SAMSUNG_PM_OPS NULL
1417 #endif /* CONFIG_PM_SLEEP */
1421 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1423 static struct uart_port *cons_uart;
1426 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1428 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1429 unsigned long ufstat, utrstat;
1431 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1432 /* fifo mode - check amount of data in fifo registers... */
1434 ufstat = rd_regl(port, S3C2410_UFSTAT);
1435 return (ufstat & info->tx_fifofull) ? 0 : 1;
1438 /* in non-fifo mode, we go and use the tx buffer empty */
1440 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1441 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1445 s3c24xx_port_configured(unsigned int ucon)
1447 /* consider the serial port configured if the tx/rx mode set */
1448 return (ucon & 0xf) != 0;
1451 #ifdef CONFIG_CONSOLE_POLL
1453 * Console polling routines for writing and reading from the uart while
1454 * in an interrupt or debug context.
1457 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1459 struct s3c24xx_uart_port *ourport = to_ourport(port);
1460 unsigned int ufstat;
1462 ufstat = rd_regl(port, S3C2410_UFSTAT);
1463 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1464 return NO_POLL_CHAR;
1466 return rd_regb(port, S3C2410_URXH);
1469 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1472 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1473 unsigned int ucon = rd_regl(port, S3C2410_UCON);
1475 /* not possible to xmit on unconfigured port */
1476 if (!s3c24xx_port_configured(ucon))
1479 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1481 wr_regb(port, S3C2410_UTXH, c);
1484 #endif /* CONFIG_CONSOLE_POLL */
1487 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1489 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1491 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1493 wr_regb(port, S3C2410_UTXH, ch);
1497 s3c24xx_serial_console_write(struct console *co, const char *s,
1500 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1502 /* not possible to xmit on unconfigured port */
1503 if (!s3c24xx_port_configured(ucon))
1506 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1510 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1511 int *parity, int *bits)
1516 unsigned int ubrdiv;
1518 unsigned int clk_sel;
1519 char clk_name[MAX_CLK_NAME_LENGTH];
1521 ulcon = rd_regl(port, S3C2410_ULCON);
1522 ucon = rd_regl(port, S3C2410_UCON);
1523 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1525 dbg("s3c24xx_serial_get_options: port=%p\n"
1526 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1527 port, ulcon, ucon, ubrdiv);
1529 if (s3c24xx_port_configured(ucon)) {
1530 switch (ulcon & S3C2410_LCON_CSMASK) {
1531 case S3C2410_LCON_CS5:
1534 case S3C2410_LCON_CS6:
1537 case S3C2410_LCON_CS7:
1541 case S3C2410_LCON_CS8:
1546 switch (ulcon & S3C2410_LCON_PMASK) {
1547 case S3C2410_LCON_PEVEN:
1551 case S3C2410_LCON_PODD:
1555 case S3C2410_LCON_PNONE:
1560 /* now calculate the baud rate */
1562 clk_sel = s3c24xx_serial_getsource(port);
1563 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1565 clk = clk_get(port->dev, clk_name);
1567 rate = clk_get_rate(clk);
1571 *baud = rate / (16 * (ubrdiv + 1));
1572 dbg("calculated baud %d\n", *baud);
1578 s3c24xx_serial_console_setup(struct console *co, char *options)
1580 struct uart_port *port;
1586 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1587 co, co->index, options);
1589 /* is this a valid port */
1591 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1594 port = &s3c24xx_serial_ports[co->index].port;
1596 /* is the port configured? */
1598 if (port->mapbase == 0x0)
1603 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1606 * Check whether an invalid uart number has been specified, and
1607 * if so, search for the first available port that does have
1611 uart_parse_options(options, &baud, &parity, &bits, &flow);
1613 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1615 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1617 return uart_set_options(port, co, baud, parity, bits, flow);
1620 static struct console s3c24xx_serial_console = {
1621 .name = S3C24XX_SERIAL_NAME,
1622 .device = uart_console_device,
1623 .flags = CON_PRINTBUFFER,
1625 .write = s3c24xx_serial_console_write,
1626 .setup = s3c24xx_serial_console_setup,
1627 .data = &s3c24xx_uart_drv,
1629 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1631 #ifdef CONFIG_CPU_S3C2410
1632 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1633 .info = &(struct s3c24xx_uart_info) {
1634 .name = "Samsung S3C2410 UART",
1635 .type = PORT_S3C2410,
1637 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1638 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1639 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1640 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1641 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1642 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1643 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1645 .clksel_mask = S3C2410_UCON_CLKMASK,
1646 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1648 .def_cfg = &(struct s3c2410_uartcfg) {
1649 .ucon = S3C2410_UCON_DEFAULT,
1650 .ufcon = S3C2410_UFCON_DEFAULT,
1653 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1655 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1658 #ifdef CONFIG_CPU_S3C2412
1659 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1660 .info = &(struct s3c24xx_uart_info) {
1661 .name = "Samsung S3C2412 UART",
1662 .type = PORT_S3C2412,
1665 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1666 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1667 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1668 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1669 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1670 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1671 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1673 .clksel_mask = S3C2412_UCON_CLKMASK,
1674 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1676 .def_cfg = &(struct s3c2410_uartcfg) {
1677 .ucon = S3C2410_UCON_DEFAULT,
1678 .ufcon = S3C2410_UFCON_DEFAULT,
1681 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1683 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1686 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1687 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1688 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1689 .info = &(struct s3c24xx_uart_info) {
1690 .name = "Samsung S3C2440 UART",
1691 .type = PORT_S3C2440,
1694 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1695 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1696 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1697 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1698 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1699 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1700 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1702 .clksel_mask = S3C2412_UCON_CLKMASK,
1703 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1705 .def_cfg = &(struct s3c2410_uartcfg) {
1706 .ucon = S3C2410_UCON_DEFAULT,
1707 .ufcon = S3C2410_UFCON_DEFAULT,
1710 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1712 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1715 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1716 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1717 defined(CONFIG_CPU_S5PC100)
1718 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1719 .info = &(struct s3c24xx_uart_info) {
1720 .name = "Samsung S3C6400 UART",
1721 .type = PORT_S3C6400,
1724 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1725 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1726 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1727 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1728 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1729 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1730 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1732 .clksel_mask = S3C6400_UCON_CLKMASK,
1733 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1735 .def_cfg = &(struct s3c2410_uartcfg) {
1736 .ucon = S3C2410_UCON_DEFAULT,
1737 .ufcon = S3C2410_UFCON_DEFAULT,
1740 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1742 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1745 #ifdef CONFIG_CPU_S5PV210
1746 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1747 .info = &(struct s3c24xx_uart_info) {
1748 .name = "Samsung S5PV210 UART",
1749 .type = PORT_S3C6400,
1751 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1752 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1753 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1754 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1755 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1756 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1757 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1759 .clksel_mask = S5PV210_UCON_CLKMASK,
1760 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1762 .def_cfg = &(struct s3c2410_uartcfg) {
1763 .ucon = S5PV210_UCON_DEFAULT,
1764 .ufcon = S5PV210_UFCON_DEFAULT,
1766 .fifosize = { 256, 64, 16, 16 },
1768 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1770 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1773 #if defined(CONFIG_ARCH_EXYNOS)
1774 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1775 .info = &(struct s3c24xx_uart_info) {
1776 .name = "Samsung Exynos4 UART",
1777 .type = PORT_S3C6400,
1779 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1780 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1781 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1782 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1783 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1784 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1785 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1790 .def_cfg = &(struct s3c2410_uartcfg) {
1791 .ucon = S5PV210_UCON_DEFAULT,
1792 .ufcon = S5PV210_UFCON_DEFAULT,
1795 .fifosize = { 256, 64, 16, 16 },
1797 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1799 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1802 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1804 .name = "s3c2410-uart",
1805 .driver_data = S3C2410_SERIAL_DRV_DATA,
1807 .name = "s3c2412-uart",
1808 .driver_data = S3C2412_SERIAL_DRV_DATA,
1810 .name = "s3c2440-uart",
1811 .driver_data = S3C2440_SERIAL_DRV_DATA,
1813 .name = "s3c6400-uart",
1814 .driver_data = S3C6400_SERIAL_DRV_DATA,
1816 .name = "s5pv210-uart",
1817 .driver_data = S5PV210_SERIAL_DRV_DATA,
1819 .name = "exynos4210-uart",
1820 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1824 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1827 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1828 { .compatible = "samsung,s3c2410-uart",
1829 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1830 { .compatible = "samsung,s3c2412-uart",
1831 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1832 { .compatible = "samsung,s3c2440-uart",
1833 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1834 { .compatible = "samsung,s3c6400-uart",
1835 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1836 { .compatible = "samsung,s5pv210-uart",
1837 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1838 { .compatible = "samsung,exynos4210-uart",
1839 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1842 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1845 static struct platform_driver samsung_serial_driver = {
1846 .probe = s3c24xx_serial_probe,
1847 .remove = s3c24xx_serial_remove,
1848 .id_table = s3c24xx_serial_driver_ids,
1850 .name = "samsung-uart",
1851 .owner = THIS_MODULE,
1852 .pm = SERIAL_SAMSUNG_PM_OPS,
1853 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1857 module_platform_driver(samsung_serial_driver);
1859 MODULE_ALIAS("platform:samsung-uart");
1860 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1861 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1862 MODULE_LICENSE("GPL v2");