2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/ioport.h>
37 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
42 #include <linux/tty_flip.h>
43 #include <linux/serial_core.h>
44 #include <linux/serial.h>
45 #include <linux/serial_s3c.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
48 #include <linux/cpufreq.h>
55 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 defined(CONFIG_DEBUG_LL) && \
59 extern void printascii(const char *);
62 static void dbg(const char *fmt, ...)
68 vscnprintf(buff, sizeof(buff), fmt, va);
75 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
78 /* UART name and device definitions */
80 #define S3C24XX_SERIAL_NAME "ttySAC"
81 #define S3C24XX_SERIAL_MAJOR 204
82 #define S3C24XX_SERIAL_MINOR 64
84 #define S3C24XX_TX_PIO 1
85 #define S3C24XX_TX_DMA 2
86 #define S3C24XX_RX_PIO 1
87 #define S3C24XX_RX_DMA 2
88 /* macros to change one thing to another */
90 #define tx_enabled(port) ((port)->unused[0])
91 #define rx_enabled(port) ((port)->unused[1])
93 /* flag to ignore all characters coming in */
94 #define RXSTAT_DUMMY_READ (0x10000000)
96 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
98 return container_of(port, struct s3c24xx_uart_port, port);
101 /* translate a port to the device name */
103 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
105 return to_platform_device(port->dev)->name;
108 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
110 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
114 * s3c64xx and later SoC's include the interrupt mask and status registers in
115 * the controller itself, unlike the s3c24xx SoC's which have these registers
116 * in the interrupt controller. Check if the port type is s3c64xx or higher.
118 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
120 return to_ourport(port)->info->type == PORT_S3C6400;
123 static void s3c24xx_serial_rx_enable(struct uart_port *port)
126 unsigned int ucon, ufcon;
129 spin_lock_irqsave(&port->lock, flags);
131 while (--count && !s3c24xx_serial_txempty_nofifo(port))
134 ufcon = rd_regl(port, S3C2410_UFCON);
135 ufcon |= S3C2410_UFCON_RESETRX;
136 wr_regl(port, S3C2410_UFCON, ufcon);
138 ucon = rd_regl(port, S3C2410_UCON);
139 ucon |= S3C2410_UCON_RXIRQMODE;
140 wr_regl(port, S3C2410_UCON, ucon);
142 rx_enabled(port) = 1;
143 spin_unlock_irqrestore(&port->lock, flags);
146 static void s3c24xx_serial_rx_disable(struct uart_port *port)
151 spin_lock_irqsave(&port->lock, flags);
153 ucon = rd_regl(port, S3C2410_UCON);
154 ucon &= ~S3C2410_UCON_RXIRQMODE;
155 wr_regl(port, S3C2410_UCON, ucon);
157 rx_enabled(port) = 0;
158 spin_unlock_irqrestore(&port->lock, flags);
161 static void s3c24xx_serial_stop_tx(struct uart_port *port)
163 struct s3c24xx_uart_port *ourport = to_ourport(port);
164 struct s3c24xx_uart_dma *dma = ourport->dma;
165 struct circ_buf *xmit = &port->state->xmit;
166 struct dma_tx_state state;
169 if (!tx_enabled(port))
172 if (s3c24xx_serial_has_interrupt_mask(port))
173 __set_bit(S3C64XX_UINTM_TXD,
174 portaddrl(port, S3C64XX_UINTM));
176 disable_irq_nosync(ourport->tx_irq);
178 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
179 dmaengine_pause(dma->tx_chan);
180 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
181 dmaengine_terminate_all(dma->tx_chan);
182 dma_sync_single_for_cpu(ourport->port.dev,
183 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
184 async_tx_ack(dma->tx_desc);
185 count = dma->tx_bytes_requested - state.residue;
186 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
187 port->icount.tx += count;
190 tx_enabled(port) = 0;
191 ourport->tx_in_progress = 0;
193 if (port->flags & UPF_CONS_FLOW)
194 s3c24xx_serial_rx_enable(port);
196 ourport->tx_mode = 0;
199 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
201 static void s3c24xx_serial_tx_dma_complete(void *args)
203 struct s3c24xx_uart_port *ourport = args;
204 struct uart_port *port = &ourport->port;
205 struct circ_buf *xmit = &port->state->xmit;
206 struct s3c24xx_uart_dma *dma = ourport->dma;
207 struct dma_tx_state state;
212 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
213 count = dma->tx_bytes_requested - state.residue;
214 async_tx_ack(dma->tx_desc);
216 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
217 dma->tx_size, DMA_TO_DEVICE);
219 spin_lock_irqsave(&port->lock, flags);
221 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
222 port->icount.tx += count;
223 ourport->tx_in_progress = 0;
225 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
226 uart_write_wakeup(port);
228 s3c24xx_serial_start_next_tx(ourport);
229 spin_unlock_irqrestore(&port->lock, flags);
232 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
234 struct uart_port *port = &ourport->port;
237 /* Mask Tx interrupt */
238 if (s3c24xx_serial_has_interrupt_mask(port))
239 __set_bit(S3C64XX_UINTM_TXD,
240 portaddrl(port, S3C64XX_UINTM));
242 disable_irq_nosync(ourport->tx_irq);
244 /* Enable tx dma mode */
245 ucon = rd_regl(port, S3C2410_UCON);
246 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
247 ucon |= (dma_get_cache_alignment() >= 16) ?
248 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
249 ucon |= S3C64XX_UCON_TXMODE_DMA;
250 wr_regl(port, S3C2410_UCON, ucon);
252 ourport->tx_mode = S3C24XX_TX_DMA;
255 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
257 struct uart_port *port = &ourport->port;
260 /* Set ufcon txtrig */
261 ourport->tx_in_progress = S3C24XX_TX_PIO;
262 ufcon = rd_regl(port, S3C2410_UFCON);
263 wr_regl(port, S3C2410_UFCON, ufcon);
265 /* Enable tx pio mode */
266 ucon = rd_regl(port, S3C2410_UCON);
267 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
268 ucon |= S3C64XX_UCON_TXMODE_CPU;
269 wr_regl(port, S3C2410_UCON, ucon);
271 /* Unmask Tx interrupt */
272 if (s3c24xx_serial_has_interrupt_mask(port))
273 __clear_bit(S3C64XX_UINTM_TXD,
274 portaddrl(port, S3C64XX_UINTM));
276 enable_irq(ourport->tx_irq);
278 ourport->tx_mode = S3C24XX_TX_PIO;
281 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
283 if (ourport->tx_mode != S3C24XX_TX_PIO)
284 enable_tx_pio(ourport);
287 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
290 struct uart_port *port = &ourport->port;
291 struct circ_buf *xmit = &port->state->xmit;
292 struct s3c24xx_uart_dma *dma = ourport->dma;
295 if (ourport->tx_mode != S3C24XX_TX_DMA)
296 enable_tx_dma(ourport);
298 while (xmit->tail & (dma_get_cache_alignment() - 1)) {
299 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
301 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
307 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
308 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
310 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
311 dma->tx_size, DMA_TO_DEVICE);
313 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
314 dma->tx_transfer_addr, dma->tx_size,
315 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
317 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
321 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
322 dma->tx_desc->callback_param = ourport;
323 dma->tx_bytes_requested = dma->tx_size;
325 ourport->tx_in_progress = S3C24XX_TX_DMA;
326 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
327 dma_async_issue_pending(dma->tx_chan);
331 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
333 struct uart_port *port = &ourport->port;
334 struct circ_buf *xmit = &port->state->xmit;
337 /* Get data size up to the end of buffer */
338 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
341 s3c24xx_serial_stop_tx(port);
345 if (!ourport->dma || !ourport->dma->tx_chan || count < port->fifosize)
346 s3c24xx_serial_start_tx_pio(ourport);
348 s3c24xx_serial_start_tx_dma(ourport, count);
351 void s3c24xx_serial_start_tx(struct uart_port *port)
353 struct s3c24xx_uart_port *ourport = to_ourport(port);
354 struct circ_buf *xmit = &port->state->xmit;
356 if (!tx_enabled(port)) {
357 if (port->flags & UPF_CONS_FLOW)
358 s3c24xx_serial_rx_disable(port);
360 tx_enabled(port) = 1;
361 if (!ourport->dma || !ourport->dma->tx_chan)
362 s3c24xx_serial_start_tx_pio(ourport);
365 if (ourport->dma && ourport->dma->tx_chan) {
366 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
367 s3c24xx_serial_start_next_tx(ourport);
371 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
372 struct tty_port *tty, int count)
374 struct s3c24xx_uart_dma *dma = ourport->dma;
380 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
381 dma->rx_size, DMA_FROM_DEVICE);
383 ourport->port.icount.rx += count;
385 dev_err(ourport->port.dev, "No tty port\n");
388 copied = tty_insert_flip_string(tty,
389 ((unsigned char *)(ourport->dma->rx_buf)), count);
390 if (copied != count) {
392 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
396 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
397 unsigned long ufstat);
399 static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
401 struct uart_port *port = &ourport->port;
402 struct tty_port *tty = &port->state->port;
403 unsigned int ch, ufstat;
406 ufstat = rd_regl(port, S3C2410_UFSTAT);
407 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
412 while (count-- > 0) {
413 ch = rd_regb(port, S3C2410_URXH);
415 ourport->port.icount.rx++;
416 tty_insert_flip_char(tty, ch, TTY_NORMAL);
419 tty_flip_buffer_push(tty);
422 static void s3c24xx_serial_stop_rx(struct uart_port *port)
424 struct s3c24xx_uart_port *ourport = to_ourport(port);
425 struct s3c24xx_uart_dma *dma = ourport->dma;
426 struct tty_port *t = &port->state->port;
427 struct dma_tx_state state;
428 enum dma_status dma_status;
429 unsigned int received;
431 if (rx_enabled(port)) {
432 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
433 if (s3c24xx_serial_has_interrupt_mask(port))
434 __set_bit(S3C64XX_UINTM_RXD,
435 portaddrl(port, S3C64XX_UINTM));
437 disable_irq_nosync(ourport->rx_irq);
438 rx_enabled(port) = 0;
440 if (dma && dma->rx_chan) {
441 dmaengine_pause(dma->tx_chan);
442 dma_status = dmaengine_tx_status(dma->rx_chan,
443 dma->rx_cookie, &state);
444 if (dma_status == DMA_IN_PROGRESS ||
445 dma_status == DMA_PAUSED) {
446 received = dma->rx_bytes_requested - state.residue;
447 dmaengine_terminate_all(dma->rx_chan);
448 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
453 static inline struct s3c24xx_uart_info
454 *s3c24xx_port_to_info(struct uart_port *port)
456 return to_ourport(port)->info;
459 static inline struct s3c2410_uartcfg
460 *s3c24xx_port_to_cfg(struct uart_port *port)
462 struct s3c24xx_uart_port *ourport;
464 if (port->dev == NULL)
467 ourport = container_of(port, struct s3c24xx_uart_port, port);
471 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
472 unsigned long ufstat)
474 struct s3c24xx_uart_info *info = ourport->info;
476 if (ufstat & info->rx_fifofull)
477 return ourport->port.fifosize;
479 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
482 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
483 static void s3c24xx_serial_rx_dma_complete(void *args)
485 struct s3c24xx_uart_port *ourport = args;
486 struct uart_port *port = &ourport->port;
488 struct s3c24xx_uart_dma *dma = ourport->dma;
489 struct tty_port *t = &port->state->port;
490 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
492 struct dma_tx_state state;
496 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
497 received = dma->rx_bytes_requested - state.residue;
498 async_tx_ack(dma->rx_desc);
500 spin_lock_irqsave(&port->lock, flags);
503 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
506 tty_flip_buffer_push(t);
510 s3c64xx_start_rx_dma(ourport);
512 spin_unlock_irqrestore(&port->lock, flags);
515 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
517 struct s3c24xx_uart_dma *dma = ourport->dma;
519 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
520 dma->rx_size, DMA_FROM_DEVICE);
522 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
523 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
526 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
530 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
531 dma->rx_desc->callback_param = ourport;
532 dma->rx_bytes_requested = dma->rx_size;
534 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
535 dma_async_issue_pending(dma->rx_chan);
538 /* ? - where has parity gone?? */
539 #define S3C2410_UERSTAT_PARITY (0x1000)
541 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
543 struct uart_port *port = &ourport->port;
546 /* set Rx mode to DMA mode */
547 ucon = rd_regl(port, S3C2410_UCON);
548 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
549 S3C64XX_UCON_TIMEOUT_MASK |
550 S3C64XX_UCON_EMPTYINT_EN |
551 S3C64XX_UCON_DMASUS_EN |
552 S3C64XX_UCON_TIMEOUT_EN |
553 S3C64XX_UCON_RXMODE_MASK);
554 ucon |= S3C64XX_UCON_RXBURST_16 |
555 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
556 S3C64XX_UCON_EMPTYINT_EN |
557 S3C64XX_UCON_TIMEOUT_EN |
558 S3C64XX_UCON_RXMODE_DMA;
559 wr_regl(port, S3C2410_UCON, ucon);
561 ourport->rx_mode = S3C24XX_RX_DMA;
564 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
566 struct uart_port *port = &ourport->port;
569 /* set Rx mode to DMA mode */
570 ucon = rd_regl(port, S3C2410_UCON);
571 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
572 S3C64XX_UCON_EMPTYINT_EN |
573 S3C64XX_UCON_DMASUS_EN |
574 S3C64XX_UCON_TIMEOUT_EN |
575 S3C64XX_UCON_RXMODE_MASK);
576 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
577 S3C64XX_UCON_TIMEOUT_EN |
578 S3C64XX_UCON_RXMODE_CPU;
579 wr_regl(port, S3C2410_UCON, ucon);
581 ourport->rx_mode = S3C24XX_RX_PIO;
584 static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
586 unsigned int utrstat, ufstat, received;
587 struct s3c24xx_uart_port *ourport = dev_id;
588 struct uart_port *port = &ourport->port;
589 struct s3c24xx_uart_dma *dma = ourport->dma;
590 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
591 struct tty_port *t = &port->state->port;
593 struct dma_tx_state state;
595 utrstat = rd_regl(port, S3C2410_UTRSTAT);
596 ufstat = rd_regl(port, S3C2410_UFSTAT);
598 spin_lock_irqsave(&port->lock, flags);
600 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
601 s3c64xx_start_rx_dma(ourport);
602 if (ourport->rx_mode == S3C24XX_RX_PIO)
603 enable_rx_dma(ourport);
607 if (ourport->rx_mode == S3C24XX_RX_DMA) {
608 dmaengine_pause(dma->rx_chan);
609 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
610 dmaengine_terminate_all(dma->rx_chan);
611 received = dma->rx_bytes_requested - state.residue;
612 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
614 enable_rx_pio(ourport);
617 uart_rx_drain_fifo(ourport);
620 tty_flip_buffer_push(t);
624 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
627 spin_unlock_irqrestore(&port->lock, flags);
632 static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
634 struct s3c24xx_uart_port *ourport = dev_id;
635 struct uart_port *port = &ourport->port;
636 unsigned int ufcon, ch, flag, ufstat, uerstat;
638 int max_count = port->fifosize;
640 spin_lock_irqsave(&port->lock, flags);
642 while (max_count-- > 0) {
643 ufcon = rd_regl(port, S3C2410_UFCON);
644 ufstat = rd_regl(port, S3C2410_UFSTAT);
646 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
649 uerstat = rd_regl(port, S3C2410_UERSTAT);
650 ch = rd_regb(port, S3C2410_URXH);
652 if (port->flags & UPF_CONS_FLOW) {
653 int txe = s3c24xx_serial_txempty_nofifo(port);
655 if (rx_enabled(port)) {
657 rx_enabled(port) = 0;
662 ufcon |= S3C2410_UFCON_RESETRX;
663 wr_regl(port, S3C2410_UFCON, ufcon);
664 rx_enabled(port) = 1;
665 spin_unlock_irqrestore(&port->lock,
673 /* insert the character into the buffer */
678 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
679 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
682 /* check for break */
683 if (uerstat & S3C2410_UERSTAT_BREAK) {
686 if (uart_handle_break(port))
690 if (uerstat & S3C2410_UERSTAT_FRAME)
691 port->icount.frame++;
692 if (uerstat & S3C2410_UERSTAT_OVERRUN)
693 port->icount.overrun++;
695 uerstat &= port->read_status_mask;
697 if (uerstat & S3C2410_UERSTAT_BREAK)
699 else if (uerstat & S3C2410_UERSTAT_PARITY)
701 else if (uerstat & (S3C2410_UERSTAT_FRAME |
702 S3C2410_UERSTAT_OVERRUN))
706 if (uart_handle_sysrq_char(port, ch))
709 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
716 spin_unlock_irqrestore(&port->lock, flags);
717 tty_flip_buffer_push(&port->state->port);
724 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
726 struct s3c24xx_uart_port *ourport = dev_id;
728 if (ourport->dma && ourport->dma->rx_chan)
729 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
730 return s3c24xx_serial_rx_chars_pio(irq, dev_id);
733 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
735 struct s3c24xx_uart_port *ourport = id;
736 struct uart_port *port = &ourport->port;
737 struct circ_buf *xmit = &port->state->xmit;
741 spin_lock_irqsave(&port->lock, flags);
743 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
745 if (ourport->dma && ourport->dma->tx_chan && count >= port->fifosize) {
746 s3c24xx_serial_start_tx_dma(ourport, count);
751 wr_regb(port, S3C2410_UTXH, port->x_char);
757 /* if there isn't anything more to transmit, or the uart is now
758 * stopped, disable the uart and exit
761 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
762 s3c24xx_serial_stop_tx(port);
766 /* try and drain the buffer... */
768 count = port->fifosize;
769 while (!uart_circ_empty(xmit) && count-- > 0) {
770 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
773 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
774 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
778 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
779 spin_unlock(&port->lock);
780 uart_write_wakeup(port);
781 spin_lock(&port->lock);
784 if (uart_circ_empty(xmit))
785 s3c24xx_serial_stop_tx(port);
788 spin_unlock_irqrestore(&port->lock, flags);
792 /* interrupt handler for s3c64xx and later SoC's.*/
793 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
795 struct s3c24xx_uart_port *ourport = id;
796 struct uart_port *port = &ourport->port;
797 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
798 irqreturn_t ret = IRQ_HANDLED;
800 if (pend & S3C64XX_UINTM_RXD_MSK) {
801 ret = s3c24xx_serial_rx_chars(irq, id);
802 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
804 if (pend & S3C64XX_UINTM_TXD_MSK) {
805 ret = s3c24xx_serial_tx_chars(irq, id);
806 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
811 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
813 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
814 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
815 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
817 if (ufcon & S3C2410_UFCON_FIFOMODE) {
818 if ((ufstat & info->tx_fifomask) != 0 ||
819 (ufstat & info->tx_fifofull))
825 return s3c24xx_serial_txempty_nofifo(port);
828 /* no modem control lines */
829 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
831 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
833 if (umstat & S3C2410_UMSTAT_CTS)
834 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
836 return TIOCM_CAR | TIOCM_DSR;
839 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
841 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
843 if (mctrl & TIOCM_RTS)
844 umcon |= S3C2410_UMCOM_RTS_LOW;
846 umcon &= ~S3C2410_UMCOM_RTS_LOW;
848 wr_regl(port, S3C2410_UMCON, umcon);
851 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
856 spin_lock_irqsave(&port->lock, flags);
858 ucon = rd_regl(port, S3C2410_UCON);
861 ucon |= S3C2410_UCON_SBREAK;
863 ucon &= ~S3C2410_UCON_SBREAK;
865 wr_regl(port, S3C2410_UCON, ucon);
867 spin_unlock_irqrestore(&port->lock, flags);
870 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
872 struct s3c24xx_uart_dma *dma = p->dma;
876 /* Default slave configuration parameters */
877 dma->rx_conf.direction = DMA_DEV_TO_MEM;
878 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
879 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
880 dma->rx_conf.src_maxburst = 16;
882 dma->tx_conf.direction = DMA_MEM_TO_DEV;
883 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
884 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
885 if (dma_get_cache_alignment() >= 16)
886 dma->tx_conf.dst_maxburst = 16;
888 dma->tx_conf.dst_maxburst = 1;
891 dma_cap_set(DMA_SLAVE, mask);
893 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
894 dma->rx_param, p->port.dev, "rx");
898 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
900 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
901 dma->tx_param, p->port.dev, "tx");
903 dma_release_channel(dma->rx_chan);
907 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
910 dma->rx_size = PAGE_SIZE;
912 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
915 dma_release_channel(dma->rx_chan);
916 dma_release_channel(dma->tx_chan);
920 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
921 dma->rx_size, DMA_FROM_DEVICE);
923 spin_lock_irqsave(&p->port.lock, flags);
926 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
927 p->port.state->xmit.buf,
928 UART_XMIT_SIZE, DMA_TO_DEVICE);
930 spin_unlock_irqrestore(&p->port.lock, flags);
935 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
937 struct s3c24xx_uart_dma *dma = p->dma;
940 dmaengine_terminate_all(dma->rx_chan);
941 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
942 dma->rx_size, DMA_FROM_DEVICE);
944 dma_release_channel(dma->rx_chan);
949 dmaengine_terminate_all(dma->tx_chan);
950 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
951 UART_XMIT_SIZE, DMA_TO_DEVICE);
952 dma_release_channel(dma->tx_chan);
957 static void s3c24xx_serial_shutdown(struct uart_port *port)
959 struct s3c24xx_uart_port *ourport = to_ourport(port);
961 if (ourport->tx_claimed) {
962 if (!s3c24xx_serial_has_interrupt_mask(port))
963 free_irq(ourport->tx_irq, ourport);
964 tx_enabled(port) = 0;
965 ourport->tx_claimed = 0;
966 ourport->tx_mode = 0;
969 if (ourport->rx_claimed) {
970 if (!s3c24xx_serial_has_interrupt_mask(port))
971 free_irq(ourport->rx_irq, ourport);
972 ourport->rx_claimed = 0;
973 rx_enabled(port) = 0;
976 /* Clear pending interrupts and mask all interrupts */
977 if (s3c24xx_serial_has_interrupt_mask(port)) {
978 free_irq(port->irq, ourport);
980 wr_regl(port, S3C64XX_UINTP, 0xf);
981 wr_regl(port, S3C64XX_UINTM, 0xf);
985 s3c24xx_serial_release_dma(ourport);
987 ourport->tx_in_progress = 0;
990 static int s3c24xx_serial_startup(struct uart_port *port)
992 struct s3c24xx_uart_port *ourport = to_ourport(port);
995 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
996 port, (unsigned long long)port->mapbase, port->membase);
998 rx_enabled(port) = 1;
1000 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1001 s3c24xx_serial_portname(port), ourport);
1004 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1008 ourport->rx_claimed = 1;
1010 dbg("requesting tx irq...\n");
1012 tx_enabled(port) = 1;
1014 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1015 s3c24xx_serial_portname(port), ourport);
1018 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1022 ourport->tx_claimed = 1;
1024 dbg("s3c24xx_serial_startup ok\n");
1026 /* the port reset code should have done the correct
1027 * register setup for the port controls */
1032 s3c24xx_serial_shutdown(port);
1036 static int s3c64xx_serial_startup(struct uart_port *port)
1038 struct s3c24xx_uart_port *ourport = to_ourport(port);
1039 unsigned long flags;
1043 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1044 port, (unsigned long long)port->mapbase, port->membase);
1046 wr_regl(port, S3C64XX_UINTM, 0xf);
1048 ret = s3c24xx_serial_request_dma(ourport);
1050 dev_warn(port->dev, "DMA request failed\n");
1055 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1056 s3c24xx_serial_portname(port), ourport);
1058 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1062 /* For compatibility with s3c24xx Soc's */
1063 rx_enabled(port) = 1;
1064 ourport->rx_claimed = 1;
1065 tx_enabled(port) = 0;
1066 ourport->tx_claimed = 1;
1068 spin_lock_irqsave(&port->lock, flags);
1070 ufcon = rd_regl(port, S3C2410_UFCON);
1071 ufcon |= S3C2410_UFCON_RESETRX | S3C2410_UFCON_RESETTX |
1072 S5PV210_UFCON_RXTRIG8;
1073 wr_regl(port, S3C2410_UFCON, ufcon);
1075 enable_rx_pio(ourport);
1077 spin_unlock_irqrestore(&port->lock, flags);
1079 /* Enable Rx Interrupt */
1080 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
1082 dbg("s3c64xx_serial_startup ok\n");
1086 /* power power management control */
1088 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1091 struct s3c24xx_uart_port *ourport = to_ourport(port);
1092 int timeout = 10000;
1094 ourport->pm_level = level;
1098 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1101 if (!IS_ERR(ourport->baudclk))
1102 clk_disable_unprepare(ourport->baudclk);
1104 clk_disable_unprepare(ourport->clk);
1108 clk_prepare_enable(ourport->clk);
1110 if (!IS_ERR(ourport->baudclk))
1111 clk_prepare_enable(ourport->baudclk);
1115 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1119 /* baud rate calculation
1121 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1122 * of different sources, including the peripheral clock ("pclk") and an
1123 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1124 * with a programmable extra divisor.
1126 * The following code goes through the clock sources, and calculates the
1127 * baud clocks (and the resultant actual baud rates) and then tries to
1128 * pick the closest one and select that.
1132 #define MAX_CLK_NAME_LENGTH 15
1134 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1136 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1139 if (info->num_clks == 1)
1142 ucon = rd_regl(port, S3C2410_UCON);
1143 ucon &= info->clksel_mask;
1144 return ucon >> info->clksel_shift;
1147 static void s3c24xx_serial_setsource(struct uart_port *port,
1148 unsigned int clk_sel)
1150 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1153 if (info->num_clks == 1)
1156 ucon = rd_regl(port, S3C2410_UCON);
1157 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1160 ucon &= ~info->clksel_mask;
1161 ucon |= clk_sel << info->clksel_shift;
1162 wr_regl(port, S3C2410_UCON, ucon);
1165 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1166 unsigned int req_baud, struct clk **best_clk,
1167 unsigned int *clk_num)
1169 struct s3c24xx_uart_info *info = ourport->info;
1172 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1173 char clkname[MAX_CLK_NAME_LENGTH];
1174 int calc_deviation, deviation = (1 << 30) - 1;
1176 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1177 ourport->info->def_clk_sel;
1178 for (cnt = 0; cnt < info->num_clks; cnt++) {
1179 if (!(clk_sel & (1 << cnt)))
1182 sprintf(clkname, "clk_uart_baud%d", cnt);
1183 clk = clk_get(ourport->port.dev, clkname);
1187 rate = clk_get_rate(clk);
1191 if (ourport->info->has_divslot) {
1192 unsigned long div = rate / req_baud;
1194 /* The UDIVSLOT register on the newer UARTs allows us to
1195 * get a divisor adjustment of 1/16th on the baud clock.
1197 * We don't keep the UDIVSLOT value (the 16ths we
1198 * calculated by not multiplying the baud by 16) as it
1199 * is easy enough to recalculate.
1205 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1206 baud = rate / (quot * 16);
1210 calc_deviation = req_baud - baud;
1211 if (calc_deviation < 0)
1212 calc_deviation = -calc_deviation;
1214 if (calc_deviation < deviation) {
1218 deviation = calc_deviation;
1227 * This table takes the fractional value of the baud divisor and gives
1228 * the recommended setting for the UDIVSLOT register.
1230 static u16 udivslot_table[16] = {
1249 static void s3c24xx_serial_set_termios(struct uart_port *port,
1250 struct ktermios *termios,
1251 struct ktermios *old)
1253 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1254 struct s3c24xx_uart_port *ourport = to_ourport(port);
1255 struct clk *clk = ERR_PTR(-EINVAL);
1256 unsigned long flags;
1257 unsigned int baud, quot, clk_sel = 0;
1260 unsigned int udivslot = 0;
1263 * We don't support modem control lines.
1265 termios->c_cflag &= ~(HUPCL | CMSPAR);
1266 termios->c_cflag |= CLOCAL;
1269 * Ask the core to calculate the divisor for us.
1272 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1273 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1274 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1275 quot = port->custom_divisor;
1279 /* check to see if we need to change clock source */
1281 if (ourport->baudclk != clk) {
1282 s3c24xx_serial_setsource(port, clk_sel);
1284 if (!IS_ERR(ourport->baudclk)) {
1285 clk_disable_unprepare(ourport->baudclk);
1286 ourport->baudclk = ERR_PTR(-EINVAL);
1289 clk_prepare_enable(clk);
1291 ourport->baudclk = clk;
1292 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1295 if (ourport->info->has_divslot) {
1296 unsigned int div = ourport->baudclk_rate / baud;
1298 if (cfg->has_fracval) {
1299 udivslot = (div & 15);
1300 dbg("fracval = %04x\n", udivslot);
1302 udivslot = udivslot_table[div & 15];
1303 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1307 switch (termios->c_cflag & CSIZE) {
1309 dbg("config: 5bits/char\n");
1310 ulcon = S3C2410_LCON_CS5;
1313 dbg("config: 6bits/char\n");
1314 ulcon = S3C2410_LCON_CS6;
1317 dbg("config: 7bits/char\n");
1318 ulcon = S3C2410_LCON_CS7;
1322 dbg("config: 8bits/char\n");
1323 ulcon = S3C2410_LCON_CS8;
1327 /* preserve original lcon IR settings */
1328 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1330 if (termios->c_cflag & CSTOPB)
1331 ulcon |= S3C2410_LCON_STOPB;
1333 if (termios->c_cflag & PARENB) {
1334 if (termios->c_cflag & PARODD)
1335 ulcon |= S3C2410_LCON_PODD;
1337 ulcon |= S3C2410_LCON_PEVEN;
1339 ulcon |= S3C2410_LCON_PNONE;
1342 spin_lock_irqsave(&port->lock, flags);
1344 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1345 ulcon, quot, udivslot);
1347 wr_regl(port, S3C2410_ULCON, ulcon);
1348 wr_regl(port, S3C2410_UBRDIV, quot);
1350 umcon = rd_regl(port, S3C2410_UMCON);
1351 if (termios->c_cflag & CRTSCTS) {
1352 umcon |= S3C2410_UMCOM_AFC;
1353 /* Disable RTS when RX FIFO contains 63 bytes */
1354 umcon &= ~S3C2412_UMCON_AFC_8;
1356 umcon &= ~S3C2410_UMCOM_AFC;
1358 wr_regl(port, S3C2410_UMCON, umcon);
1360 if (ourport->info->has_divslot)
1361 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1363 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1364 rd_regl(port, S3C2410_ULCON),
1365 rd_regl(port, S3C2410_UCON),
1366 rd_regl(port, S3C2410_UFCON));
1369 * Update the per-port timeout.
1371 uart_update_timeout(port, termios->c_cflag, baud);
1374 * Which character status flags are we interested in?
1376 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1377 if (termios->c_iflag & INPCK)
1378 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1379 S3C2410_UERSTAT_PARITY;
1381 * Which character status flags should we ignore?
1383 port->ignore_status_mask = 0;
1384 if (termios->c_iflag & IGNPAR)
1385 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1386 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1387 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1390 * Ignore all characters if CREAD is not set.
1392 if ((termios->c_cflag & CREAD) == 0)
1393 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1395 spin_unlock_irqrestore(&port->lock, flags);
1398 static const char *s3c24xx_serial_type(struct uart_port *port)
1400 switch (port->type) {
1408 return "S3C6400/10";
1414 #define MAP_SIZE (0x100)
1416 static void s3c24xx_serial_release_port(struct uart_port *port)
1418 release_mem_region(port->mapbase, MAP_SIZE);
1421 static int s3c24xx_serial_request_port(struct uart_port *port)
1423 const char *name = s3c24xx_serial_portname(port);
1424 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1427 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1429 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1431 if (flags & UART_CONFIG_TYPE &&
1432 s3c24xx_serial_request_port(port) == 0)
1433 port->type = info->type;
1437 * verify the new serial_struct (for TIOCSSERIAL).
1440 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1442 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1444 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1451 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1453 static struct console s3c24xx_serial_console;
1455 static int __init s3c24xx_serial_console_init(void)
1457 register_console(&s3c24xx_serial_console);
1460 console_initcall(s3c24xx_serial_console_init);
1462 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1464 #define S3C24XX_SERIAL_CONSOLE NULL
1467 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1468 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1469 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1473 static struct uart_ops s3c24xx_serial_ops = {
1474 .pm = s3c24xx_serial_pm,
1475 .tx_empty = s3c24xx_serial_tx_empty,
1476 .get_mctrl = s3c24xx_serial_get_mctrl,
1477 .set_mctrl = s3c24xx_serial_set_mctrl,
1478 .stop_tx = s3c24xx_serial_stop_tx,
1479 .start_tx = s3c24xx_serial_start_tx,
1480 .stop_rx = s3c24xx_serial_stop_rx,
1481 .break_ctl = s3c24xx_serial_break_ctl,
1482 .startup = s3c24xx_serial_startup,
1483 .shutdown = s3c24xx_serial_shutdown,
1484 .set_termios = s3c24xx_serial_set_termios,
1485 .type = s3c24xx_serial_type,
1486 .release_port = s3c24xx_serial_release_port,
1487 .request_port = s3c24xx_serial_request_port,
1488 .config_port = s3c24xx_serial_config_port,
1489 .verify_port = s3c24xx_serial_verify_port,
1490 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1491 .poll_get_char = s3c24xx_serial_get_poll_char,
1492 .poll_put_char = s3c24xx_serial_put_poll_char,
1496 static struct uart_driver s3c24xx_uart_drv = {
1497 .owner = THIS_MODULE,
1498 .driver_name = "s3c2410_serial",
1499 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1500 .cons = S3C24XX_SERIAL_CONSOLE,
1501 .dev_name = S3C24XX_SERIAL_NAME,
1502 .major = S3C24XX_SERIAL_MAJOR,
1503 .minor = S3C24XX_SERIAL_MINOR,
1506 #define __PORT_LOCK_UNLOCKED(i) \
1507 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1508 static struct s3c24xx_uart_port
1509 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1512 .lock = __PORT_LOCK_UNLOCKED(0),
1516 .ops = &s3c24xx_serial_ops,
1517 .flags = UPF_BOOT_AUTOCONF,
1523 .lock = __PORT_LOCK_UNLOCKED(1),
1527 .ops = &s3c24xx_serial_ops,
1528 .flags = UPF_BOOT_AUTOCONF,
1532 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1536 .lock = __PORT_LOCK_UNLOCKED(2),
1540 .ops = &s3c24xx_serial_ops,
1541 .flags = UPF_BOOT_AUTOCONF,
1546 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1549 .lock = __PORT_LOCK_UNLOCKED(3),
1553 .ops = &s3c24xx_serial_ops,
1554 .flags = UPF_BOOT_AUTOCONF,
1560 #undef __PORT_LOCK_UNLOCKED
1562 /* s3c24xx_serial_resetport
1564 * reset the fifos and other the settings.
1567 static void s3c24xx_serial_resetport(struct uart_port *port,
1568 struct s3c2410_uartcfg *cfg)
1570 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1571 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1572 unsigned int ucon_mask;
1574 ucon_mask = info->clksel_mask;
1575 if (info->type == PORT_S3C2440)
1576 ucon_mask |= S3C2440_UCON0_DIVMASK;
1579 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1581 /* reset both fifos */
1582 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1583 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1585 /* some delay is required after fifo reset */
1590 #ifdef CONFIG_CPU_FREQ
1592 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1593 unsigned long val, void *data)
1595 struct s3c24xx_uart_port *port;
1596 struct uart_port *uport;
1598 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1599 uport = &port->port;
1601 /* check to see if port is enabled */
1603 if (port->pm_level != 0)
1606 /* try and work out if the baudrate is changing, we can detect
1607 * a change in rate, but we do not have support for detecting
1608 * a disturbance in the clock-rate over the change.
1611 if (IS_ERR(port->baudclk))
1614 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1617 if (val == CPUFREQ_PRECHANGE) {
1618 /* we should really shut the port down whilst the
1619 * frequency change is in progress. */
1621 } else if (val == CPUFREQ_POSTCHANGE) {
1622 struct ktermios *termios;
1623 struct tty_struct *tty;
1625 if (uport->state == NULL)
1628 tty = uport->state->port.tty;
1633 termios = &tty->termios;
1635 if (termios == NULL) {
1636 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1640 s3c24xx_serial_set_termios(uport, termios, NULL);
1648 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1650 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1652 return cpufreq_register_notifier(&port->freq_transition,
1653 CPUFREQ_TRANSITION_NOTIFIER);
1657 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1659 cpufreq_unregister_notifier(&port->freq_transition,
1660 CPUFREQ_TRANSITION_NOTIFIER);
1665 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1671 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1676 /* s3c24xx_serial_init_port
1678 * initialise a single serial port from the platform device given
1681 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1682 struct platform_device *platdev)
1684 struct uart_port *port = &ourport->port;
1685 struct s3c2410_uartcfg *cfg = ourport->cfg;
1686 struct resource *res;
1689 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1691 if (platdev == NULL)
1694 if (port->mapbase != 0)
1697 /* setup info for port */
1698 port->dev = &platdev->dev;
1700 /* Startup sequence is different for s3c64xx and higher SoC's */
1701 if (s3c24xx_serial_has_interrupt_mask(port))
1702 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1706 if (cfg->uart_flags & UPF_CONS_FLOW) {
1707 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1708 port->flags |= UPF_CONS_FLOW;
1711 /* sort our the physical and virtual addresses for each UART */
1713 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1715 dev_err(port->dev, "failed to find memory resource for uart\n");
1719 dbg("resource %pR)\n", res);
1721 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1722 if (!port->membase) {
1723 dev_err(port->dev, "failed to remap controller address\n");
1727 port->mapbase = res->start;
1728 ret = platform_get_irq(platdev, 0);
1733 ourport->rx_irq = ret;
1734 ourport->tx_irq = ret + 1;
1737 ret = platform_get_irq(platdev, 1);
1739 ourport->tx_irq = ret;
1741 * DMA is currently supported only on DT platforms, if DMA properties
1744 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1746 ourport->dma = devm_kzalloc(port->dev,
1747 sizeof(*ourport->dma),
1753 ourport->clk = clk_get(&platdev->dev, "uart");
1754 if (IS_ERR(ourport->clk)) {
1755 pr_err("%s: Controller clock not found\n",
1756 dev_name(&platdev->dev));
1757 return PTR_ERR(ourport->clk);
1760 ret = clk_prepare_enable(ourport->clk);
1762 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1763 clk_put(ourport->clk);
1767 /* Keep all interrupts masked and cleared */
1768 if (s3c24xx_serial_has_interrupt_mask(port)) {
1769 wr_regl(port, S3C64XX_UINTM, 0xf);
1770 wr_regl(port, S3C64XX_UINTP, 0xf);
1771 wr_regl(port, S3C64XX_UINTSP, 0xf);
1774 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1775 &port->mapbase, port->membase, port->irq,
1776 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1778 /* reset the fifos (and setup the uart) */
1779 s3c24xx_serial_resetport(port, cfg);
1783 /* Device driver serial port probe */
1785 static const struct of_device_id s3c24xx_uart_dt_match[];
1786 static int probe_index;
1788 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1789 struct platform_device *pdev)
1792 if (pdev->dev.of_node) {
1793 const struct of_device_id *match;
1794 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1795 return (struct s3c24xx_serial_drv_data *)match->data;
1798 return (struct s3c24xx_serial_drv_data *)
1799 platform_get_device_id(pdev)->driver_data;
1802 static int s3c24xx_serial_probe(struct platform_device *pdev)
1804 struct device_node *np = pdev->dev.of_node;
1805 struct s3c24xx_uart_port *ourport;
1806 int index = probe_index;
1810 ret = of_alias_get_id(np, "serial");
1815 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1817 ourport = &s3c24xx_serial_ports[index];
1819 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1820 if (!ourport->drv_data) {
1821 dev_err(&pdev->dev, "could not find driver data\n");
1825 ourport->baudclk = ERR_PTR(-EINVAL);
1826 ourport->info = ourport->drv_data->info;
1827 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1828 dev_get_platdata(&pdev->dev) :
1829 ourport->drv_data->def_cfg;
1832 of_property_read_u32(np,
1833 "samsung,uart-fifosize", &ourport->port.fifosize);
1835 if (ourport->drv_data->fifosize[index])
1836 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1837 else if (ourport->info->fifosize)
1838 ourport->port.fifosize = ourport->info->fifosize;
1842 dbg("%s: initialising port %p...\n", __func__, ourport);
1844 ret = s3c24xx_serial_init_port(ourport, pdev);
1848 if (!s3c24xx_uart_drv.state) {
1849 ret = uart_register_driver(&s3c24xx_uart_drv);
1851 pr_err("Failed to register Samsung UART driver\n");
1856 dbg("%s: adding port\n", __func__);
1857 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1858 platform_set_drvdata(pdev, &ourport->port);
1861 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1862 * so that a potential re-enablement through the pm-callback overlaps
1863 * and keeps the clock enabled in this case.
1865 clk_disable_unprepare(ourport->clk);
1867 ret = s3c24xx_serial_cpufreq_register(ourport);
1869 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1874 static int s3c24xx_serial_remove(struct platform_device *dev)
1876 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1879 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1880 uart_remove_one_port(&s3c24xx_uart_drv, port);
1883 uart_unregister_driver(&s3c24xx_uart_drv);
1888 /* UART power management code */
1889 #ifdef CONFIG_PM_SLEEP
1890 static int s3c24xx_serial_suspend(struct device *dev)
1892 struct uart_port *port = s3c24xx_dev_to_port(dev);
1895 uart_suspend_port(&s3c24xx_uart_drv, port);
1900 static int s3c24xx_serial_resume(struct device *dev)
1902 struct uart_port *port = s3c24xx_dev_to_port(dev);
1903 struct s3c24xx_uart_port *ourport = to_ourport(port);
1906 clk_prepare_enable(ourport->clk);
1907 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1908 clk_disable_unprepare(ourport->clk);
1910 uart_resume_port(&s3c24xx_uart_drv, port);
1916 static int s3c24xx_serial_resume_noirq(struct device *dev)
1918 struct uart_port *port = s3c24xx_dev_to_port(dev);
1921 /* restore IRQ mask */
1922 if (s3c24xx_serial_has_interrupt_mask(port)) {
1923 unsigned int uintm = 0xf;
1924 if (tx_enabled(port))
1925 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1926 if (rx_enabled(port))
1927 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1928 wr_regl(port, S3C64XX_UINTM, uintm);
1935 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1936 .suspend = s3c24xx_serial_suspend,
1937 .resume = s3c24xx_serial_resume,
1938 .resume_noirq = s3c24xx_serial_resume_noirq,
1940 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1942 #else /* !CONFIG_PM_SLEEP */
1944 #define SERIAL_SAMSUNG_PM_OPS NULL
1945 #endif /* CONFIG_PM_SLEEP */
1949 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1951 static struct uart_port *cons_uart;
1954 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1956 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1957 unsigned long ufstat, utrstat;
1959 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1960 /* fifo mode - check amount of data in fifo registers... */
1962 ufstat = rd_regl(port, S3C2410_UFSTAT);
1963 return (ufstat & info->tx_fifofull) ? 0 : 1;
1966 /* in non-fifo mode, we go and use the tx buffer empty */
1968 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1969 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1973 s3c24xx_port_configured(unsigned int ucon)
1975 /* consider the serial port configured if the tx/rx mode set */
1976 return (ucon & 0xf) != 0;
1979 #ifdef CONFIG_CONSOLE_POLL
1981 * Console polling routines for writing and reading from the uart while
1982 * in an interrupt or debug context.
1985 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1987 struct s3c24xx_uart_port *ourport = to_ourport(port);
1988 unsigned int ufstat;
1990 ufstat = rd_regl(port, S3C2410_UFSTAT);
1991 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1992 return NO_POLL_CHAR;
1994 return rd_regb(port, S3C2410_URXH);
1997 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2000 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2001 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2003 /* not possible to xmit on unconfigured port */
2004 if (!s3c24xx_port_configured(ucon))
2007 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2009 wr_regb(port, S3C2410_UTXH, c);
2012 #endif /* CONFIG_CONSOLE_POLL */
2015 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2017 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2019 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2021 wr_regb(port, S3C2410_UTXH, ch);
2025 s3c24xx_serial_console_write(struct console *co, const char *s,
2028 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2030 /* not possible to xmit on unconfigured port */
2031 if (!s3c24xx_port_configured(ucon))
2034 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2038 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2039 int *parity, int *bits)
2044 unsigned int ubrdiv;
2046 unsigned int clk_sel;
2047 char clk_name[MAX_CLK_NAME_LENGTH];
2049 ulcon = rd_regl(port, S3C2410_ULCON);
2050 ucon = rd_regl(port, S3C2410_UCON);
2051 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2053 dbg("s3c24xx_serial_get_options: port=%p\n"
2054 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2055 port, ulcon, ucon, ubrdiv);
2057 if (s3c24xx_port_configured(ucon)) {
2058 switch (ulcon & S3C2410_LCON_CSMASK) {
2059 case S3C2410_LCON_CS5:
2062 case S3C2410_LCON_CS6:
2065 case S3C2410_LCON_CS7:
2068 case S3C2410_LCON_CS8:
2074 switch (ulcon & S3C2410_LCON_PMASK) {
2075 case S3C2410_LCON_PEVEN:
2079 case S3C2410_LCON_PODD:
2083 case S3C2410_LCON_PNONE:
2088 /* now calculate the baud rate */
2090 clk_sel = s3c24xx_serial_getsource(port);
2091 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2093 clk = clk_get(port->dev, clk_name);
2095 rate = clk_get_rate(clk);
2099 *baud = rate / (16 * (ubrdiv + 1));
2100 dbg("calculated baud %d\n", *baud);
2106 s3c24xx_serial_console_setup(struct console *co, char *options)
2108 struct uart_port *port;
2114 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2115 co, co->index, options);
2117 /* is this a valid port */
2119 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2122 port = &s3c24xx_serial_ports[co->index].port;
2124 /* is the port configured? */
2126 if (port->mapbase == 0x0)
2131 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2134 * Check whether an invalid uart number has been specified, and
2135 * if so, search for the first available port that does have
2139 uart_parse_options(options, &baud, &parity, &bits, &flow);
2141 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2143 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2145 return uart_set_options(port, co, baud, parity, bits, flow);
2148 static struct console s3c24xx_serial_console = {
2149 .name = S3C24XX_SERIAL_NAME,
2150 .device = uart_console_device,
2151 .flags = CON_PRINTBUFFER,
2153 .write = s3c24xx_serial_console_write,
2154 .setup = s3c24xx_serial_console_setup,
2155 .data = &s3c24xx_uart_drv,
2157 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2159 #ifdef CONFIG_CPU_S3C2410
2160 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2161 .info = &(struct s3c24xx_uart_info) {
2162 .name = "Samsung S3C2410 UART",
2163 .type = PORT_S3C2410,
2165 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2166 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2167 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2168 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2169 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2170 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2171 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2173 .clksel_mask = S3C2410_UCON_CLKMASK,
2174 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2176 .def_cfg = &(struct s3c2410_uartcfg) {
2177 .ucon = S3C2410_UCON_DEFAULT,
2178 .ufcon = S3C2410_UFCON_DEFAULT,
2181 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2183 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2186 #ifdef CONFIG_CPU_S3C2412
2187 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2188 .info = &(struct s3c24xx_uart_info) {
2189 .name = "Samsung S3C2412 UART",
2190 .type = PORT_S3C2412,
2193 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2194 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2195 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2196 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2197 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2198 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2199 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2201 .clksel_mask = S3C2412_UCON_CLKMASK,
2202 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2204 .def_cfg = &(struct s3c2410_uartcfg) {
2205 .ucon = S3C2410_UCON_DEFAULT,
2206 .ufcon = S3C2410_UFCON_DEFAULT,
2209 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2211 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2214 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2215 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2216 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2217 .info = &(struct s3c24xx_uart_info) {
2218 .name = "Samsung S3C2440 UART",
2219 .type = PORT_S3C2440,
2222 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2223 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2224 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2225 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2226 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2227 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2228 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2230 .clksel_mask = S3C2412_UCON_CLKMASK,
2231 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2233 .def_cfg = &(struct s3c2410_uartcfg) {
2234 .ucon = S3C2410_UCON_DEFAULT,
2235 .ufcon = S3C2410_UFCON_DEFAULT,
2238 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2240 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2243 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2244 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2245 .info = &(struct s3c24xx_uart_info) {
2246 .name = "Samsung S3C6400 UART",
2247 .type = PORT_S3C6400,
2250 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2251 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2252 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2253 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2254 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2255 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2256 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2258 .clksel_mask = S3C6400_UCON_CLKMASK,
2259 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2261 .def_cfg = &(struct s3c2410_uartcfg) {
2262 .ucon = S3C2410_UCON_DEFAULT,
2263 .ufcon = S3C2410_UFCON_DEFAULT,
2266 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2268 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2271 #ifdef CONFIG_CPU_S5PV210
2272 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2273 .info = &(struct s3c24xx_uart_info) {
2274 .name = "Samsung S5PV210 UART",
2275 .type = PORT_S3C6400,
2277 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2278 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2279 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2280 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2281 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2282 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2283 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2285 .clksel_mask = S5PV210_UCON_CLKMASK,
2286 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2288 .def_cfg = &(struct s3c2410_uartcfg) {
2289 .ucon = S5PV210_UCON_DEFAULT,
2290 .ufcon = S5PV210_UFCON_DEFAULT,
2292 .fifosize = { 256, 64, 16, 16 },
2294 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2296 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2299 #if defined(CONFIG_ARCH_EXYNOS)
2300 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2301 .info = &(struct s3c24xx_uart_info) { \
2302 .name = "Samsung Exynos UART", \
2303 .type = PORT_S3C6400, \
2305 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2306 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2307 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2308 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2309 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2310 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2311 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2314 .clksel_shift = 0, \
2316 .def_cfg = &(struct s3c2410_uartcfg) { \
2317 .ucon = S5PV210_UCON_DEFAULT, \
2318 .ufcon = S5PV210_UFCON_DEFAULT, \
2322 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2323 EXYNOS_COMMON_SERIAL_DRV_DATA,
2324 .fifosize = { 256, 64, 16, 16 },
2327 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2328 EXYNOS_COMMON_SERIAL_DRV_DATA,
2329 .fifosize = { 64, 256, 16, 256 },
2332 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2333 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2335 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2336 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2339 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
2341 .name = "s3c2410-uart",
2342 .driver_data = S3C2410_SERIAL_DRV_DATA,
2344 .name = "s3c2412-uart",
2345 .driver_data = S3C2412_SERIAL_DRV_DATA,
2347 .name = "s3c2440-uart",
2348 .driver_data = S3C2440_SERIAL_DRV_DATA,
2350 .name = "s3c6400-uart",
2351 .driver_data = S3C6400_SERIAL_DRV_DATA,
2353 .name = "s5pv210-uart",
2354 .driver_data = S5PV210_SERIAL_DRV_DATA,
2356 .name = "exynos4210-uart",
2357 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2359 .name = "exynos5433-uart",
2360 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2364 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2367 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2368 { .compatible = "samsung,s3c2410-uart",
2369 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2370 { .compatible = "samsung,s3c2412-uart",
2371 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2372 { .compatible = "samsung,s3c2440-uart",
2373 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2374 { .compatible = "samsung,s3c6400-uart",
2375 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2376 { .compatible = "samsung,s5pv210-uart",
2377 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2378 { .compatible = "samsung,exynos4210-uart",
2379 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2380 { .compatible = "samsung,exynos5433-uart",
2381 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2384 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2387 static struct platform_driver samsung_serial_driver = {
2388 .probe = s3c24xx_serial_probe,
2389 .remove = s3c24xx_serial_remove,
2390 .id_table = s3c24xx_serial_driver_ids,
2392 .name = "samsung-uart",
2393 .pm = SERIAL_SAMSUNG_PM_OPS,
2394 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2398 module_platform_driver(samsung_serial_driver);
2400 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2405 struct samsung_early_console_data {
2409 static void samsung_early_busyuart(struct uart_port *port)
2411 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2415 static void samsung_early_busyuart_fifo(struct uart_port *port)
2417 struct samsung_early_console_data *data = port->private_data;
2419 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2423 static void samsung_early_putc(struct uart_port *port, int c)
2425 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2426 samsung_early_busyuart_fifo(port);
2428 samsung_early_busyuart(port);
2430 writeb(c, port->membase + S3C2410_UTXH);
2433 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2435 struct earlycon_device *dev = con->data;
2437 uart_console_write(&dev->port, s, n, samsung_early_putc);
2440 static int __init samsung_early_console_setup(struct earlycon_device *device,
2443 if (!device->port.membase)
2446 device->con->write = samsung_early_write;
2451 static struct samsung_early_console_data s3c2410_early_console_data = {
2452 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2455 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2458 device->port.private_data = &s3c2410_early_console_data;
2459 return samsung_early_console_setup(device, opt);
2461 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2462 s3c2410_early_console_setup);
2463 EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2465 /* S3C2412, S3C2440, S3C64xx */
2466 static struct samsung_early_console_data s3c2440_early_console_data = {
2467 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2470 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2473 device->port.private_data = &s3c2440_early_console_data;
2474 return samsung_early_console_setup(device, opt);
2476 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2477 s3c2440_early_console_setup);
2478 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2479 s3c2440_early_console_setup);
2480 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2481 s3c2440_early_console_setup);
2482 EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2483 EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2484 EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2486 /* S5PV210, EXYNOS */
2487 static struct samsung_early_console_data s5pv210_early_console_data = {
2488 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2491 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2494 device->port.private_data = &s5pv210_early_console_data;
2495 return samsung_early_console_setup(device, opt);
2497 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2498 s5pv210_early_console_setup);
2499 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2500 s5pv210_early_console_setup);
2501 EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2502 EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2505 MODULE_ALIAS("platform:samsung-uart");
2506 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2507 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2508 MODULE_LICENSE("GPL v2");