2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
56 /* UART name and device definitions */
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
62 /* macros to change one thing to another */
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
67 /* flag to ignore all characters coming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
70 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
72 return container_of(port, struct s3c24xx_uart_port, port);
75 /* translate a port to the device name */
77 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
79 return to_platform_device(port->dev)->name;
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
92 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
94 return to_ourport(port)->info->type == PORT_S3C6400;
97 static void s3c24xx_serial_rx_enable(struct uart_port *port)
100 unsigned int ucon, ufcon;
103 spin_lock_irqsave(&port->lock, flags);
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
120 static void s3c24xx_serial_rx_disable(struct uart_port *port)
125 spin_lock_irqsave(&port->lock, flags);
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
135 static void s3c24xx_serial_stop_tx(struct uart_port *port)
137 struct s3c24xx_uart_port *ourport = to_ourport(port);
139 if (tx_enabled(port)) {
140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
144 disable_irq_nosync(ourport->tx_irq);
145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
151 static void s3c24xx_serial_start_tx(struct uart_port *port)
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
163 enable_irq(ourport->tx_irq);
164 tx_enabled(port) = 1;
168 static void s3c24xx_serial_stop_rx(struct uart_port *port)
170 struct s3c24xx_uart_port *ourport = to_ourport(port);
172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
178 disable_irq_nosync(ourport->rx_irq);
179 rx_enabled(port) = 0;
183 static void s3c24xx_serial_enable_ms(struct uart_port *port)
187 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
189 return to_ourport(port)->info;
192 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
194 struct s3c24xx_uart_port *ourport;
196 if (port->dev == NULL)
199 ourport = container_of(port, struct s3c24xx_uart_port, port);
203 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
206 struct s3c24xx_uart_info *info = ourport->info;
208 if (ufstat & info->rx_fifofull)
209 return ourport->port.fifosize;
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
215 /* ? - where has parity gone?? */
216 #define S3C2410_UERSTAT_PARITY (0x1000)
219 s3c24xx_serial_rx_chars(int irq, void *dev_id)
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
223 unsigned int ufcon, ch, flag, ufstat, uerstat;
227 spin_lock_irqsave(&port->lock, flags);
229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
242 if (rx_enabled(port)) {
244 rx_enabled(port) = 0;
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 spin_unlock_irqrestore(&port->lock,
260 /* insert the character into the buffer */
265 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
266 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
269 /* check for break */
270 if (uerstat & S3C2410_UERSTAT_BREAK) {
273 if (uart_handle_break(port))
277 if (uerstat & S3C2410_UERSTAT_FRAME)
278 port->icount.frame++;
279 if (uerstat & S3C2410_UERSTAT_OVERRUN)
280 port->icount.overrun++;
282 uerstat &= port->read_status_mask;
284 if (uerstat & S3C2410_UERSTAT_BREAK)
286 else if (uerstat & S3C2410_UERSTAT_PARITY)
288 else if (uerstat & (S3C2410_UERSTAT_FRAME |
289 S3C2410_UERSTAT_OVERRUN))
293 if (uart_handle_sysrq_char(port, ch))
296 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
303 spin_unlock_irqrestore(&port->lock, flags);
304 tty_flip_buffer_push(&port->state->port);
310 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
312 struct s3c24xx_uart_port *ourport = id;
313 struct uart_port *port = &ourport->port;
314 struct circ_buf *xmit = &port->state->xmit;
318 spin_lock_irqsave(&port->lock, flags);
321 wr_regb(port, S3C2410_UTXH, port->x_char);
327 /* if there isn't anything more to transmit, or the uart is now
328 * stopped, disable the uart and exit
331 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
332 s3c24xx_serial_stop_tx(port);
336 /* try and drain the buffer... */
338 while (!uart_circ_empty(xmit) && count-- > 0) {
339 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
342 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
348 spin_unlock(&port->lock);
349 uart_write_wakeup(port);
350 spin_lock(&port->lock);
353 if (uart_circ_empty(xmit))
354 s3c24xx_serial_stop_tx(port);
357 spin_unlock_irqrestore(&port->lock, flags);
361 /* interrupt handler for s3c64xx and later SoC's.*/
362 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
364 struct s3c24xx_uart_port *ourport = id;
365 struct uart_port *port = &ourport->port;
366 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
367 irqreturn_t ret = IRQ_HANDLED;
369 if (pend & S3C64XX_UINTM_RXD_MSK) {
370 ret = s3c24xx_serial_rx_chars(irq, id);
371 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
373 if (pend & S3C64XX_UINTM_TXD_MSK) {
374 ret = s3c24xx_serial_tx_chars(irq, id);
375 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
380 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
382 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
383 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
384 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
386 if (ufcon & S3C2410_UFCON_FIFOMODE) {
387 if ((ufstat & info->tx_fifomask) != 0 ||
388 (ufstat & info->tx_fifofull))
394 return s3c24xx_serial_txempty_nofifo(port);
397 /* no modem control lines */
398 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
400 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
402 if (umstat & S3C2410_UMSTAT_CTS)
403 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
405 return TIOCM_CAR | TIOCM_DSR;
408 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
410 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
412 if (mctrl & TIOCM_RTS)
413 umcon |= S3C2410_UMCOM_RTS_LOW;
415 umcon &= ~S3C2410_UMCOM_RTS_LOW;
417 wr_regl(port, S3C2410_UMCON, umcon);
420 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
425 spin_lock_irqsave(&port->lock, flags);
427 ucon = rd_regl(port, S3C2410_UCON);
430 ucon |= S3C2410_UCON_SBREAK;
432 ucon &= ~S3C2410_UCON_SBREAK;
434 wr_regl(port, S3C2410_UCON, ucon);
436 spin_unlock_irqrestore(&port->lock, flags);
439 static void s3c24xx_serial_shutdown(struct uart_port *port)
441 struct s3c24xx_uart_port *ourport = to_ourport(port);
443 if (ourport->tx_claimed) {
444 if (!s3c24xx_serial_has_interrupt_mask(port))
445 free_irq(ourport->tx_irq, ourport);
446 tx_enabled(port) = 0;
447 ourport->tx_claimed = 0;
450 if (ourport->rx_claimed) {
451 if (!s3c24xx_serial_has_interrupt_mask(port))
452 free_irq(ourport->rx_irq, ourport);
453 ourport->rx_claimed = 0;
454 rx_enabled(port) = 0;
457 /* Clear pending interrupts and mask all interrupts */
458 if (s3c24xx_serial_has_interrupt_mask(port)) {
459 free_irq(port->irq, ourport);
461 wr_regl(port, S3C64XX_UINTP, 0xf);
462 wr_regl(port, S3C64XX_UINTM, 0xf);
466 static int s3c24xx_serial_startup(struct uart_port *port)
468 struct s3c24xx_uart_port *ourport = to_ourport(port);
471 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
472 port->mapbase, port->membase);
474 rx_enabled(port) = 1;
476 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
477 s3c24xx_serial_portname(port), ourport);
480 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
484 ourport->rx_claimed = 1;
486 dbg("requesting tx irq...\n");
488 tx_enabled(port) = 1;
490 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
491 s3c24xx_serial_portname(port), ourport);
494 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
498 ourport->tx_claimed = 1;
500 dbg("s3c24xx_serial_startup ok\n");
502 /* the port reset code should have done the correct
503 * register setup for the port controls */
508 s3c24xx_serial_shutdown(port);
512 static int s3c64xx_serial_startup(struct uart_port *port)
514 struct s3c24xx_uart_port *ourport = to_ourport(port);
517 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
518 port->mapbase, port->membase);
520 wr_regl(port, S3C64XX_UINTM, 0xf);
522 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
523 s3c24xx_serial_portname(port), ourport);
525 dev_err(port->dev, "cannot get irq %d\n", port->irq);
529 /* For compatibility with s3c24xx Soc's */
530 rx_enabled(port) = 1;
531 ourport->rx_claimed = 1;
532 tx_enabled(port) = 0;
533 ourport->tx_claimed = 1;
535 /* Enable Rx Interrupt */
536 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
537 dbg("s3c64xx_serial_startup ok\n");
541 /* power power management control */
543 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
546 struct s3c24xx_uart_port *ourport = to_ourport(port);
548 ourport->pm_level = level;
552 if (!IS_ERR(ourport->baudclk))
553 clk_disable_unprepare(ourport->baudclk);
555 clk_disable_unprepare(ourport->clk);
559 clk_prepare_enable(ourport->clk);
561 if (!IS_ERR(ourport->baudclk))
562 clk_prepare_enable(ourport->baudclk);
566 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
570 /* baud rate calculation
572 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
573 * of different sources, including the peripheral clock ("pclk") and an
574 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
575 * with a programmable extra divisor.
577 * The following code goes through the clock sources, and calculates the
578 * baud clocks (and the resultant actual baud rates) and then tries to
579 * pick the closest one and select that.
583 #define MAX_CLK_NAME_LENGTH 15
585 static inline int s3c24xx_serial_getsource(struct uart_port *port)
587 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
590 if (info->num_clks == 1)
593 ucon = rd_regl(port, S3C2410_UCON);
594 ucon &= info->clksel_mask;
595 return ucon >> info->clksel_shift;
598 static void s3c24xx_serial_setsource(struct uart_port *port,
599 unsigned int clk_sel)
601 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
604 if (info->num_clks == 1)
607 ucon = rd_regl(port, S3C2410_UCON);
608 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
611 ucon &= ~info->clksel_mask;
612 ucon |= clk_sel << info->clksel_shift;
613 wr_regl(port, S3C2410_UCON, ucon);
616 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
617 unsigned int req_baud, struct clk **best_clk,
618 unsigned int *clk_num)
620 struct s3c24xx_uart_info *info = ourport->info;
623 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
624 char clkname[MAX_CLK_NAME_LENGTH];
625 int calc_deviation, deviation = (1 << 30) - 1;
627 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
628 ourport->info->def_clk_sel;
629 for (cnt = 0; cnt < info->num_clks; cnt++) {
630 if (!(clk_sel & (1 << cnt)))
633 sprintf(clkname, "clk_uart_baud%d", cnt);
634 clk = clk_get(ourport->port.dev, clkname);
638 rate = clk_get_rate(clk);
642 if (ourport->info->has_divslot) {
643 unsigned long div = rate / req_baud;
645 /* The UDIVSLOT register on the newer UARTs allows us to
646 * get a divisor adjustment of 1/16th on the baud clock.
648 * We don't keep the UDIVSLOT value (the 16ths we
649 * calculated by not multiplying the baud by 16) as it
650 * is easy enough to recalculate.
656 quot = (rate + (8 * req_baud)) / (16 * req_baud);
657 baud = rate / (quot * 16);
661 calc_deviation = req_baud - baud;
662 if (calc_deviation < 0)
663 calc_deviation = -calc_deviation;
665 if (calc_deviation < deviation) {
669 deviation = calc_deviation;
678 * This table takes the fractional value of the baud divisor and gives
679 * the recommended setting for the UDIVSLOT register.
681 static u16 udivslot_table[16] = {
700 static void s3c24xx_serial_set_termios(struct uart_port *port,
701 struct ktermios *termios,
702 struct ktermios *old)
704 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
705 struct s3c24xx_uart_port *ourport = to_ourport(port);
706 struct clk *clk = ERR_PTR(-EINVAL);
708 unsigned int baud, quot, clk_sel = 0;
711 unsigned int udivslot = 0;
714 * We don't support modem control lines.
716 termios->c_cflag &= ~(HUPCL | CMSPAR);
717 termios->c_cflag |= CLOCAL;
720 * Ask the core to calculate the divisor for us.
723 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
724 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
725 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
726 quot = port->custom_divisor;
730 /* check to see if we need to change clock source */
732 if (ourport->baudclk != clk) {
733 s3c24xx_serial_setsource(port, clk_sel);
735 if (!IS_ERR(ourport->baudclk)) {
736 clk_disable_unprepare(ourport->baudclk);
737 ourport->baudclk = ERR_PTR(-EINVAL);
740 clk_prepare_enable(clk);
742 ourport->baudclk = clk;
743 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
746 if (ourport->info->has_divslot) {
747 unsigned int div = ourport->baudclk_rate / baud;
749 if (cfg->has_fracval) {
750 udivslot = (div & 15);
751 dbg("fracval = %04x\n", udivslot);
753 udivslot = udivslot_table[div & 15];
754 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
758 switch (termios->c_cflag & CSIZE) {
760 dbg("config: 5bits/char\n");
761 ulcon = S3C2410_LCON_CS5;
764 dbg("config: 6bits/char\n");
765 ulcon = S3C2410_LCON_CS6;
768 dbg("config: 7bits/char\n");
769 ulcon = S3C2410_LCON_CS7;
773 dbg("config: 8bits/char\n");
774 ulcon = S3C2410_LCON_CS8;
778 /* preserve original lcon IR settings */
779 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
781 if (termios->c_cflag & CSTOPB)
782 ulcon |= S3C2410_LCON_STOPB;
784 if (termios->c_cflag & PARENB) {
785 if (termios->c_cflag & PARODD)
786 ulcon |= S3C2410_LCON_PODD;
788 ulcon |= S3C2410_LCON_PEVEN;
790 ulcon |= S3C2410_LCON_PNONE;
793 spin_lock_irqsave(&port->lock, flags);
795 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
796 ulcon, quot, udivslot);
798 wr_regl(port, S3C2410_ULCON, ulcon);
799 wr_regl(port, S3C2410_UBRDIV, quot);
801 umcon = rd_regl(port, S3C2410_UMCON);
802 if (termios->c_cflag & CRTSCTS) {
803 umcon |= S3C2410_UMCOM_AFC;
804 /* Disable RTS when RX FIFO contains 63 bytes */
805 umcon &= ~S3C2412_UMCON_AFC_8;
807 umcon &= ~S3C2410_UMCOM_AFC;
809 wr_regl(port, S3C2410_UMCON, umcon);
811 if (ourport->info->has_divslot)
812 wr_regl(port, S3C2443_DIVSLOT, udivslot);
814 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
815 rd_regl(port, S3C2410_ULCON),
816 rd_regl(port, S3C2410_UCON),
817 rd_regl(port, S3C2410_UFCON));
820 * Update the per-port timeout.
822 uart_update_timeout(port, termios->c_cflag, baud);
825 * Which character status flags are we interested in?
827 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
828 if (termios->c_iflag & INPCK)
829 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
832 * Which character status flags should we ignore?
834 port->ignore_status_mask = 0;
835 if (termios->c_iflag & IGNPAR)
836 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
837 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
838 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
841 * Ignore all characters if CREAD is not set.
843 if ((termios->c_cflag & CREAD) == 0)
844 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
846 spin_unlock_irqrestore(&port->lock, flags);
849 static const char *s3c24xx_serial_type(struct uart_port *port)
851 switch (port->type) {
865 #define MAP_SIZE (0x100)
867 static void s3c24xx_serial_release_port(struct uart_port *port)
869 release_mem_region(port->mapbase, MAP_SIZE);
872 static int s3c24xx_serial_request_port(struct uart_port *port)
874 const char *name = s3c24xx_serial_portname(port);
875 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
878 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
880 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
882 if (flags & UART_CONFIG_TYPE &&
883 s3c24xx_serial_request_port(port) == 0)
884 port->type = info->type;
888 * verify the new serial_struct (for TIOCSSERIAL).
891 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
893 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
895 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
902 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
904 static struct console s3c24xx_serial_console;
906 static int __init s3c24xx_serial_console_init(void)
908 register_console(&s3c24xx_serial_console);
911 console_initcall(s3c24xx_serial_console_init);
913 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
915 #define S3C24XX_SERIAL_CONSOLE NULL
918 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
919 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
920 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
924 static struct uart_ops s3c24xx_serial_ops = {
925 .pm = s3c24xx_serial_pm,
926 .tx_empty = s3c24xx_serial_tx_empty,
927 .get_mctrl = s3c24xx_serial_get_mctrl,
928 .set_mctrl = s3c24xx_serial_set_mctrl,
929 .stop_tx = s3c24xx_serial_stop_tx,
930 .start_tx = s3c24xx_serial_start_tx,
931 .stop_rx = s3c24xx_serial_stop_rx,
932 .enable_ms = s3c24xx_serial_enable_ms,
933 .break_ctl = s3c24xx_serial_break_ctl,
934 .startup = s3c24xx_serial_startup,
935 .shutdown = s3c24xx_serial_shutdown,
936 .set_termios = s3c24xx_serial_set_termios,
937 .type = s3c24xx_serial_type,
938 .release_port = s3c24xx_serial_release_port,
939 .request_port = s3c24xx_serial_request_port,
940 .config_port = s3c24xx_serial_config_port,
941 .verify_port = s3c24xx_serial_verify_port,
942 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
943 .poll_get_char = s3c24xx_serial_get_poll_char,
944 .poll_put_char = s3c24xx_serial_put_poll_char,
948 static struct uart_driver s3c24xx_uart_drv = {
949 .owner = THIS_MODULE,
950 .driver_name = "s3c2410_serial",
951 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
952 .cons = S3C24XX_SERIAL_CONSOLE,
953 .dev_name = S3C24XX_SERIAL_NAME,
954 .major = S3C24XX_SERIAL_MAJOR,
955 .minor = S3C24XX_SERIAL_MINOR,
958 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
961 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
965 .ops = &s3c24xx_serial_ops,
966 .flags = UPF_BOOT_AUTOCONF,
972 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
976 .ops = &s3c24xx_serial_ops,
977 .flags = UPF_BOOT_AUTOCONF,
981 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
985 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
989 .ops = &s3c24xx_serial_ops,
990 .flags = UPF_BOOT_AUTOCONF,
995 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
998 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1002 .ops = &s3c24xx_serial_ops,
1003 .flags = UPF_BOOT_AUTOCONF,
1010 /* s3c24xx_serial_resetport
1012 * reset the fifos and other the settings.
1015 static void s3c24xx_serial_resetport(struct uart_port *port,
1016 struct s3c2410_uartcfg *cfg)
1018 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1019 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1020 unsigned int ucon_mask;
1022 ucon_mask = info->clksel_mask;
1023 if (info->type == PORT_S3C2440)
1024 ucon_mask |= S3C2440_UCON0_DIVMASK;
1027 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1029 /* reset both fifos */
1030 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1031 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1033 /* some delay is required after fifo reset */
1038 #ifdef CONFIG_CPU_FREQ
1040 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1041 unsigned long val, void *data)
1043 struct s3c24xx_uart_port *port;
1044 struct uart_port *uport;
1046 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1047 uport = &port->port;
1049 /* check to see if port is enabled */
1051 if (port->pm_level != 0)
1054 /* try and work out if the baudrate is changing, we can detect
1055 * a change in rate, but we do not have support for detecting
1056 * a disturbance in the clock-rate over the change.
1059 if (IS_ERR(port->baudclk))
1062 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1065 if (val == CPUFREQ_PRECHANGE) {
1066 /* we should really shut the port down whilst the
1067 * frequency change is in progress. */
1069 } else if (val == CPUFREQ_POSTCHANGE) {
1070 struct ktermios *termios;
1071 struct tty_struct *tty;
1073 if (uport->state == NULL)
1076 tty = uport->state->port.tty;
1081 termios = &tty->termios;
1083 if (termios == NULL) {
1084 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1088 s3c24xx_serial_set_termios(uport, termios, NULL);
1095 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1097 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1099 return cpufreq_register_notifier(&port->freq_transition,
1100 CPUFREQ_TRANSITION_NOTIFIER);
1103 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1105 cpufreq_unregister_notifier(&port->freq_transition,
1106 CPUFREQ_TRANSITION_NOTIFIER);
1110 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1115 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1120 /* s3c24xx_serial_init_port
1122 * initialise a single serial port from the platform device given
1125 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1126 struct platform_device *platdev)
1128 struct uart_port *port = &ourport->port;
1129 struct s3c2410_uartcfg *cfg = ourport->cfg;
1130 struct resource *res;
1133 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1135 if (platdev == NULL)
1138 if (port->mapbase != 0)
1141 /* setup info for port */
1142 port->dev = &platdev->dev;
1144 /* Startup sequence is different for s3c64xx and higher SoC's */
1145 if (s3c24xx_serial_has_interrupt_mask(port))
1146 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1150 if (cfg->uart_flags & UPF_CONS_FLOW) {
1151 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1152 port->flags |= UPF_CONS_FLOW;
1155 /* sort our the physical and virtual addresses for each UART */
1157 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1159 dev_err(port->dev, "failed to find memory resource for uart\n");
1163 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1165 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1166 if (!port->membase) {
1167 dev_err(port->dev, "failed to remap controller address\n");
1171 port->mapbase = res->start;
1172 ret = platform_get_irq(platdev, 0);
1177 ourport->rx_irq = ret;
1178 ourport->tx_irq = ret + 1;
1181 ret = platform_get_irq(platdev, 1);
1183 ourport->tx_irq = ret;
1185 ourport->clk = clk_get(&platdev->dev, "uart");
1186 if (IS_ERR(ourport->clk)) {
1187 pr_err("%s: Controller clock not found\n",
1188 dev_name(&platdev->dev));
1189 return PTR_ERR(ourport->clk);
1192 ret = clk_prepare_enable(ourport->clk);
1194 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1195 clk_put(ourport->clk);
1199 /* Keep all interrupts masked and cleared */
1200 if (s3c24xx_serial_has_interrupt_mask(port)) {
1201 wr_regl(port, S3C64XX_UINTM, 0xf);
1202 wr_regl(port, S3C64XX_UINTP, 0xf);
1203 wr_regl(port, S3C64XX_UINTSP, 0xf);
1206 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1207 port->mapbase, port->membase, port->irq,
1208 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1210 /* reset the fifos (and setup the uart) */
1211 s3c24xx_serial_resetport(port, cfg);
1212 clk_disable_unprepare(ourport->clk);
1216 #ifdef CONFIG_SAMSUNG_CLOCK
1217 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1218 struct device_attribute *attr,
1221 struct uart_port *port = s3c24xx_dev_to_port(dev);
1222 struct s3c24xx_uart_port *ourport = to_ourport(port);
1224 if (IS_ERR(ourport->baudclk))
1227 return snprintf(buf, PAGE_SIZE, "* %s\n",
1228 ourport->baudclk->name ?: "(null)");
1231 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1234 /* Device driver serial port probe */
1236 static const struct of_device_id s3c24xx_uart_dt_match[];
1237 static int probe_index;
1239 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1240 struct platform_device *pdev)
1243 if (pdev->dev.of_node) {
1244 const struct of_device_id *match;
1245 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1246 return (struct s3c24xx_serial_drv_data *)match->data;
1249 return (struct s3c24xx_serial_drv_data *)
1250 platform_get_device_id(pdev)->driver_data;
1253 static int s3c24xx_serial_probe(struct platform_device *pdev)
1255 struct s3c24xx_uart_port *ourport;
1258 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1260 ourport = &s3c24xx_serial_ports[probe_index];
1262 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1263 if (!ourport->drv_data) {
1264 dev_err(&pdev->dev, "could not find driver data\n");
1268 ourport->baudclk = ERR_PTR(-EINVAL);
1269 ourport->info = ourport->drv_data->info;
1270 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1271 dev_get_platdata(&pdev->dev) :
1272 ourport->drv_data->def_cfg;
1274 ourport->port.fifosize = (ourport->info->fifosize) ?
1275 ourport->info->fifosize :
1276 ourport->drv_data->fifosize[probe_index];
1280 dbg("%s: initialising port %p...\n", __func__, ourport);
1282 ret = s3c24xx_serial_init_port(ourport, pdev);
1286 dbg("%s: adding port\n", __func__);
1287 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1288 platform_set_drvdata(pdev, &ourport->port);
1290 #ifdef CONFIG_SAMSUNG_CLOCK
1291 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1293 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1296 ret = s3c24xx_serial_cpufreq_register(ourport);
1298 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1306 static int s3c24xx_serial_remove(struct platform_device *dev)
1308 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1311 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1312 #ifdef CONFIG_SAMSUNG_CLOCK
1313 device_remove_file(&dev->dev, &dev_attr_clock_source);
1315 uart_remove_one_port(&s3c24xx_uart_drv, port);
1321 /* UART power management code */
1322 #ifdef CONFIG_PM_SLEEP
1323 static int s3c24xx_serial_suspend(struct device *dev)
1325 struct uart_port *port = s3c24xx_dev_to_port(dev);
1328 uart_suspend_port(&s3c24xx_uart_drv, port);
1333 static int s3c24xx_serial_resume(struct device *dev)
1335 struct uart_port *port = s3c24xx_dev_to_port(dev);
1336 struct s3c24xx_uart_port *ourport = to_ourport(port);
1339 clk_prepare_enable(ourport->clk);
1340 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1341 clk_disable_unprepare(ourport->clk);
1343 uart_resume_port(&s3c24xx_uart_drv, port);
1349 static int s3c24xx_serial_resume_noirq(struct device *dev)
1351 struct uart_port *port = s3c24xx_dev_to_port(dev);
1354 /* restore IRQ mask */
1355 if (s3c24xx_serial_has_interrupt_mask(port)) {
1356 unsigned int uintm = 0xf;
1357 if (tx_enabled(port))
1358 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1359 if (rx_enabled(port))
1360 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1361 wr_regl(port, S3C64XX_UINTM, uintm);
1368 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1369 .suspend = s3c24xx_serial_suspend,
1370 .resume = s3c24xx_serial_resume,
1371 .resume_noirq = s3c24xx_serial_resume_noirq,
1373 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1375 #else /* !CONFIG_PM_SLEEP */
1377 #define SERIAL_SAMSUNG_PM_OPS NULL
1378 #endif /* CONFIG_PM_SLEEP */
1382 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1384 static struct uart_port *cons_uart;
1387 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1389 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1390 unsigned long ufstat, utrstat;
1392 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1393 /* fifo mode - check amount of data in fifo registers... */
1395 ufstat = rd_regl(port, S3C2410_UFSTAT);
1396 return (ufstat & info->tx_fifofull) ? 0 : 1;
1399 /* in non-fifo mode, we go and use the tx buffer empty */
1401 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1402 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1406 s3c24xx_port_configured(unsigned int ucon)
1408 /* consider the serial port configured if the tx/rx mode set */
1409 return (ucon & 0xf) != 0;
1412 #ifdef CONFIG_CONSOLE_POLL
1414 * Console polling routines for writing and reading from the uart while
1415 * in an interrupt or debug context.
1418 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1420 struct s3c24xx_uart_port *ourport = to_ourport(port);
1421 unsigned int ufstat;
1423 ufstat = rd_regl(port, S3C2410_UFSTAT);
1424 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1425 return NO_POLL_CHAR;
1427 return rd_regb(port, S3C2410_URXH);
1430 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1433 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1434 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1436 /* not possible to xmit on unconfigured port */
1437 if (!s3c24xx_port_configured(ucon))
1440 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1442 wr_regb(cons_uart, S3C2410_UTXH, c);
1445 #endif /* CONFIG_CONSOLE_POLL */
1448 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1450 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1451 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1453 /* not possible to xmit on unconfigured port */
1454 if (!s3c24xx_port_configured(ucon))
1457 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1459 wr_regb(cons_uart, S3C2410_UTXH, ch);
1463 s3c24xx_serial_console_write(struct console *co, const char *s,
1466 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1470 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1471 int *parity, int *bits)
1476 unsigned int ubrdiv;
1478 unsigned int clk_sel;
1479 char clk_name[MAX_CLK_NAME_LENGTH];
1481 ulcon = rd_regl(port, S3C2410_ULCON);
1482 ucon = rd_regl(port, S3C2410_UCON);
1483 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1485 dbg("s3c24xx_serial_get_options: port=%p\n"
1486 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1487 port, ulcon, ucon, ubrdiv);
1489 if (s3c24xx_port_configured(ucon)) {
1490 switch (ulcon & S3C2410_LCON_CSMASK) {
1491 case S3C2410_LCON_CS5:
1494 case S3C2410_LCON_CS6:
1497 case S3C2410_LCON_CS7:
1501 case S3C2410_LCON_CS8:
1506 switch (ulcon & S3C2410_LCON_PMASK) {
1507 case S3C2410_LCON_PEVEN:
1511 case S3C2410_LCON_PODD:
1515 case S3C2410_LCON_PNONE:
1520 /* now calculate the baud rate */
1522 clk_sel = s3c24xx_serial_getsource(port);
1523 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1525 clk = clk_get(port->dev, clk_name);
1527 rate = clk_get_rate(clk);
1531 *baud = rate / (16 * (ubrdiv + 1));
1532 dbg("calculated baud %d\n", *baud);
1538 s3c24xx_serial_console_setup(struct console *co, char *options)
1540 struct uart_port *port;
1546 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1547 co, co->index, options);
1549 /* is this a valid port */
1551 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1554 port = &s3c24xx_serial_ports[co->index].port;
1556 /* is the port configured? */
1558 if (port->mapbase == 0x0)
1563 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1566 * Check whether an invalid uart number has been specified, and
1567 * if so, search for the first available port that does have
1571 uart_parse_options(options, &baud, &parity, &bits, &flow);
1573 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1575 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1577 return uart_set_options(port, co, baud, parity, bits, flow);
1580 static struct console s3c24xx_serial_console = {
1581 .name = S3C24XX_SERIAL_NAME,
1582 .device = uart_console_device,
1583 .flags = CON_PRINTBUFFER,
1585 .write = s3c24xx_serial_console_write,
1586 .setup = s3c24xx_serial_console_setup,
1587 .data = &s3c24xx_uart_drv,
1589 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1591 #ifdef CONFIG_CPU_S3C2410
1592 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1593 .info = &(struct s3c24xx_uart_info) {
1594 .name = "Samsung S3C2410 UART",
1595 .type = PORT_S3C2410,
1597 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1598 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1599 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1600 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1601 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1602 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1603 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1605 .clksel_mask = S3C2410_UCON_CLKMASK,
1606 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1608 .def_cfg = &(struct s3c2410_uartcfg) {
1609 .ucon = S3C2410_UCON_DEFAULT,
1610 .ufcon = S3C2410_UFCON_DEFAULT,
1613 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1615 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1618 #ifdef CONFIG_CPU_S3C2412
1619 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1620 .info = &(struct s3c24xx_uart_info) {
1621 .name = "Samsung S3C2412 UART",
1622 .type = PORT_S3C2412,
1625 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1626 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1627 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1628 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1629 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1630 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1631 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1633 .clksel_mask = S3C2412_UCON_CLKMASK,
1634 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1636 .def_cfg = &(struct s3c2410_uartcfg) {
1637 .ucon = S3C2410_UCON_DEFAULT,
1638 .ufcon = S3C2410_UFCON_DEFAULT,
1641 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1643 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1646 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1647 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1648 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1649 .info = &(struct s3c24xx_uart_info) {
1650 .name = "Samsung S3C2440 UART",
1651 .type = PORT_S3C2440,
1654 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1655 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1656 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1657 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1658 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1659 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1660 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1662 .clksel_mask = S3C2412_UCON_CLKMASK,
1663 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1665 .def_cfg = &(struct s3c2410_uartcfg) {
1666 .ucon = S3C2410_UCON_DEFAULT,
1667 .ufcon = S3C2410_UFCON_DEFAULT,
1670 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1672 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1675 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1676 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1677 defined(CONFIG_CPU_S5PC100)
1678 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1679 .info = &(struct s3c24xx_uart_info) {
1680 .name = "Samsung S3C6400 UART",
1681 .type = PORT_S3C6400,
1684 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1685 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1686 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1687 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1688 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1689 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1690 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1692 .clksel_mask = S3C6400_UCON_CLKMASK,
1693 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1695 .def_cfg = &(struct s3c2410_uartcfg) {
1696 .ucon = S3C2410_UCON_DEFAULT,
1697 .ufcon = S3C2410_UFCON_DEFAULT,
1700 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1702 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1705 #ifdef CONFIG_CPU_S5PV210
1706 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1707 .info = &(struct s3c24xx_uart_info) {
1708 .name = "Samsung S5PV210 UART",
1709 .type = PORT_S3C6400,
1711 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1712 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1713 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1714 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1715 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1716 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1717 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1719 .clksel_mask = S5PV210_UCON_CLKMASK,
1720 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1722 .def_cfg = &(struct s3c2410_uartcfg) {
1723 .ucon = S5PV210_UCON_DEFAULT,
1724 .ufcon = S5PV210_UFCON_DEFAULT,
1726 .fifosize = { 256, 64, 16, 16 },
1728 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1730 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1733 #if defined(CONFIG_ARCH_EXYNOS)
1734 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1735 .info = &(struct s3c24xx_uart_info) {
1736 .name = "Samsung Exynos4 UART",
1737 .type = PORT_S3C6400,
1739 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1740 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1741 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1742 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1743 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1744 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1745 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1750 .def_cfg = &(struct s3c2410_uartcfg) {
1751 .ucon = S5PV210_UCON_DEFAULT,
1752 .ufcon = S5PV210_UFCON_DEFAULT,
1755 .fifosize = { 256, 64, 16, 16 },
1757 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1759 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1762 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1764 .name = "s3c2410-uart",
1765 .driver_data = S3C2410_SERIAL_DRV_DATA,
1767 .name = "s3c2412-uart",
1768 .driver_data = S3C2412_SERIAL_DRV_DATA,
1770 .name = "s3c2440-uart",
1771 .driver_data = S3C2440_SERIAL_DRV_DATA,
1773 .name = "s3c6400-uart",
1774 .driver_data = S3C6400_SERIAL_DRV_DATA,
1776 .name = "s5pv210-uart",
1777 .driver_data = S5PV210_SERIAL_DRV_DATA,
1779 .name = "exynos4210-uart",
1780 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1784 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1787 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1788 { .compatible = "samsung,s3c2410-uart",
1789 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1790 { .compatible = "samsung,s3c2412-uart",
1791 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1792 { .compatible = "samsung,s3c2440-uart",
1793 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1794 { .compatible = "samsung,s3c6400-uart",
1795 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1796 { .compatible = "samsung,s5pv210-uart",
1797 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1798 { .compatible = "samsung,exynos4210-uart",
1799 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1802 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1805 static struct platform_driver samsung_serial_driver = {
1806 .probe = s3c24xx_serial_probe,
1807 .remove = s3c24xx_serial_remove,
1808 .id_table = s3c24xx_serial_driver_ids,
1810 .name = "samsung-uart",
1811 .owner = THIS_MODULE,
1812 .pm = SERIAL_SAMSUNG_PM_OPS,
1813 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1817 /* module initialisation code */
1819 static int __init s3c24xx_serial_modinit(void)
1823 ret = uart_register_driver(&s3c24xx_uart_drv);
1825 pr_err("Failed to register Samsung UART driver\n");
1829 ret = platform_driver_register(&samsung_serial_driver);
1831 pr_err("Failed to register platform driver\n");
1832 uart_unregister_driver(&s3c24xx_uart_drv);
1838 static void __exit s3c24xx_serial_modexit(void)
1840 platform_driver_unregister(&samsung_serial_driver);
1841 uart_unregister_driver(&s3c24xx_uart_drv);
1844 module_init(s3c24xx_serial_modinit);
1845 module_exit(s3c24xx_serial_modexit);
1847 MODULE_ALIAS("platform:samsung-uart");
1848 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1849 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1850 MODULE_LICENSE("GPL v2");