2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
60 #include "serial_mctrl_gpio.h"
63 /* Offsets into the sci_port->irqs array */
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104 struct plat_sci_reg {
108 struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
113 struct uart_port port;
115 /* Platform configuration */
116 const struct sci_port_params *params;
117 struct plat_sci_port *cfg;
118 unsigned int overrun_reg;
119 unsigned int overrun_mask;
120 unsigned int error_mask;
121 unsigned int error_clear;
122 unsigned int sampling_rate_mask;
123 resource_size_t reg_size;
124 struct mctrl_gpios *gpios;
127 struct timer_list break_timer;
131 struct clk *clks[SCI_NUM_CLKS];
132 unsigned long clk_rates[SCI_NUM_CLKS];
134 int irqs[SCIx_NR_IRQS];
135 char *irqstr[SCIx_NR_IRQS];
137 struct dma_chan *chan_tx;
138 struct dma_chan *chan_rx;
140 #ifdef CONFIG_SERIAL_SH_SCI_DMA
141 dma_cookie_t cookie_tx;
142 dma_cookie_t cookie_rx[2];
143 dma_cookie_t active_rx;
144 dma_addr_t tx_dma_addr;
145 unsigned int tx_dma_len;
146 struct scatterlist sg_rx[2];
149 struct work_struct work_tx;
150 struct timer_list rx_timer;
151 unsigned int rx_timeout;
157 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
159 static struct sci_port sci_ports[SCI_NPORTS];
160 static struct uart_driver sci_uart_driver;
162 static inline struct sci_port *
163 to_sci_port(struct uart_port *uart)
165 return container_of(uart, struct sci_port, port);
168 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
170 * Common SCI definitions, dependent on the port's regshift
173 [SCIx_SCI_REGTYPE] = {
175 [SCSMR] = { 0x00, 8 },
176 [SCBRR] = { 0x01, 8 },
177 [SCSCR] = { 0x02, 8 },
178 [SCxTDR] = { 0x03, 8 },
179 [SCxSR] = { 0x04, 8 },
180 [SCxRDR] = { 0x05, 8 },
185 * Common definitions for legacy IrDA ports.
187 [SCIx_IRDA_REGTYPE] = {
189 [SCSMR] = { 0x00, 8 },
190 [SCBRR] = { 0x02, 8 },
191 [SCSCR] = { 0x04, 8 },
192 [SCxTDR] = { 0x06, 8 },
193 [SCxSR] = { 0x08, 16 },
194 [SCxRDR] = { 0x0a, 8 },
195 [SCFCR] = { 0x0c, 8 },
196 [SCFDR] = { 0x0e, 16 },
201 * Common SCIFA definitions.
203 [SCIx_SCIFA_REGTYPE] = {
205 [SCSMR] = { 0x00, 16 },
206 [SCBRR] = { 0x04, 8 },
207 [SCSCR] = { 0x08, 16 },
208 [SCxTDR] = { 0x20, 8 },
209 [SCxSR] = { 0x14, 16 },
210 [SCxRDR] = { 0x24, 8 },
211 [SCFCR] = { 0x18, 16 },
212 [SCFDR] = { 0x1c, 16 },
213 [SCPCR] = { 0x30, 16 },
214 [SCPDR] = { 0x34, 16 },
219 * Common SCIFB definitions.
221 [SCIx_SCIFB_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x40, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x60, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCTFDR] = { 0x38, 16 },
231 [SCRFDR] = { 0x3c, 16 },
232 [SCPCR] = { 0x30, 16 },
233 [SCPDR] = { 0x34, 16 },
238 * Common SH-2(A) SCIF definitions for ports with FIFO data
241 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x0c, 8 },
247 [SCxSR] = { 0x10, 16 },
248 [SCxRDR] = { 0x14, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCSPTR] = { 0x20, 16 },
252 [SCLSR] = { 0x24, 16 },
257 * Common SH-3 SCIF definitions.
259 [SCIx_SH3_SCIF_REGTYPE] = {
261 [SCSMR] = { 0x00, 8 },
262 [SCBRR] = { 0x02, 8 },
263 [SCSCR] = { 0x04, 8 },
264 [SCxTDR] = { 0x06, 8 },
265 [SCxSR] = { 0x08, 16 },
266 [SCxRDR] = { 0x0a, 8 },
267 [SCFCR] = { 0x0c, 8 },
268 [SCFDR] = { 0x0e, 16 },
273 * Common SH-4(A) SCIF(B) definitions.
275 [SCIx_SH4_SCIF_REGTYPE] = {
277 [SCSMR] = { 0x00, 16 },
278 [SCBRR] = { 0x04, 8 },
279 [SCSCR] = { 0x08, 16 },
280 [SCxTDR] = { 0x0c, 8 },
281 [SCxSR] = { 0x10, 16 },
282 [SCxRDR] = { 0x14, 8 },
283 [SCFCR] = { 0x18, 16 },
284 [SCFDR] = { 0x1c, 16 },
285 [SCSPTR] = { 0x20, 16 },
286 [SCLSR] = { 0x24, 16 },
291 * Common SCIF definitions for ports with a Baud Rate Generator for
292 * External Clock (BRG).
294 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
296 [SCSMR] = { 0x00, 16 },
297 [SCBRR] = { 0x04, 8 },
298 [SCSCR] = { 0x08, 16 },
299 [SCxTDR] = { 0x0c, 8 },
300 [SCxSR] = { 0x10, 16 },
301 [SCxRDR] = { 0x14, 8 },
302 [SCFCR] = { 0x18, 16 },
303 [SCFDR] = { 0x1c, 16 },
304 [SCSPTR] = { 0x20, 16 },
305 [SCLSR] = { 0x24, 16 },
306 [SCDL] = { 0x30, 16 },
307 [SCCKS] = { 0x34, 16 },
312 * Common HSCIF definitions.
314 [SCIx_HSCIF_REGTYPE] = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 [HSSRR] = { 0x40, 16 },
327 [SCDL] = { 0x30, 16 },
328 [SCCKS] = { 0x34, 16 },
333 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
336 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
338 [SCSMR] = { 0x00, 16 },
339 [SCBRR] = { 0x04, 8 },
340 [SCSCR] = { 0x08, 16 },
341 [SCxTDR] = { 0x0c, 8 },
342 [SCxSR] = { 0x10, 16 },
343 [SCxRDR] = { 0x14, 8 },
344 [SCFCR] = { 0x18, 16 },
345 [SCFDR] = { 0x1c, 16 },
346 [SCLSR] = { 0x24, 16 },
351 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
354 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
356 [SCSMR] = { 0x00, 16 },
357 [SCBRR] = { 0x04, 8 },
358 [SCSCR] = { 0x08, 16 },
359 [SCxTDR] = { 0x0c, 8 },
360 [SCxSR] = { 0x10, 16 },
361 [SCxRDR] = { 0x14, 8 },
362 [SCFCR] = { 0x18, 16 },
363 [SCFDR] = { 0x1c, 16 },
364 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
365 [SCRFDR] = { 0x20, 16 },
366 [SCSPTR] = { 0x24, 16 },
367 [SCLSR] = { 0x28, 16 },
372 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
375 [SCIx_SH7705_SCIF_REGTYPE] = {
377 [SCSMR] = { 0x00, 16 },
378 [SCBRR] = { 0x04, 8 },
379 [SCSCR] = { 0x08, 16 },
380 [SCxTDR] = { 0x20, 8 },
381 [SCxSR] = { 0x14, 16 },
382 [SCxRDR] = { 0x24, 8 },
383 [SCFCR] = { 0x18, 16 },
384 [SCFDR] = { 0x1c, 16 },
389 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
392 * The "offset" here is rather misleading, in that it refers to an enum
393 * value relative to the port mapping rather than the fixed offset
394 * itself, which needs to be manually retrieved from the platform's
395 * register map for the given port.
397 static unsigned int sci_serial_in(struct uart_port *p, int offset)
399 const struct plat_sci_reg *reg = sci_getreg(p, offset);
402 return ioread8(p->membase + (reg->offset << p->regshift));
403 else if (reg->size == 16)
404 return ioread16(p->membase + (reg->offset << p->regshift));
406 WARN(1, "Invalid register access\n");
411 static void sci_serial_out(struct uart_port *p, int offset, int value)
413 const struct plat_sci_reg *reg = sci_getreg(p, offset);
416 iowrite8(value, p->membase + (reg->offset << p->regshift));
417 else if (reg->size == 16)
418 iowrite16(value, p->membase + (reg->offset << p->regshift));
420 WARN(1, "Invalid register access\n");
423 static int sci_probe_regmap(struct plat_sci_port *cfg)
427 cfg->regtype = SCIx_SCI_REGTYPE;
430 cfg->regtype = SCIx_IRDA_REGTYPE;
433 cfg->regtype = SCIx_SCIFA_REGTYPE;
436 cfg->regtype = SCIx_SCIFB_REGTYPE;
440 * The SH-4 is a bit of a misnomer here, although that's
441 * where this particular port layout originated. This
442 * configuration (or some slight variation thereof)
443 * remains the dominant model for all SCIFs.
445 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
448 cfg->regtype = SCIx_HSCIF_REGTYPE;
451 pr_err("Can't probe register map for given port\n");
458 static void sci_port_enable(struct sci_port *sci_port)
462 if (!sci_port->port.dev)
465 pm_runtime_get_sync(sci_port->port.dev);
467 for (i = 0; i < SCI_NUM_CLKS; i++) {
468 clk_prepare_enable(sci_port->clks[i]);
469 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
471 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
474 static void sci_port_disable(struct sci_port *sci_port)
478 if (!sci_port->port.dev)
481 /* Cancel the break timer to ensure that the timer handler will not try
482 * to access the hardware with clocks and power disabled. Reset the
483 * break flag to make the break debouncing state machine ready for the
486 del_timer_sync(&sci_port->break_timer);
487 sci_port->break_flag = 0;
489 for (i = SCI_NUM_CLKS; i-- > 0; )
490 clk_disable_unprepare(sci_port->clks[i]);
492 pm_runtime_put_sync(sci_port->port.dev);
495 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
498 * Not all ports (such as SCIFA) will support REIE. Rather than
499 * special-casing the port type, we check the port initialization
500 * IRQ enable mask to see whether the IRQ is desired at all. If
501 * it's unset, it's logically inferred that there's no point in
504 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
507 static void sci_start_tx(struct uart_port *port)
509 struct sci_port *s = to_sci_port(port);
512 #ifdef CONFIG_SERIAL_SH_SCI_DMA
513 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
514 u16 new, scr = serial_port_in(port, SCSCR);
516 new = scr | SCSCR_TDRQE;
518 new = scr & ~SCSCR_TDRQE;
520 serial_port_out(port, SCSCR, new);
523 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
524 dma_submit_error(s->cookie_tx)) {
526 schedule_work(&s->work_tx);
530 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
531 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
532 ctrl = serial_port_in(port, SCSCR);
533 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
537 static void sci_stop_tx(struct uart_port *port)
541 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
542 ctrl = serial_port_in(port, SCSCR);
544 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
545 ctrl &= ~SCSCR_TDRQE;
549 serial_port_out(port, SCSCR, ctrl);
552 static void sci_start_rx(struct uart_port *port)
556 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
558 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
559 ctrl &= ~SCSCR_RDRQE;
561 serial_port_out(port, SCSCR, ctrl);
564 static void sci_stop_rx(struct uart_port *port)
568 ctrl = serial_port_in(port, SCSCR);
570 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
571 ctrl &= ~SCSCR_RDRQE;
573 ctrl &= ~port_rx_irq_mask(port);
575 serial_port_out(port, SCSCR, ctrl);
578 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
580 if (port->type == PORT_SCI) {
581 /* Just store the mask */
582 serial_port_out(port, SCxSR, mask);
583 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
584 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
585 /* Only clear the status bits we want to clear */
586 serial_port_out(port, SCxSR,
587 serial_port_in(port, SCxSR) & mask);
589 /* Store the mask, clear parity/framing errors */
590 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
594 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
595 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
597 #ifdef CONFIG_CONSOLE_POLL
598 static int sci_poll_get_char(struct uart_port *port)
600 unsigned short status;
604 status = serial_port_in(port, SCxSR);
605 if (status & SCxSR_ERRORS(port)) {
606 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
612 if (!(status & SCxSR_RDxF(port)))
615 c = serial_port_in(port, SCxRDR);
618 serial_port_in(port, SCxSR);
619 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
625 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
627 unsigned short status;
630 status = serial_port_in(port, SCxSR);
631 } while (!(status & SCxSR_TDxE(port)));
633 serial_port_out(port, SCxTDR, c);
634 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
636 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
637 CONFIG_SERIAL_SH_SCI_EARLYCON */
639 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
641 struct sci_port *s = to_sci_port(port);
644 * Use port-specific handler if provided.
646 if (s->cfg->ops && s->cfg->ops->init_pins) {
647 s->cfg->ops->init_pins(port, cflag);
651 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
652 u16 ctrl = serial_port_in(port, SCPCR);
654 /* Enable RXD and TXD pin functions */
655 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
656 if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
657 /* RTS# is output, driven 1 */
659 serial_port_out(port, SCPDR,
660 serial_port_in(port, SCPDR) | SCPDR_RTSD);
661 /* Enable CTS# pin function */
664 serial_port_out(port, SCPCR, ctrl);
665 } else if (sci_getreg(port, SCSPTR)->size) {
666 u16 status = serial_port_in(port, SCSPTR);
668 /* RTS# is output, driven 1 */
669 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
670 /* CTS# and SCK are inputs */
671 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
672 serial_port_out(port, SCSPTR, status);
676 static int sci_txfill(struct uart_port *port)
678 const struct plat_sci_reg *reg;
680 reg = sci_getreg(port, SCTFDR);
682 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
684 reg = sci_getreg(port, SCFDR);
686 return serial_port_in(port, SCFDR) >> 8;
688 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
691 static int sci_txroom(struct uart_port *port)
693 return port->fifosize - sci_txfill(port);
696 static int sci_rxfill(struct uart_port *port)
698 const struct plat_sci_reg *reg;
700 reg = sci_getreg(port, SCRFDR);
702 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
704 reg = sci_getreg(port, SCFDR);
706 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
708 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
712 * SCI helper for checking the state of the muxed port/RXD pins.
714 static inline int sci_rxd_in(struct uart_port *port)
716 struct sci_port *s = to_sci_port(port);
718 if (s->cfg->port_reg <= 0)
721 /* Cast for ARM damage */
722 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
725 /* ********************************************************************** *
726 * the interrupt related routines *
727 * ********************************************************************** */
729 static void sci_transmit_chars(struct uart_port *port)
731 struct circ_buf *xmit = &port->state->xmit;
732 unsigned int stopped = uart_tx_stopped(port);
733 unsigned short status;
737 status = serial_port_in(port, SCxSR);
738 if (!(status & SCxSR_TDxE(port))) {
739 ctrl = serial_port_in(port, SCSCR);
740 if (uart_circ_empty(xmit))
744 serial_port_out(port, SCSCR, ctrl);
748 count = sci_txroom(port);
756 } else if (!uart_circ_empty(xmit) && !stopped) {
757 c = xmit->buf[xmit->tail];
758 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
763 serial_port_out(port, SCxTDR, c);
766 } while (--count > 0);
768 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
770 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
771 uart_write_wakeup(port);
772 if (uart_circ_empty(xmit)) {
775 ctrl = serial_port_in(port, SCSCR);
777 if (port->type != PORT_SCI) {
778 serial_port_in(port, SCxSR); /* Dummy read */
779 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
783 serial_port_out(port, SCSCR, ctrl);
787 /* On SH3, SCIF may read end-of-break as a space->mark char */
788 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
790 static void sci_receive_chars(struct uart_port *port)
792 struct sci_port *sci_port = to_sci_port(port);
793 struct tty_port *tport = &port->state->port;
794 int i, count, copied = 0;
795 unsigned short status;
798 status = serial_port_in(port, SCxSR);
799 if (!(status & SCxSR_RDxF(port)))
803 /* Don't copy more bytes than there is room for in the buffer */
804 count = tty_buffer_request_room(tport, sci_rxfill(port));
806 /* If for any reason we can't copy more data, we're done! */
810 if (port->type == PORT_SCI) {
811 char c = serial_port_in(port, SCxRDR);
812 if (uart_handle_sysrq_char(port, c) ||
813 sci_port->break_flag)
816 tty_insert_flip_char(tport, c, TTY_NORMAL);
818 for (i = 0; i < count; i++) {
819 char c = serial_port_in(port, SCxRDR);
821 status = serial_port_in(port, SCxSR);
822 #if defined(CONFIG_CPU_SH3)
823 /* Skip "chars" during break */
824 if (sci_port->break_flag) {
826 (status & SCxSR_FER(port))) {
831 /* Nonzero => end-of-break */
832 dev_dbg(port->dev, "debounce<%02x>\n", c);
833 sci_port->break_flag = 0;
840 #endif /* CONFIG_CPU_SH3 */
841 if (uart_handle_sysrq_char(port, c)) {
846 /* Store data and status */
847 if (status & SCxSR_FER(port)) {
849 port->icount.frame++;
850 dev_notice(port->dev, "frame error\n");
851 } else if (status & SCxSR_PER(port)) {
853 port->icount.parity++;
854 dev_notice(port->dev, "parity error\n");
858 tty_insert_flip_char(tport, c, flag);
862 serial_port_in(port, SCxSR); /* dummy read */
863 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
866 port->icount.rx += count;
870 /* Tell the rest of the system the news. New characters! */
871 tty_flip_buffer_push(tport);
873 serial_port_in(port, SCxSR); /* dummy read */
874 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
878 #define SCI_BREAK_JIFFIES (HZ/20)
881 * The sci generates interrupts during the break,
882 * 1 per millisecond or so during the break period, for 9600 baud.
883 * So dont bother disabling interrupts.
884 * But dont want more than 1 break event.
885 * Use a kernel timer to periodically poll the rx line until
886 * the break is finished.
888 static inline void sci_schedule_break_timer(struct sci_port *port)
890 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
893 /* Ensure that two consecutive samples find the break over. */
894 static void sci_break_timer(unsigned long data)
896 struct sci_port *port = (struct sci_port *)data;
898 if (sci_rxd_in(&port->port) == 0) {
899 port->break_flag = 1;
900 sci_schedule_break_timer(port);
901 } else if (port->break_flag == 1) {
903 port->break_flag = 2;
904 sci_schedule_break_timer(port);
906 port->break_flag = 0;
909 static int sci_handle_errors(struct uart_port *port)
912 unsigned short status = serial_port_in(port, SCxSR);
913 struct tty_port *tport = &port->state->port;
914 struct sci_port *s = to_sci_port(port);
916 /* Handle overruns */
917 if (status & s->overrun_mask) {
918 port->icount.overrun++;
921 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
924 dev_notice(port->dev, "overrun error\n");
927 if (status & SCxSR_FER(port)) {
928 if (sci_rxd_in(port) == 0) {
929 /* Notify of BREAK */
930 struct sci_port *sci_port = to_sci_port(port);
932 if (!sci_port->break_flag) {
935 sci_port->break_flag = 1;
936 sci_schedule_break_timer(sci_port);
938 /* Do sysrq handling. */
939 if (uart_handle_break(port))
942 dev_dbg(port->dev, "BREAK detected\n");
944 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
950 port->icount.frame++;
952 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
955 dev_notice(port->dev, "frame error\n");
959 if (status & SCxSR_PER(port)) {
961 port->icount.parity++;
963 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
966 dev_notice(port->dev, "parity error\n");
970 tty_flip_buffer_push(tport);
975 static int sci_handle_fifo_overrun(struct uart_port *port)
977 struct tty_port *tport = &port->state->port;
978 struct sci_port *s = to_sci_port(port);
979 const struct plat_sci_reg *reg;
983 reg = sci_getreg(port, s->overrun_reg);
987 status = serial_port_in(port, s->overrun_reg);
988 if (status & s->overrun_mask) {
989 status &= ~s->overrun_mask;
990 serial_port_out(port, s->overrun_reg, status);
992 port->icount.overrun++;
994 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
995 tty_flip_buffer_push(tport);
997 dev_dbg(port->dev, "overrun error\n");
1004 static int sci_handle_breaks(struct uart_port *port)
1007 unsigned short status = serial_port_in(port, SCxSR);
1008 struct tty_port *tport = &port->state->port;
1009 struct sci_port *s = to_sci_port(port);
1011 if (uart_handle_break(port))
1014 if (!s->break_flag && status & SCxSR_BRK(port)) {
1015 #if defined(CONFIG_CPU_SH3)
1016 /* Debounce break */
1022 /* Notify of BREAK */
1023 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1026 dev_dbg(port->dev, "BREAK detected\n");
1030 tty_flip_buffer_push(tport);
1032 copied += sci_handle_fifo_overrun(port);
1037 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1038 static void sci_dma_tx_complete(void *arg)
1040 struct sci_port *s = arg;
1041 struct uart_port *port = &s->port;
1042 struct circ_buf *xmit = &port->state->xmit;
1043 unsigned long flags;
1045 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1047 spin_lock_irqsave(&port->lock, flags);
1049 xmit->tail += s->tx_dma_len;
1050 xmit->tail &= UART_XMIT_SIZE - 1;
1052 port->icount.tx += s->tx_dma_len;
1054 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1055 uart_write_wakeup(port);
1057 if (!uart_circ_empty(xmit)) {
1059 schedule_work(&s->work_tx);
1061 s->cookie_tx = -EINVAL;
1062 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1063 u16 ctrl = serial_port_in(port, SCSCR);
1064 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1068 spin_unlock_irqrestore(&port->lock, flags);
1071 /* Locking: called with port lock held */
1072 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1074 struct uart_port *port = &s->port;
1075 struct tty_port *tport = &port->state->port;
1078 copied = tty_insert_flip_string(tport, buf, count);
1080 port->icount.buf_overrun++;
1082 port->icount.rx += copied;
1087 static int sci_dma_rx_find_active(struct sci_port *s)
1091 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1092 if (s->active_rx == s->cookie_rx[i])
1098 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1100 struct dma_chan *chan = s->chan_rx;
1101 struct uart_port *port = &s->port;
1102 unsigned long flags;
1104 spin_lock_irqsave(&port->lock, flags);
1106 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1107 spin_unlock_irqrestore(&port->lock, flags);
1108 dmaengine_terminate_all(chan);
1109 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1110 sg_dma_address(&s->sg_rx[0]));
1111 dma_release_channel(chan);
1116 static void sci_dma_rx_complete(void *arg)
1118 struct sci_port *s = arg;
1119 struct dma_chan *chan = s->chan_rx;
1120 struct uart_port *port = &s->port;
1121 struct dma_async_tx_descriptor *desc;
1122 unsigned long flags;
1123 int active, count = 0;
1125 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1128 spin_lock_irqsave(&port->lock, flags);
1130 active = sci_dma_rx_find_active(s);
1132 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1134 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1137 tty_flip_buffer_push(&port->state->port);
1139 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1141 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1145 desc->callback = sci_dma_rx_complete;
1146 desc->callback_param = s;
1147 s->cookie_rx[active] = dmaengine_submit(desc);
1148 if (dma_submit_error(s->cookie_rx[active]))
1151 s->active_rx = s->cookie_rx[!active];
1153 dma_async_issue_pending(chan);
1155 spin_unlock_irqrestore(&port->lock, flags);
1156 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1157 __func__, s->cookie_rx[active], active, s->active_rx);
1161 spin_unlock_irqrestore(&port->lock, flags);
1162 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1163 sci_rx_dma_release(s, true);
1166 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1168 struct dma_chan *chan = s->chan_tx;
1169 struct uart_port *port = &s->port;
1170 unsigned long flags;
1172 spin_lock_irqsave(&port->lock, flags);
1174 s->cookie_tx = -EINVAL;
1175 spin_unlock_irqrestore(&port->lock, flags);
1176 dmaengine_terminate_all(chan);
1177 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1179 dma_release_channel(chan);
1184 static void sci_submit_rx(struct sci_port *s)
1186 struct dma_chan *chan = s->chan_rx;
1189 for (i = 0; i < 2; i++) {
1190 struct scatterlist *sg = &s->sg_rx[i];
1191 struct dma_async_tx_descriptor *desc;
1193 desc = dmaengine_prep_slave_sg(chan,
1194 sg, 1, DMA_DEV_TO_MEM,
1195 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1199 desc->callback = sci_dma_rx_complete;
1200 desc->callback_param = s;
1201 s->cookie_rx[i] = dmaengine_submit(desc);
1202 if (dma_submit_error(s->cookie_rx[i]))
1207 s->active_rx = s->cookie_rx[0];
1209 dma_async_issue_pending(chan);
1214 dmaengine_terminate_all(chan);
1215 for (i = 0; i < 2; i++)
1216 s->cookie_rx[i] = -EINVAL;
1217 s->active_rx = -EINVAL;
1218 sci_rx_dma_release(s, true);
1221 static void work_fn_tx(struct work_struct *work)
1223 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1224 struct dma_async_tx_descriptor *desc;
1225 struct dma_chan *chan = s->chan_tx;
1226 struct uart_port *port = &s->port;
1227 struct circ_buf *xmit = &port->state->xmit;
1232 * Port xmit buffer is already mapped, and it is one page... Just adjust
1233 * offsets and lengths. Since it is a circular buffer, we have to
1234 * transmit till the end, and then the rest. Take the port lock to get a
1235 * consistent xmit buffer state.
1237 spin_lock_irq(&port->lock);
1238 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1239 s->tx_dma_len = min_t(unsigned int,
1240 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1241 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1242 spin_unlock_irq(&port->lock);
1244 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1246 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1248 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1250 sci_tx_dma_release(s, true);
1254 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1257 spin_lock_irq(&port->lock);
1258 desc->callback = sci_dma_tx_complete;
1259 desc->callback_param = s;
1260 spin_unlock_irq(&port->lock);
1261 s->cookie_tx = dmaengine_submit(desc);
1262 if (dma_submit_error(s->cookie_tx)) {
1263 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1265 sci_tx_dma_release(s, true);
1269 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1270 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1272 dma_async_issue_pending(chan);
1275 static void rx_timer_fn(unsigned long arg)
1277 struct sci_port *s = (struct sci_port *)arg;
1278 struct dma_chan *chan = s->chan_rx;
1279 struct uart_port *port = &s->port;
1280 struct dma_tx_state state;
1281 enum dma_status status;
1282 unsigned long flags;
1287 dev_dbg(port->dev, "DMA Rx timed out\n");
1289 spin_lock_irqsave(&port->lock, flags);
1291 active = sci_dma_rx_find_active(s);
1293 spin_unlock_irqrestore(&port->lock, flags);
1297 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1298 if (status == DMA_COMPLETE) {
1299 spin_unlock_irqrestore(&port->lock, flags);
1300 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1301 s->active_rx, active);
1303 /* Let packet complete handler take care of the packet */
1307 dmaengine_pause(chan);
1310 * sometimes DMA transfer doesn't stop even if it is stopped and
1311 * data keeps on coming until transaction is complete so check
1312 * for DMA_COMPLETE again
1313 * Let packet complete handler take care of the packet
1315 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1316 if (status == DMA_COMPLETE) {
1317 spin_unlock_irqrestore(&port->lock, flags);
1318 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1322 /* Handle incomplete DMA receive */
1323 dmaengine_terminate_all(s->chan_rx);
1324 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1327 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1329 tty_flip_buffer_push(&port->state->port);
1332 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1335 /* Direct new serial port interrupts back to CPU */
1336 scr = serial_port_in(port, SCSCR);
1337 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1338 scr &= ~SCSCR_RDRQE;
1339 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1341 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1343 spin_unlock_irqrestore(&port->lock, flags);
1346 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1347 enum dma_transfer_direction dir,
1350 dma_cap_mask_t mask;
1351 struct dma_chan *chan;
1352 struct dma_slave_config cfg;
1356 dma_cap_set(DMA_SLAVE, mask);
1358 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1359 (void *)(unsigned long)id, port->dev,
1360 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1363 "dma_request_slave_channel_compat failed\n");
1367 memset(&cfg, 0, sizeof(cfg));
1368 cfg.direction = dir;
1369 if (dir == DMA_MEM_TO_DEV) {
1370 cfg.dst_addr = port->mapbase +
1371 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1372 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1374 cfg.src_addr = port->mapbase +
1375 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1376 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1379 ret = dmaengine_slave_config(chan, &cfg);
1381 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1382 dma_release_channel(chan);
1389 static void sci_request_dma(struct uart_port *port)
1391 struct sci_port *s = to_sci_port(port);
1392 struct dma_chan *chan;
1394 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1396 if (!port->dev->of_node &&
1397 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1400 s->cookie_tx = -EINVAL;
1401 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1402 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1405 /* UART circular tx buffer is an aligned page. */
1406 s->tx_dma_addr = dma_map_single(chan->device->dev,
1407 port->state->xmit.buf,
1410 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1411 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1412 dma_release_channel(chan);
1415 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1416 __func__, UART_XMIT_SIZE,
1417 port->state->xmit.buf, &s->tx_dma_addr);
1420 INIT_WORK(&s->work_tx, work_fn_tx);
1423 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1424 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1432 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1433 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1437 "Failed to allocate Rx dma buffer, using PIO\n");
1438 dma_release_channel(chan);
1443 for (i = 0; i < 2; i++) {
1444 struct scatterlist *sg = &s->sg_rx[i];
1446 sg_init_table(sg, 1);
1448 sg_dma_address(sg) = dma;
1449 sg_dma_len(sg) = s->buf_len_rx;
1451 buf += s->buf_len_rx;
1452 dma += s->buf_len_rx;
1455 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1457 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1462 static void sci_free_dma(struct uart_port *port)
1464 struct sci_port *s = to_sci_port(port);
1467 sci_tx_dma_release(s, false);
1469 sci_rx_dma_release(s, false);
1472 static inline void sci_request_dma(struct uart_port *port)
1476 static inline void sci_free_dma(struct uart_port *port)
1481 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1483 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1484 struct uart_port *port = ptr;
1485 struct sci_port *s = to_sci_port(port);
1488 u16 scr = serial_port_in(port, SCSCR);
1489 u16 ssr = serial_port_in(port, SCxSR);
1491 /* Disable future Rx interrupts */
1492 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1493 disable_irq_nosync(irq);
1499 serial_port_out(port, SCSCR, scr);
1500 /* Clear current interrupt */
1501 serial_port_out(port, SCxSR,
1502 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1503 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1504 jiffies, s->rx_timeout);
1505 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1511 /* I think sci_receive_chars has to be called irrespective
1512 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1515 sci_receive_chars(ptr);
1520 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1522 struct uart_port *port = ptr;
1523 unsigned long flags;
1525 spin_lock_irqsave(&port->lock, flags);
1526 sci_transmit_chars(port);
1527 spin_unlock_irqrestore(&port->lock, flags);
1532 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1534 struct uart_port *port = ptr;
1535 struct sci_port *s = to_sci_port(port);
1538 if (port->type == PORT_SCI) {
1539 if (sci_handle_errors(port)) {
1540 /* discard character in rx buffer */
1541 serial_port_in(port, SCxSR);
1542 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1545 sci_handle_fifo_overrun(port);
1547 sci_receive_chars(ptr);
1550 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1552 /* Kick the transmission */
1554 sci_tx_interrupt(irq, ptr);
1559 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1561 struct uart_port *port = ptr;
1564 sci_handle_breaks(port);
1565 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1570 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1572 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1573 struct uart_port *port = ptr;
1574 struct sci_port *s = to_sci_port(port);
1575 irqreturn_t ret = IRQ_NONE;
1577 ssr_status = serial_port_in(port, SCxSR);
1578 scr_status = serial_port_in(port, SCSCR);
1579 if (s->overrun_reg == SCxSR)
1580 orer_status = ssr_status;
1582 if (sci_getreg(port, s->overrun_reg)->size)
1583 orer_status = serial_port_in(port, s->overrun_reg);
1586 err_enabled = scr_status & port_rx_irq_mask(port);
1589 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1591 ret = sci_tx_interrupt(irq, ptr);
1594 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1597 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1598 (scr_status & SCSCR_RIE))
1599 ret = sci_rx_interrupt(irq, ptr);
1601 /* Error Interrupt */
1602 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1603 ret = sci_er_interrupt(irq, ptr);
1605 /* Break Interrupt */
1606 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1607 ret = sci_br_interrupt(irq, ptr);
1609 /* Overrun Interrupt */
1610 if (orer_status & s->overrun_mask) {
1611 sci_handle_fifo_overrun(port);
1618 static const struct sci_irq_desc {
1620 irq_handler_t handler;
1621 } sci_irq_desc[] = {
1623 * Split out handlers, the default case.
1627 .handler = sci_er_interrupt,
1632 .handler = sci_rx_interrupt,
1637 .handler = sci_tx_interrupt,
1642 .handler = sci_br_interrupt,
1646 * Special muxed handler.
1650 .handler = sci_mpxed_interrupt,
1654 static int sci_request_irq(struct sci_port *port)
1656 struct uart_port *up = &port->port;
1659 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1660 const struct sci_irq_desc *desc;
1663 if (SCIx_IRQ_IS_MUXED(port)) {
1667 irq = port->irqs[i];
1670 * Certain port types won't support all of the
1671 * available interrupt sources.
1673 if (unlikely(irq < 0))
1677 desc = sci_irq_desc + i;
1678 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1679 dev_name(up->dev), desc->desc);
1680 if (!port->irqstr[j]) {
1685 ret = request_irq(irq, desc->handler, up->irqflags,
1686 port->irqstr[j], port);
1687 if (unlikely(ret)) {
1688 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1697 free_irq(port->irqs[i], port);
1701 kfree(port->irqstr[j]);
1706 static void sci_free_irq(struct sci_port *port)
1711 * Intentionally in reverse order so we iterate over the muxed
1714 for (i = 0; i < SCIx_NR_IRQS; i++) {
1715 int irq = port->irqs[i];
1718 * Certain port types won't support all of the available
1719 * interrupt sources.
1721 if (unlikely(irq < 0))
1724 free_irq(port->irqs[i], port);
1725 kfree(port->irqstr[i]);
1727 if (SCIx_IRQ_IS_MUXED(port)) {
1728 /* If there's only one IRQ, we're done. */
1734 static unsigned int sci_tx_empty(struct uart_port *port)
1736 unsigned short status = serial_port_in(port, SCxSR);
1737 unsigned short in_tx_fifo = sci_txfill(port);
1739 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1742 static void sci_set_rts(struct uart_port *port, bool state)
1744 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1745 u16 data = serial_port_in(port, SCPDR);
1749 data &= ~SCPDR_RTSD;
1752 serial_port_out(port, SCPDR, data);
1754 /* RTS# is output */
1755 serial_port_out(port, SCPCR,
1756 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1757 } else if (sci_getreg(port, SCSPTR)->size) {
1758 u16 ctrl = serial_port_in(port, SCSPTR);
1762 ctrl &= ~SCSPTR_RTSDT;
1764 ctrl |= SCSPTR_RTSDT;
1765 serial_port_out(port, SCSPTR, ctrl);
1769 static bool sci_get_cts(struct uart_port *port)
1771 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1773 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1774 } else if (sci_getreg(port, SCSPTR)->size) {
1776 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1783 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1784 * CTS/RTS is supported in hardware by at least one port and controlled
1785 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1786 * handled via the ->init_pins() op, which is a bit of a one-way street,
1787 * lacking any ability to defer pin control -- this will later be
1788 * converted over to the GPIO framework).
1790 * Other modes (such as loopback) are supported generically on certain
1791 * port types, but not others. For these it's sufficient to test for the
1792 * existence of the support register and simply ignore the port type.
1794 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1796 struct sci_port *s = to_sci_port(port);
1798 if (mctrl & TIOCM_LOOP) {
1799 const struct plat_sci_reg *reg;
1802 * Standard loopback mode for SCFCR ports.
1804 reg = sci_getreg(port, SCFCR);
1806 serial_port_out(port, SCFCR,
1807 serial_port_in(port, SCFCR) |
1811 mctrl_gpio_set(s->gpios, mctrl);
1813 if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
1816 if (!(mctrl & TIOCM_RTS)) {
1817 /* Disable Auto RTS */
1818 serial_port_out(port, SCFCR,
1819 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1822 sci_set_rts(port, 0);
1823 } else if (s->autorts) {
1824 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1825 /* Enable RTS# pin function */
1826 serial_port_out(port, SCPCR,
1827 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1830 /* Enable Auto RTS */
1831 serial_port_out(port, SCFCR,
1832 serial_port_in(port, SCFCR) | SCFCR_MCE);
1835 sci_set_rts(port, 1);
1839 static unsigned int sci_get_mctrl(struct uart_port *port)
1841 struct sci_port *s = to_sci_port(port);
1842 struct mctrl_gpios *gpios = s->gpios;
1843 unsigned int mctrl = 0;
1845 mctrl_gpio_get(gpios, &mctrl);
1848 * CTS/RTS is handled in hardware when supported, while nothing
1852 if (sci_get_cts(port))
1854 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
1857 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1859 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1865 static void sci_enable_ms(struct uart_port *port)
1867 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1870 static void sci_break_ctl(struct uart_port *port, int break_state)
1872 unsigned short scscr, scsptr;
1874 /* check wheter the port has SCSPTR */
1875 if (!sci_getreg(port, SCSPTR)->size) {
1877 * Not supported by hardware. Most parts couple break and rx
1878 * interrupts together, with break detection always enabled.
1883 scsptr = serial_port_in(port, SCSPTR);
1884 scscr = serial_port_in(port, SCSCR);
1886 if (break_state == -1) {
1887 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1890 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1894 serial_port_out(port, SCSPTR, scsptr);
1895 serial_port_out(port, SCSCR, scscr);
1898 static int sci_startup(struct uart_port *port)
1900 struct sci_port *s = to_sci_port(port);
1903 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1905 ret = sci_request_irq(s);
1906 if (unlikely(ret < 0))
1909 sci_request_dma(port);
1914 static void sci_shutdown(struct uart_port *port)
1916 struct sci_port *s = to_sci_port(port);
1917 unsigned long flags;
1920 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1923 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1925 spin_lock_irqsave(&port->lock, flags);
1928 /* Stop RX and TX, disable related interrupts, keep clock source */
1929 scr = serial_port_in(port, SCSCR);
1930 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
1931 spin_unlock_irqrestore(&port->lock, flags);
1933 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1935 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1937 del_timer_sync(&s->rx_timer);
1945 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1948 unsigned long freq = s->clk_rates[SCI_SCK];
1949 int err, min_err = INT_MAX;
1952 if (s->port.type != PORT_HSCIF)
1955 for_each_sr(sr, s) {
1956 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1957 if (abs(err) >= abs(min_err))
1967 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1972 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1973 unsigned long freq, unsigned int *dlr,
1976 int err, min_err = INT_MAX;
1977 unsigned int sr, dl;
1979 if (s->port.type != PORT_HSCIF)
1982 for_each_sr(sr, s) {
1983 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1984 dl = clamp(dl, 1U, 65535U);
1986 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1987 if (abs(err) >= abs(min_err))
1998 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1999 min_err, *dlr, *srr + 1);
2003 /* calculate sample rate, BRR, and clock select */
2004 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2005 unsigned int *brr, unsigned int *srr,
2008 unsigned long freq = s->clk_rates[SCI_FCK];
2009 unsigned int sr, br, prediv, scrate, c;
2010 int err, min_err = INT_MAX;
2012 if (s->port.type != PORT_HSCIF)
2016 * Find the combination of sample rate and clock select with the
2017 * smallest deviation from the desired baud rate.
2018 * Prefer high sample rates to maximise the receive margin.
2020 * M: Receive margin (%)
2021 * N: Ratio of bit rate to clock (N = sampling rate)
2022 * D: Clock duty (D = 0 to 1.0)
2023 * L: Frame length (L = 9 to 12)
2024 * F: Absolute value of clock frequency deviation
2026 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2027 * (|D - 0.5| / N * (1 + F))|
2028 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2030 for_each_sr(sr, s) {
2031 for (c = 0; c <= 3; c++) {
2032 /* integerized formulas from HSCIF documentation */
2033 prediv = sr * (1 << (2 * c + 1));
2036 * We need to calculate:
2038 * br = freq / (prediv * bps) clamped to [1..256]
2039 * err = freq / (br * prediv) - bps
2041 * Watch out for overflow when calculating the desired
2042 * sampling clock rate!
2044 if (bps > UINT_MAX / prediv)
2047 scrate = prediv * bps;
2048 br = DIV_ROUND_CLOSEST(freq, scrate);
2049 br = clamp(br, 1U, 256U);
2051 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2052 if (abs(err) >= abs(min_err))
2066 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2067 min_err, *brr, *srr + 1, *cks);
2071 static void sci_reset(struct uart_port *port)
2073 const struct plat_sci_reg *reg;
2074 unsigned int status;
2077 status = serial_port_in(port, SCxSR);
2078 } while (!(status & SCxSR_TEND(port)));
2080 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2082 reg = sci_getreg(port, SCFCR);
2084 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2086 sci_clear_SCxSR(port,
2087 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2088 SCxSR_BREAK_CLEAR(port));
2089 if (sci_getreg(port, SCLSR)->size) {
2090 status = serial_port_in(port, SCLSR);
2091 status &= ~(SCLSR_TO | SCLSR_ORER);
2092 serial_port_out(port, SCLSR, status);
2096 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2097 struct ktermios *old)
2099 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2100 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2101 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2102 struct sci_port *s = to_sci_port(port);
2103 const struct plat_sci_reg *reg;
2104 int min_err = INT_MAX, err;
2105 unsigned long max_freq = 0;
2108 if ((termios->c_cflag & CSIZE) == CS7)
2109 smr_val |= SCSMR_CHR;
2110 if (termios->c_cflag & PARENB)
2111 smr_val |= SCSMR_PE;
2112 if (termios->c_cflag & PARODD)
2113 smr_val |= SCSMR_PE | SCSMR_ODD;
2114 if (termios->c_cflag & CSTOPB)
2115 smr_val |= SCSMR_STOP;
2118 * earlyprintk comes here early on with port->uartclk set to zero.
2119 * the clock framework is not up and running at this point so here
2120 * we assume that 115200 is the maximum baud rate. please note that
2121 * the baud rate is not programmed during earlyprintk - it is assumed
2122 * that the previous boot loader has enabled required clocks and
2123 * setup the baud rate generator hardware for us already.
2125 if (!port->uartclk) {
2126 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2130 for (i = 0; i < SCI_NUM_CLKS; i++)
2131 max_freq = max(max_freq, s->clk_rates[i]);
2133 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2138 * There can be multiple sources for the sampling clock. Find the one
2139 * that gives us the smallest deviation from the desired baud rate.
2142 /* Optional Undivided External Clock */
2143 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2144 port->type != PORT_SCIFB) {
2145 err = sci_sck_calc(s, baud, &srr1);
2146 if (abs(err) < abs(min_err)) {
2148 scr_val = SCSCR_CKE1;
2157 /* Optional BRG Frequency Divided External Clock */
2158 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2159 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2161 if (abs(err) < abs(min_err)) {
2162 best_clk = SCI_SCIF_CLK;
2163 scr_val = SCSCR_CKE1;
2173 /* Optional BRG Frequency Divided Internal Clock */
2174 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2175 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2177 if (abs(err) < abs(min_err)) {
2178 best_clk = SCI_BRG_INT;
2179 scr_val = SCSCR_CKE1;
2189 /* Divided Functional Clock using standard Bit Rate Register */
2190 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2191 if (abs(err) < abs(min_err)) {
2202 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2203 s->clks[best_clk], baud, min_err);
2208 * Program the optional External Baud Rate Generator (BRG) first.
2209 * It controls the mux to select (H)SCK or frequency divided clock.
2211 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2212 serial_port_out(port, SCDL, dl);
2213 serial_port_out(port, SCCKS, sccks);
2218 uart_update_timeout(port, termios->c_cflag, baud);
2220 if (best_clk >= 0) {
2221 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2223 case 5: smr_val |= SCSMR_SRC_5; break;
2224 case 7: smr_val |= SCSMR_SRC_7; break;
2225 case 11: smr_val |= SCSMR_SRC_11; break;
2226 case 13: smr_val |= SCSMR_SRC_13; break;
2227 case 16: smr_val |= SCSMR_SRC_16; break;
2228 case 17: smr_val |= SCSMR_SRC_17; break;
2229 case 19: smr_val |= SCSMR_SRC_19; break;
2230 case 27: smr_val |= SCSMR_SRC_27; break;
2234 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2235 scr_val, smr_val, brr, sccks, dl, srr);
2236 serial_port_out(port, SCSCR, scr_val);
2237 serial_port_out(port, SCSMR, smr_val);
2238 serial_port_out(port, SCBRR, brr);
2239 if (sci_getreg(port, HSSRR)->size)
2240 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2242 /* Wait one bit interval */
2243 udelay((1000000 + (baud - 1)) / baud);
2245 /* Don't touch the bit rate configuration */
2246 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2247 smr_val |= serial_port_in(port, SCSMR) &
2248 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2249 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2250 serial_port_out(port, SCSCR, scr_val);
2251 serial_port_out(port, SCSMR, smr_val);
2254 sci_init_pins(port, termios->c_cflag);
2256 port->status &= ~UPSTAT_AUTOCTS;
2258 reg = sci_getreg(port, SCFCR);
2260 unsigned short ctrl = serial_port_in(port, SCFCR);
2262 if ((port->flags & UPF_HARD_FLOW) &&
2263 (termios->c_cflag & CRTSCTS)) {
2264 /* There is no CTS interrupt to restart the hardware */
2265 port->status |= UPSTAT_AUTOCTS;
2266 /* MCE is enabled when RTS is raised */
2271 * As we've done a sci_reset() above, ensure we don't
2272 * interfere with the FIFOs while toggling MCE. As the
2273 * reset values could still be set, simply mask them out.
2275 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2277 serial_port_out(port, SCFCR, ctrl);
2280 scr_val |= SCSCR_RE | SCSCR_TE |
2281 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2282 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2283 serial_port_out(port, SCSCR, scr_val);
2284 if ((srr + 1 == 5) &&
2285 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2287 * In asynchronous mode, when the sampling rate is 1/5, first
2288 * received data may become invalid on some SCIFA and SCIFB.
2289 * To avoid this problem wait more than 1 serial data time (1
2290 * bit time x serial data number) after setting SCSCR.RE = 1.
2292 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2295 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2297 * Calculate delay for 2 DMA buffers (4 FIFO).
2298 * See serial_core.c::uart_update_timeout().
2299 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2300 * function calculates 1 jiffie for the data plus 5 jiffies for the
2301 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2302 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2303 * value obtained by this formula is too small. Therefore, if the value
2304 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2309 /* byte size and parity */
2310 switch (termios->c_cflag & CSIZE) {
2325 if (termios->c_cflag & CSTOPB)
2327 if (termios->c_cflag & PARENB)
2329 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2331 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2332 s->rx_timeout * 1000 / HZ, port->timeout);
2333 if (s->rx_timeout < msecs_to_jiffies(20))
2334 s->rx_timeout = msecs_to_jiffies(20);
2338 if ((termios->c_cflag & CREAD) != 0)
2341 sci_port_disable(s);
2343 if (UART_ENABLE_MS(port, termios->c_cflag))
2344 sci_enable_ms(port);
2347 static void sci_pm(struct uart_port *port, unsigned int state,
2348 unsigned int oldstate)
2350 struct sci_port *sci_port = to_sci_port(port);
2353 case UART_PM_STATE_OFF:
2354 sci_port_disable(sci_port);
2357 sci_port_enable(sci_port);
2362 static const char *sci_type(struct uart_port *port)
2364 switch (port->type) {
2382 static int sci_remap_port(struct uart_port *port)
2384 struct sci_port *sport = to_sci_port(port);
2387 * Nothing to do if there's already an established membase.
2392 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2393 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2394 if (unlikely(!port->membase)) {
2395 dev_err(port->dev, "can't remap port#%d\n", port->line);
2400 * For the simple (and majority of) cases where we don't
2401 * need to do any remapping, just cast the cookie
2404 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2410 static void sci_release_port(struct uart_port *port)
2412 struct sci_port *sport = to_sci_port(port);
2414 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2415 iounmap(port->membase);
2416 port->membase = NULL;
2419 release_mem_region(port->mapbase, sport->reg_size);
2422 static int sci_request_port(struct uart_port *port)
2424 struct resource *res;
2425 struct sci_port *sport = to_sci_port(port);
2428 res = request_mem_region(port->mapbase, sport->reg_size,
2429 dev_name(port->dev));
2430 if (unlikely(res == NULL)) {
2431 dev_err(port->dev, "request_mem_region failed.");
2435 ret = sci_remap_port(port);
2436 if (unlikely(ret != 0)) {
2437 release_resource(res);
2444 static void sci_config_port(struct uart_port *port, int flags)
2446 if (flags & UART_CONFIG_TYPE) {
2447 struct sci_port *sport = to_sci_port(port);
2449 port->type = sport->cfg->type;
2450 sci_request_port(port);
2454 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2456 if (ser->baud_base < 2400)
2457 /* No paper tape reader for Mitch.. */
2463 static const struct uart_ops sci_uart_ops = {
2464 .tx_empty = sci_tx_empty,
2465 .set_mctrl = sci_set_mctrl,
2466 .get_mctrl = sci_get_mctrl,
2467 .start_tx = sci_start_tx,
2468 .stop_tx = sci_stop_tx,
2469 .stop_rx = sci_stop_rx,
2470 .enable_ms = sci_enable_ms,
2471 .break_ctl = sci_break_ctl,
2472 .startup = sci_startup,
2473 .shutdown = sci_shutdown,
2474 .set_termios = sci_set_termios,
2477 .release_port = sci_release_port,
2478 .request_port = sci_request_port,
2479 .config_port = sci_config_port,
2480 .verify_port = sci_verify_port,
2481 #ifdef CONFIG_CONSOLE_POLL
2482 .poll_get_char = sci_poll_get_char,
2483 .poll_put_char = sci_poll_put_char,
2487 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2489 const char *clk_names[] = {
2492 [SCI_BRG_INT] = "brg_int",
2493 [SCI_SCIF_CLK] = "scif_clk",
2498 if (sci_port->cfg->type == PORT_HSCIF)
2499 clk_names[SCI_SCK] = "hsck";
2501 for (i = 0; i < SCI_NUM_CLKS; i++) {
2502 clk = devm_clk_get(dev, clk_names[i]);
2503 if (PTR_ERR(clk) == -EPROBE_DEFER)
2504 return -EPROBE_DEFER;
2506 if (IS_ERR(clk) && i == SCI_FCK) {
2508 * "fck" used to be called "sci_ick", and we need to
2509 * maintain DT backward compatibility.
2511 clk = devm_clk_get(dev, "sci_ick");
2512 if (PTR_ERR(clk) == -EPROBE_DEFER)
2513 return -EPROBE_DEFER;
2519 * Not all SH platforms declare a clock lookup entry
2520 * for SCI devices, in which case we need to get the
2521 * global "peripheral_clk" clock.
2523 clk = devm_clk_get(dev, "peripheral_clk");
2527 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2529 return PTR_ERR(clk);
2534 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2537 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2539 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2544 static int sci_init_single(struct platform_device *dev,
2545 struct sci_port *sci_port, unsigned int index,
2546 struct plat_sci_port *p, bool early)
2548 struct uart_port *port = &sci_port->port;
2549 const struct resource *res;
2555 port->ops = &sci_uart_ops;
2556 port->iotype = UPIO_MEM;
2559 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2563 port->mapbase = res->start;
2564 sci_port->reg_size = resource_size(res);
2566 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2567 sci_port->irqs[i] = platform_get_irq(dev, i);
2569 /* The SCI generates several interrupts. They can be muxed together or
2570 * connected to different interrupt lines. In the muxed case only one
2571 * interrupt resource is specified. In the non-muxed case three or four
2572 * interrupt resources are specified, as the BRI interrupt is optional.
2574 if (sci_port->irqs[0] < 0)
2577 if (sci_port->irqs[1] < 0) {
2578 sci_port->irqs[1] = sci_port->irqs[0];
2579 sci_port->irqs[2] = sci_port->irqs[0];
2580 sci_port->irqs[3] = sci_port->irqs[0];
2583 if (p->regtype == SCIx_PROBE_REGTYPE) {
2584 ret = sci_probe_regmap(p);
2589 sci_port->params = &sci_port_params[p->regtype];
2593 port->fifosize = 256;
2594 sci_port->overrun_reg = SCxSR;
2595 sci_port->overrun_mask = SCIFA_ORER;
2596 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2599 port->fifosize = 128;
2600 sci_port->overrun_reg = SCLSR;
2601 sci_port->overrun_mask = SCLSR_ORER;
2602 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2605 port->fifosize = 64;
2606 sci_port->overrun_reg = SCxSR;
2607 sci_port->overrun_mask = SCIFA_ORER;
2608 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2611 port->fifosize = 16;
2612 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2613 sci_port->overrun_reg = SCxSR;
2614 sci_port->overrun_mask = SCIFA_ORER;
2615 sci_port->sampling_rate_mask = SCI_SR(16);
2617 sci_port->overrun_reg = SCLSR;
2618 sci_port->overrun_mask = SCLSR_ORER;
2619 sci_port->sampling_rate_mask = SCI_SR(32);
2624 sci_port->overrun_reg = SCxSR;
2625 sci_port->overrun_mask = SCI_ORER;
2626 sci_port->sampling_rate_mask = SCI_SR(32);
2630 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2631 * match the SoC datasheet, this should be investigated. Let platform
2632 * data override the sampling rate for now.
2634 if (p->sampling_rate)
2635 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2638 ret = sci_init_clocks(sci_port, &dev->dev);
2642 port->dev = &dev->dev;
2644 pm_runtime_enable(&dev->dev);
2647 sci_port->break_timer.data = (unsigned long)sci_port;
2648 sci_port->break_timer.function = sci_break_timer;
2649 init_timer(&sci_port->break_timer);
2652 * Establish some sensible defaults for the error detection.
2654 if (p->type == PORT_SCI) {
2655 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2656 sci_port->error_clear = SCI_ERROR_CLEAR;
2658 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2659 sci_port->error_clear = SCIF_ERROR_CLEAR;
2663 * Make the error mask inclusive of overrun detection, if
2666 if (sci_port->overrun_reg == SCxSR) {
2667 sci_port->error_mask |= sci_port->overrun_mask;
2668 sci_port->error_clear &= ~sci_port->overrun_mask;
2671 port->type = p->type;
2672 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2673 port->regshift = p->regshift;
2676 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2677 * for the multi-IRQ ports, which is where we are primarily
2678 * concerned with the shutdown path synchronization.
2680 * For the muxed case there's nothing more to do.
2682 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2685 port->serial_in = sci_serial_in;
2686 port->serial_out = sci_serial_out;
2688 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2689 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2690 p->dma_slave_tx, p->dma_slave_rx);
2695 static void sci_cleanup_single(struct sci_port *port)
2697 pm_runtime_disable(port->port.dev);
2700 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2701 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2702 static void serial_console_putchar(struct uart_port *port, int ch)
2704 sci_poll_put_char(port, ch);
2708 * Print a string to the serial port trying not to disturb
2709 * any possible real use of the port...
2711 static void serial_console_write(struct console *co, const char *s,
2714 struct sci_port *sci_port = &sci_ports[co->index];
2715 struct uart_port *port = &sci_port->port;
2716 unsigned short bits, ctrl, ctrl_temp;
2717 unsigned long flags;
2720 local_irq_save(flags);
2721 #if defined(SUPPORT_SYSRQ)
2726 if (oops_in_progress)
2727 locked = spin_trylock(&port->lock);
2729 spin_lock(&port->lock);
2731 /* first save SCSCR then disable interrupts, keep clock source */
2732 ctrl = serial_port_in(port, SCSCR);
2733 ctrl_temp = SCSCR_RE | SCSCR_TE |
2734 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2735 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2736 serial_port_out(port, SCSCR, ctrl_temp);
2738 uart_console_write(port, s, count, serial_console_putchar);
2740 /* wait until fifo is empty and last bit has been transmitted */
2741 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2742 while ((serial_port_in(port, SCxSR) & bits) != bits)
2745 /* restore the SCSCR */
2746 serial_port_out(port, SCSCR, ctrl);
2749 spin_unlock(&port->lock);
2750 local_irq_restore(flags);
2753 static int serial_console_setup(struct console *co, char *options)
2755 struct sci_port *sci_port;
2756 struct uart_port *port;
2764 * Refuse to handle any bogus ports.
2766 if (co->index < 0 || co->index >= SCI_NPORTS)
2769 sci_port = &sci_ports[co->index];
2770 port = &sci_port->port;
2773 * Refuse to handle uninitialized ports.
2778 ret = sci_remap_port(port);
2779 if (unlikely(ret != 0))
2783 uart_parse_options(options, &baud, &parity, &bits, &flow);
2785 return uart_set_options(port, co, baud, parity, bits, flow);
2788 static struct console serial_console = {
2790 .device = uart_console_device,
2791 .write = serial_console_write,
2792 .setup = serial_console_setup,
2793 .flags = CON_PRINTBUFFER,
2795 .data = &sci_uart_driver,
2798 static struct console early_serial_console = {
2799 .name = "early_ttySC",
2800 .write = serial_console_write,
2801 .flags = CON_PRINTBUFFER,
2805 static char early_serial_buf[32];
2807 static int sci_probe_earlyprintk(struct platform_device *pdev)
2809 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2811 if (early_serial_console.data)
2814 early_serial_console.index = pdev->id;
2816 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2818 serial_console_setup(&early_serial_console, early_serial_buf);
2820 if (!strstr(early_serial_buf, "keep"))
2821 early_serial_console.flags |= CON_BOOT;
2823 register_console(&early_serial_console);
2827 #define SCI_CONSOLE (&serial_console)
2830 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2835 #define SCI_CONSOLE NULL
2837 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2839 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2841 static struct uart_driver sci_uart_driver = {
2842 .owner = THIS_MODULE,
2843 .driver_name = "sci",
2844 .dev_name = "ttySC",
2846 .minor = SCI_MINOR_START,
2848 .cons = SCI_CONSOLE,
2851 static int sci_remove(struct platform_device *dev)
2853 struct sci_port *port = platform_get_drvdata(dev);
2855 uart_remove_one_port(&sci_uart_driver, &port->port);
2857 sci_cleanup_single(port);
2863 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2864 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2865 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2867 static const struct of_device_id of_sci_match[] = {
2868 /* SoC-specific types */
2870 .compatible = "renesas,scif-r7s72100",
2871 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2873 /* Family-specific types */
2875 .compatible = "renesas,rcar-gen1-scif",
2876 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2878 .compatible = "renesas,rcar-gen2-scif",
2879 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2881 .compatible = "renesas,rcar-gen3-scif",
2882 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2886 .compatible = "renesas,scif",
2887 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2889 .compatible = "renesas,scifa",
2890 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2892 .compatible = "renesas,scifb",
2893 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2895 .compatible = "renesas,hscif",
2896 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2898 .compatible = "renesas,sci",
2899 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2904 MODULE_DEVICE_TABLE(of, of_sci_match);
2906 static struct plat_sci_port *
2907 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2909 struct device_node *np = pdev->dev.of_node;
2910 const struct of_device_id *match;
2911 struct plat_sci_port *p;
2914 if (!IS_ENABLED(CONFIG_OF) || !np)
2917 match = of_match_node(of_sci_match, np);
2921 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2925 /* Get the line number from the aliases node. */
2926 id = of_alias_get_id(np, "serial");
2928 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2934 p->type = SCI_OF_TYPE(match->data);
2935 p->regtype = SCI_OF_REGTYPE(match->data);
2937 if (of_find_property(np, "uart-has-rtscts", NULL))
2938 p->capabilities |= SCIx_HAVE_RTSCTS;
2943 static int sci_probe_single(struct platform_device *dev,
2945 struct plat_sci_port *p,
2946 struct sci_port *sciport)
2951 if (unlikely(index >= SCI_NPORTS)) {
2952 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2953 index+1, SCI_NPORTS);
2954 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2958 ret = sci_init_single(dev, sciport, index, p, false);
2962 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
2963 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
2964 return PTR_ERR(sciport->gpios);
2966 if (p->capabilities & SCIx_HAVE_RTSCTS) {
2967 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2969 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2971 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
2974 sciport->port.flags |= UPF_HARD_FLOW;
2977 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2979 sci_cleanup_single(sciport);
2986 static int sci_probe(struct platform_device *dev)
2988 struct plat_sci_port *p;
2989 struct sci_port *sp;
2990 unsigned int dev_id;
2994 * If we've come here via earlyprintk initialization, head off to
2995 * the special early probe. We don't have sufficient device state
2996 * to make it beyond this yet.
2998 if (is_early_platform_device(dev))
2999 return sci_probe_earlyprintk(dev);
3001 if (dev->dev.of_node) {
3002 p = sci_parse_dt(dev, &dev_id);
3006 p = dev->dev.platform_data;
3008 dev_err(&dev->dev, "no platform data supplied\n");
3015 sp = &sci_ports[dev_id];
3016 platform_set_drvdata(dev, sp);
3018 ret = sci_probe_single(dev, dev_id, p, sp);
3022 #ifdef CONFIG_SH_STANDARD_BIOS
3023 sh_bios_gdb_detach();
3029 static __maybe_unused int sci_suspend(struct device *dev)
3031 struct sci_port *sport = dev_get_drvdata(dev);
3034 uart_suspend_port(&sci_uart_driver, &sport->port);
3039 static __maybe_unused int sci_resume(struct device *dev)
3041 struct sci_port *sport = dev_get_drvdata(dev);
3044 uart_resume_port(&sci_uart_driver, &sport->port);
3049 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3051 static struct platform_driver sci_driver = {
3053 .remove = sci_remove,
3056 .pm = &sci_dev_pm_ops,
3057 .of_match_table = of_match_ptr(of_sci_match),
3061 static int __init sci_init(void)
3065 pr_info("%s\n", banner);
3067 ret = uart_register_driver(&sci_uart_driver);
3068 if (likely(ret == 0)) {
3069 ret = platform_driver_register(&sci_driver);
3071 uart_unregister_driver(&sci_uart_driver);
3077 static void __exit sci_exit(void)
3079 platform_driver_unregister(&sci_driver);
3080 uart_unregister_driver(&sci_uart_driver);
3083 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3084 early_platform_init_buffer("earlyprintk", &sci_driver,
3085 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3087 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3088 static struct __init plat_sci_port port_cfg;
3090 static int __init early_console_setup(struct earlycon_device *device,
3093 if (!device->port.membase)
3096 device->port.serial_in = sci_serial_in;
3097 device->port.serial_out = sci_serial_out;
3098 device->port.type = type;
3099 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3100 sci_ports[0].cfg = &port_cfg;
3101 sci_ports[0].cfg->type = type;
3102 sci_probe_regmap(sci_ports[0].cfg);
3103 sci_ports[0].params = &sci_port_params[sci_ports[0].cfg->regtype];
3104 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3105 sci_serial_out(&sci_ports[0].port, SCSCR,
3106 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3108 device->con->write = serial_console_write;
3111 static int __init sci_early_console_setup(struct earlycon_device *device,
3114 return early_console_setup(device, PORT_SCI);
3116 static int __init scif_early_console_setup(struct earlycon_device *device,
3119 return early_console_setup(device, PORT_SCIF);
3121 static int __init scifa_early_console_setup(struct earlycon_device *device,
3124 return early_console_setup(device, PORT_SCIFA);
3126 static int __init scifb_early_console_setup(struct earlycon_device *device,
3129 return early_console_setup(device, PORT_SCIFB);
3131 static int __init hscif_early_console_setup(struct earlycon_device *device,
3134 return early_console_setup(device, PORT_HSCIF);
3137 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3138 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3139 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3140 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3141 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3142 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3144 module_init(sci_init);
3145 module_exit(sci_exit);
3147 MODULE_LICENSE("GPL");
3148 MODULE_ALIAS("platform:sh-sci");
3149 MODULE_AUTHOR("Paul Mundt");
3150 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");