2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
87 /* Bit x set means sampling rate x + 1 is supported */
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
92 #define max_sr(_port) fls((_port)->sampling_rate_mask)
94 /* Iterate over all supported sampling rates, from high to low */
95 #define for_each_sr(_sr, _port) \
96 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
97 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
100 struct uart_port port;
102 /* Platform configuration */
103 struct plat_sci_port *cfg;
104 unsigned int overrun_reg;
105 unsigned int overrun_mask;
106 unsigned int error_mask;
107 unsigned int error_clear;
108 unsigned int sampling_rate_mask;
109 resource_size_t reg_size;
112 struct timer_list break_timer;
116 struct clk *clks[SCI_NUM_CLKS];
117 unsigned long clk_rates[SCI_NUM_CLKS];
119 int irqs[SCIx_NR_IRQS];
120 char *irqstr[SCIx_NR_IRQS];
122 struct dma_chan *chan_tx;
123 struct dma_chan *chan_rx;
125 #ifdef CONFIG_SERIAL_SH_SCI_DMA
126 dma_cookie_t cookie_tx;
127 dma_cookie_t cookie_rx[2];
128 dma_cookie_t active_rx;
129 dma_addr_t tx_dma_addr;
130 unsigned int tx_dma_len;
131 struct scatterlist sg_rx[2];
134 struct work_struct work_tx;
135 struct timer_list rx_timer;
136 unsigned int rx_timeout;
140 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
142 static struct sci_port sci_ports[SCI_NPORTS];
143 static struct uart_driver sci_uart_driver;
145 static inline struct sci_port *
146 to_sci_port(struct uart_port *uart)
148 return container_of(uart, struct sci_port, port);
151 struct plat_sci_reg {
155 /* Helper for invalidating specific entries of an inherited map. */
156 #define sci_reg_invalid { .offset = 0, .size = 0 }
158 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
159 [SCIx_PROBE_REGTYPE] = {
160 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
164 * Common SCI definitions, dependent on the port's regshift
167 [SCIx_SCI_REGTYPE] = {
168 [SCSMR] = { 0x00, 8 },
169 [SCBRR] = { 0x01, 8 },
170 [SCSCR] = { 0x02, 8 },
171 [SCxTDR] = { 0x03, 8 },
172 [SCxSR] = { 0x04, 8 },
173 [SCxRDR] = { 0x05, 8 },
174 [SCFCR] = sci_reg_invalid,
175 [SCFDR] = sci_reg_invalid,
176 [SCTFDR] = sci_reg_invalid,
177 [SCRFDR] = sci_reg_invalid,
178 [SCSPTR] = sci_reg_invalid,
179 [SCLSR] = sci_reg_invalid,
180 [HSSRR] = sci_reg_invalid,
181 [SCPCR] = sci_reg_invalid,
182 [SCPDR] = sci_reg_invalid,
183 [SCDL] = sci_reg_invalid,
184 [SCCKS] = sci_reg_invalid,
188 * Common definitions for legacy IrDA ports, dependent on
191 [SCIx_IRDA_REGTYPE] = {
192 [SCSMR] = { 0x00, 8 },
193 [SCBRR] = { 0x01, 8 },
194 [SCSCR] = { 0x02, 8 },
195 [SCxTDR] = { 0x03, 8 },
196 [SCxSR] = { 0x04, 8 },
197 [SCxRDR] = { 0x05, 8 },
198 [SCFCR] = { 0x06, 8 },
199 [SCFDR] = { 0x07, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 [HSSRR] = sci_reg_invalid,
205 [SCPCR] = sci_reg_invalid,
206 [SCPDR] = sci_reg_invalid,
207 [SCDL] = sci_reg_invalid,
208 [SCCKS] = sci_reg_invalid,
212 * Common SCIFA definitions.
214 [SCIx_SCIFA_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x20, 8 },
219 [SCxSR] = { 0x14, 16 },
220 [SCxRDR] = { 0x24, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = { 0x1c, 16 },
223 [SCTFDR] = sci_reg_invalid,
224 [SCRFDR] = sci_reg_invalid,
225 [SCSPTR] = sci_reg_invalid,
226 [SCLSR] = sci_reg_invalid,
227 [HSSRR] = sci_reg_invalid,
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
230 [SCDL] = sci_reg_invalid,
231 [SCCKS] = sci_reg_invalid,
235 * Common SCIFB definitions.
237 [SCIx_SCIFB_REGTYPE] = {
238 [SCSMR] = { 0x00, 16 },
239 [SCBRR] = { 0x04, 8 },
240 [SCSCR] = { 0x08, 16 },
241 [SCxTDR] = { 0x40, 8 },
242 [SCxSR] = { 0x14, 16 },
243 [SCxRDR] = { 0x60, 8 },
244 [SCFCR] = { 0x18, 16 },
245 [SCFDR] = sci_reg_invalid,
246 [SCTFDR] = { 0x38, 16 },
247 [SCRFDR] = { 0x3c, 16 },
248 [SCSPTR] = sci_reg_invalid,
249 [SCLSR] = sci_reg_invalid,
250 [HSSRR] = sci_reg_invalid,
251 [SCPCR] = { 0x30, 16 },
252 [SCPDR] = { 0x34, 16 },
253 [SCDL] = sci_reg_invalid,
254 [SCCKS] = sci_reg_invalid,
258 * Common SH-2(A) SCIF definitions for ports with FIFO data
261 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
262 [SCSMR] = { 0x00, 16 },
263 [SCBRR] = { 0x04, 8 },
264 [SCSCR] = { 0x08, 16 },
265 [SCxTDR] = { 0x0c, 8 },
266 [SCxSR] = { 0x10, 16 },
267 [SCxRDR] = { 0x14, 8 },
268 [SCFCR] = { 0x18, 16 },
269 [SCFDR] = { 0x1c, 16 },
270 [SCTFDR] = sci_reg_invalid,
271 [SCRFDR] = sci_reg_invalid,
272 [SCSPTR] = { 0x20, 16 },
273 [SCLSR] = { 0x24, 16 },
274 [HSSRR] = sci_reg_invalid,
275 [SCPCR] = sci_reg_invalid,
276 [SCPDR] = sci_reg_invalid,
277 [SCDL] = sci_reg_invalid,
278 [SCCKS] = sci_reg_invalid,
282 * Common SH-3 SCIF definitions.
284 [SCIx_SH3_SCIF_REGTYPE] = {
285 [SCSMR] = { 0x00, 8 },
286 [SCBRR] = { 0x02, 8 },
287 [SCSCR] = { 0x04, 8 },
288 [SCxTDR] = { 0x06, 8 },
289 [SCxSR] = { 0x08, 16 },
290 [SCxRDR] = { 0x0a, 8 },
291 [SCFCR] = { 0x0c, 8 },
292 [SCFDR] = { 0x0e, 16 },
293 [SCTFDR] = sci_reg_invalid,
294 [SCRFDR] = sci_reg_invalid,
295 [SCSPTR] = sci_reg_invalid,
296 [SCLSR] = sci_reg_invalid,
297 [HSSRR] = sci_reg_invalid,
298 [SCPCR] = sci_reg_invalid,
299 [SCPDR] = sci_reg_invalid,
300 [SCDL] = sci_reg_invalid,
301 [SCCKS] = sci_reg_invalid,
305 * Common SH-4(A) SCIF(B) definitions.
307 [SCIx_SH4_SCIF_REGTYPE] = {
308 [SCSMR] = { 0x00, 16 },
309 [SCBRR] = { 0x04, 8 },
310 [SCSCR] = { 0x08, 16 },
311 [SCxTDR] = { 0x0c, 8 },
312 [SCxSR] = { 0x10, 16 },
313 [SCxRDR] = { 0x14, 8 },
314 [SCFCR] = { 0x18, 16 },
315 [SCFDR] = { 0x1c, 16 },
316 [SCTFDR] = sci_reg_invalid,
317 [SCRFDR] = sci_reg_invalid,
318 [SCSPTR] = { 0x20, 16 },
319 [SCLSR] = { 0x24, 16 },
320 [HSSRR] = sci_reg_invalid,
321 [SCPCR] = sci_reg_invalid,
322 [SCPDR] = sci_reg_invalid,
323 [SCDL] = sci_reg_invalid,
324 [SCCKS] = sci_reg_invalid,
328 * Common SCIF definitions for ports with a Baud Rate Generator for
329 * External Clock (BRG).
331 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
332 [SCSMR] = { 0x00, 16 },
333 [SCBRR] = { 0x04, 8 },
334 [SCSCR] = { 0x08, 16 },
335 [SCxTDR] = { 0x0c, 8 },
336 [SCxSR] = { 0x10, 16 },
337 [SCxRDR] = { 0x14, 8 },
338 [SCFCR] = { 0x18, 16 },
339 [SCFDR] = { 0x1c, 16 },
340 [SCTFDR] = sci_reg_invalid,
341 [SCRFDR] = sci_reg_invalid,
342 [SCSPTR] = { 0x20, 16 },
343 [SCLSR] = { 0x24, 16 },
344 [HSSRR] = sci_reg_invalid,
345 [SCPCR] = sci_reg_invalid,
346 [SCPDR] = sci_reg_invalid,
347 [SCDL] = { 0x30, 16 },
348 [SCCKS] = { 0x34, 16 },
352 * Common HSCIF definitions.
354 [SCIx_HSCIF_REGTYPE] = {
355 [SCSMR] = { 0x00, 16 },
356 [SCBRR] = { 0x04, 8 },
357 [SCSCR] = { 0x08, 16 },
358 [SCxTDR] = { 0x0c, 8 },
359 [SCxSR] = { 0x10, 16 },
360 [SCxRDR] = { 0x14, 8 },
361 [SCFCR] = { 0x18, 16 },
362 [SCFDR] = { 0x1c, 16 },
363 [SCTFDR] = sci_reg_invalid,
364 [SCRFDR] = sci_reg_invalid,
365 [SCSPTR] = { 0x20, 16 },
366 [SCLSR] = { 0x24, 16 },
367 [HSSRR] = { 0x40, 16 },
368 [SCPCR] = sci_reg_invalid,
369 [SCPDR] = sci_reg_invalid,
370 [SCDL] = { 0x30, 16 },
371 [SCCKS] = { 0x34, 16 },
375 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
378 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
379 [SCSMR] = { 0x00, 16 },
380 [SCBRR] = { 0x04, 8 },
381 [SCSCR] = { 0x08, 16 },
382 [SCxTDR] = { 0x0c, 8 },
383 [SCxSR] = { 0x10, 16 },
384 [SCxRDR] = { 0x14, 8 },
385 [SCFCR] = { 0x18, 16 },
386 [SCFDR] = { 0x1c, 16 },
387 [SCTFDR] = sci_reg_invalid,
388 [SCRFDR] = sci_reg_invalid,
389 [SCSPTR] = sci_reg_invalid,
390 [SCLSR] = { 0x24, 16 },
391 [HSSRR] = sci_reg_invalid,
392 [SCPCR] = sci_reg_invalid,
393 [SCPDR] = sci_reg_invalid,
394 [SCDL] = sci_reg_invalid,
395 [SCCKS] = sci_reg_invalid,
399 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
402 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
403 [SCSMR] = { 0x00, 16 },
404 [SCBRR] = { 0x04, 8 },
405 [SCSCR] = { 0x08, 16 },
406 [SCxTDR] = { 0x0c, 8 },
407 [SCxSR] = { 0x10, 16 },
408 [SCxRDR] = { 0x14, 8 },
409 [SCFCR] = { 0x18, 16 },
410 [SCFDR] = { 0x1c, 16 },
411 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
412 [SCRFDR] = { 0x20, 16 },
413 [SCSPTR] = { 0x24, 16 },
414 [SCLSR] = { 0x28, 16 },
415 [HSSRR] = sci_reg_invalid,
416 [SCPCR] = sci_reg_invalid,
417 [SCPDR] = sci_reg_invalid,
418 [SCDL] = sci_reg_invalid,
419 [SCCKS] = sci_reg_invalid,
423 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
426 [SCIx_SH7705_SCIF_REGTYPE] = {
427 [SCSMR] = { 0x00, 16 },
428 [SCBRR] = { 0x04, 8 },
429 [SCSCR] = { 0x08, 16 },
430 [SCxTDR] = { 0x20, 8 },
431 [SCxSR] = { 0x14, 16 },
432 [SCxRDR] = { 0x24, 8 },
433 [SCFCR] = { 0x18, 16 },
434 [SCFDR] = { 0x1c, 16 },
435 [SCTFDR] = sci_reg_invalid,
436 [SCRFDR] = sci_reg_invalid,
437 [SCSPTR] = sci_reg_invalid,
438 [SCLSR] = sci_reg_invalid,
439 [HSSRR] = sci_reg_invalid,
440 [SCPCR] = sci_reg_invalid,
441 [SCPDR] = sci_reg_invalid,
442 [SCDL] = sci_reg_invalid,
443 [SCCKS] = sci_reg_invalid,
447 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
450 * The "offset" here is rather misleading, in that it refers to an enum
451 * value relative to the port mapping rather than the fixed offset
452 * itself, which needs to be manually retrieved from the platform's
453 * register map for the given port.
455 static unsigned int sci_serial_in(struct uart_port *p, int offset)
457 const struct plat_sci_reg *reg = sci_getreg(p, offset);
460 return ioread8(p->membase + (reg->offset << p->regshift));
461 else if (reg->size == 16)
462 return ioread16(p->membase + (reg->offset << p->regshift));
464 WARN(1, "Invalid register access\n");
469 static void sci_serial_out(struct uart_port *p, int offset, int value)
471 const struct plat_sci_reg *reg = sci_getreg(p, offset);
474 iowrite8(value, p->membase + (reg->offset << p->regshift));
475 else if (reg->size == 16)
476 iowrite16(value, p->membase + (reg->offset << p->regshift));
478 WARN(1, "Invalid register access\n");
481 static int sci_probe_regmap(struct plat_sci_port *cfg)
485 cfg->regtype = SCIx_SCI_REGTYPE;
488 cfg->regtype = SCIx_IRDA_REGTYPE;
491 cfg->regtype = SCIx_SCIFA_REGTYPE;
494 cfg->regtype = SCIx_SCIFB_REGTYPE;
498 * The SH-4 is a bit of a misnomer here, although that's
499 * where this particular port layout originated. This
500 * configuration (or some slight variation thereof)
501 * remains the dominant model for all SCIFs.
503 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
506 cfg->regtype = SCIx_HSCIF_REGTYPE;
509 pr_err("Can't probe register map for given port\n");
516 static void sci_port_enable(struct sci_port *sci_port)
520 if (!sci_port->port.dev)
523 pm_runtime_get_sync(sci_port->port.dev);
525 for (i = 0; i < SCI_NUM_CLKS; i++) {
526 clk_prepare_enable(sci_port->clks[i]);
527 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
529 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
532 static void sci_port_disable(struct sci_port *sci_port)
536 if (!sci_port->port.dev)
539 /* Cancel the break timer to ensure that the timer handler will not try
540 * to access the hardware with clocks and power disabled. Reset the
541 * break flag to make the break debouncing state machine ready for the
544 del_timer_sync(&sci_port->break_timer);
545 sci_port->break_flag = 0;
547 for (i = SCI_NUM_CLKS; i-- > 0; )
548 clk_disable_unprepare(sci_port->clks[i]);
550 pm_runtime_put_sync(sci_port->port.dev);
553 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
556 * Not all ports (such as SCIFA) will support REIE. Rather than
557 * special-casing the port type, we check the port initialization
558 * IRQ enable mask to see whether the IRQ is desired at all. If
559 * it's unset, it's logically inferred that there's no point in
562 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
565 static void sci_start_tx(struct uart_port *port)
567 struct sci_port *s = to_sci_port(port);
570 #ifdef CONFIG_SERIAL_SH_SCI_DMA
571 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
572 u16 new, scr = serial_port_in(port, SCSCR);
574 new = scr | SCSCR_TDRQE;
576 new = scr & ~SCSCR_TDRQE;
578 serial_port_out(port, SCSCR, new);
581 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
582 dma_submit_error(s->cookie_tx)) {
584 schedule_work(&s->work_tx);
588 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
589 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
590 ctrl = serial_port_in(port, SCSCR);
591 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
595 static void sci_stop_tx(struct uart_port *port)
599 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
600 ctrl = serial_port_in(port, SCSCR);
602 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
603 ctrl &= ~SCSCR_TDRQE;
607 serial_port_out(port, SCSCR, ctrl);
610 static void sci_start_rx(struct uart_port *port)
614 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
616 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
617 ctrl &= ~SCSCR_RDRQE;
619 serial_port_out(port, SCSCR, ctrl);
622 static void sci_stop_rx(struct uart_port *port)
626 ctrl = serial_port_in(port, SCSCR);
628 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
629 ctrl &= ~SCSCR_RDRQE;
631 ctrl &= ~port_rx_irq_mask(port);
633 serial_port_out(port, SCSCR, ctrl);
636 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
638 if (port->type == PORT_SCI) {
639 /* Just store the mask */
640 serial_port_out(port, SCxSR, mask);
641 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
642 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
643 /* Only clear the status bits we want to clear */
644 serial_port_out(port, SCxSR,
645 serial_port_in(port, SCxSR) & mask);
647 /* Store the mask, clear parity/framing errors */
648 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
652 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
653 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
655 #ifdef CONFIG_CONSOLE_POLL
656 static int sci_poll_get_char(struct uart_port *port)
658 unsigned short status;
662 status = serial_port_in(port, SCxSR);
663 if (status & SCxSR_ERRORS(port)) {
664 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
670 if (!(status & SCxSR_RDxF(port)))
673 c = serial_port_in(port, SCxRDR);
676 serial_port_in(port, SCxSR);
677 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
683 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
685 unsigned short status;
688 status = serial_port_in(port, SCxSR);
689 } while (!(status & SCxSR_TDxE(port)));
691 serial_port_out(port, SCxTDR, c);
692 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
694 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
695 CONFIG_SERIAL_SH_SCI_EARLYCON */
697 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
699 struct sci_port *s = to_sci_port(port);
700 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
703 * Use port-specific handler if provided.
705 if (s->cfg->ops && s->cfg->ops->init_pins) {
706 s->cfg->ops->init_pins(port, cflag);
711 * For the generic path SCSPTR is necessary. Bail out if that's
717 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
718 ((!(cflag & CRTSCTS)))) {
719 unsigned short status;
721 status = serial_port_in(port, SCSPTR);
722 status &= ~SCSPTR_CTSIO;
723 status |= SCSPTR_RTSIO;
724 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
728 static int sci_txfill(struct uart_port *port)
730 const struct plat_sci_reg *reg;
732 reg = sci_getreg(port, SCTFDR);
734 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
736 reg = sci_getreg(port, SCFDR);
738 return serial_port_in(port, SCFDR) >> 8;
740 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
743 static int sci_txroom(struct uart_port *port)
745 return port->fifosize - sci_txfill(port);
748 static int sci_rxfill(struct uart_port *port)
750 const struct plat_sci_reg *reg;
752 reg = sci_getreg(port, SCRFDR);
754 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
756 reg = sci_getreg(port, SCFDR);
758 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
760 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
764 * SCI helper for checking the state of the muxed port/RXD pins.
766 static inline int sci_rxd_in(struct uart_port *port)
768 struct sci_port *s = to_sci_port(port);
770 if (s->cfg->port_reg <= 0)
773 /* Cast for ARM damage */
774 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
777 /* ********************************************************************** *
778 * the interrupt related routines *
779 * ********************************************************************** */
781 static void sci_transmit_chars(struct uart_port *port)
783 struct circ_buf *xmit = &port->state->xmit;
784 unsigned int stopped = uart_tx_stopped(port);
785 unsigned short status;
789 status = serial_port_in(port, SCxSR);
790 if (!(status & SCxSR_TDxE(port))) {
791 ctrl = serial_port_in(port, SCSCR);
792 if (uart_circ_empty(xmit))
796 serial_port_out(port, SCSCR, ctrl);
800 count = sci_txroom(port);
808 } else if (!uart_circ_empty(xmit) && !stopped) {
809 c = xmit->buf[xmit->tail];
810 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
815 serial_port_out(port, SCxTDR, c);
818 } while (--count > 0);
820 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
822 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
823 uart_write_wakeup(port);
824 if (uart_circ_empty(xmit)) {
827 ctrl = serial_port_in(port, SCSCR);
829 if (port->type != PORT_SCI) {
830 serial_port_in(port, SCxSR); /* Dummy read */
831 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
835 serial_port_out(port, SCSCR, ctrl);
839 /* On SH3, SCIF may read end-of-break as a space->mark char */
840 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
842 static void sci_receive_chars(struct uart_port *port)
844 struct sci_port *sci_port = to_sci_port(port);
845 struct tty_port *tport = &port->state->port;
846 int i, count, copied = 0;
847 unsigned short status;
850 status = serial_port_in(port, SCxSR);
851 if (!(status & SCxSR_RDxF(port)))
855 /* Don't copy more bytes than there is room for in the buffer */
856 count = tty_buffer_request_room(tport, sci_rxfill(port));
858 /* If for any reason we can't copy more data, we're done! */
862 if (port->type == PORT_SCI) {
863 char c = serial_port_in(port, SCxRDR);
864 if (uart_handle_sysrq_char(port, c) ||
865 sci_port->break_flag)
868 tty_insert_flip_char(tport, c, TTY_NORMAL);
870 for (i = 0; i < count; i++) {
871 char c = serial_port_in(port, SCxRDR);
873 status = serial_port_in(port, SCxSR);
874 #if defined(CONFIG_CPU_SH3)
875 /* Skip "chars" during break */
876 if (sci_port->break_flag) {
878 (status & SCxSR_FER(port))) {
883 /* Nonzero => end-of-break */
884 dev_dbg(port->dev, "debounce<%02x>\n", c);
885 sci_port->break_flag = 0;
892 #endif /* CONFIG_CPU_SH3 */
893 if (uart_handle_sysrq_char(port, c)) {
898 /* Store data and status */
899 if (status & SCxSR_FER(port)) {
901 port->icount.frame++;
902 dev_notice(port->dev, "frame error\n");
903 } else if (status & SCxSR_PER(port)) {
905 port->icount.parity++;
906 dev_notice(port->dev, "parity error\n");
910 tty_insert_flip_char(tport, c, flag);
914 serial_port_in(port, SCxSR); /* dummy read */
915 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
918 port->icount.rx += count;
922 /* Tell the rest of the system the news. New characters! */
923 tty_flip_buffer_push(tport);
925 serial_port_in(port, SCxSR); /* dummy read */
926 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
930 #define SCI_BREAK_JIFFIES (HZ/20)
933 * The sci generates interrupts during the break,
934 * 1 per millisecond or so during the break period, for 9600 baud.
935 * So dont bother disabling interrupts.
936 * But dont want more than 1 break event.
937 * Use a kernel timer to periodically poll the rx line until
938 * the break is finished.
940 static inline void sci_schedule_break_timer(struct sci_port *port)
942 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
945 /* Ensure that two consecutive samples find the break over. */
946 static void sci_break_timer(unsigned long data)
948 struct sci_port *port = (struct sci_port *)data;
950 if (sci_rxd_in(&port->port) == 0) {
951 port->break_flag = 1;
952 sci_schedule_break_timer(port);
953 } else if (port->break_flag == 1) {
955 port->break_flag = 2;
956 sci_schedule_break_timer(port);
958 port->break_flag = 0;
961 static int sci_handle_errors(struct uart_port *port)
964 unsigned short status = serial_port_in(port, SCxSR);
965 struct tty_port *tport = &port->state->port;
966 struct sci_port *s = to_sci_port(port);
968 /* Handle overruns */
969 if (status & s->overrun_mask) {
970 port->icount.overrun++;
973 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
976 dev_notice(port->dev, "overrun error\n");
979 if (status & SCxSR_FER(port)) {
980 if (sci_rxd_in(port) == 0) {
981 /* Notify of BREAK */
982 struct sci_port *sci_port = to_sci_port(port);
984 if (!sci_port->break_flag) {
987 sci_port->break_flag = 1;
988 sci_schedule_break_timer(sci_port);
990 /* Do sysrq handling. */
991 if (uart_handle_break(port))
994 dev_dbg(port->dev, "BREAK detected\n");
996 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1002 port->icount.frame++;
1004 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1007 dev_notice(port->dev, "frame error\n");
1011 if (status & SCxSR_PER(port)) {
1013 port->icount.parity++;
1015 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1018 dev_notice(port->dev, "parity error\n");
1022 tty_flip_buffer_push(tport);
1027 static int sci_handle_fifo_overrun(struct uart_port *port)
1029 struct tty_port *tport = &port->state->port;
1030 struct sci_port *s = to_sci_port(port);
1031 const struct plat_sci_reg *reg;
1035 reg = sci_getreg(port, s->overrun_reg);
1039 status = serial_port_in(port, s->overrun_reg);
1040 if (status & s->overrun_mask) {
1041 status &= ~s->overrun_mask;
1042 serial_port_out(port, s->overrun_reg, status);
1044 port->icount.overrun++;
1046 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1047 tty_flip_buffer_push(tport);
1049 dev_dbg(port->dev, "overrun error\n");
1056 static int sci_handle_breaks(struct uart_port *port)
1059 unsigned short status = serial_port_in(port, SCxSR);
1060 struct tty_port *tport = &port->state->port;
1061 struct sci_port *s = to_sci_port(port);
1063 if (uart_handle_break(port))
1066 if (!s->break_flag && status & SCxSR_BRK(port)) {
1067 #if defined(CONFIG_CPU_SH3)
1068 /* Debounce break */
1074 /* Notify of BREAK */
1075 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1078 dev_dbg(port->dev, "BREAK detected\n");
1082 tty_flip_buffer_push(tport);
1084 copied += sci_handle_fifo_overrun(port);
1089 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1090 static void sci_dma_tx_complete(void *arg)
1092 struct sci_port *s = arg;
1093 struct uart_port *port = &s->port;
1094 struct circ_buf *xmit = &port->state->xmit;
1095 unsigned long flags;
1097 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1099 spin_lock_irqsave(&port->lock, flags);
1101 xmit->tail += s->tx_dma_len;
1102 xmit->tail &= UART_XMIT_SIZE - 1;
1104 port->icount.tx += s->tx_dma_len;
1106 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1107 uart_write_wakeup(port);
1109 if (!uart_circ_empty(xmit)) {
1111 schedule_work(&s->work_tx);
1113 s->cookie_tx = -EINVAL;
1114 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1115 u16 ctrl = serial_port_in(port, SCSCR);
1116 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1120 spin_unlock_irqrestore(&port->lock, flags);
1123 /* Locking: called with port lock held */
1124 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1126 struct uart_port *port = &s->port;
1127 struct tty_port *tport = &port->state->port;
1130 copied = tty_insert_flip_string(tport, buf, count);
1131 if (copied < count) {
1132 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1134 port->icount.buf_overrun++;
1137 port->icount.rx += copied;
1142 static int sci_dma_rx_find_active(struct sci_port *s)
1146 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1147 if (s->active_rx == s->cookie_rx[i])
1150 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1155 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1157 struct dma_chan *chan = s->chan_rx;
1158 struct uart_port *port = &s->port;
1159 unsigned long flags;
1161 spin_lock_irqsave(&port->lock, flags);
1163 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1164 spin_unlock_irqrestore(&port->lock, flags);
1165 dmaengine_terminate_all(chan);
1166 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1167 sg_dma_address(&s->sg_rx[0]));
1168 dma_release_channel(chan);
1173 static void sci_dma_rx_complete(void *arg)
1175 struct sci_port *s = arg;
1176 struct dma_chan *chan = s->chan_rx;
1177 struct uart_port *port = &s->port;
1178 struct dma_async_tx_descriptor *desc;
1179 unsigned long flags;
1180 int active, count = 0;
1182 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1185 spin_lock_irqsave(&port->lock, flags);
1187 active = sci_dma_rx_find_active(s);
1189 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1191 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1194 tty_flip_buffer_push(&port->state->port);
1196 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1198 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1202 desc->callback = sci_dma_rx_complete;
1203 desc->callback_param = s;
1204 s->cookie_rx[active] = dmaengine_submit(desc);
1205 if (dma_submit_error(s->cookie_rx[active]))
1208 s->active_rx = s->cookie_rx[!active];
1210 dma_async_issue_pending(chan);
1212 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1213 __func__, s->cookie_rx[active], active, s->active_rx);
1214 spin_unlock_irqrestore(&port->lock, flags);
1218 spin_unlock_irqrestore(&port->lock, flags);
1219 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1220 sci_rx_dma_release(s, true);
1223 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1225 struct dma_chan *chan = s->chan_tx;
1226 struct uart_port *port = &s->port;
1227 unsigned long flags;
1229 spin_lock_irqsave(&port->lock, flags);
1231 s->cookie_tx = -EINVAL;
1232 spin_unlock_irqrestore(&port->lock, flags);
1233 dmaengine_terminate_all(chan);
1234 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1236 dma_release_channel(chan);
1241 static void sci_submit_rx(struct sci_port *s)
1243 struct dma_chan *chan = s->chan_rx;
1246 for (i = 0; i < 2; i++) {
1247 struct scatterlist *sg = &s->sg_rx[i];
1248 struct dma_async_tx_descriptor *desc;
1250 desc = dmaengine_prep_slave_sg(chan,
1251 sg, 1, DMA_DEV_TO_MEM,
1252 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1256 desc->callback = sci_dma_rx_complete;
1257 desc->callback_param = s;
1258 s->cookie_rx[i] = dmaengine_submit(desc);
1259 if (dma_submit_error(s->cookie_rx[i]))
1262 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1263 s->cookie_rx[i], i);
1266 s->active_rx = s->cookie_rx[0];
1268 dma_async_issue_pending(chan);
1273 dmaengine_terminate_all(chan);
1274 for (i = 0; i < 2; i++)
1275 s->cookie_rx[i] = -EINVAL;
1276 s->active_rx = -EINVAL;
1277 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1278 sci_rx_dma_release(s, true);
1281 static void work_fn_tx(struct work_struct *work)
1283 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1284 struct dma_async_tx_descriptor *desc;
1285 struct dma_chan *chan = s->chan_tx;
1286 struct uart_port *port = &s->port;
1287 struct circ_buf *xmit = &port->state->xmit;
1292 * Port xmit buffer is already mapped, and it is one page... Just adjust
1293 * offsets and lengths. Since it is a circular buffer, we have to
1294 * transmit till the end, and then the rest. Take the port lock to get a
1295 * consistent xmit buffer state.
1297 spin_lock_irq(&port->lock);
1298 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1299 s->tx_dma_len = min_t(unsigned int,
1300 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1301 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1302 spin_unlock_irq(&port->lock);
1304 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1308 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1310 sci_tx_dma_release(s, true);
1314 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1317 spin_lock_irq(&port->lock);
1318 desc->callback = sci_dma_tx_complete;
1319 desc->callback_param = s;
1320 spin_unlock_irq(&port->lock);
1321 s->cookie_tx = dmaengine_submit(desc);
1322 if (dma_submit_error(s->cookie_tx)) {
1323 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1325 sci_tx_dma_release(s, true);
1329 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1330 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1332 dma_async_issue_pending(chan);
1335 static void rx_timer_fn(unsigned long arg)
1337 struct sci_port *s = (struct sci_port *)arg;
1338 struct dma_chan *chan = s->chan_rx;
1339 struct uart_port *port = &s->port;
1340 struct dma_tx_state state;
1341 enum dma_status status;
1342 unsigned long flags;
1347 spin_lock_irqsave(&port->lock, flags);
1349 dev_dbg(port->dev, "DMA Rx timed out\n");
1351 active = sci_dma_rx_find_active(s);
1353 spin_unlock_irqrestore(&port->lock, flags);
1357 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1358 if (status == DMA_COMPLETE) {
1359 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1360 s->active_rx, active);
1361 spin_unlock_irqrestore(&port->lock, flags);
1363 /* Let packet complete handler take care of the packet */
1367 dmaengine_pause(chan);
1370 * sometimes DMA transfer doesn't stop even if it is stopped and
1371 * data keeps on coming until transaction is complete so check
1372 * for DMA_COMPLETE again
1373 * Let packet complete handler take care of the packet
1375 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1376 if (status == DMA_COMPLETE) {
1377 spin_unlock_irqrestore(&port->lock, flags);
1378 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1382 /* Handle incomplete DMA receive */
1383 dmaengine_terminate_all(s->chan_rx);
1384 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1385 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1389 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1391 tty_flip_buffer_push(&port->state->port);
1394 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1397 /* Direct new serial port interrupts back to CPU */
1398 scr = serial_port_in(port, SCSCR);
1399 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1400 scr &= ~SCSCR_RDRQE;
1401 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1403 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1405 spin_unlock_irqrestore(&port->lock, flags);
1408 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1409 enum dma_transfer_direction dir,
1412 dma_cap_mask_t mask;
1413 struct dma_chan *chan;
1414 struct dma_slave_config cfg;
1418 dma_cap_set(DMA_SLAVE, mask);
1420 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1421 (void *)(unsigned long)id, port->dev,
1422 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1425 "dma_request_slave_channel_compat failed\n");
1429 memset(&cfg, 0, sizeof(cfg));
1430 cfg.direction = dir;
1431 if (dir == DMA_MEM_TO_DEV) {
1432 cfg.dst_addr = port->mapbase +
1433 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1434 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1436 cfg.src_addr = port->mapbase +
1437 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1438 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1441 ret = dmaengine_slave_config(chan, &cfg);
1443 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1444 dma_release_channel(chan);
1451 static void sci_request_dma(struct uart_port *port)
1453 struct sci_port *s = to_sci_port(port);
1454 struct dma_chan *chan;
1456 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1458 if (!port->dev->of_node &&
1459 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1462 s->cookie_tx = -EINVAL;
1463 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1464 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1467 /* UART circular tx buffer is an aligned page. */
1468 s->tx_dma_addr = dma_map_single(chan->device->dev,
1469 port->state->xmit.buf,
1472 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1473 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1474 dma_release_channel(chan);
1477 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1478 __func__, UART_XMIT_SIZE,
1479 port->state->xmit.buf, &s->tx_dma_addr);
1482 INIT_WORK(&s->work_tx, work_fn_tx);
1485 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1486 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1494 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1495 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1499 "Failed to allocate Rx dma buffer, using PIO\n");
1500 dma_release_channel(chan);
1505 for (i = 0; i < 2; i++) {
1506 struct scatterlist *sg = &s->sg_rx[i];
1508 sg_init_table(sg, 1);
1510 sg_dma_address(sg) = dma;
1511 sg_dma_len(sg) = s->buf_len_rx;
1513 buf += s->buf_len_rx;
1514 dma += s->buf_len_rx;
1517 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1519 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1524 static void sci_free_dma(struct uart_port *port)
1526 struct sci_port *s = to_sci_port(port);
1529 sci_tx_dma_release(s, false);
1531 sci_rx_dma_release(s, false);
1534 static inline void sci_request_dma(struct uart_port *port)
1538 static inline void sci_free_dma(struct uart_port *port)
1543 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1545 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1546 struct uart_port *port = ptr;
1547 struct sci_port *s = to_sci_port(port);
1550 u16 scr = serial_port_in(port, SCSCR);
1551 u16 ssr = serial_port_in(port, SCxSR);
1553 /* Disable future Rx interrupts */
1554 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1555 disable_irq_nosync(irq);
1561 serial_port_out(port, SCSCR, scr);
1562 /* Clear current interrupt */
1563 serial_port_out(port, SCxSR,
1564 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1565 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1566 jiffies, s->rx_timeout);
1567 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1573 /* I think sci_receive_chars has to be called irrespective
1574 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1577 sci_receive_chars(ptr);
1582 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1584 struct uart_port *port = ptr;
1585 unsigned long flags;
1587 spin_lock_irqsave(&port->lock, flags);
1588 sci_transmit_chars(port);
1589 spin_unlock_irqrestore(&port->lock, flags);
1594 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1596 struct uart_port *port = ptr;
1597 struct sci_port *s = to_sci_port(port);
1600 if (port->type == PORT_SCI) {
1601 if (sci_handle_errors(port)) {
1602 /* discard character in rx buffer */
1603 serial_port_in(port, SCxSR);
1604 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1607 sci_handle_fifo_overrun(port);
1609 sci_receive_chars(ptr);
1612 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1614 /* Kick the transmission */
1616 sci_tx_interrupt(irq, ptr);
1621 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1623 struct uart_port *port = ptr;
1626 sci_handle_breaks(port);
1627 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1632 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1634 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1635 struct uart_port *port = ptr;
1636 struct sci_port *s = to_sci_port(port);
1637 irqreturn_t ret = IRQ_NONE;
1639 ssr_status = serial_port_in(port, SCxSR);
1640 scr_status = serial_port_in(port, SCSCR);
1641 if (s->overrun_reg == SCxSR)
1642 orer_status = ssr_status;
1644 if (sci_getreg(port, s->overrun_reg)->size)
1645 orer_status = serial_port_in(port, s->overrun_reg);
1648 err_enabled = scr_status & port_rx_irq_mask(port);
1651 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1653 ret = sci_tx_interrupt(irq, ptr);
1656 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1659 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1660 (scr_status & SCSCR_RIE))
1661 ret = sci_rx_interrupt(irq, ptr);
1663 /* Error Interrupt */
1664 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1665 ret = sci_er_interrupt(irq, ptr);
1667 /* Break Interrupt */
1668 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1669 ret = sci_br_interrupt(irq, ptr);
1671 /* Overrun Interrupt */
1672 if (orer_status & s->overrun_mask) {
1673 sci_handle_fifo_overrun(port);
1680 static const struct sci_irq_desc {
1682 irq_handler_t handler;
1683 } sci_irq_desc[] = {
1685 * Split out handlers, the default case.
1689 .handler = sci_er_interrupt,
1694 .handler = sci_rx_interrupt,
1699 .handler = sci_tx_interrupt,
1704 .handler = sci_br_interrupt,
1708 * Special muxed handler.
1712 .handler = sci_mpxed_interrupt,
1716 static int sci_request_irq(struct sci_port *port)
1718 struct uart_port *up = &port->port;
1721 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1722 const struct sci_irq_desc *desc;
1725 if (SCIx_IRQ_IS_MUXED(port)) {
1729 irq = port->irqs[i];
1732 * Certain port types won't support all of the
1733 * available interrupt sources.
1735 if (unlikely(irq < 0))
1739 desc = sci_irq_desc + i;
1740 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1741 dev_name(up->dev), desc->desc);
1742 if (!port->irqstr[j])
1745 ret = request_irq(irq, desc->handler, up->irqflags,
1746 port->irqstr[j], port);
1747 if (unlikely(ret)) {
1748 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1757 free_irq(port->irqs[i], port);
1761 kfree(port->irqstr[j]);
1766 static void sci_free_irq(struct sci_port *port)
1771 * Intentionally in reverse order so we iterate over the muxed
1774 for (i = 0; i < SCIx_NR_IRQS; i++) {
1775 int irq = port->irqs[i];
1778 * Certain port types won't support all of the available
1779 * interrupt sources.
1781 if (unlikely(irq < 0))
1784 free_irq(port->irqs[i], port);
1785 kfree(port->irqstr[i]);
1787 if (SCIx_IRQ_IS_MUXED(port)) {
1788 /* If there's only one IRQ, we're done. */
1794 static unsigned int sci_tx_empty(struct uart_port *port)
1796 unsigned short status = serial_port_in(port, SCxSR);
1797 unsigned short in_tx_fifo = sci_txfill(port);
1799 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1803 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1804 * CTS/RTS is supported in hardware by at least one port and controlled
1805 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1806 * handled via the ->init_pins() op, which is a bit of a one-way street,
1807 * lacking any ability to defer pin control -- this will later be
1808 * converted over to the GPIO framework).
1810 * Other modes (such as loopback) are supported generically on certain
1811 * port types, but not others. For these it's sufficient to test for the
1812 * existence of the support register and simply ignore the port type.
1814 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1816 if (mctrl & TIOCM_LOOP) {
1817 const struct plat_sci_reg *reg;
1820 * Standard loopback mode for SCFCR ports.
1822 reg = sci_getreg(port, SCFCR);
1824 serial_port_out(port, SCFCR,
1825 serial_port_in(port, SCFCR) |
1830 static unsigned int sci_get_mctrl(struct uart_port *port)
1833 * CTS/RTS is handled in hardware when supported, while nothing
1834 * else is wired up. Keep it simple and simply assert DSR/CAR.
1836 return TIOCM_DSR | TIOCM_CAR;
1839 static void sci_break_ctl(struct uart_port *port, int break_state)
1841 struct sci_port *s = to_sci_port(port);
1842 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1843 unsigned short scscr, scsptr;
1845 /* check wheter the port has SCSPTR */
1848 * Not supported by hardware. Most parts couple break and rx
1849 * interrupts together, with break detection always enabled.
1854 scsptr = serial_port_in(port, SCSPTR);
1855 scscr = serial_port_in(port, SCSCR);
1857 if (break_state == -1) {
1858 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1861 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1865 serial_port_out(port, SCSPTR, scsptr);
1866 serial_port_out(port, SCSCR, scscr);
1869 static int sci_startup(struct uart_port *port)
1871 struct sci_port *s = to_sci_port(port);
1872 unsigned long flags;
1875 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1877 ret = sci_request_irq(s);
1878 if (unlikely(ret < 0))
1881 sci_request_dma(port);
1883 spin_lock_irqsave(&port->lock, flags);
1886 spin_unlock_irqrestore(&port->lock, flags);
1891 static void sci_shutdown(struct uart_port *port)
1893 struct sci_port *s = to_sci_port(port);
1894 unsigned long flags;
1896 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1898 spin_lock_irqsave(&port->lock, flags);
1901 spin_unlock_irqrestore(&port->lock, flags);
1903 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1905 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1907 del_timer_sync(&s->rx_timer);
1915 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1918 unsigned long freq = s->clk_rates[SCI_SCK];
1919 int err, min_err = INT_MAX;
1922 if (s->port.type != PORT_HSCIF)
1925 for_each_sr(sr, s) {
1926 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1927 if (abs(err) >= abs(min_err))
1937 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1942 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1943 unsigned long freq, unsigned int *dlr,
1946 int err, min_err = INT_MAX;
1947 unsigned int sr, dl;
1949 if (s->port.type != PORT_HSCIF)
1952 for_each_sr(sr, s) {
1953 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1954 dl = clamp(dl, 1U, 65535U);
1956 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1957 if (abs(err) >= abs(min_err))
1968 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1969 min_err, *dlr, *srr + 1);
1973 /* calculate sample rate, BRR, and clock select */
1974 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1975 unsigned int *brr, unsigned int *srr,
1978 unsigned long freq = s->clk_rates[SCI_FCK];
1979 unsigned int sr, br, prediv, scrate, c;
1980 int err, min_err = INT_MAX;
1982 if (s->port.type != PORT_HSCIF)
1986 * Find the combination of sample rate and clock select with the
1987 * smallest deviation from the desired baud rate.
1988 * Prefer high sample rates to maximise the receive margin.
1990 * M: Receive margin (%)
1991 * N: Ratio of bit rate to clock (N = sampling rate)
1992 * D: Clock duty (D = 0 to 1.0)
1993 * L: Frame length (L = 9 to 12)
1994 * F: Absolute value of clock frequency deviation
1996 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1997 * (|D - 0.5| / N * (1 + F))|
1998 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2000 for_each_sr(sr, s) {
2001 for (c = 0; c <= 3; c++) {
2002 /* integerized formulas from HSCIF documentation */
2003 prediv = sr * (1 << (2 * c + 1));
2006 * We need to calculate:
2008 * br = freq / (prediv * bps) clamped to [1..256]
2009 * err = freq / (br * prediv) - bps
2011 * Watch out for overflow when calculating the desired
2012 * sampling clock rate!
2014 if (bps > UINT_MAX / prediv)
2017 scrate = prediv * bps;
2018 br = DIV_ROUND_CLOSEST(freq, scrate);
2019 br = clamp(br, 1U, 256U);
2021 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2022 if (abs(err) >= abs(min_err))
2036 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2037 min_err, *brr, *srr + 1, *cks);
2041 static void sci_reset(struct uart_port *port)
2043 const struct plat_sci_reg *reg;
2044 unsigned int status;
2047 status = serial_port_in(port, SCxSR);
2048 } while (!(status & SCxSR_TEND(port)));
2050 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2052 reg = sci_getreg(port, SCFCR);
2054 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2057 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2058 struct ktermios *old)
2060 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2061 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2062 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2063 struct sci_port *s = to_sci_port(port);
2064 const struct plat_sci_reg *reg;
2065 int min_err = INT_MAX, err;
2066 unsigned long max_freq = 0;
2069 if ((termios->c_cflag & CSIZE) == CS7)
2070 smr_val |= SCSMR_CHR;
2071 if (termios->c_cflag & PARENB)
2072 smr_val |= SCSMR_PE;
2073 if (termios->c_cflag & PARODD)
2074 smr_val |= SCSMR_PE | SCSMR_ODD;
2075 if (termios->c_cflag & CSTOPB)
2076 smr_val |= SCSMR_STOP;
2079 * earlyprintk comes here early on with port->uartclk set to zero.
2080 * the clock framework is not up and running at this point so here
2081 * we assume that 115200 is the maximum baud rate. please note that
2082 * the baud rate is not programmed during earlyprintk - it is assumed
2083 * that the previous boot loader has enabled required clocks and
2084 * setup the baud rate generator hardware for us already.
2086 if (!port->uartclk) {
2087 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2091 for (i = 0; i < SCI_NUM_CLKS; i++)
2092 max_freq = max(max_freq, s->clk_rates[i]);
2094 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2099 * There can be multiple sources for the sampling clock. Find the one
2100 * that gives us the smallest deviation from the desired baud rate.
2103 /* Optional Undivided External Clock */
2104 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2105 port->type != PORT_SCIFB) {
2106 err = sci_sck_calc(s, baud, &srr1);
2107 if (abs(err) < abs(min_err)) {
2109 scr_val = SCSCR_CKE1;
2118 /* Optional BRG Frequency Divided External Clock */
2119 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2120 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2122 if (abs(err) < abs(min_err)) {
2123 best_clk = SCI_SCIF_CLK;
2124 scr_val = SCSCR_CKE1;
2134 /* Optional BRG Frequency Divided Internal Clock */
2135 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2136 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2138 if (abs(err) < abs(min_err)) {
2139 best_clk = SCI_BRG_INT;
2140 scr_val = SCSCR_CKE1;
2150 /* Divided Functional Clock using standard Bit Rate Register */
2151 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2152 if (abs(err) < abs(min_err)) {
2163 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2164 s->clks[best_clk], baud, min_err);
2169 * Program the optional External Baud Rate Generator (BRG) first.
2170 * It controls the mux to select (H)SCK or frequency divided clock.
2172 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2173 serial_port_out(port, SCDL, dl);
2174 serial_port_out(port, SCCKS, sccks);
2179 uart_update_timeout(port, termios->c_cflag, baud);
2181 if (best_clk >= 0) {
2184 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2185 scr_val, smr_val, brr, sccks, dl, srr);
2186 serial_port_out(port, SCSCR, scr_val);
2187 serial_port_out(port, SCSMR, smr_val);
2188 serial_port_out(port, SCBRR, brr);
2189 if (sci_getreg(port, HSSRR)->size)
2190 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2192 /* Wait one bit interval */
2193 udelay((1000000 + (baud - 1)) / baud);
2195 /* Don't touch the bit rate configuration */
2196 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2197 smr_val |= serial_port_in(port, SCSMR) &
2198 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2199 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2200 serial_port_out(port, SCSCR, scr_val);
2201 serial_port_out(port, SCSMR, smr_val);
2204 sci_init_pins(port, termios->c_cflag);
2206 reg = sci_getreg(port, SCFCR);
2208 unsigned short ctrl = serial_port_in(port, SCFCR);
2210 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2211 if (termios->c_cflag & CRTSCTS)
2218 * As we've done a sci_reset() above, ensure we don't
2219 * interfere with the FIFOs while toggling MCE. As the
2220 * reset values could still be set, simply mask them out.
2222 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2224 serial_port_out(port, SCFCR, ctrl);
2227 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2228 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2229 serial_port_out(port, SCSCR, scr_val);
2231 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2233 * Calculate delay for 2 DMA buffers (4 FIFO).
2234 * See serial_core.c::uart_update_timeout().
2235 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2236 * function calculates 1 jiffie for the data plus 5 jiffies for the
2237 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2238 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2239 * value obtained by this formula is too small. Therefore, if the value
2240 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2245 /* byte size and parity */
2246 switch (termios->c_cflag & CSIZE) {
2261 if (termios->c_cflag & CSTOPB)
2263 if (termios->c_cflag & PARENB)
2265 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2267 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2268 s->rx_timeout * 1000 / HZ, port->timeout);
2269 if (s->rx_timeout < msecs_to_jiffies(20))
2270 s->rx_timeout = msecs_to_jiffies(20);
2274 if ((termios->c_cflag & CREAD) != 0)
2277 sci_port_disable(s);
2280 static void sci_pm(struct uart_port *port, unsigned int state,
2281 unsigned int oldstate)
2283 struct sci_port *sci_port = to_sci_port(port);
2286 case UART_PM_STATE_OFF:
2287 sci_port_disable(sci_port);
2290 sci_port_enable(sci_port);
2295 static const char *sci_type(struct uart_port *port)
2297 switch (port->type) {
2315 static int sci_remap_port(struct uart_port *port)
2317 struct sci_port *sport = to_sci_port(port);
2320 * Nothing to do if there's already an established membase.
2325 if (port->flags & UPF_IOREMAP) {
2326 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2327 if (unlikely(!port->membase)) {
2328 dev_err(port->dev, "can't remap port#%d\n", port->line);
2333 * For the simple (and majority of) cases where we don't
2334 * need to do any remapping, just cast the cookie
2337 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2343 static void sci_release_port(struct uart_port *port)
2345 struct sci_port *sport = to_sci_port(port);
2347 if (port->flags & UPF_IOREMAP) {
2348 iounmap(port->membase);
2349 port->membase = NULL;
2352 release_mem_region(port->mapbase, sport->reg_size);
2355 static int sci_request_port(struct uart_port *port)
2357 struct resource *res;
2358 struct sci_port *sport = to_sci_port(port);
2361 res = request_mem_region(port->mapbase, sport->reg_size,
2362 dev_name(port->dev));
2363 if (unlikely(res == NULL)) {
2364 dev_err(port->dev, "request_mem_region failed.");
2368 ret = sci_remap_port(port);
2369 if (unlikely(ret != 0)) {
2370 release_resource(res);
2377 static void sci_config_port(struct uart_port *port, int flags)
2379 if (flags & UART_CONFIG_TYPE) {
2380 struct sci_port *sport = to_sci_port(port);
2382 port->type = sport->cfg->type;
2383 sci_request_port(port);
2387 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2389 if (ser->baud_base < 2400)
2390 /* No paper tape reader for Mitch.. */
2396 static struct uart_ops sci_uart_ops = {
2397 .tx_empty = sci_tx_empty,
2398 .set_mctrl = sci_set_mctrl,
2399 .get_mctrl = sci_get_mctrl,
2400 .start_tx = sci_start_tx,
2401 .stop_tx = sci_stop_tx,
2402 .stop_rx = sci_stop_rx,
2403 .break_ctl = sci_break_ctl,
2404 .startup = sci_startup,
2405 .shutdown = sci_shutdown,
2406 .set_termios = sci_set_termios,
2409 .release_port = sci_release_port,
2410 .request_port = sci_request_port,
2411 .config_port = sci_config_port,
2412 .verify_port = sci_verify_port,
2413 #ifdef CONFIG_CONSOLE_POLL
2414 .poll_get_char = sci_poll_get_char,
2415 .poll_put_char = sci_poll_put_char,
2419 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2421 const char *clk_names[] = {
2424 [SCI_BRG_INT] = "brg_int",
2425 [SCI_SCIF_CLK] = "scif_clk",
2430 if (sci_port->cfg->type == PORT_HSCIF)
2431 clk_names[SCI_SCK] = "hsck";
2433 for (i = 0; i < SCI_NUM_CLKS; i++) {
2434 clk = devm_clk_get(dev, clk_names[i]);
2435 if (PTR_ERR(clk) == -EPROBE_DEFER)
2436 return -EPROBE_DEFER;
2438 if (IS_ERR(clk) && i == SCI_FCK) {
2440 * "fck" used to be called "sci_ick", and we need to
2441 * maintain DT backward compatibility.
2443 clk = devm_clk_get(dev, "sci_ick");
2444 if (PTR_ERR(clk) == -EPROBE_DEFER)
2445 return -EPROBE_DEFER;
2451 * Not all SH platforms declare a clock lookup entry
2452 * for SCI devices, in which case we need to get the
2453 * global "peripheral_clk" clock.
2455 clk = devm_clk_get(dev, "peripheral_clk");
2459 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2461 return PTR_ERR(clk);
2466 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2469 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2471 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2476 static int sci_init_single(struct platform_device *dev,
2477 struct sci_port *sci_port, unsigned int index,
2478 struct plat_sci_port *p, bool early)
2480 struct uart_port *port = &sci_port->port;
2481 const struct resource *res;
2487 port->ops = &sci_uart_ops;
2488 port->iotype = UPIO_MEM;
2491 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2495 port->mapbase = res->start;
2496 sci_port->reg_size = resource_size(res);
2498 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2499 sci_port->irqs[i] = platform_get_irq(dev, i);
2501 /* The SCI generates several interrupts. They can be muxed together or
2502 * connected to different interrupt lines. In the muxed case only one
2503 * interrupt resource is specified. In the non-muxed case three or four
2504 * interrupt resources are specified, as the BRI interrupt is optional.
2506 if (sci_port->irqs[0] < 0)
2509 if (sci_port->irqs[1] < 0) {
2510 sci_port->irqs[1] = sci_port->irqs[0];
2511 sci_port->irqs[2] = sci_port->irqs[0];
2512 sci_port->irqs[3] = sci_port->irqs[0];
2515 if (p->regtype == SCIx_PROBE_REGTYPE) {
2516 ret = sci_probe_regmap(p);
2523 port->fifosize = 256;
2524 sci_port->overrun_reg = SCxSR;
2525 sci_port->overrun_mask = SCIFA_ORER;
2526 sci_port->sampling_rate_mask = SCI_SR(16);
2529 port->fifosize = 128;
2530 sci_port->overrun_reg = SCLSR;
2531 sci_port->overrun_mask = SCLSR_ORER;
2532 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2535 port->fifosize = 64;
2536 sci_port->overrun_reg = SCxSR;
2537 sci_port->overrun_mask = SCIFA_ORER;
2538 sci_port->sampling_rate_mask = SCI_SR(16);
2541 port->fifosize = 16;
2542 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2543 sci_port->overrun_reg = SCxSR;
2544 sci_port->overrun_mask = SCIFA_ORER;
2545 sci_port->sampling_rate_mask = SCI_SR(16);
2547 sci_port->overrun_reg = SCLSR;
2548 sci_port->overrun_mask = SCLSR_ORER;
2549 sci_port->sampling_rate_mask = SCI_SR(32);
2554 sci_port->overrun_reg = SCxSR;
2555 sci_port->overrun_mask = SCI_ORER;
2556 sci_port->sampling_rate_mask = SCI_SR(32);
2560 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2561 * match the SoC datasheet, this should be investigated. Let platform
2562 * data override the sampling rate for now.
2564 if (p->sampling_rate)
2565 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2568 ret = sci_init_clocks(sci_port, &dev->dev);
2572 port->dev = &dev->dev;
2574 pm_runtime_enable(&dev->dev);
2577 sci_port->break_timer.data = (unsigned long)sci_port;
2578 sci_port->break_timer.function = sci_break_timer;
2579 init_timer(&sci_port->break_timer);
2582 * Establish some sensible defaults for the error detection.
2584 if (p->type == PORT_SCI) {
2585 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2586 sci_port->error_clear = SCI_ERROR_CLEAR;
2588 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2589 sci_port->error_clear = SCIF_ERROR_CLEAR;
2593 * Make the error mask inclusive of overrun detection, if
2596 if (sci_port->overrun_reg == SCxSR) {
2597 sci_port->error_mask |= sci_port->overrun_mask;
2598 sci_port->error_clear &= ~sci_port->overrun_mask;
2601 port->type = p->type;
2602 port->flags = UPF_FIXED_PORT | p->flags;
2603 port->regshift = p->regshift;
2606 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2607 * for the multi-IRQ ports, which is where we are primarily
2608 * concerned with the shutdown path synchronization.
2610 * For the muxed case there's nothing more to do.
2612 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2615 port->serial_in = sci_serial_in;
2616 port->serial_out = sci_serial_out;
2618 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2619 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2620 p->dma_slave_tx, p->dma_slave_rx);
2625 static void sci_cleanup_single(struct sci_port *port)
2627 pm_runtime_disable(port->port.dev);
2630 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2631 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2632 static void serial_console_putchar(struct uart_port *port, int ch)
2634 sci_poll_put_char(port, ch);
2638 * Print a string to the serial port trying not to disturb
2639 * any possible real use of the port...
2641 static void serial_console_write(struct console *co, const char *s,
2644 struct sci_port *sci_port = &sci_ports[co->index];
2645 struct uart_port *port = &sci_port->port;
2646 unsigned short bits, ctrl, ctrl_temp;
2647 unsigned long flags;
2650 local_irq_save(flags);
2651 #if defined(SUPPORT_SYSRQ)
2656 if (oops_in_progress)
2657 locked = spin_trylock(&port->lock);
2659 spin_lock(&port->lock);
2661 /* first save SCSCR then disable interrupts, keep clock source */
2662 ctrl = serial_port_in(port, SCSCR);
2663 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2664 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2665 serial_port_out(port, SCSCR, ctrl_temp);
2667 uart_console_write(port, s, count, serial_console_putchar);
2669 /* wait until fifo is empty and last bit has been transmitted */
2670 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2671 while ((serial_port_in(port, SCxSR) & bits) != bits)
2674 /* restore the SCSCR */
2675 serial_port_out(port, SCSCR, ctrl);
2678 spin_unlock(&port->lock);
2679 local_irq_restore(flags);
2682 static int serial_console_setup(struct console *co, char *options)
2684 struct sci_port *sci_port;
2685 struct uart_port *port;
2693 * Refuse to handle any bogus ports.
2695 if (co->index < 0 || co->index >= SCI_NPORTS)
2698 sci_port = &sci_ports[co->index];
2699 port = &sci_port->port;
2702 * Refuse to handle uninitialized ports.
2707 ret = sci_remap_port(port);
2708 if (unlikely(ret != 0))
2712 uart_parse_options(options, &baud, &parity, &bits, &flow);
2714 return uart_set_options(port, co, baud, parity, bits, flow);
2717 static struct console serial_console = {
2719 .device = uart_console_device,
2720 .write = serial_console_write,
2721 .setup = serial_console_setup,
2722 .flags = CON_PRINTBUFFER,
2724 .data = &sci_uart_driver,
2727 static struct console early_serial_console = {
2728 .name = "early_ttySC",
2729 .write = serial_console_write,
2730 .flags = CON_PRINTBUFFER,
2734 static char early_serial_buf[32];
2736 static int sci_probe_earlyprintk(struct platform_device *pdev)
2738 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2740 if (early_serial_console.data)
2743 early_serial_console.index = pdev->id;
2745 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2747 serial_console_setup(&early_serial_console, early_serial_buf);
2749 if (!strstr(early_serial_buf, "keep"))
2750 early_serial_console.flags |= CON_BOOT;
2752 register_console(&early_serial_console);
2756 #define SCI_CONSOLE (&serial_console)
2759 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2764 #define SCI_CONSOLE NULL
2766 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2768 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2770 static struct uart_driver sci_uart_driver = {
2771 .owner = THIS_MODULE,
2772 .driver_name = "sci",
2773 .dev_name = "ttySC",
2775 .minor = SCI_MINOR_START,
2777 .cons = SCI_CONSOLE,
2780 static int sci_remove(struct platform_device *dev)
2782 struct sci_port *port = platform_get_drvdata(dev);
2784 uart_remove_one_port(&sci_uart_driver, &port->port);
2786 sci_cleanup_single(port);
2792 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2793 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2794 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2796 static const struct of_device_id of_sci_match[] = {
2797 /* SoC-specific types */
2799 .compatible = "renesas,scif-r7s72100",
2800 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2802 /* Family-specific types */
2804 .compatible = "renesas,rcar-gen1-scif",
2805 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2807 .compatible = "renesas,rcar-gen2-scif",
2808 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2810 .compatible = "renesas,rcar-gen3-scif",
2811 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2815 .compatible = "renesas,scif",
2816 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2818 .compatible = "renesas,scifa",
2819 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2821 .compatible = "renesas,scifb",
2822 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2824 .compatible = "renesas,hscif",
2825 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2827 .compatible = "renesas,sci",
2828 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2833 MODULE_DEVICE_TABLE(of, of_sci_match);
2835 static struct plat_sci_port *
2836 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2838 struct device_node *np = pdev->dev.of_node;
2839 const struct of_device_id *match;
2840 struct plat_sci_port *p;
2843 if (!IS_ENABLED(CONFIG_OF) || !np)
2846 match = of_match_node(of_sci_match, np);
2850 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2854 /* Get the line number from the aliases node. */
2855 id = of_alias_get_id(np, "serial");
2857 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2863 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2864 p->type = SCI_OF_TYPE(match->data);
2865 p->regtype = SCI_OF_REGTYPE(match->data);
2866 p->scscr = SCSCR_RE | SCSCR_TE;
2871 static int sci_probe_single(struct platform_device *dev,
2873 struct plat_sci_port *p,
2874 struct sci_port *sciport)
2879 if (unlikely(index >= SCI_NPORTS)) {
2880 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2881 index+1, SCI_NPORTS);
2882 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2886 ret = sci_init_single(dev, sciport, index, p, false);
2890 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2892 sci_cleanup_single(sciport);
2899 static int sci_probe(struct platform_device *dev)
2901 struct plat_sci_port *p;
2902 struct sci_port *sp;
2903 unsigned int dev_id;
2907 * If we've come here via earlyprintk initialization, head off to
2908 * the special early probe. We don't have sufficient device state
2909 * to make it beyond this yet.
2911 if (is_early_platform_device(dev))
2912 return sci_probe_earlyprintk(dev);
2914 if (dev->dev.of_node) {
2915 p = sci_parse_dt(dev, &dev_id);
2919 p = dev->dev.platform_data;
2921 dev_err(&dev->dev, "no platform data supplied\n");
2928 sp = &sci_ports[dev_id];
2929 platform_set_drvdata(dev, sp);
2931 ret = sci_probe_single(dev, dev_id, p, sp);
2935 #ifdef CONFIG_SH_STANDARD_BIOS
2936 sh_bios_gdb_detach();
2942 static __maybe_unused int sci_suspend(struct device *dev)
2944 struct sci_port *sport = dev_get_drvdata(dev);
2947 uart_suspend_port(&sci_uart_driver, &sport->port);
2952 static __maybe_unused int sci_resume(struct device *dev)
2954 struct sci_port *sport = dev_get_drvdata(dev);
2957 uart_resume_port(&sci_uart_driver, &sport->port);
2962 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2964 static struct platform_driver sci_driver = {
2966 .remove = sci_remove,
2969 .pm = &sci_dev_pm_ops,
2970 .of_match_table = of_match_ptr(of_sci_match),
2974 static int __init sci_init(void)
2978 pr_info("%s\n", banner);
2980 ret = uart_register_driver(&sci_uart_driver);
2981 if (likely(ret == 0)) {
2982 ret = platform_driver_register(&sci_driver);
2984 uart_unregister_driver(&sci_uart_driver);
2990 static void __exit sci_exit(void)
2992 platform_driver_unregister(&sci_driver);
2993 uart_unregister_driver(&sci_uart_driver);
2996 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2997 early_platform_init_buffer("earlyprintk", &sci_driver,
2998 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3000 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3001 static struct __init plat_sci_port port_cfg;
3003 static int __init early_console_setup(struct earlycon_device *device,
3006 if (!device->port.membase)
3009 device->port.serial_in = sci_serial_in;
3010 device->port.serial_out = sci_serial_out;
3011 device->port.type = type;
3012 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3013 sci_ports[0].cfg = &port_cfg;
3014 sci_ports[0].cfg->type = type;
3015 sci_probe_regmap(sci_ports[0].cfg);
3016 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3017 SCSCR_RE | SCSCR_TE;
3018 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3020 device->con->write = serial_console_write;
3023 static int __init sci_early_console_setup(struct earlycon_device *device,
3026 return early_console_setup(device, PORT_SCI);
3028 static int __init scif_early_console_setup(struct earlycon_device *device,
3031 return early_console_setup(device, PORT_SCIF);
3033 static int __init scifa_early_console_setup(struct earlycon_device *device,
3036 return early_console_setup(device, PORT_SCIFA);
3038 static int __init scifb_early_console_setup(struct earlycon_device *device,
3041 return early_console_setup(device, PORT_SCIFB);
3043 static int __init hscif_early_console_setup(struct earlycon_device *device,
3046 return early_console_setup(device, PORT_HSCIF);
3049 EARLYCON_DECLARE(sci, sci_early_console_setup);
3050 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3051 EARLYCON_DECLARE(scif, scif_early_console_setup);
3052 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3053 EARLYCON_DECLARE(scifa, scifa_early_console_setup);
3054 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3055 EARLYCON_DECLARE(scifb, scifb_early_console_setup);
3056 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3057 EARLYCON_DECLARE(hscif, hscif_early_console_setup);
3058 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3059 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3061 module_init(sci_init);
3062 module_exit(sci_exit);
3064 MODULE_LICENSE("GPL");
3065 MODULE_ALIAS("platform:sh-sci");
3066 MODULE_AUTHOR("Paul Mundt");
3067 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");