2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/sh_dma.h>
29 #include <linux/timer.h>
30 #include <linux/interrupt.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/sysrq.h>
37 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/console.h>
42 #include <linux/platform_device.h>
43 #include <linux/serial_sci.h>
44 #include <linux/notifier.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/slab.h>
54 #include <linux/gpio.h>
58 #include <asm/sh_bios.h>
64 struct uart_port port;
66 /* Platform configuration */
67 struct plat_sci_port *cfg;
70 struct timer_list break_timer;
78 char *irqstr[SCIx_NR_IRQS];
79 char *gpiostr[SCIx_NR_FNS];
81 struct dma_chan *chan_tx;
82 struct dma_chan *chan_rx;
84 #ifdef CONFIG_SERIAL_SH_SCI_DMA
85 struct dma_async_tx_descriptor *desc_tx;
86 struct dma_async_tx_descriptor *desc_rx[2];
87 dma_cookie_t cookie_tx;
88 dma_cookie_t cookie_rx[2];
89 dma_cookie_t active_rx;
90 struct scatterlist sg_tx;
91 unsigned int sg_len_tx;
92 struct scatterlist sg_rx[2];
94 struct sh_dmae_slave param_tx;
95 struct sh_dmae_slave param_rx;
96 struct work_struct work_tx;
97 struct work_struct work_rx;
98 struct timer_list rx_timer;
99 unsigned int rx_timeout;
102 struct notifier_block freq_transition;
105 /* Function prototypes */
106 static void sci_start_tx(struct uart_port *port);
107 static void sci_stop_tx(struct uart_port *port);
108 static void sci_start_rx(struct uart_port *port);
110 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
112 static struct sci_port sci_ports[SCI_NPORTS];
113 static struct uart_driver sci_uart_driver;
115 static inline struct sci_port *
116 to_sci_port(struct uart_port *uart)
118 return container_of(uart, struct sci_port, port);
121 struct plat_sci_reg {
125 /* Helper for invalidating specific entries of an inherited map. */
126 #define sci_reg_invalid { .offset = 0, .size = 0 }
128 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
129 [SCIx_PROBE_REGTYPE] = {
130 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
134 * Common SCI definitions, dependent on the port's regshift
137 [SCIx_SCI_REGTYPE] = {
138 [SCSMR] = { 0x00, 8 },
139 [SCBRR] = { 0x01, 8 },
140 [SCSCR] = { 0x02, 8 },
141 [SCxTDR] = { 0x03, 8 },
142 [SCxSR] = { 0x04, 8 },
143 [SCxRDR] = { 0x05, 8 },
144 [SCFCR] = sci_reg_invalid,
145 [SCFDR] = sci_reg_invalid,
146 [SCTFDR] = sci_reg_invalid,
147 [SCRFDR] = sci_reg_invalid,
148 [SCSPTR] = sci_reg_invalid,
149 [SCLSR] = sci_reg_invalid,
153 * Common definitions for legacy IrDA ports, dependent on
156 [SCIx_IRDA_REGTYPE] = {
157 [SCSMR] = { 0x00, 8 },
158 [SCBRR] = { 0x01, 8 },
159 [SCSCR] = { 0x02, 8 },
160 [SCxTDR] = { 0x03, 8 },
161 [SCxSR] = { 0x04, 8 },
162 [SCxRDR] = { 0x05, 8 },
163 [SCFCR] = { 0x06, 8 },
164 [SCFDR] = { 0x07, 16 },
165 [SCTFDR] = sci_reg_invalid,
166 [SCRFDR] = sci_reg_invalid,
167 [SCSPTR] = sci_reg_invalid,
168 [SCLSR] = sci_reg_invalid,
172 * Common SCIFA definitions.
174 [SCIx_SCIFA_REGTYPE] = {
175 [SCSMR] = { 0x00, 16 },
176 [SCBRR] = { 0x04, 8 },
177 [SCSCR] = { 0x08, 16 },
178 [SCxTDR] = { 0x20, 8 },
179 [SCxSR] = { 0x14, 16 },
180 [SCxRDR] = { 0x24, 8 },
181 [SCFCR] = { 0x18, 16 },
182 [SCFDR] = { 0x1c, 16 },
183 [SCTFDR] = sci_reg_invalid,
184 [SCRFDR] = sci_reg_invalid,
185 [SCSPTR] = sci_reg_invalid,
186 [SCLSR] = sci_reg_invalid,
190 * Common SCIFB definitions.
192 [SCIx_SCIFB_REGTYPE] = {
193 [SCSMR] = { 0x00, 16 },
194 [SCBRR] = { 0x04, 8 },
195 [SCSCR] = { 0x08, 16 },
196 [SCxTDR] = { 0x40, 8 },
197 [SCxSR] = { 0x14, 16 },
198 [SCxRDR] = { 0x60, 8 },
199 [SCFCR] = { 0x18, 16 },
200 [SCFDR] = sci_reg_invalid,
201 [SCTFDR] = { 0x38, 16 },
202 [SCRFDR] = { 0x3c, 16 },
203 [SCSPTR] = sci_reg_invalid,
204 [SCLSR] = sci_reg_invalid,
208 * Common SH-2(A) SCIF definitions for ports with FIFO data
211 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
212 [SCSMR] = { 0x00, 16 },
213 [SCBRR] = { 0x04, 8 },
214 [SCSCR] = { 0x08, 16 },
215 [SCxTDR] = { 0x0c, 8 },
216 [SCxSR] = { 0x10, 16 },
217 [SCxRDR] = { 0x14, 8 },
218 [SCFCR] = { 0x18, 16 },
219 [SCFDR] = { 0x1c, 16 },
220 [SCTFDR] = sci_reg_invalid,
221 [SCRFDR] = sci_reg_invalid,
222 [SCSPTR] = { 0x20, 16 },
223 [SCLSR] = { 0x24, 16 },
227 * Common SH-3 SCIF definitions.
229 [SCIx_SH3_SCIF_REGTYPE] = {
230 [SCSMR] = { 0x00, 8 },
231 [SCBRR] = { 0x02, 8 },
232 [SCSCR] = { 0x04, 8 },
233 [SCxTDR] = { 0x06, 8 },
234 [SCxSR] = { 0x08, 16 },
235 [SCxRDR] = { 0x0a, 8 },
236 [SCFCR] = { 0x0c, 8 },
237 [SCFDR] = { 0x0e, 16 },
238 [SCTFDR] = sci_reg_invalid,
239 [SCRFDR] = sci_reg_invalid,
240 [SCSPTR] = sci_reg_invalid,
241 [SCLSR] = sci_reg_invalid,
245 * Common SH-4(A) SCIF(B) definitions.
247 [SCIx_SH4_SCIF_REGTYPE] = {
248 [SCSMR] = { 0x00, 16 },
249 [SCBRR] = { 0x04, 8 },
250 [SCSCR] = { 0x08, 16 },
251 [SCxTDR] = { 0x0c, 8 },
252 [SCxSR] = { 0x10, 16 },
253 [SCxRDR] = { 0x14, 8 },
254 [SCFCR] = { 0x18, 16 },
255 [SCFDR] = { 0x1c, 16 },
256 [SCTFDR] = sci_reg_invalid,
257 [SCRFDR] = sci_reg_invalid,
258 [SCSPTR] = { 0x20, 16 },
259 [SCLSR] = { 0x24, 16 },
263 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
266 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
267 [SCSMR] = { 0x00, 16 },
268 [SCBRR] = { 0x04, 8 },
269 [SCSCR] = { 0x08, 16 },
270 [SCxTDR] = { 0x0c, 8 },
271 [SCxSR] = { 0x10, 16 },
272 [SCxRDR] = { 0x14, 8 },
273 [SCFCR] = { 0x18, 16 },
274 [SCFDR] = { 0x1c, 16 },
275 [SCTFDR] = sci_reg_invalid,
276 [SCRFDR] = sci_reg_invalid,
277 [SCSPTR] = sci_reg_invalid,
278 [SCLSR] = { 0x24, 16 },
282 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
285 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
286 [SCSMR] = { 0x00, 16 },
287 [SCBRR] = { 0x04, 8 },
288 [SCSCR] = { 0x08, 16 },
289 [SCxTDR] = { 0x0c, 8 },
290 [SCxSR] = { 0x10, 16 },
291 [SCxRDR] = { 0x14, 8 },
292 [SCFCR] = { 0x18, 16 },
293 [SCFDR] = { 0x1c, 16 },
294 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
295 [SCRFDR] = { 0x20, 16 },
296 [SCSPTR] = { 0x24, 16 },
297 [SCLSR] = { 0x28, 16 },
301 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
304 [SCIx_SH7705_SCIF_REGTYPE] = {
305 [SCSMR] = { 0x00, 16 },
306 [SCBRR] = { 0x04, 8 },
307 [SCSCR] = { 0x08, 16 },
308 [SCxTDR] = { 0x20, 8 },
309 [SCxSR] = { 0x14, 16 },
310 [SCxRDR] = { 0x24, 8 },
311 [SCFCR] = { 0x18, 16 },
312 [SCFDR] = { 0x1c, 16 },
313 [SCTFDR] = sci_reg_invalid,
314 [SCRFDR] = sci_reg_invalid,
315 [SCSPTR] = sci_reg_invalid,
316 [SCLSR] = sci_reg_invalid,
320 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
323 * The "offset" here is rather misleading, in that it refers to an enum
324 * value relative to the port mapping rather than the fixed offset
325 * itself, which needs to be manually retrieved from the platform's
326 * register map for the given port.
328 static unsigned int sci_serial_in(struct uart_port *p, int offset)
330 struct plat_sci_reg *reg = sci_getreg(p, offset);
333 return ioread8(p->membase + (reg->offset << p->regshift));
334 else if (reg->size == 16)
335 return ioread16(p->membase + (reg->offset << p->regshift));
337 WARN(1, "Invalid register access\n");
342 static void sci_serial_out(struct uart_port *p, int offset, int value)
344 struct plat_sci_reg *reg = sci_getreg(p, offset);
347 iowrite8(value, p->membase + (reg->offset << p->regshift));
348 else if (reg->size == 16)
349 iowrite16(value, p->membase + (reg->offset << p->regshift));
351 WARN(1, "Invalid register access\n");
354 static int sci_probe_regmap(struct plat_sci_port *cfg)
358 cfg->regtype = SCIx_SCI_REGTYPE;
361 cfg->regtype = SCIx_IRDA_REGTYPE;
364 cfg->regtype = SCIx_SCIFA_REGTYPE;
367 cfg->regtype = SCIx_SCIFB_REGTYPE;
371 * The SH-4 is a bit of a misnomer here, although that's
372 * where this particular port layout originated. This
373 * configuration (or some slight variation thereof)
374 * remains the dominant model for all SCIFs.
376 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
379 printk(KERN_ERR "Can't probe register map for given port\n");
386 static void sci_port_enable(struct sci_port *sci_port)
388 if (!sci_port->port.dev)
391 pm_runtime_get_sync(sci_port->port.dev);
393 clk_enable(sci_port->iclk);
394 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
395 clk_enable(sci_port->fclk);
398 static void sci_port_disable(struct sci_port *sci_port)
400 if (!sci_port->port.dev)
403 clk_disable(sci_port->fclk);
404 clk_disable(sci_port->iclk);
406 pm_runtime_put_sync(sci_port->port.dev);
409 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
411 #ifdef CONFIG_CONSOLE_POLL
412 static int sci_poll_get_char(struct uart_port *port)
414 unsigned short status;
418 status = serial_port_in(port, SCxSR);
419 if (status & SCxSR_ERRORS(port)) {
420 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
426 if (!(status & SCxSR_RDxF(port)))
429 c = serial_port_in(port, SCxRDR);
432 serial_port_in(port, SCxSR);
433 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
439 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
441 unsigned short status;
444 status = serial_port_in(port, SCxSR);
445 } while (!(status & SCxSR_TDxE(port)));
447 serial_port_out(port, SCxTDR, c);
448 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
450 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
452 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
454 struct sci_port *s = to_sci_port(port);
455 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
458 * Use port-specific handler if provided.
460 if (s->cfg->ops && s->cfg->ops->init_pins) {
461 s->cfg->ops->init_pins(port, cflag);
466 * For the generic path SCSPTR is necessary. Bail out if that's
472 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
473 ((!(cflag & CRTSCTS)))) {
474 unsigned short status;
476 status = serial_port_in(port, SCSPTR);
477 status &= ~SCSPTR_CTSIO;
478 status |= SCSPTR_RTSIO;
479 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
483 static int sci_txfill(struct uart_port *port)
485 struct plat_sci_reg *reg;
487 reg = sci_getreg(port, SCTFDR);
489 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
491 reg = sci_getreg(port, SCFDR);
493 return serial_port_in(port, SCFDR) >> 8;
495 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
498 static int sci_txroom(struct uart_port *port)
500 return port->fifosize - sci_txfill(port);
503 static int sci_rxfill(struct uart_port *port)
505 struct plat_sci_reg *reg;
507 reg = sci_getreg(port, SCRFDR);
509 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
511 reg = sci_getreg(port, SCFDR);
513 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
515 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
519 * SCI helper for checking the state of the muxed port/RXD pins.
521 static inline int sci_rxd_in(struct uart_port *port)
523 struct sci_port *s = to_sci_port(port);
525 if (s->cfg->port_reg <= 0)
528 /* Cast for ARM damage */
529 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
532 /* ********************************************************************** *
533 * the interrupt related routines *
534 * ********************************************************************** */
536 static void sci_transmit_chars(struct uart_port *port)
538 struct circ_buf *xmit = &port->state->xmit;
539 unsigned int stopped = uart_tx_stopped(port);
540 unsigned short status;
544 status = serial_port_in(port, SCxSR);
545 if (!(status & SCxSR_TDxE(port))) {
546 ctrl = serial_port_in(port, SCSCR);
547 if (uart_circ_empty(xmit))
551 serial_port_out(port, SCSCR, ctrl);
555 count = sci_txroom(port);
563 } else if (!uart_circ_empty(xmit) && !stopped) {
564 c = xmit->buf[xmit->tail];
565 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
570 serial_port_out(port, SCxTDR, c);
573 } while (--count > 0);
575 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
577 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
578 uart_write_wakeup(port);
579 if (uart_circ_empty(xmit)) {
582 ctrl = serial_port_in(port, SCSCR);
584 if (port->type != PORT_SCI) {
585 serial_port_in(port, SCxSR); /* Dummy read */
586 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
590 serial_port_out(port, SCSCR, ctrl);
594 /* On SH3, SCIF may read end-of-break as a space->mark char */
595 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
597 static void sci_receive_chars(struct uart_port *port)
599 struct sci_port *sci_port = to_sci_port(port);
600 struct tty_port *tport = &port->state->port;
601 int i, count, copied = 0;
602 unsigned short status;
605 status = serial_port_in(port, SCxSR);
606 if (!(status & SCxSR_RDxF(port)))
610 /* Don't copy more bytes than there is room for in the buffer */
611 count = tty_buffer_request_room(tport, sci_rxfill(port));
613 /* If for any reason we can't copy more data, we're done! */
617 if (port->type == PORT_SCI) {
618 char c = serial_port_in(port, SCxRDR);
619 if (uart_handle_sysrq_char(port, c) ||
620 sci_port->break_flag)
623 tty_insert_flip_char(tport, c, TTY_NORMAL);
625 for (i = 0; i < count; i++) {
626 char c = serial_port_in(port, SCxRDR);
628 status = serial_port_in(port, SCxSR);
629 #if defined(CONFIG_CPU_SH3)
630 /* Skip "chars" during break */
631 if (sci_port->break_flag) {
633 (status & SCxSR_FER(port))) {
638 /* Nonzero => end-of-break */
639 dev_dbg(port->dev, "debounce<%02x>\n", c);
640 sci_port->break_flag = 0;
647 #endif /* CONFIG_CPU_SH3 */
648 if (uart_handle_sysrq_char(port, c)) {
653 /* Store data and status */
654 if (status & SCxSR_FER(port)) {
656 port->icount.frame++;
657 dev_notice(port->dev, "frame error\n");
658 } else if (status & SCxSR_PER(port)) {
660 port->icount.parity++;
661 dev_notice(port->dev, "parity error\n");
665 tty_insert_flip_char(tport, c, flag);
669 serial_port_in(port, SCxSR); /* dummy read */
670 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
673 port->icount.rx += count;
677 /* Tell the rest of the system the news. New characters! */
678 tty_flip_buffer_push(tport);
680 serial_port_in(port, SCxSR); /* dummy read */
681 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
685 #define SCI_BREAK_JIFFIES (HZ/20)
688 * The sci generates interrupts during the break,
689 * 1 per millisecond or so during the break period, for 9600 baud.
690 * So dont bother disabling interrupts.
691 * But dont want more than 1 break event.
692 * Use a kernel timer to periodically poll the rx line until
693 * the break is finished.
695 static inline void sci_schedule_break_timer(struct sci_port *port)
697 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
700 /* Ensure that two consecutive samples find the break over. */
701 static void sci_break_timer(unsigned long data)
703 struct sci_port *port = (struct sci_port *)data;
705 sci_port_enable(port);
707 if (sci_rxd_in(&port->port) == 0) {
708 port->break_flag = 1;
709 sci_schedule_break_timer(port);
710 } else if (port->break_flag == 1) {
712 port->break_flag = 2;
713 sci_schedule_break_timer(port);
715 port->break_flag = 0;
717 sci_port_disable(port);
720 static int sci_handle_errors(struct uart_port *port)
723 unsigned short status = serial_port_in(port, SCxSR);
724 struct tty_port *tport = &port->state->port;
725 struct sci_port *s = to_sci_port(port);
728 * Handle overruns, if supported.
730 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
731 if (status & (1 << s->cfg->overrun_bit)) {
732 port->icount.overrun++;
735 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
738 dev_notice(port->dev, "overrun error");
742 if (status & SCxSR_FER(port)) {
743 if (sci_rxd_in(port) == 0) {
744 /* Notify of BREAK */
745 struct sci_port *sci_port = to_sci_port(port);
747 if (!sci_port->break_flag) {
750 sci_port->break_flag = 1;
751 sci_schedule_break_timer(sci_port);
753 /* Do sysrq handling. */
754 if (uart_handle_break(port))
757 dev_dbg(port->dev, "BREAK detected\n");
759 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
765 port->icount.frame++;
767 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
770 dev_notice(port->dev, "frame error\n");
774 if (status & SCxSR_PER(port)) {
776 port->icount.parity++;
778 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
781 dev_notice(port->dev, "parity error");
785 tty_flip_buffer_push(tport);
790 static int sci_handle_fifo_overrun(struct uart_port *port)
792 struct tty_port *tport = &port->state->port;
793 struct sci_port *s = to_sci_port(port);
794 struct plat_sci_reg *reg;
797 reg = sci_getreg(port, SCLSR);
801 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
802 serial_port_out(port, SCLSR, 0);
804 port->icount.overrun++;
806 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
807 tty_flip_buffer_push(tport);
809 dev_notice(port->dev, "overrun error\n");
816 static int sci_handle_breaks(struct uart_port *port)
819 unsigned short status = serial_port_in(port, SCxSR);
820 struct tty_port *tport = &port->state->port;
821 struct sci_port *s = to_sci_port(port);
823 if (uart_handle_break(port))
826 if (!s->break_flag && status & SCxSR_BRK(port)) {
827 #if defined(CONFIG_CPU_SH3)
834 /* Notify of BREAK */
835 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
838 dev_dbg(port->dev, "BREAK detected\n");
842 tty_flip_buffer_push(tport);
844 copied += sci_handle_fifo_overrun(port);
849 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
851 #ifdef CONFIG_SERIAL_SH_SCI_DMA
852 struct uart_port *port = ptr;
853 struct sci_port *s = to_sci_port(port);
856 u16 scr = serial_port_in(port, SCSCR);
857 u16 ssr = serial_port_in(port, SCxSR);
859 /* Disable future Rx interrupts */
860 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
861 disable_irq_nosync(irq);
866 serial_port_out(port, SCSCR, scr);
867 /* Clear current interrupt */
868 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
869 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
870 jiffies, s->rx_timeout);
871 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
877 /* I think sci_receive_chars has to be called irrespective
878 * of whether the I_IXOFF is set, otherwise, how is the interrupt
881 sci_receive_chars(ptr);
886 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
888 struct uart_port *port = ptr;
891 spin_lock_irqsave(&port->lock, flags);
892 sci_transmit_chars(port);
893 spin_unlock_irqrestore(&port->lock, flags);
898 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
900 struct uart_port *port = ptr;
903 if (port->type == PORT_SCI) {
904 if (sci_handle_errors(port)) {
905 /* discard character in rx buffer */
906 serial_port_in(port, SCxSR);
907 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
910 sci_handle_fifo_overrun(port);
911 sci_rx_interrupt(irq, ptr);
914 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
916 /* Kick the transmission */
917 sci_tx_interrupt(irq, ptr);
922 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
924 struct uart_port *port = ptr;
927 sci_handle_breaks(port);
928 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
933 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
936 * Not all ports (such as SCIFA) will support REIE. Rather than
937 * special-casing the port type, we check the port initialization
938 * IRQ enable mask to see whether the IRQ is desired at all. If
939 * it's unset, it's logically inferred that there's no point in
942 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
945 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
947 unsigned short ssr_status, scr_status, err_enabled;
948 struct uart_port *port = ptr;
949 struct sci_port *s = to_sci_port(port);
950 irqreturn_t ret = IRQ_NONE;
952 ssr_status = serial_port_in(port, SCxSR);
953 scr_status = serial_port_in(port, SCSCR);
954 err_enabled = scr_status & port_rx_irq_mask(port);
957 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
959 ret = sci_tx_interrupt(irq, ptr);
962 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
965 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
966 (scr_status & SCSCR_RIE))
967 ret = sci_rx_interrupt(irq, ptr);
969 /* Error Interrupt */
970 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
971 ret = sci_er_interrupt(irq, ptr);
973 /* Break Interrupt */
974 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
975 ret = sci_br_interrupt(irq, ptr);
981 * Here we define a transition notifier so that we can update all of our
982 * ports' baud rate when the peripheral clock changes.
984 static int sci_notifier(struct notifier_block *self,
985 unsigned long phase, void *p)
987 struct sci_port *sci_port;
990 sci_port = container_of(self, struct sci_port, freq_transition);
992 if ((phase == CPUFREQ_POSTCHANGE) ||
993 (phase == CPUFREQ_RESUMECHANGE)) {
994 struct uart_port *port = &sci_port->port;
996 spin_lock_irqsave(&port->lock, flags);
997 port->uartclk = clk_get_rate(sci_port->iclk);
998 spin_unlock_irqrestore(&port->lock, flags);
1004 static struct sci_irq_desc {
1006 irq_handler_t handler;
1007 } sci_irq_desc[] = {
1009 * Split out handlers, the default case.
1013 .handler = sci_er_interrupt,
1018 .handler = sci_rx_interrupt,
1023 .handler = sci_tx_interrupt,
1028 .handler = sci_br_interrupt,
1032 * Special muxed handler.
1036 .handler = sci_mpxed_interrupt,
1040 static int sci_request_irq(struct sci_port *port)
1042 struct uart_port *up = &port->port;
1045 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1046 struct sci_irq_desc *desc;
1049 if (SCIx_IRQ_IS_MUXED(port)) {
1053 irq = port->cfg->irqs[i];
1056 * Certain port types won't support all of the
1057 * available interrupt sources.
1063 desc = sci_irq_desc + i;
1064 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1065 dev_name(up->dev), desc->desc);
1066 if (!port->irqstr[j]) {
1067 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1072 ret = request_irq(irq, desc->handler, up->irqflags,
1073 port->irqstr[j], port);
1074 if (unlikely(ret)) {
1075 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1084 free_irq(port->cfg->irqs[i], port);
1088 kfree(port->irqstr[j]);
1093 static void sci_free_irq(struct sci_port *port)
1098 * Intentionally in reverse order so we iterate over the muxed
1101 for (i = 0; i < SCIx_NR_IRQS; i++) {
1102 unsigned int irq = port->cfg->irqs[i];
1105 * Certain port types won't support all of the available
1106 * interrupt sources.
1111 free_irq(port->cfg->irqs[i], port);
1112 kfree(port->irqstr[i]);
1114 if (SCIx_IRQ_IS_MUXED(port)) {
1115 /* If there's only one IRQ, we're done. */
1121 static const char *sci_gpio_names[SCIx_NR_FNS] = {
1122 "sck", "rxd", "txd", "cts", "rts",
1125 static const char *sci_gpio_str(unsigned int index)
1127 return sci_gpio_names[index];
1130 static void sci_init_gpios(struct sci_port *port)
1132 struct uart_port *up = &port->port;
1138 for (i = 0; i < SCIx_NR_FNS; i++) {
1142 if (!port->cfg->gpios[i])
1145 desc = sci_gpio_str(i);
1147 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1148 dev_name(up->dev), desc);
1151 * If we've failed the allocation, we can still continue
1152 * on with a NULL string.
1154 if (!port->gpiostr[i])
1155 dev_notice(up->dev, "%s string allocation failure\n",
1158 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1159 if (unlikely(ret != 0)) {
1160 dev_notice(up->dev, "failed %s gpio request\n", desc);
1163 * If we can't get the GPIO for whatever reason,
1164 * no point in keeping the verbose string around.
1166 kfree(port->gpiostr[i]);
1171 static void sci_free_gpios(struct sci_port *port)
1175 for (i = 0; i < SCIx_NR_FNS; i++)
1176 if (port->cfg->gpios[i]) {
1177 gpio_free(port->cfg->gpios[i]);
1178 kfree(port->gpiostr[i]);
1182 static unsigned int sci_tx_empty(struct uart_port *port)
1184 unsigned short status = serial_port_in(port, SCxSR);
1185 unsigned short in_tx_fifo = sci_txfill(port);
1187 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1191 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1192 * CTS/RTS is supported in hardware by at least one port and controlled
1193 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1194 * handled via the ->init_pins() op, which is a bit of a one-way street,
1195 * lacking any ability to defer pin control -- this will later be
1196 * converted over to the GPIO framework).
1198 * Other modes (such as loopback) are supported generically on certain
1199 * port types, but not others. For these it's sufficient to test for the
1200 * existence of the support register and simply ignore the port type.
1202 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1204 if (mctrl & TIOCM_LOOP) {
1205 struct plat_sci_reg *reg;
1208 * Standard loopback mode for SCFCR ports.
1210 reg = sci_getreg(port, SCFCR);
1212 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1216 static unsigned int sci_get_mctrl(struct uart_port *port)
1219 * CTS/RTS is handled in hardware when supported, while nothing
1220 * else is wired up. Keep it simple and simply assert DSR/CAR.
1222 return TIOCM_DSR | TIOCM_CAR;
1225 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1226 static void sci_dma_tx_complete(void *arg)
1228 struct sci_port *s = arg;
1229 struct uart_port *port = &s->port;
1230 struct circ_buf *xmit = &port->state->xmit;
1231 unsigned long flags;
1233 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1235 spin_lock_irqsave(&port->lock, flags);
1237 xmit->tail += sg_dma_len(&s->sg_tx);
1238 xmit->tail &= UART_XMIT_SIZE - 1;
1240 port->icount.tx += sg_dma_len(&s->sg_tx);
1242 async_tx_ack(s->desc_tx);
1245 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1246 uart_write_wakeup(port);
1248 if (!uart_circ_empty(xmit)) {
1250 schedule_work(&s->work_tx);
1252 s->cookie_tx = -EINVAL;
1253 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1254 u16 ctrl = serial_port_in(port, SCSCR);
1255 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1259 spin_unlock_irqrestore(&port->lock, flags);
1262 /* Locking: called with port lock held */
1263 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1265 struct uart_port *port = &s->port;
1266 struct tty_port *tport = &port->state->port;
1267 int i, active, room;
1269 room = tty_buffer_request_room(tport, count);
1271 if (s->active_rx == s->cookie_rx[0]) {
1273 } else if (s->active_rx == s->cookie_rx[1]) {
1276 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1281 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1286 for (i = 0; i < room; i++)
1287 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1290 port->icount.rx += room;
1295 static void sci_dma_rx_complete(void *arg)
1297 struct sci_port *s = arg;
1298 struct uart_port *port = &s->port;
1299 unsigned long flags;
1302 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1304 spin_lock_irqsave(&port->lock, flags);
1306 count = sci_dma_rx_push(s, s->buf_len_rx);
1308 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1310 spin_unlock_irqrestore(&port->lock, flags);
1313 tty_flip_buffer_push(&port->state->port);
1315 schedule_work(&s->work_rx);
1318 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1320 struct dma_chan *chan = s->chan_rx;
1321 struct uart_port *port = &s->port;
1324 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1325 dma_release_channel(chan);
1326 if (sg_dma_address(&s->sg_rx[0]))
1327 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1328 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1333 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1335 struct dma_chan *chan = s->chan_tx;
1336 struct uart_port *port = &s->port;
1339 s->cookie_tx = -EINVAL;
1340 dma_release_channel(chan);
1345 static void sci_submit_rx(struct sci_port *s)
1347 struct dma_chan *chan = s->chan_rx;
1350 for (i = 0; i < 2; i++) {
1351 struct scatterlist *sg = &s->sg_rx[i];
1352 struct dma_async_tx_descriptor *desc;
1354 desc = dmaengine_prep_slave_sg(chan,
1355 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1358 s->desc_rx[i] = desc;
1359 desc->callback = sci_dma_rx_complete;
1360 desc->callback_param = s;
1361 s->cookie_rx[i] = desc->tx_submit(desc);
1364 if (!desc || s->cookie_rx[i] < 0) {
1366 async_tx_ack(s->desc_rx[0]);
1367 s->cookie_rx[0] = -EINVAL;
1371 s->cookie_rx[i] = -EINVAL;
1373 dev_warn(s->port.dev,
1374 "failed to re-start DMA, using PIO\n");
1375 sci_rx_dma_release(s, true);
1378 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1379 s->cookie_rx[i], i);
1382 s->active_rx = s->cookie_rx[0];
1384 dma_async_issue_pending(chan);
1387 static void work_fn_rx(struct work_struct *work)
1389 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1390 struct uart_port *port = &s->port;
1391 struct dma_async_tx_descriptor *desc;
1394 if (s->active_rx == s->cookie_rx[0]) {
1396 } else if (s->active_rx == s->cookie_rx[1]) {
1399 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1402 desc = s->desc_rx[new];
1404 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1406 /* Handle incomplete DMA receive */
1407 struct dma_chan *chan = s->chan_rx;
1408 struct shdma_desc *sh_desc = container_of(desc,
1409 struct shdma_desc, async_tx);
1410 unsigned long flags;
1413 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1414 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1415 sh_desc->partial, sh_desc->cookie);
1417 spin_lock_irqsave(&port->lock, flags);
1418 count = sci_dma_rx_push(s, sh_desc->partial);
1419 spin_unlock_irqrestore(&port->lock, flags);
1422 tty_flip_buffer_push(&port->state->port);
1429 s->cookie_rx[new] = desc->tx_submit(desc);
1430 if (s->cookie_rx[new] < 0) {
1431 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1432 sci_rx_dma_release(s, true);
1436 s->active_rx = s->cookie_rx[!new];
1438 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1439 s->cookie_rx[new], new, s->active_rx);
1442 static void work_fn_tx(struct work_struct *work)
1444 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1445 struct dma_async_tx_descriptor *desc;
1446 struct dma_chan *chan = s->chan_tx;
1447 struct uart_port *port = &s->port;
1448 struct circ_buf *xmit = &port->state->xmit;
1449 struct scatterlist *sg = &s->sg_tx;
1453 * Port xmit buffer is already mapped, and it is one page... Just adjust
1454 * offsets and lengths. Since it is a circular buffer, we have to
1455 * transmit till the end, and then the rest. Take the port lock to get a
1456 * consistent xmit buffer state.
1458 spin_lock_irq(&port->lock);
1459 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1460 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1462 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1463 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1464 spin_unlock_irq(&port->lock);
1466 BUG_ON(!sg_dma_len(sg));
1468 desc = dmaengine_prep_slave_sg(chan,
1469 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1470 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1473 sci_tx_dma_release(s, true);
1477 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1479 spin_lock_irq(&port->lock);
1481 desc->callback = sci_dma_tx_complete;
1482 desc->callback_param = s;
1483 spin_unlock_irq(&port->lock);
1484 s->cookie_tx = desc->tx_submit(desc);
1485 if (s->cookie_tx < 0) {
1486 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1488 sci_tx_dma_release(s, true);
1492 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1493 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1495 dma_async_issue_pending(chan);
1499 static void sci_start_tx(struct uart_port *port)
1501 struct sci_port *s = to_sci_port(port);
1502 unsigned short ctrl;
1504 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1505 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1506 u16 new, scr = serial_port_in(port, SCSCR);
1510 new = scr & ~0x8000;
1512 serial_port_out(port, SCSCR, new);
1515 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1518 schedule_work(&s->work_tx);
1522 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1523 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1524 ctrl = serial_port_in(port, SCSCR);
1525 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1529 static void sci_stop_tx(struct uart_port *port)
1531 unsigned short ctrl;
1533 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1534 ctrl = serial_port_in(port, SCSCR);
1536 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1541 serial_port_out(port, SCSCR, ctrl);
1544 static void sci_start_rx(struct uart_port *port)
1546 unsigned short ctrl;
1548 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1553 serial_port_out(port, SCSCR, ctrl);
1556 static void sci_stop_rx(struct uart_port *port)
1558 unsigned short ctrl;
1560 ctrl = serial_port_in(port, SCSCR);
1562 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1565 ctrl &= ~port_rx_irq_mask(port);
1567 serial_port_out(port, SCSCR, ctrl);
1570 static void sci_enable_ms(struct uart_port *port)
1573 * Not supported by hardware, always a nop.
1577 static void sci_break_ctl(struct uart_port *port, int break_state)
1579 struct sci_port *s = to_sci_port(port);
1580 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1581 unsigned short scscr, scsptr;
1583 /* check wheter the port has SCSPTR */
1586 * Not supported by hardware. Most parts couple break and rx
1587 * interrupts together, with break detection always enabled.
1592 scsptr = serial_port_in(port, SCSPTR);
1593 scscr = serial_port_in(port, SCSCR);
1595 if (break_state == -1) {
1596 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1599 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1603 serial_port_out(port, SCSPTR, scsptr);
1604 serial_port_out(port, SCSCR, scscr);
1607 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1608 static bool filter(struct dma_chan *chan, void *slave)
1610 struct sh_dmae_slave *param = slave;
1612 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1613 param->shdma_slave.slave_id);
1615 chan->private = ¶m->shdma_slave;
1619 static void rx_timer_fn(unsigned long arg)
1621 struct sci_port *s = (struct sci_port *)arg;
1622 struct uart_port *port = &s->port;
1623 u16 scr = serial_port_in(port, SCSCR);
1625 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1627 enable_irq(s->cfg->irqs[1]);
1629 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1630 dev_dbg(port->dev, "DMA Rx timed out\n");
1631 schedule_work(&s->work_rx);
1634 static void sci_request_dma(struct uart_port *port)
1636 struct sci_port *s = to_sci_port(port);
1637 struct sh_dmae_slave *param;
1638 struct dma_chan *chan;
1639 dma_cap_mask_t mask;
1642 dev_dbg(port->dev, "%s: port %d\n", __func__,
1645 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1649 dma_cap_set(DMA_SLAVE, mask);
1651 param = &s->param_tx;
1653 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1654 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1656 s->cookie_tx = -EINVAL;
1657 chan = dma_request_channel(mask, filter, param);
1658 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1661 sg_init_table(&s->sg_tx, 1);
1662 /* UART circular tx buffer is an aligned page. */
1663 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1664 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1665 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1666 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1668 sci_tx_dma_release(s, false);
1670 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1671 sg_dma_len(&s->sg_tx),
1672 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1674 s->sg_len_tx = nent;
1676 INIT_WORK(&s->work_tx, work_fn_tx);
1679 param = &s->param_rx;
1681 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1682 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1684 chan = dma_request_channel(mask, filter, param);
1685 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1693 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1694 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1695 &dma[0], GFP_KERNEL);
1699 "failed to allocate dma buffer, using PIO\n");
1700 sci_rx_dma_release(s, true);
1704 buf[1] = buf[0] + s->buf_len_rx;
1705 dma[1] = dma[0] + s->buf_len_rx;
1707 for (i = 0; i < 2; i++) {
1708 struct scatterlist *sg = &s->sg_rx[i];
1710 sg_init_table(sg, 1);
1711 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1712 (int)buf[i] & ~PAGE_MASK);
1713 sg_dma_address(sg) = dma[i];
1716 INIT_WORK(&s->work_rx, work_fn_rx);
1717 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1723 static void sci_free_dma(struct uart_port *port)
1725 struct sci_port *s = to_sci_port(port);
1728 sci_tx_dma_release(s, false);
1730 sci_rx_dma_release(s, false);
1733 static inline void sci_request_dma(struct uart_port *port)
1737 static inline void sci_free_dma(struct uart_port *port)
1742 static int sci_startup(struct uart_port *port)
1744 struct sci_port *s = to_sci_port(port);
1745 unsigned long flags;
1748 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1750 ret = sci_request_irq(s);
1751 if (unlikely(ret < 0))
1754 sci_request_dma(port);
1756 spin_lock_irqsave(&port->lock, flags);
1759 spin_unlock_irqrestore(&port->lock, flags);
1764 static void sci_shutdown(struct uart_port *port)
1766 struct sci_port *s = to_sci_port(port);
1767 unsigned long flags;
1769 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1771 spin_lock_irqsave(&port->lock, flags);
1774 spin_unlock_irqrestore(&port->lock, flags);
1780 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1785 return ((freq + 16 * bps) / (16 * bps) - 1);
1787 return ((freq + 16 * bps) / (32 * bps) - 1);
1789 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1791 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1793 return (((freq * 1000 / 32) / bps) - 1);
1796 /* Warn, but use a safe default */
1799 return ((freq + 16 * bps) / (32 * bps) - 1);
1802 static void sci_reset(struct uart_port *port)
1804 struct plat_sci_reg *reg;
1805 unsigned int status;
1808 status = serial_port_in(port, SCxSR);
1809 } while (!(status & SCxSR_TEND(port)));
1811 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1813 reg = sci_getreg(port, SCFCR);
1815 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1818 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1819 struct ktermios *old)
1821 struct sci_port *s = to_sci_port(port);
1822 struct plat_sci_reg *reg;
1823 unsigned int baud, smr_val, max_baud, cks;
1827 * earlyprintk comes here early on with port->uartclk set to zero.
1828 * the clock framework is not up and running at this point so here
1829 * we assume that 115200 is the maximum baud rate. please note that
1830 * the baud rate is not programmed during earlyprintk - it is assumed
1831 * that the previous boot loader has enabled required clocks and
1832 * setup the baud rate generator hardware for us already.
1834 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1836 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1837 if (likely(baud && port->uartclk))
1838 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1844 smr_val = serial_port_in(port, SCSMR) & 3;
1846 if ((termios->c_cflag & CSIZE) == CS7)
1848 if (termios->c_cflag & PARENB)
1850 if (termios->c_cflag & PARODD)
1852 if (termios->c_cflag & CSTOPB)
1855 uart_update_timeout(port, termios->c_cflag, baud);
1857 for (cks = 0; t >= 256 && cks <= 3; cks++)
1860 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1861 __func__, smr_val, cks, t, s->cfg->scscr);
1864 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1865 serial_port_out(port, SCBRR, t);
1866 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1868 serial_port_out(port, SCSMR, smr_val);
1870 sci_init_pins(port, termios->c_cflag);
1872 reg = sci_getreg(port, SCFCR);
1874 unsigned short ctrl = serial_port_in(port, SCFCR);
1876 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1877 if (termios->c_cflag & CRTSCTS)
1884 * As we've done a sci_reset() above, ensure we don't
1885 * interfere with the FIFOs while toggling MCE. As the
1886 * reset values could still be set, simply mask them out.
1888 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1890 serial_port_out(port, SCFCR, ctrl);
1893 serial_port_out(port, SCSCR, s->cfg->scscr);
1895 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1897 * Calculate delay for 1.5 DMA buffers: see
1898 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1899 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1900 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1901 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1902 * sizes), but it has been found out experimentally, that this is not
1903 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1904 * as a minimum seem to work perfectly.
1907 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1910 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1911 s->rx_timeout * 1000 / HZ, port->timeout);
1912 if (s->rx_timeout < msecs_to_jiffies(20))
1913 s->rx_timeout = msecs_to_jiffies(20);
1917 if ((termios->c_cflag & CREAD) != 0)
1920 sci_port_disable(s);
1923 static void sci_pm(struct uart_port *port, unsigned int state,
1924 unsigned int oldstate)
1926 struct sci_port *sci_port = to_sci_port(port);
1930 sci_port_disable(sci_port);
1933 sci_port_enable(sci_port);
1938 static const char *sci_type(struct uart_port *port)
1940 switch (port->type) {
1956 static inline unsigned long sci_port_size(struct uart_port *port)
1959 * Pick an arbitrary size that encapsulates all of the base
1960 * registers by default. This can be optimized later, or derived
1961 * from platform resource data at such a time that ports begin to
1962 * behave more erratically.
1967 static int sci_remap_port(struct uart_port *port)
1969 unsigned long size = sci_port_size(port);
1972 * Nothing to do if there's already an established membase.
1977 if (port->flags & UPF_IOREMAP) {
1978 port->membase = ioremap_nocache(port->mapbase, size);
1979 if (unlikely(!port->membase)) {
1980 dev_err(port->dev, "can't remap port#%d\n", port->line);
1985 * For the simple (and majority of) cases where we don't
1986 * need to do any remapping, just cast the cookie
1989 port->membase = (void __iomem *)port->mapbase;
1995 static void sci_release_port(struct uart_port *port)
1997 if (port->flags & UPF_IOREMAP) {
1998 iounmap(port->membase);
1999 port->membase = NULL;
2002 release_mem_region(port->mapbase, sci_port_size(port));
2005 static int sci_request_port(struct uart_port *port)
2007 unsigned long size = sci_port_size(port);
2008 struct resource *res;
2011 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2012 if (unlikely(res == NULL))
2015 ret = sci_remap_port(port);
2016 if (unlikely(ret != 0)) {
2017 release_resource(res);
2024 static void sci_config_port(struct uart_port *port, int flags)
2026 if (flags & UART_CONFIG_TYPE) {
2027 struct sci_port *sport = to_sci_port(port);
2029 port->type = sport->cfg->type;
2030 sci_request_port(port);
2034 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2036 struct sci_port *s = to_sci_port(port);
2038 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
2040 if (ser->baud_base < 2400)
2041 /* No paper tape reader for Mitch.. */
2047 static struct uart_ops sci_uart_ops = {
2048 .tx_empty = sci_tx_empty,
2049 .set_mctrl = sci_set_mctrl,
2050 .get_mctrl = sci_get_mctrl,
2051 .start_tx = sci_start_tx,
2052 .stop_tx = sci_stop_tx,
2053 .stop_rx = sci_stop_rx,
2054 .enable_ms = sci_enable_ms,
2055 .break_ctl = sci_break_ctl,
2056 .startup = sci_startup,
2057 .shutdown = sci_shutdown,
2058 .set_termios = sci_set_termios,
2061 .release_port = sci_release_port,
2062 .request_port = sci_request_port,
2063 .config_port = sci_config_port,
2064 .verify_port = sci_verify_port,
2065 #ifdef CONFIG_CONSOLE_POLL
2066 .poll_get_char = sci_poll_get_char,
2067 .poll_put_char = sci_poll_put_char,
2071 static int sci_init_single(struct platform_device *dev,
2072 struct sci_port *sci_port,
2074 struct plat_sci_port *p)
2076 struct uart_port *port = &sci_port->port;
2081 port->ops = &sci_uart_ops;
2082 port->iotype = UPIO_MEM;
2087 port->fifosize = 256;
2090 port->fifosize = 64;
2093 port->fifosize = 16;
2100 if (p->regtype == SCIx_PROBE_REGTYPE) {
2101 ret = sci_probe_regmap(p);
2107 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2108 if (IS_ERR(sci_port->iclk)) {
2109 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2110 if (IS_ERR(sci_port->iclk)) {
2111 dev_err(&dev->dev, "can't get iclk\n");
2112 return PTR_ERR(sci_port->iclk);
2117 * The function clock is optional, ignore it if we can't
2120 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2121 if (IS_ERR(sci_port->fclk))
2122 sci_port->fclk = NULL;
2124 port->dev = &dev->dev;
2126 sci_init_gpios(sci_port);
2128 pm_runtime_enable(&dev->dev);
2131 sci_port->break_timer.data = (unsigned long)sci_port;
2132 sci_port->break_timer.function = sci_break_timer;
2133 init_timer(&sci_port->break_timer);
2136 * Establish some sensible defaults for the error detection.
2139 p->error_mask = (p->type == PORT_SCI) ?
2140 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2143 * Establish sensible defaults for the overrun detection, unless
2144 * the part has explicitly disabled support for it.
2146 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2147 if (p->type == PORT_SCI)
2149 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2155 * Make the error mask inclusive of overrun detection, if
2158 p->error_mask |= (1 << p->overrun_bit);
2161 port->mapbase = p->mapbase;
2162 port->type = p->type;
2163 port->flags = p->flags;
2164 port->regshift = p->regshift;
2167 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2168 * for the multi-IRQ ports, which is where we are primarily
2169 * concerned with the shutdown path synchronization.
2171 * For the muxed case there's nothing more to do.
2173 port->irq = p->irqs[SCIx_RXI_IRQ];
2176 port->serial_in = sci_serial_in;
2177 port->serial_out = sci_serial_out;
2179 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2180 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2181 p->dma_slave_tx, p->dma_slave_rx);
2186 static void sci_cleanup_single(struct sci_port *port)
2188 sci_free_gpios(port);
2190 clk_put(port->iclk);
2191 clk_put(port->fclk);
2193 pm_runtime_disable(port->port.dev);
2196 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2197 static void serial_console_putchar(struct uart_port *port, int ch)
2199 sci_poll_put_char(port, ch);
2203 * Print a string to the serial port trying not to disturb
2204 * any possible real use of the port...
2206 static void serial_console_write(struct console *co, const char *s,
2209 struct sci_port *sci_port = &sci_ports[co->index];
2210 struct uart_port *port = &sci_port->port;
2211 unsigned short bits, ctrl;
2212 unsigned long flags;
2215 local_irq_save(flags);
2218 else if (oops_in_progress)
2219 locked = spin_trylock(&port->lock);
2221 spin_lock(&port->lock);
2223 /* first save the SCSCR then disable the interrupts */
2224 ctrl = serial_port_in(port, SCSCR);
2225 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2227 uart_console_write(port, s, count, serial_console_putchar);
2229 /* wait until fifo is empty and last bit has been transmitted */
2230 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2231 while ((serial_port_in(port, SCxSR) & bits) != bits)
2234 /* restore the SCSCR */
2235 serial_port_out(port, SCSCR, ctrl);
2238 spin_unlock(&port->lock);
2239 local_irq_restore(flags);
2242 static int serial_console_setup(struct console *co, char *options)
2244 struct sci_port *sci_port;
2245 struct uart_port *port;
2253 * Refuse to handle any bogus ports.
2255 if (co->index < 0 || co->index >= SCI_NPORTS)
2258 sci_port = &sci_ports[co->index];
2259 port = &sci_port->port;
2262 * Refuse to handle uninitialized ports.
2267 ret = sci_remap_port(port);
2268 if (unlikely(ret != 0))
2272 uart_parse_options(options, &baud, &parity, &bits, &flow);
2274 return uart_set_options(port, co, baud, parity, bits, flow);
2277 static struct console serial_console = {
2279 .device = uart_console_device,
2280 .write = serial_console_write,
2281 .setup = serial_console_setup,
2282 .flags = CON_PRINTBUFFER,
2284 .data = &sci_uart_driver,
2287 static struct console early_serial_console = {
2288 .name = "early_ttySC",
2289 .write = serial_console_write,
2290 .flags = CON_PRINTBUFFER,
2294 static char early_serial_buf[32];
2296 static int sci_probe_earlyprintk(struct platform_device *pdev)
2298 struct plat_sci_port *cfg = pdev->dev.platform_data;
2300 if (early_serial_console.data)
2303 early_serial_console.index = pdev->id;
2305 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2307 serial_console_setup(&early_serial_console, early_serial_buf);
2309 if (!strstr(early_serial_buf, "keep"))
2310 early_serial_console.flags |= CON_BOOT;
2312 register_console(&early_serial_console);
2316 #define SCI_CONSOLE (&serial_console)
2319 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2324 #define SCI_CONSOLE NULL
2326 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2328 static char banner[] __initdata =
2329 KERN_INFO "SuperH SCI(F) driver initialized\n";
2331 static struct uart_driver sci_uart_driver = {
2332 .owner = THIS_MODULE,
2333 .driver_name = "sci",
2334 .dev_name = "ttySC",
2336 .minor = SCI_MINOR_START,
2338 .cons = SCI_CONSOLE,
2341 static int sci_remove(struct platform_device *dev)
2343 struct sci_port *port = platform_get_drvdata(dev);
2345 cpufreq_unregister_notifier(&port->freq_transition,
2346 CPUFREQ_TRANSITION_NOTIFIER);
2348 uart_remove_one_port(&sci_uart_driver, &port->port);
2350 sci_cleanup_single(port);
2356 static const struct of_device_id of_sci_match[] = {
2357 { .compatible = "renesas,sci-SCI-uart",
2358 .data = (void *)PORT_SCI },
2359 { .compatible = "renesas,sci-SCIF-uart",
2360 .data = (void *)PORT_SCIF },
2361 { .compatible = "renesas,sci-IRDA-uart",
2362 .data = (void *)PORT_IRDA },
2363 { .compatible = "renesas,sci-SCIFA-uart",
2364 .data = (void *)PORT_SCIFA },
2365 { .compatible = "renesas,sci-SCIFB-uart",
2366 .data = (void *)PORT_SCIFB },
2369 MODULE_DEVICE_TABLE(of, of_sci_match);
2371 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
2374 struct plat_sci_port *p;
2375 struct device_node *np = pdev->dev.of_node;
2376 const struct of_device_id *match;
2377 struct resource *res;
2381 match = of_match_node(of_sci_match, pdev->dev.of_node);
2382 if (!match || !match->data) {
2383 dev_err(&pdev->dev, "OF match error\n");
2387 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2389 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2395 dev_err(&pdev->dev, "failed to get I/O memory\n");
2398 p->mapbase = res->start;
2400 for (i = 0; i < SCIx_NR_IRQS; i++) {
2401 irq = platform_get_irq(pdev, i);
2403 dev_err(&pdev->dev, "failed to get irq data %d\n", i);
2409 prop = of_get_property(np, "cell-index", NULL);
2411 dev_err(&pdev->dev, "required DT prop cell-index missing\n");
2414 *dev_id = be32_to_cpup(prop);
2416 prop = of_get_property(np, "renesas,scscr", NULL);
2418 dev_err(&pdev->dev, "required DT prop scscr missing\n");
2421 p->scscr = be32_to_cpup(prop);
2423 prop = of_get_property(np, "renesas,scbrr-algo-id", NULL);
2425 dev_err(&pdev->dev, "required DT prop scbrr-algo-id missing\n");
2428 val = be32_to_cpup(prop);
2429 if (val <= SCBRR_ALGO_INVALID || val >= SCBRR_NR_ALGOS) {
2430 dev_err(&pdev->dev, "DT prop scbrr-algo-id out of range\n");
2433 p->scbrr_algo_id = val;
2435 p->flags = UPF_IOREMAP;
2436 if (of_get_property(np, "renesas,autoconf", NULL))
2437 p->flags |= UPF_BOOT_AUTOCONF;
2439 prop = of_get_property(np, "renesas,regtype", NULL);
2441 val = be32_to_cpup(prop);
2442 if (val < SCIx_PROBE_REGTYPE || val >= SCIx_NR_REGTYPES) {
2443 dev_err(&pdev->dev, "DT prop regtype out of range\n");
2449 p->type = (unsigned int)match->data;
2454 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
2459 #endif /* CONFIG_OF */
2461 static int sci_probe_single(struct platform_device *dev,
2463 struct plat_sci_port *p,
2464 struct sci_port *sciport)
2469 if (unlikely(index >= SCI_NPORTS)) {
2470 dev_notice(&dev->dev, "Attempting to register port "
2471 "%d when only %d are available.\n",
2472 index+1, SCI_NPORTS);
2473 dev_notice(&dev->dev, "Consider bumping "
2474 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2478 ret = sci_init_single(dev, sciport, index, p);
2482 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2484 sci_cleanup_single(sciport);
2491 static int sci_probe(struct platform_device *dev)
2493 struct plat_sci_port *p;
2494 struct sci_port *sp;
2495 int ret, dev_id = dev->id;
2498 * If we've come here via earlyprintk initialization, head off to
2499 * the special early probe. We don't have sufficient device state
2500 * to make it beyond this yet.
2502 if (is_early_platform_device(dev))
2503 return sci_probe_earlyprintk(dev);
2505 if (dev->dev.of_node)
2506 p = sci_parse_dt(dev, &dev_id);
2508 p = dev->dev.platform_data;
2511 dev_err(&dev->dev, "no setup data supplied\n");
2515 sp = &sci_ports[dev_id];
2516 platform_set_drvdata(dev, sp);
2518 ret = sci_probe_single(dev, dev_id, p, sp);
2522 sp->freq_transition.notifier_call = sci_notifier;
2524 ret = cpufreq_register_notifier(&sp->freq_transition,
2525 CPUFREQ_TRANSITION_NOTIFIER);
2526 if (unlikely(ret < 0)) {
2527 sci_cleanup_single(sp);
2531 #ifdef CONFIG_SH_STANDARD_BIOS
2532 sh_bios_gdb_detach();
2538 static int sci_suspend(struct device *dev)
2540 struct sci_port *sport = dev_get_drvdata(dev);
2543 uart_suspend_port(&sci_uart_driver, &sport->port);
2548 static int sci_resume(struct device *dev)
2550 struct sci_port *sport = dev_get_drvdata(dev);
2553 uart_resume_port(&sci_uart_driver, &sport->port);
2558 static const struct dev_pm_ops sci_dev_pm_ops = {
2559 .suspend = sci_suspend,
2560 .resume = sci_resume,
2563 static struct platform_driver sci_driver = {
2565 .remove = sci_remove,
2568 .owner = THIS_MODULE,
2569 .pm = &sci_dev_pm_ops,
2570 .of_match_table = of_match_ptr(of_sci_match),
2574 static int __init sci_init(void)
2580 ret = uart_register_driver(&sci_uart_driver);
2581 if (likely(ret == 0)) {
2582 ret = platform_driver_register(&sci_driver);
2584 uart_unregister_driver(&sci_uart_driver);
2590 static void __exit sci_exit(void)
2592 platform_driver_unregister(&sci_driver);
2593 uart_unregister_driver(&sci_uart_driver);
2596 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2597 early_platform_init_buffer("earlyprintk", &sci_driver,
2598 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2600 module_init(sci_init);
2601 module_exit(sci_exit);
2603 MODULE_LICENSE("GPL");
2604 MODULE_ALIAS("platform:sh-sci");
2605 MODULE_AUTHOR("Paul Mundt");
2606 MODULE_DESCRIPTION("SuperH SCI(F) serial driver");