2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/sh_dma.h>
29 #include <linux/timer.h>
30 #include <linux/interrupt.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/sysrq.h>
37 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/console.h>
42 #include <linux/platform_device.h>
43 #include <linux/serial_sci.h>
44 #include <linux/notifier.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/slab.h>
54 #include <linux/gpio.h>
57 #include <asm/sh_bios.h>
63 struct uart_port port;
65 /* Platform configuration */
66 struct plat_sci_port *cfg;
69 struct timer_list break_timer;
77 char *irqstr[SCIx_NR_IRQS];
78 char *gpiostr[SCIx_NR_FNS];
80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
83 #ifdef CONFIG_SERIAL_SH_SCI_DMA
84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
98 unsigned int rx_timeout;
101 struct notifier_block freq_transition;
104 /* Function prototypes */
105 static void sci_start_tx(struct uart_port *port);
106 static void sci_stop_tx(struct uart_port *port);
107 static void sci_start_rx(struct uart_port *port);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports[SCI_NPORTS];
112 static struct uart_driver sci_uart_driver;
114 static inline struct sci_port *
115 to_sci_port(struct uart_port *uart)
117 return container_of(uart, struct sci_port, port);
120 struct plat_sci_reg {
124 /* Helper for invalidating specific entries of an inherited map. */
125 #define sci_reg_invalid { .offset = 0, .size = 0 }
127 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 * Common SCI definitions, dependent on the port's regshift
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
152 * Common definitions for legacy IrDA ports, dependent on
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
171 * Common SCIFA definitions.
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
189 * Common SCIFB definitions.
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = sci_reg_invalid,
200 [SCTFDR] = { 0x38, 16 },
201 [SCRFDR] = { 0x3c, 16 },
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
207 * Common SH-2(A) SCIF definitions for ports with FIFO data
210 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
211 [SCSMR] = { 0x00, 16 },
212 [SCBRR] = { 0x04, 8 },
213 [SCSCR] = { 0x08, 16 },
214 [SCxTDR] = { 0x0c, 8 },
215 [SCxSR] = { 0x10, 16 },
216 [SCxRDR] = { 0x14, 8 },
217 [SCFCR] = { 0x18, 16 },
218 [SCFDR] = { 0x1c, 16 },
219 [SCTFDR] = sci_reg_invalid,
220 [SCRFDR] = sci_reg_invalid,
221 [SCSPTR] = { 0x20, 16 },
222 [SCLSR] = { 0x24, 16 },
226 * Common SH-3 SCIF definitions.
228 [SCIx_SH3_SCIF_REGTYPE] = {
229 [SCSMR] = { 0x00, 8 },
230 [SCBRR] = { 0x02, 8 },
231 [SCSCR] = { 0x04, 8 },
232 [SCxTDR] = { 0x06, 8 },
233 [SCxSR] = { 0x08, 16 },
234 [SCxRDR] = { 0x0a, 8 },
235 [SCFCR] = { 0x0c, 8 },
236 [SCFDR] = { 0x0e, 16 },
237 [SCTFDR] = sci_reg_invalid,
238 [SCRFDR] = sci_reg_invalid,
239 [SCSPTR] = sci_reg_invalid,
240 [SCLSR] = sci_reg_invalid,
244 * Common SH-4(A) SCIF(B) definitions.
246 [SCIx_SH4_SCIF_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = { 0x20, 16 },
258 [SCLSR] = { 0x24, 16 },
262 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
265 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = { 0x24, 16 },
281 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
284 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x0c, 8 },
289 [SCxSR] = { 0x10, 16 },
290 [SCxRDR] = { 0x14, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
294 [SCRFDR] = { 0x20, 16 },
295 [SCSPTR] = { 0x24, 16 },
296 [SCLSR] = { 0x28, 16 },
300 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
303 [SCIx_SH7705_SCIF_REGTYPE] = {
304 [SCSMR] = { 0x00, 16 },
305 [SCBRR] = { 0x04, 8 },
306 [SCSCR] = { 0x08, 16 },
307 [SCxTDR] = { 0x20, 8 },
308 [SCxSR] = { 0x14, 16 },
309 [SCxRDR] = { 0x24, 8 },
310 [SCFCR] = { 0x18, 16 },
311 [SCFDR] = { 0x1c, 16 },
312 [SCTFDR] = sci_reg_invalid,
313 [SCRFDR] = sci_reg_invalid,
314 [SCSPTR] = sci_reg_invalid,
315 [SCLSR] = sci_reg_invalid,
319 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
322 * The "offset" here is rather misleading, in that it refers to an enum
323 * value relative to the port mapping rather than the fixed offset
324 * itself, which needs to be manually retrieved from the platform's
325 * register map for the given port.
327 static unsigned int sci_serial_in(struct uart_port *p, int offset)
329 struct plat_sci_reg *reg = sci_getreg(p, offset);
332 return ioread8(p->membase + (reg->offset << p->regshift));
333 else if (reg->size == 16)
334 return ioread16(p->membase + (reg->offset << p->regshift));
336 WARN(1, "Invalid register access\n");
341 static void sci_serial_out(struct uart_port *p, int offset, int value)
343 struct plat_sci_reg *reg = sci_getreg(p, offset);
346 iowrite8(value, p->membase + (reg->offset << p->regshift));
347 else if (reg->size == 16)
348 iowrite16(value, p->membase + (reg->offset << p->regshift));
350 WARN(1, "Invalid register access\n");
353 static int sci_probe_regmap(struct plat_sci_port *cfg)
357 cfg->regtype = SCIx_SCI_REGTYPE;
360 cfg->regtype = SCIx_IRDA_REGTYPE;
363 cfg->regtype = SCIx_SCIFA_REGTYPE;
366 cfg->regtype = SCIx_SCIFB_REGTYPE;
370 * The SH-4 is a bit of a misnomer here, although that's
371 * where this particular port layout originated. This
372 * configuration (or some slight variation thereof)
373 * remains the dominant model for all SCIFs.
375 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
378 printk(KERN_ERR "Can't probe register map for given port\n");
385 static void sci_port_enable(struct sci_port *sci_port)
387 if (!sci_port->port.dev)
390 pm_runtime_get_sync(sci_port->port.dev);
392 clk_enable(sci_port->iclk);
393 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
394 clk_enable(sci_port->fclk);
397 static void sci_port_disable(struct sci_port *sci_port)
399 if (!sci_port->port.dev)
402 clk_disable(sci_port->fclk);
403 clk_disable(sci_port->iclk);
405 pm_runtime_put_sync(sci_port->port.dev);
408 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
410 #ifdef CONFIG_CONSOLE_POLL
411 static int sci_poll_get_char(struct uart_port *port)
413 unsigned short status;
417 status = serial_port_in(port, SCxSR);
418 if (status & SCxSR_ERRORS(port)) {
419 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
425 if (!(status & SCxSR_RDxF(port)))
428 c = serial_port_in(port, SCxRDR);
431 serial_port_in(port, SCxSR);
432 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
438 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
440 unsigned short status;
443 status = serial_port_in(port, SCxSR);
444 } while (!(status & SCxSR_TDxE(port)));
446 serial_port_out(port, SCxTDR, c);
447 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
449 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
451 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
453 struct sci_port *s = to_sci_port(port);
454 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
457 * Use port-specific handler if provided.
459 if (s->cfg->ops && s->cfg->ops->init_pins) {
460 s->cfg->ops->init_pins(port, cflag);
465 * For the generic path SCSPTR is necessary. Bail out if that's
471 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
472 ((!(cflag & CRTSCTS)))) {
473 unsigned short status;
475 status = serial_port_in(port, SCSPTR);
476 status &= ~SCSPTR_CTSIO;
477 status |= SCSPTR_RTSIO;
478 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
482 static int sci_txfill(struct uart_port *port)
484 struct plat_sci_reg *reg;
486 reg = sci_getreg(port, SCTFDR);
488 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
490 reg = sci_getreg(port, SCFDR);
492 return serial_port_in(port, SCFDR) >> 8;
494 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
497 static int sci_txroom(struct uart_port *port)
499 return port->fifosize - sci_txfill(port);
502 static int sci_rxfill(struct uart_port *port)
504 struct plat_sci_reg *reg;
506 reg = sci_getreg(port, SCRFDR);
508 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
510 reg = sci_getreg(port, SCFDR);
512 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
514 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
518 * SCI helper for checking the state of the muxed port/RXD pins.
520 static inline int sci_rxd_in(struct uart_port *port)
522 struct sci_port *s = to_sci_port(port);
524 if (s->cfg->port_reg <= 0)
527 /* Cast for ARM damage */
528 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
531 /* ********************************************************************** *
532 * the interrupt related routines *
533 * ********************************************************************** */
535 static void sci_transmit_chars(struct uart_port *port)
537 struct circ_buf *xmit = &port->state->xmit;
538 unsigned int stopped = uart_tx_stopped(port);
539 unsigned short status;
543 status = serial_port_in(port, SCxSR);
544 if (!(status & SCxSR_TDxE(port))) {
545 ctrl = serial_port_in(port, SCSCR);
546 if (uart_circ_empty(xmit))
550 serial_port_out(port, SCSCR, ctrl);
554 count = sci_txroom(port);
562 } else if (!uart_circ_empty(xmit) && !stopped) {
563 c = xmit->buf[xmit->tail];
564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
569 serial_port_out(port, SCxTDR, c);
572 } while (--count > 0);
574 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
576 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
577 uart_write_wakeup(port);
578 if (uart_circ_empty(xmit)) {
581 ctrl = serial_port_in(port, SCSCR);
583 if (port->type != PORT_SCI) {
584 serial_port_in(port, SCxSR); /* Dummy read */
585 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
589 serial_port_out(port, SCSCR, ctrl);
593 /* On SH3, SCIF may read end-of-break as a space->mark char */
594 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
596 static void sci_receive_chars(struct uart_port *port)
598 struct sci_port *sci_port = to_sci_port(port);
599 struct tty_port *tport = &port->state->port;
600 struct tty_struct *tty = tport->tty;
601 int i, count, copied = 0;
602 unsigned short status;
605 status = serial_port_in(port, SCxSR);
606 if (!(status & SCxSR_RDxF(port)))
610 /* Don't copy more bytes than there is room for in the buffer */
611 count = tty_buffer_request_room(tport, sci_rxfill(port));
613 /* If for any reason we can't copy more data, we're done! */
617 if (port->type == PORT_SCI) {
618 char c = serial_port_in(port, SCxRDR);
619 if (uart_handle_sysrq_char(port, c) ||
620 sci_port->break_flag)
623 tty_insert_flip_char(tport, c, TTY_NORMAL);
625 for (i = 0; i < count; i++) {
626 char c = serial_port_in(port, SCxRDR);
628 status = serial_port_in(port, SCxSR);
629 #if defined(CONFIG_CPU_SH3)
630 /* Skip "chars" during break */
631 if (sci_port->break_flag) {
633 (status & SCxSR_FER(port))) {
638 /* Nonzero => end-of-break */
639 dev_dbg(port->dev, "debounce<%02x>\n", c);
640 sci_port->break_flag = 0;
647 #endif /* CONFIG_CPU_SH3 */
648 if (uart_handle_sysrq_char(port, c)) {
653 /* Store data and status */
654 if (status & SCxSR_FER(port)) {
656 port->icount.frame++;
657 dev_notice(port->dev, "frame error\n");
658 } else if (status & SCxSR_PER(port)) {
660 port->icount.parity++;
661 dev_notice(port->dev, "parity error\n");
665 tty_insert_flip_char(tport, c, flag);
669 serial_port_in(port, SCxSR); /* dummy read */
670 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
673 port->icount.rx += count;
677 /* Tell the rest of the system the news. New characters! */
678 tty_flip_buffer_push(tty);
680 serial_port_in(port, SCxSR); /* dummy read */
681 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
685 #define SCI_BREAK_JIFFIES (HZ/20)
688 * The sci generates interrupts during the break,
689 * 1 per millisecond or so during the break period, for 9600 baud.
690 * So dont bother disabling interrupts.
691 * But dont want more than 1 break event.
692 * Use a kernel timer to periodically poll the rx line until
693 * the break is finished.
695 static inline void sci_schedule_break_timer(struct sci_port *port)
697 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
700 /* Ensure that two consecutive samples find the break over. */
701 static void sci_break_timer(unsigned long data)
703 struct sci_port *port = (struct sci_port *)data;
705 sci_port_enable(port);
707 if (sci_rxd_in(&port->port) == 0) {
708 port->break_flag = 1;
709 sci_schedule_break_timer(port);
710 } else if (port->break_flag == 1) {
712 port->break_flag = 2;
713 sci_schedule_break_timer(port);
715 port->break_flag = 0;
717 sci_port_disable(port);
720 static int sci_handle_errors(struct uart_port *port)
723 unsigned short status = serial_port_in(port, SCxSR);
724 struct tty_port *tport = &port->state->port;
725 struct tty_struct *tty = tport->tty;
726 struct sci_port *s = to_sci_port(port);
729 * Handle overruns, if supported.
731 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
732 if (status & (1 << s->cfg->overrun_bit)) {
733 port->icount.overrun++;
736 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
739 dev_notice(port->dev, "overrun error");
743 if (status & SCxSR_FER(port)) {
744 if (sci_rxd_in(port) == 0) {
745 /* Notify of BREAK */
746 struct sci_port *sci_port = to_sci_port(port);
748 if (!sci_port->break_flag) {
751 sci_port->break_flag = 1;
752 sci_schedule_break_timer(sci_port);
754 /* Do sysrq handling. */
755 if (uart_handle_break(port))
758 dev_dbg(port->dev, "BREAK detected\n");
760 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
766 port->icount.frame++;
768 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
771 dev_notice(port->dev, "frame error\n");
775 if (status & SCxSR_PER(port)) {
777 port->icount.parity++;
779 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
782 dev_notice(port->dev, "parity error");
786 tty_flip_buffer_push(tty);
791 static int sci_handle_fifo_overrun(struct uart_port *port)
793 struct tty_port *tport = &port->state->port;
794 struct tty_struct *tty = tport->tty;
795 struct sci_port *s = to_sci_port(port);
796 struct plat_sci_reg *reg;
799 reg = sci_getreg(port, SCLSR);
803 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
804 serial_port_out(port, SCLSR, 0);
806 port->icount.overrun++;
808 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
809 tty_flip_buffer_push(tty);
811 dev_notice(port->dev, "overrun error\n");
818 static int sci_handle_breaks(struct uart_port *port)
821 unsigned short status = serial_port_in(port, SCxSR);
822 struct tty_port *tport = &port->state->port;
823 struct tty_struct *tty = tport->tty;
824 struct sci_port *s = to_sci_port(port);
826 if (uart_handle_break(port))
829 if (!s->break_flag && status & SCxSR_BRK(port)) {
830 #if defined(CONFIG_CPU_SH3)
837 /* Notify of BREAK */
838 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
841 dev_dbg(port->dev, "BREAK detected\n");
845 tty_flip_buffer_push(tty);
847 copied += sci_handle_fifo_overrun(port);
852 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
854 #ifdef CONFIG_SERIAL_SH_SCI_DMA
855 struct uart_port *port = ptr;
856 struct sci_port *s = to_sci_port(port);
859 u16 scr = serial_port_in(port, SCSCR);
860 u16 ssr = serial_port_in(port, SCxSR);
862 /* Disable future Rx interrupts */
863 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
864 disable_irq_nosync(irq);
869 serial_port_out(port, SCSCR, scr);
870 /* Clear current interrupt */
871 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
872 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
873 jiffies, s->rx_timeout);
874 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
880 /* I think sci_receive_chars has to be called irrespective
881 * of whether the I_IXOFF is set, otherwise, how is the interrupt
884 sci_receive_chars(ptr);
889 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
891 struct uart_port *port = ptr;
894 spin_lock_irqsave(&port->lock, flags);
895 sci_transmit_chars(port);
896 spin_unlock_irqrestore(&port->lock, flags);
901 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
903 struct uart_port *port = ptr;
906 if (port->type == PORT_SCI) {
907 if (sci_handle_errors(port)) {
908 /* discard character in rx buffer */
909 serial_port_in(port, SCxSR);
910 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
913 sci_handle_fifo_overrun(port);
914 sci_rx_interrupt(irq, ptr);
917 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
919 /* Kick the transmission */
920 sci_tx_interrupt(irq, ptr);
925 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
927 struct uart_port *port = ptr;
930 sci_handle_breaks(port);
931 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
936 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
939 * Not all ports (such as SCIFA) will support REIE. Rather than
940 * special-casing the port type, we check the port initialization
941 * IRQ enable mask to see whether the IRQ is desired at all. If
942 * it's unset, it's logically inferred that there's no point in
945 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
948 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
950 unsigned short ssr_status, scr_status, err_enabled;
951 struct uart_port *port = ptr;
952 struct sci_port *s = to_sci_port(port);
953 irqreturn_t ret = IRQ_NONE;
955 ssr_status = serial_port_in(port, SCxSR);
956 scr_status = serial_port_in(port, SCSCR);
957 err_enabled = scr_status & port_rx_irq_mask(port);
960 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
962 ret = sci_tx_interrupt(irq, ptr);
965 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
968 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
969 (scr_status & SCSCR_RIE))
970 ret = sci_rx_interrupt(irq, ptr);
972 /* Error Interrupt */
973 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
974 ret = sci_er_interrupt(irq, ptr);
976 /* Break Interrupt */
977 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
978 ret = sci_br_interrupt(irq, ptr);
984 * Here we define a transition notifier so that we can update all of our
985 * ports' baud rate when the peripheral clock changes.
987 static int sci_notifier(struct notifier_block *self,
988 unsigned long phase, void *p)
990 struct sci_port *sci_port;
993 sci_port = container_of(self, struct sci_port, freq_transition);
995 if ((phase == CPUFREQ_POSTCHANGE) ||
996 (phase == CPUFREQ_RESUMECHANGE)) {
997 struct uart_port *port = &sci_port->port;
999 spin_lock_irqsave(&port->lock, flags);
1000 port->uartclk = clk_get_rate(sci_port->iclk);
1001 spin_unlock_irqrestore(&port->lock, flags);
1007 static struct sci_irq_desc {
1009 irq_handler_t handler;
1010 } sci_irq_desc[] = {
1012 * Split out handlers, the default case.
1016 .handler = sci_er_interrupt,
1021 .handler = sci_rx_interrupt,
1026 .handler = sci_tx_interrupt,
1031 .handler = sci_br_interrupt,
1035 * Special muxed handler.
1039 .handler = sci_mpxed_interrupt,
1043 static int sci_request_irq(struct sci_port *port)
1045 struct uart_port *up = &port->port;
1048 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1049 struct sci_irq_desc *desc;
1052 if (SCIx_IRQ_IS_MUXED(port)) {
1056 irq = port->cfg->irqs[i];
1059 * Certain port types won't support all of the
1060 * available interrupt sources.
1066 desc = sci_irq_desc + i;
1067 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1068 dev_name(up->dev), desc->desc);
1069 if (!port->irqstr[j]) {
1070 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1075 ret = request_irq(irq, desc->handler, up->irqflags,
1076 port->irqstr[j], port);
1077 if (unlikely(ret)) {
1078 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1087 free_irq(port->cfg->irqs[i], port);
1091 kfree(port->irqstr[j]);
1096 static void sci_free_irq(struct sci_port *port)
1101 * Intentionally in reverse order so we iterate over the muxed
1104 for (i = 0; i < SCIx_NR_IRQS; i++) {
1105 unsigned int irq = port->cfg->irqs[i];
1108 * Certain port types won't support all of the available
1109 * interrupt sources.
1114 free_irq(port->cfg->irqs[i], port);
1115 kfree(port->irqstr[i]);
1117 if (SCIx_IRQ_IS_MUXED(port)) {
1118 /* If there's only one IRQ, we're done. */
1124 static const char *sci_gpio_names[SCIx_NR_FNS] = {
1125 "sck", "rxd", "txd", "cts", "rts",
1128 static const char *sci_gpio_str(unsigned int index)
1130 return sci_gpio_names[index];
1133 static void sci_init_gpios(struct sci_port *port)
1135 struct uart_port *up = &port->port;
1141 for (i = 0; i < SCIx_NR_FNS; i++) {
1145 if (!port->cfg->gpios[i])
1148 desc = sci_gpio_str(i);
1150 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1151 dev_name(up->dev), desc);
1154 * If we've failed the allocation, we can still continue
1155 * on with a NULL string.
1157 if (!port->gpiostr[i])
1158 dev_notice(up->dev, "%s string allocation failure\n",
1161 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1162 if (unlikely(ret != 0)) {
1163 dev_notice(up->dev, "failed %s gpio request\n", desc);
1166 * If we can't get the GPIO for whatever reason,
1167 * no point in keeping the verbose string around.
1169 kfree(port->gpiostr[i]);
1174 static void sci_free_gpios(struct sci_port *port)
1178 for (i = 0; i < SCIx_NR_FNS; i++)
1179 if (port->cfg->gpios[i]) {
1180 gpio_free(port->cfg->gpios[i]);
1181 kfree(port->gpiostr[i]);
1185 static unsigned int sci_tx_empty(struct uart_port *port)
1187 unsigned short status = serial_port_in(port, SCxSR);
1188 unsigned short in_tx_fifo = sci_txfill(port);
1190 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1194 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1195 * CTS/RTS is supported in hardware by at least one port and controlled
1196 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1197 * handled via the ->init_pins() op, which is a bit of a one-way street,
1198 * lacking any ability to defer pin control -- this will later be
1199 * converted over to the GPIO framework).
1201 * Other modes (such as loopback) are supported generically on certain
1202 * port types, but not others. For these it's sufficient to test for the
1203 * existence of the support register and simply ignore the port type.
1205 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1207 if (mctrl & TIOCM_LOOP) {
1208 struct plat_sci_reg *reg;
1211 * Standard loopback mode for SCFCR ports.
1213 reg = sci_getreg(port, SCFCR);
1215 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1219 static unsigned int sci_get_mctrl(struct uart_port *port)
1222 * CTS/RTS is handled in hardware when supported, while nothing
1223 * else is wired up. Keep it simple and simply assert DSR/CAR.
1225 return TIOCM_DSR | TIOCM_CAR;
1228 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1229 static void sci_dma_tx_complete(void *arg)
1231 struct sci_port *s = arg;
1232 struct uart_port *port = &s->port;
1233 struct circ_buf *xmit = &port->state->xmit;
1234 unsigned long flags;
1236 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1238 spin_lock_irqsave(&port->lock, flags);
1240 xmit->tail += sg_dma_len(&s->sg_tx);
1241 xmit->tail &= UART_XMIT_SIZE - 1;
1243 port->icount.tx += sg_dma_len(&s->sg_tx);
1245 async_tx_ack(s->desc_tx);
1248 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1249 uart_write_wakeup(port);
1251 if (!uart_circ_empty(xmit)) {
1253 schedule_work(&s->work_tx);
1255 s->cookie_tx = -EINVAL;
1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1257 u16 ctrl = serial_port_in(port, SCSCR);
1258 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1262 spin_unlock_irqrestore(&port->lock, flags);
1265 /* Locking: called with port lock held */
1266 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1268 struct uart_port *port = &s->port;
1269 struct tty_port *tport = &port->state->port;
1270 int i, active, room;
1272 room = tty_buffer_request_room(tport, count);
1274 if (s->active_rx == s->cookie_rx[0]) {
1276 } else if (s->active_rx == s->cookie_rx[1]) {
1279 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1284 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1289 for (i = 0; i < room; i++)
1290 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1293 port->icount.rx += room;
1298 static void sci_dma_rx_complete(void *arg)
1300 struct sci_port *s = arg;
1301 struct uart_port *port = &s->port;
1302 struct tty_struct *tty = port->state->port.tty;
1303 unsigned long flags;
1306 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1308 spin_lock_irqsave(&port->lock, flags);
1310 count = sci_dma_rx_push(s, s->buf_len_rx);
1312 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1314 spin_unlock_irqrestore(&port->lock, flags);
1317 tty_flip_buffer_push(tty);
1319 schedule_work(&s->work_rx);
1322 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1324 struct dma_chan *chan = s->chan_rx;
1325 struct uart_port *port = &s->port;
1328 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1329 dma_release_channel(chan);
1330 if (sg_dma_address(&s->sg_rx[0]))
1331 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1332 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1337 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1339 struct dma_chan *chan = s->chan_tx;
1340 struct uart_port *port = &s->port;
1343 s->cookie_tx = -EINVAL;
1344 dma_release_channel(chan);
1349 static void sci_submit_rx(struct sci_port *s)
1351 struct dma_chan *chan = s->chan_rx;
1354 for (i = 0; i < 2; i++) {
1355 struct scatterlist *sg = &s->sg_rx[i];
1356 struct dma_async_tx_descriptor *desc;
1358 desc = dmaengine_prep_slave_sg(chan,
1359 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1362 s->desc_rx[i] = desc;
1363 desc->callback = sci_dma_rx_complete;
1364 desc->callback_param = s;
1365 s->cookie_rx[i] = desc->tx_submit(desc);
1368 if (!desc || s->cookie_rx[i] < 0) {
1370 async_tx_ack(s->desc_rx[0]);
1371 s->cookie_rx[0] = -EINVAL;
1375 s->cookie_rx[i] = -EINVAL;
1377 dev_warn(s->port.dev,
1378 "failed to re-start DMA, using PIO\n");
1379 sci_rx_dma_release(s, true);
1382 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1383 s->cookie_rx[i], i);
1386 s->active_rx = s->cookie_rx[0];
1388 dma_async_issue_pending(chan);
1391 static void work_fn_rx(struct work_struct *work)
1393 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1394 struct uart_port *port = &s->port;
1395 struct dma_async_tx_descriptor *desc;
1398 if (s->active_rx == s->cookie_rx[0]) {
1400 } else if (s->active_rx == s->cookie_rx[1]) {
1403 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1406 desc = s->desc_rx[new];
1408 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1410 /* Handle incomplete DMA receive */
1411 struct tty_struct *tty = port->state->port.tty;
1412 struct dma_chan *chan = s->chan_rx;
1413 struct shdma_desc *sh_desc = container_of(desc,
1414 struct shdma_desc, async_tx);
1415 unsigned long flags;
1418 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1419 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1420 sh_desc->partial, sh_desc->cookie);
1422 spin_lock_irqsave(&port->lock, flags);
1423 count = sci_dma_rx_push(s, sh_desc->partial);
1424 spin_unlock_irqrestore(&port->lock, flags);
1427 tty_flip_buffer_push(tty);
1434 s->cookie_rx[new] = desc->tx_submit(desc);
1435 if (s->cookie_rx[new] < 0) {
1436 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1437 sci_rx_dma_release(s, true);
1441 s->active_rx = s->cookie_rx[!new];
1443 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1444 s->cookie_rx[new], new, s->active_rx);
1447 static void work_fn_tx(struct work_struct *work)
1449 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1450 struct dma_async_tx_descriptor *desc;
1451 struct dma_chan *chan = s->chan_tx;
1452 struct uart_port *port = &s->port;
1453 struct circ_buf *xmit = &port->state->xmit;
1454 struct scatterlist *sg = &s->sg_tx;
1458 * Port xmit buffer is already mapped, and it is one page... Just adjust
1459 * offsets and lengths. Since it is a circular buffer, we have to
1460 * transmit till the end, and then the rest. Take the port lock to get a
1461 * consistent xmit buffer state.
1463 spin_lock_irq(&port->lock);
1464 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1465 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1467 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1468 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1469 spin_unlock_irq(&port->lock);
1471 BUG_ON(!sg_dma_len(sg));
1473 desc = dmaengine_prep_slave_sg(chan,
1474 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1475 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1478 sci_tx_dma_release(s, true);
1482 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1484 spin_lock_irq(&port->lock);
1486 desc->callback = sci_dma_tx_complete;
1487 desc->callback_param = s;
1488 spin_unlock_irq(&port->lock);
1489 s->cookie_tx = desc->tx_submit(desc);
1490 if (s->cookie_tx < 0) {
1491 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1493 sci_tx_dma_release(s, true);
1497 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1498 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1500 dma_async_issue_pending(chan);
1504 static void sci_start_tx(struct uart_port *port)
1506 struct sci_port *s = to_sci_port(port);
1507 unsigned short ctrl;
1509 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1510 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1511 u16 new, scr = serial_port_in(port, SCSCR);
1515 new = scr & ~0x8000;
1517 serial_port_out(port, SCSCR, new);
1520 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1523 schedule_work(&s->work_tx);
1527 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1528 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1529 ctrl = serial_port_in(port, SCSCR);
1530 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1534 static void sci_stop_tx(struct uart_port *port)
1536 unsigned short ctrl;
1538 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1539 ctrl = serial_port_in(port, SCSCR);
1541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1546 serial_port_out(port, SCSCR, ctrl);
1549 static void sci_start_rx(struct uart_port *port)
1551 unsigned short ctrl;
1553 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1558 serial_port_out(port, SCSCR, ctrl);
1561 static void sci_stop_rx(struct uart_port *port)
1563 unsigned short ctrl;
1565 ctrl = serial_port_in(port, SCSCR);
1567 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1570 ctrl &= ~port_rx_irq_mask(port);
1572 serial_port_out(port, SCSCR, ctrl);
1575 static void sci_enable_ms(struct uart_port *port)
1578 * Not supported by hardware, always a nop.
1582 static void sci_break_ctl(struct uart_port *port, int break_state)
1584 struct sci_port *s = to_sci_port(port);
1585 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1586 unsigned short scscr, scsptr;
1588 /* check wheter the port has SCSPTR */
1591 * Not supported by hardware. Most parts couple break and rx
1592 * interrupts together, with break detection always enabled.
1597 scsptr = serial_port_in(port, SCSPTR);
1598 scscr = serial_port_in(port, SCSCR);
1600 if (break_state == -1) {
1601 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1604 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1608 serial_port_out(port, SCSPTR, scsptr);
1609 serial_port_out(port, SCSCR, scscr);
1612 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1613 static bool filter(struct dma_chan *chan, void *slave)
1615 struct sh_dmae_slave *param = slave;
1617 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1618 param->shdma_slave.slave_id);
1620 chan->private = ¶m->shdma_slave;
1624 static void rx_timer_fn(unsigned long arg)
1626 struct sci_port *s = (struct sci_port *)arg;
1627 struct uart_port *port = &s->port;
1628 u16 scr = serial_port_in(port, SCSCR);
1630 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1632 enable_irq(s->cfg->irqs[1]);
1634 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1635 dev_dbg(port->dev, "DMA Rx timed out\n");
1636 schedule_work(&s->work_rx);
1639 static void sci_request_dma(struct uart_port *port)
1641 struct sci_port *s = to_sci_port(port);
1642 struct sh_dmae_slave *param;
1643 struct dma_chan *chan;
1644 dma_cap_mask_t mask;
1647 dev_dbg(port->dev, "%s: port %d\n", __func__,
1650 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1654 dma_cap_set(DMA_SLAVE, mask);
1656 param = &s->param_tx;
1658 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1659 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1661 s->cookie_tx = -EINVAL;
1662 chan = dma_request_channel(mask, filter, param);
1663 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1666 sg_init_table(&s->sg_tx, 1);
1667 /* UART circular tx buffer is an aligned page. */
1668 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1669 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1670 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1671 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1673 sci_tx_dma_release(s, false);
1675 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1676 sg_dma_len(&s->sg_tx),
1677 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1679 s->sg_len_tx = nent;
1681 INIT_WORK(&s->work_tx, work_fn_tx);
1684 param = &s->param_rx;
1686 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1687 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1689 chan = dma_request_channel(mask, filter, param);
1690 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1698 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1699 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1700 &dma[0], GFP_KERNEL);
1704 "failed to allocate dma buffer, using PIO\n");
1705 sci_rx_dma_release(s, true);
1709 buf[1] = buf[0] + s->buf_len_rx;
1710 dma[1] = dma[0] + s->buf_len_rx;
1712 for (i = 0; i < 2; i++) {
1713 struct scatterlist *sg = &s->sg_rx[i];
1715 sg_init_table(sg, 1);
1716 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1717 (int)buf[i] & ~PAGE_MASK);
1718 sg_dma_address(sg) = dma[i];
1721 INIT_WORK(&s->work_rx, work_fn_rx);
1722 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1728 static void sci_free_dma(struct uart_port *port)
1730 struct sci_port *s = to_sci_port(port);
1733 sci_tx_dma_release(s, false);
1735 sci_rx_dma_release(s, false);
1738 static inline void sci_request_dma(struct uart_port *port)
1742 static inline void sci_free_dma(struct uart_port *port)
1747 static int sci_startup(struct uart_port *port)
1749 struct sci_port *s = to_sci_port(port);
1750 unsigned long flags;
1753 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1755 ret = sci_request_irq(s);
1756 if (unlikely(ret < 0))
1759 sci_request_dma(port);
1761 spin_lock_irqsave(&port->lock, flags);
1764 spin_unlock_irqrestore(&port->lock, flags);
1769 static void sci_shutdown(struct uart_port *port)
1771 struct sci_port *s = to_sci_port(port);
1772 unsigned long flags;
1774 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1776 spin_lock_irqsave(&port->lock, flags);
1779 spin_unlock_irqrestore(&port->lock, flags);
1785 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1790 return ((freq + 16 * bps) / (16 * bps) - 1);
1792 return ((freq + 16 * bps) / (32 * bps) - 1);
1794 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1796 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1798 return (((freq * 1000 / 32) / bps) - 1);
1801 /* Warn, but use a safe default */
1804 return ((freq + 16 * bps) / (32 * bps) - 1);
1807 static void sci_reset(struct uart_port *port)
1809 struct plat_sci_reg *reg;
1810 unsigned int status;
1813 status = serial_port_in(port, SCxSR);
1814 } while (!(status & SCxSR_TEND(port)));
1816 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1818 reg = sci_getreg(port, SCFCR);
1820 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1823 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1824 struct ktermios *old)
1826 struct sci_port *s = to_sci_port(port);
1827 struct plat_sci_reg *reg;
1828 unsigned int baud, smr_val, max_baud, cks;
1832 * earlyprintk comes here early on with port->uartclk set to zero.
1833 * the clock framework is not up and running at this point so here
1834 * we assume that 115200 is the maximum baud rate. please note that
1835 * the baud rate is not programmed during earlyprintk - it is assumed
1836 * that the previous boot loader has enabled required clocks and
1837 * setup the baud rate generator hardware for us already.
1839 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1841 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1842 if (likely(baud && port->uartclk))
1843 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1849 smr_val = serial_port_in(port, SCSMR) & 3;
1851 if ((termios->c_cflag & CSIZE) == CS7)
1853 if (termios->c_cflag & PARENB)
1855 if (termios->c_cflag & PARODD)
1857 if (termios->c_cflag & CSTOPB)
1860 uart_update_timeout(port, termios->c_cflag, baud);
1862 for (cks = 0; t >= 256 && cks <= 3; cks++)
1865 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1866 __func__, smr_val, cks, t, s->cfg->scscr);
1869 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1870 serial_port_out(port, SCBRR, t);
1871 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1873 serial_port_out(port, SCSMR, smr_val);
1875 sci_init_pins(port, termios->c_cflag);
1877 reg = sci_getreg(port, SCFCR);
1879 unsigned short ctrl = serial_port_in(port, SCFCR);
1881 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1882 if (termios->c_cflag & CRTSCTS)
1889 * As we've done a sci_reset() above, ensure we don't
1890 * interfere with the FIFOs while toggling MCE. As the
1891 * reset values could still be set, simply mask them out.
1893 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1895 serial_port_out(port, SCFCR, ctrl);
1898 serial_port_out(port, SCSCR, s->cfg->scscr);
1900 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1902 * Calculate delay for 1.5 DMA buffers: see
1903 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1904 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1905 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1906 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1907 * sizes), but it has been found out experimentally, that this is not
1908 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1909 * as a minimum seem to work perfectly.
1912 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1915 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1916 s->rx_timeout * 1000 / HZ, port->timeout);
1917 if (s->rx_timeout < msecs_to_jiffies(20))
1918 s->rx_timeout = msecs_to_jiffies(20);
1922 if ((termios->c_cflag & CREAD) != 0)
1925 sci_port_disable(s);
1928 static void sci_pm(struct uart_port *port, unsigned int state,
1929 unsigned int oldstate)
1931 struct sci_port *sci_port = to_sci_port(port);
1935 sci_port_disable(sci_port);
1938 sci_port_enable(sci_port);
1943 static const char *sci_type(struct uart_port *port)
1945 switch (port->type) {
1961 static inline unsigned long sci_port_size(struct uart_port *port)
1964 * Pick an arbitrary size that encapsulates all of the base
1965 * registers by default. This can be optimized later, or derived
1966 * from platform resource data at such a time that ports begin to
1967 * behave more erratically.
1972 static int sci_remap_port(struct uart_port *port)
1974 unsigned long size = sci_port_size(port);
1977 * Nothing to do if there's already an established membase.
1982 if (port->flags & UPF_IOREMAP) {
1983 port->membase = ioremap_nocache(port->mapbase, size);
1984 if (unlikely(!port->membase)) {
1985 dev_err(port->dev, "can't remap port#%d\n", port->line);
1990 * For the simple (and majority of) cases where we don't
1991 * need to do any remapping, just cast the cookie
1994 port->membase = (void __iomem *)port->mapbase;
2000 static void sci_release_port(struct uart_port *port)
2002 if (port->flags & UPF_IOREMAP) {
2003 iounmap(port->membase);
2004 port->membase = NULL;
2007 release_mem_region(port->mapbase, sci_port_size(port));
2010 static int sci_request_port(struct uart_port *port)
2012 unsigned long size = sci_port_size(port);
2013 struct resource *res;
2016 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2017 if (unlikely(res == NULL))
2020 ret = sci_remap_port(port);
2021 if (unlikely(ret != 0)) {
2022 release_resource(res);
2029 static void sci_config_port(struct uart_port *port, int flags)
2031 if (flags & UART_CONFIG_TYPE) {
2032 struct sci_port *sport = to_sci_port(port);
2034 port->type = sport->cfg->type;
2035 sci_request_port(port);
2039 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2041 struct sci_port *s = to_sci_port(port);
2043 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
2045 if (ser->baud_base < 2400)
2046 /* No paper tape reader for Mitch.. */
2052 static struct uart_ops sci_uart_ops = {
2053 .tx_empty = sci_tx_empty,
2054 .set_mctrl = sci_set_mctrl,
2055 .get_mctrl = sci_get_mctrl,
2056 .start_tx = sci_start_tx,
2057 .stop_tx = sci_stop_tx,
2058 .stop_rx = sci_stop_rx,
2059 .enable_ms = sci_enable_ms,
2060 .break_ctl = sci_break_ctl,
2061 .startup = sci_startup,
2062 .shutdown = sci_shutdown,
2063 .set_termios = sci_set_termios,
2066 .release_port = sci_release_port,
2067 .request_port = sci_request_port,
2068 .config_port = sci_config_port,
2069 .verify_port = sci_verify_port,
2070 #ifdef CONFIG_CONSOLE_POLL
2071 .poll_get_char = sci_poll_get_char,
2072 .poll_put_char = sci_poll_put_char,
2076 static int sci_init_single(struct platform_device *dev,
2077 struct sci_port *sci_port,
2079 struct plat_sci_port *p)
2081 struct uart_port *port = &sci_port->port;
2086 port->ops = &sci_uart_ops;
2087 port->iotype = UPIO_MEM;
2092 port->fifosize = 256;
2095 port->fifosize = 64;
2098 port->fifosize = 16;
2105 if (p->regtype == SCIx_PROBE_REGTYPE) {
2106 ret = sci_probe_regmap(p);
2112 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2113 if (IS_ERR(sci_port->iclk)) {
2114 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2115 if (IS_ERR(sci_port->iclk)) {
2116 dev_err(&dev->dev, "can't get iclk\n");
2117 return PTR_ERR(sci_port->iclk);
2122 * The function clock is optional, ignore it if we can't
2125 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2126 if (IS_ERR(sci_port->fclk))
2127 sci_port->fclk = NULL;
2129 port->dev = &dev->dev;
2131 sci_init_gpios(sci_port);
2133 pm_runtime_enable(&dev->dev);
2136 sci_port->break_timer.data = (unsigned long)sci_port;
2137 sci_port->break_timer.function = sci_break_timer;
2138 init_timer(&sci_port->break_timer);
2141 * Establish some sensible defaults for the error detection.
2144 p->error_mask = (p->type == PORT_SCI) ?
2145 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2148 * Establish sensible defaults for the overrun detection, unless
2149 * the part has explicitly disabled support for it.
2151 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2152 if (p->type == PORT_SCI)
2154 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2160 * Make the error mask inclusive of overrun detection, if
2163 p->error_mask |= (1 << p->overrun_bit);
2166 port->mapbase = p->mapbase;
2167 port->type = p->type;
2168 port->flags = p->flags;
2169 port->regshift = p->regshift;
2172 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2173 * for the multi-IRQ ports, which is where we are primarily
2174 * concerned with the shutdown path synchronization.
2176 * For the muxed case there's nothing more to do.
2178 port->irq = p->irqs[SCIx_RXI_IRQ];
2181 port->serial_in = sci_serial_in;
2182 port->serial_out = sci_serial_out;
2184 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2185 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2186 p->dma_slave_tx, p->dma_slave_rx);
2191 static void sci_cleanup_single(struct sci_port *port)
2193 sci_free_gpios(port);
2195 clk_put(port->iclk);
2196 clk_put(port->fclk);
2198 pm_runtime_disable(port->port.dev);
2201 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2202 static void serial_console_putchar(struct uart_port *port, int ch)
2204 sci_poll_put_char(port, ch);
2208 * Print a string to the serial port trying not to disturb
2209 * any possible real use of the port...
2211 static void serial_console_write(struct console *co, const char *s,
2214 struct sci_port *sci_port = &sci_ports[co->index];
2215 struct uart_port *port = &sci_port->port;
2216 unsigned short bits, ctrl;
2217 unsigned long flags;
2220 local_irq_save(flags);
2223 else if (oops_in_progress)
2224 locked = spin_trylock(&port->lock);
2226 spin_lock(&port->lock);
2228 /* first save the SCSCR then disable the interrupts */
2229 ctrl = serial_port_in(port, SCSCR);
2230 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2232 uart_console_write(port, s, count, serial_console_putchar);
2234 /* wait until fifo is empty and last bit has been transmitted */
2235 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2236 while ((serial_port_in(port, SCxSR) & bits) != bits)
2239 /* restore the SCSCR */
2240 serial_port_out(port, SCSCR, ctrl);
2243 spin_unlock(&port->lock);
2244 local_irq_restore(flags);
2247 static int serial_console_setup(struct console *co, char *options)
2249 struct sci_port *sci_port;
2250 struct uart_port *port;
2258 * Refuse to handle any bogus ports.
2260 if (co->index < 0 || co->index >= SCI_NPORTS)
2263 sci_port = &sci_ports[co->index];
2264 port = &sci_port->port;
2267 * Refuse to handle uninitialized ports.
2272 ret = sci_remap_port(port);
2273 if (unlikely(ret != 0))
2277 uart_parse_options(options, &baud, &parity, &bits, &flow);
2279 return uart_set_options(port, co, baud, parity, bits, flow);
2282 static struct console serial_console = {
2284 .device = uart_console_device,
2285 .write = serial_console_write,
2286 .setup = serial_console_setup,
2287 .flags = CON_PRINTBUFFER,
2289 .data = &sci_uart_driver,
2292 static struct console early_serial_console = {
2293 .name = "early_ttySC",
2294 .write = serial_console_write,
2295 .flags = CON_PRINTBUFFER,
2299 static char early_serial_buf[32];
2301 static int sci_probe_earlyprintk(struct platform_device *pdev)
2303 struct plat_sci_port *cfg = pdev->dev.platform_data;
2305 if (early_serial_console.data)
2308 early_serial_console.index = pdev->id;
2310 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2312 serial_console_setup(&early_serial_console, early_serial_buf);
2314 if (!strstr(early_serial_buf, "keep"))
2315 early_serial_console.flags |= CON_BOOT;
2317 register_console(&early_serial_console);
2321 #define SCI_CONSOLE (&serial_console)
2324 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2329 #define SCI_CONSOLE NULL
2331 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2333 static char banner[] __initdata =
2334 KERN_INFO "SuperH SCI(F) driver initialized\n";
2336 static struct uart_driver sci_uart_driver = {
2337 .owner = THIS_MODULE,
2338 .driver_name = "sci",
2339 .dev_name = "ttySC",
2341 .minor = SCI_MINOR_START,
2343 .cons = SCI_CONSOLE,
2346 static int sci_remove(struct platform_device *dev)
2348 struct sci_port *port = platform_get_drvdata(dev);
2350 cpufreq_unregister_notifier(&port->freq_transition,
2351 CPUFREQ_TRANSITION_NOTIFIER);
2353 uart_remove_one_port(&sci_uart_driver, &port->port);
2355 sci_cleanup_single(port);
2360 static int sci_probe_single(struct platform_device *dev,
2362 struct plat_sci_port *p,
2363 struct sci_port *sciport)
2368 if (unlikely(index >= SCI_NPORTS)) {
2369 dev_notice(&dev->dev, "Attempting to register port "
2370 "%d when only %d are available.\n",
2371 index+1, SCI_NPORTS);
2372 dev_notice(&dev->dev, "Consider bumping "
2373 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2377 ret = sci_init_single(dev, sciport, index, p);
2381 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2383 sci_cleanup_single(sciport);
2390 static int sci_probe(struct platform_device *dev)
2392 struct plat_sci_port *p = dev->dev.platform_data;
2393 struct sci_port *sp = &sci_ports[dev->id];
2397 * If we've come here via earlyprintk initialization, head off to
2398 * the special early probe. We don't have sufficient device state
2399 * to make it beyond this yet.
2401 if (is_early_platform_device(dev))
2402 return sci_probe_earlyprintk(dev);
2404 platform_set_drvdata(dev, sp);
2406 ret = sci_probe_single(dev, dev->id, p, sp);
2410 sp->freq_transition.notifier_call = sci_notifier;
2412 ret = cpufreq_register_notifier(&sp->freq_transition,
2413 CPUFREQ_TRANSITION_NOTIFIER);
2414 if (unlikely(ret < 0)) {
2415 sci_cleanup_single(sp);
2419 #ifdef CONFIG_SH_STANDARD_BIOS
2420 sh_bios_gdb_detach();
2426 static int sci_suspend(struct device *dev)
2428 struct sci_port *sport = dev_get_drvdata(dev);
2431 uart_suspend_port(&sci_uart_driver, &sport->port);
2436 static int sci_resume(struct device *dev)
2438 struct sci_port *sport = dev_get_drvdata(dev);
2441 uart_resume_port(&sci_uart_driver, &sport->port);
2446 static const struct dev_pm_ops sci_dev_pm_ops = {
2447 .suspend = sci_suspend,
2448 .resume = sci_resume,
2451 static struct platform_driver sci_driver = {
2453 .remove = sci_remove,
2456 .owner = THIS_MODULE,
2457 .pm = &sci_dev_pm_ops,
2461 static int __init sci_init(void)
2467 ret = uart_register_driver(&sci_uart_driver);
2468 if (likely(ret == 0)) {
2469 ret = platform_driver_register(&sci_driver);
2471 uart_unregister_driver(&sci_uart_driver);
2477 static void __exit sci_exit(void)
2479 platform_driver_unregister(&sci_driver);
2480 uart_unregister_driver(&sci_uart_driver);
2483 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2484 early_platform_init_buffer("earlyprintk", &sci_driver,
2485 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2487 module_init(sci_init);
2488 module_exit(sci_exit);
2490 MODULE_LICENSE("GPL");
2491 MODULE_ALIAS("platform:sh-sci");
2492 MODULE_AUTHOR("Paul Mundt");
2493 MODULE_DESCRIPTION("SuperH SCI(F) serial driver");