2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/sh_dma.h>
29 #include <linux/timer.h>
30 #include <linux/interrupt.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/sysrq.h>
37 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/console.h>
42 #include <linux/platform_device.h>
43 #include <linux/serial_sci.h>
44 #include <linux/notifier.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/slab.h>
54 #include <linux/gpio.h>
58 #include <asm/sh_bios.h>
64 struct uart_port port;
66 /* Platform configuration */
67 struct plat_sci_port *cfg;
70 struct timer_list break_timer;
78 char *irqstr[SCIx_NR_IRQS];
79 char *gpiostr[SCIx_NR_FNS];
81 struct dma_chan *chan_tx;
82 struct dma_chan *chan_rx;
84 #ifdef CONFIG_SERIAL_SH_SCI_DMA
85 struct dma_async_tx_descriptor *desc_tx;
86 struct dma_async_tx_descriptor *desc_rx[2];
87 dma_cookie_t cookie_tx;
88 dma_cookie_t cookie_rx[2];
89 dma_cookie_t active_rx;
90 struct scatterlist sg_tx;
91 unsigned int sg_len_tx;
92 struct scatterlist sg_rx[2];
94 struct sh_dmae_slave param_tx;
95 struct sh_dmae_slave param_rx;
96 struct work_struct work_tx;
97 struct work_struct work_rx;
98 struct timer_list rx_timer;
99 unsigned int rx_timeout;
102 struct notifier_block freq_transition;
105 /* Function prototypes */
106 static void sci_start_tx(struct uart_port *port);
107 static void sci_stop_tx(struct uart_port *port);
108 static void sci_start_rx(struct uart_port *port);
110 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
112 static struct sci_port sci_ports[SCI_NPORTS];
113 static struct uart_driver sci_uart_driver;
115 static inline struct sci_port *
116 to_sci_port(struct uart_port *uart)
118 return container_of(uart, struct sci_port, port);
121 struct plat_sci_reg {
125 /* Helper for invalidating specific entries of an inherited map. */
126 #define sci_reg_invalid { .offset = 0, .size = 0 }
128 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
129 [SCIx_PROBE_REGTYPE] = {
130 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
134 * Common SCI definitions, dependent on the port's regshift
137 [SCIx_SCI_REGTYPE] = {
138 [SCSMR] = { 0x00, 8 },
139 [SCBRR] = { 0x01, 8 },
140 [SCSCR] = { 0x02, 8 },
141 [SCxTDR] = { 0x03, 8 },
142 [SCxSR] = { 0x04, 8 },
143 [SCxRDR] = { 0x05, 8 },
144 [SCFCR] = sci_reg_invalid,
145 [SCFDR] = sci_reg_invalid,
146 [SCTFDR] = sci_reg_invalid,
147 [SCRFDR] = sci_reg_invalid,
148 [SCSPTR] = sci_reg_invalid,
149 [SCLSR] = sci_reg_invalid,
150 [HSSRR] = sci_reg_invalid,
154 * Common definitions for legacy IrDA ports, dependent on
157 [SCIx_IRDA_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = { 0x06, 8 },
165 [SCFDR] = { 0x07, 16 },
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
170 [HSSRR] = sci_reg_invalid,
174 * Common SCIFA definitions.
176 [SCIx_SCIFA_REGTYPE] = {
177 [SCSMR] = { 0x00, 16 },
178 [SCBRR] = { 0x04, 8 },
179 [SCSCR] = { 0x08, 16 },
180 [SCxTDR] = { 0x20, 8 },
181 [SCxSR] = { 0x14, 16 },
182 [SCxRDR] = { 0x24, 8 },
183 [SCFCR] = { 0x18, 16 },
184 [SCFDR] = { 0x1c, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
189 [HSSRR] = sci_reg_invalid,
193 * Common SCIFB definitions.
195 [SCIx_SCIFB_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x40, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x60, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = sci_reg_invalid,
204 [SCTFDR] = { 0x38, 16 },
205 [SCRFDR] = { 0x3c, 16 },
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
212 * Common SH-2(A) SCIF definitions for ports with FIFO data
215 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x0c, 8 },
220 [SCxSR] = { 0x10, 16 },
221 [SCxRDR] = { 0x14, 8 },
222 [SCFCR] = { 0x18, 16 },
223 [SCFDR] = { 0x1c, 16 },
224 [SCTFDR] = sci_reg_invalid,
225 [SCRFDR] = sci_reg_invalid,
226 [SCSPTR] = { 0x20, 16 },
227 [SCLSR] = { 0x24, 16 },
228 [HSSRR] = sci_reg_invalid,
232 * Common SH-3 SCIF definitions.
234 [SCIx_SH3_SCIF_REGTYPE] = {
235 [SCSMR] = { 0x00, 8 },
236 [SCBRR] = { 0x02, 8 },
237 [SCSCR] = { 0x04, 8 },
238 [SCxTDR] = { 0x06, 8 },
239 [SCxSR] = { 0x08, 16 },
240 [SCxRDR] = { 0x0a, 8 },
241 [SCFCR] = { 0x0c, 8 },
242 [SCFDR] = { 0x0e, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = sci_reg_invalid,
246 [SCLSR] = sci_reg_invalid,
247 [HSSRR] = sci_reg_invalid,
251 * Common SH-4(A) SCIF(B) definitions.
253 [SCIx_SH4_SCIF_REGTYPE] = {
254 [SCSMR] = { 0x00, 16 },
255 [SCBRR] = { 0x04, 8 },
256 [SCSCR] = { 0x08, 16 },
257 [SCxTDR] = { 0x0c, 8 },
258 [SCxSR] = { 0x10, 16 },
259 [SCxRDR] = { 0x14, 8 },
260 [SCFCR] = { 0x18, 16 },
261 [SCFDR] = { 0x1c, 16 },
262 [SCTFDR] = sci_reg_invalid,
263 [SCRFDR] = sci_reg_invalid,
264 [SCSPTR] = { 0x20, 16 },
265 [SCLSR] = { 0x24, 16 },
266 [HSSRR] = sci_reg_invalid,
270 * Common HSCIF definitions.
272 [SCIx_HSCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 [HSSRR] = { 0x40, 16 },
289 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
292 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = sci_reg_invalid,
304 [SCLSR] = { 0x24, 16 },
305 [HSSRR] = sci_reg_invalid,
309 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
312 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
322 [SCRFDR] = { 0x20, 16 },
323 [SCSPTR] = { 0x24, 16 },
324 [SCLSR] = { 0x28, 16 },
325 [HSSRR] = sci_reg_invalid,
329 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
332 [SCIx_SH7705_SCIF_REGTYPE] = {
333 [SCSMR] = { 0x00, 16 },
334 [SCBRR] = { 0x04, 8 },
335 [SCSCR] = { 0x08, 16 },
336 [SCxTDR] = { 0x20, 8 },
337 [SCxSR] = { 0x14, 16 },
338 [SCxRDR] = { 0x24, 8 },
339 [SCFCR] = { 0x18, 16 },
340 [SCFDR] = { 0x1c, 16 },
341 [SCTFDR] = sci_reg_invalid,
342 [SCRFDR] = sci_reg_invalid,
343 [SCSPTR] = sci_reg_invalid,
344 [SCLSR] = sci_reg_invalid,
345 [HSSRR] = sci_reg_invalid,
349 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
352 * The "offset" here is rather misleading, in that it refers to an enum
353 * value relative to the port mapping rather than the fixed offset
354 * itself, which needs to be manually retrieved from the platform's
355 * register map for the given port.
357 static unsigned int sci_serial_in(struct uart_port *p, int offset)
359 struct plat_sci_reg *reg = sci_getreg(p, offset);
362 return ioread8(p->membase + (reg->offset << p->regshift));
363 else if (reg->size == 16)
364 return ioread16(p->membase + (reg->offset << p->regshift));
366 WARN(1, "Invalid register access\n");
371 static void sci_serial_out(struct uart_port *p, int offset, int value)
373 struct plat_sci_reg *reg = sci_getreg(p, offset);
376 iowrite8(value, p->membase + (reg->offset << p->regshift));
377 else if (reg->size == 16)
378 iowrite16(value, p->membase + (reg->offset << p->regshift));
380 WARN(1, "Invalid register access\n");
383 static int sci_probe_regmap(struct plat_sci_port *cfg)
387 cfg->regtype = SCIx_SCI_REGTYPE;
390 cfg->regtype = SCIx_IRDA_REGTYPE;
393 cfg->regtype = SCIx_SCIFA_REGTYPE;
396 cfg->regtype = SCIx_SCIFB_REGTYPE;
400 * The SH-4 is a bit of a misnomer here, although that's
401 * where this particular port layout originated. This
402 * configuration (or some slight variation thereof)
403 * remains the dominant model for all SCIFs.
405 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
408 cfg->regtype = SCIx_HSCIF_REGTYPE;
411 printk(KERN_ERR "Can't probe register map for given port\n");
418 static void sci_port_enable(struct sci_port *sci_port)
420 if (!sci_port->port.dev)
423 pm_runtime_get_sync(sci_port->port.dev);
425 clk_enable(sci_port->iclk);
426 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
427 clk_enable(sci_port->fclk);
430 static void sci_port_disable(struct sci_port *sci_port)
432 if (!sci_port->port.dev)
435 clk_disable(sci_port->fclk);
436 clk_disable(sci_port->iclk);
438 pm_runtime_put_sync(sci_port->port.dev);
441 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
443 #ifdef CONFIG_CONSOLE_POLL
444 static int sci_poll_get_char(struct uart_port *port)
446 unsigned short status;
450 status = serial_port_in(port, SCxSR);
451 if (status & SCxSR_ERRORS(port)) {
452 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
458 if (!(status & SCxSR_RDxF(port)))
461 c = serial_port_in(port, SCxRDR);
464 serial_port_in(port, SCxSR);
465 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
471 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
473 unsigned short status;
476 status = serial_port_in(port, SCxSR);
477 } while (!(status & SCxSR_TDxE(port)));
479 serial_port_out(port, SCxTDR, c);
480 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
482 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
484 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
486 struct sci_port *s = to_sci_port(port);
487 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
490 * Use port-specific handler if provided.
492 if (s->cfg->ops && s->cfg->ops->init_pins) {
493 s->cfg->ops->init_pins(port, cflag);
498 * For the generic path SCSPTR is necessary. Bail out if that's
504 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
505 ((!(cflag & CRTSCTS)))) {
506 unsigned short status;
508 status = serial_port_in(port, SCSPTR);
509 status &= ~SCSPTR_CTSIO;
510 status |= SCSPTR_RTSIO;
511 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
515 static int sci_txfill(struct uart_port *port)
517 struct plat_sci_reg *reg;
519 reg = sci_getreg(port, SCTFDR);
521 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
523 reg = sci_getreg(port, SCFDR);
525 return serial_port_in(port, SCFDR) >> 8;
527 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
530 static int sci_txroom(struct uart_port *port)
532 return port->fifosize - sci_txfill(port);
535 static int sci_rxfill(struct uart_port *port)
537 struct plat_sci_reg *reg;
539 reg = sci_getreg(port, SCRFDR);
541 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
543 reg = sci_getreg(port, SCFDR);
545 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
547 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
551 * SCI helper for checking the state of the muxed port/RXD pins.
553 static inline int sci_rxd_in(struct uart_port *port)
555 struct sci_port *s = to_sci_port(port);
557 if (s->cfg->port_reg <= 0)
560 /* Cast for ARM damage */
561 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
564 /* ********************************************************************** *
565 * the interrupt related routines *
566 * ********************************************************************** */
568 static void sci_transmit_chars(struct uart_port *port)
570 struct circ_buf *xmit = &port->state->xmit;
571 unsigned int stopped = uart_tx_stopped(port);
572 unsigned short status;
576 status = serial_port_in(port, SCxSR);
577 if (!(status & SCxSR_TDxE(port))) {
578 ctrl = serial_port_in(port, SCSCR);
579 if (uart_circ_empty(xmit))
583 serial_port_out(port, SCSCR, ctrl);
587 count = sci_txroom(port);
595 } else if (!uart_circ_empty(xmit) && !stopped) {
596 c = xmit->buf[xmit->tail];
597 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
602 serial_port_out(port, SCxTDR, c);
605 } while (--count > 0);
607 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
609 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
610 uart_write_wakeup(port);
611 if (uart_circ_empty(xmit)) {
614 ctrl = serial_port_in(port, SCSCR);
616 if (port->type != PORT_SCI) {
617 serial_port_in(port, SCxSR); /* Dummy read */
618 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
622 serial_port_out(port, SCSCR, ctrl);
626 /* On SH3, SCIF may read end-of-break as a space->mark char */
627 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
629 static void sci_receive_chars(struct uart_port *port)
631 struct sci_port *sci_port = to_sci_port(port);
632 struct tty_port *tport = &port->state->port;
633 int i, count, copied = 0;
634 unsigned short status;
637 status = serial_port_in(port, SCxSR);
638 if (!(status & SCxSR_RDxF(port)))
642 /* Don't copy more bytes than there is room for in the buffer */
643 count = tty_buffer_request_room(tport, sci_rxfill(port));
645 /* If for any reason we can't copy more data, we're done! */
649 if (port->type == PORT_SCI) {
650 char c = serial_port_in(port, SCxRDR);
651 if (uart_handle_sysrq_char(port, c) ||
652 sci_port->break_flag)
655 tty_insert_flip_char(tport, c, TTY_NORMAL);
657 for (i = 0; i < count; i++) {
658 char c = serial_port_in(port, SCxRDR);
660 status = serial_port_in(port, SCxSR);
661 #if defined(CONFIG_CPU_SH3)
662 /* Skip "chars" during break */
663 if (sci_port->break_flag) {
665 (status & SCxSR_FER(port))) {
670 /* Nonzero => end-of-break */
671 dev_dbg(port->dev, "debounce<%02x>\n", c);
672 sci_port->break_flag = 0;
679 #endif /* CONFIG_CPU_SH3 */
680 if (uart_handle_sysrq_char(port, c)) {
685 /* Store data and status */
686 if (status & SCxSR_FER(port)) {
688 port->icount.frame++;
689 dev_notice(port->dev, "frame error\n");
690 } else if (status & SCxSR_PER(port)) {
692 port->icount.parity++;
693 dev_notice(port->dev, "parity error\n");
697 tty_insert_flip_char(tport, c, flag);
701 serial_port_in(port, SCxSR); /* dummy read */
702 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
705 port->icount.rx += count;
709 /* Tell the rest of the system the news. New characters! */
710 tty_flip_buffer_push(tport);
712 serial_port_in(port, SCxSR); /* dummy read */
713 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
717 #define SCI_BREAK_JIFFIES (HZ/20)
720 * The sci generates interrupts during the break,
721 * 1 per millisecond or so during the break period, for 9600 baud.
722 * So dont bother disabling interrupts.
723 * But dont want more than 1 break event.
724 * Use a kernel timer to periodically poll the rx line until
725 * the break is finished.
727 static inline void sci_schedule_break_timer(struct sci_port *port)
729 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
732 /* Ensure that two consecutive samples find the break over. */
733 static void sci_break_timer(unsigned long data)
735 struct sci_port *port = (struct sci_port *)data;
737 sci_port_enable(port);
739 if (sci_rxd_in(&port->port) == 0) {
740 port->break_flag = 1;
741 sci_schedule_break_timer(port);
742 } else if (port->break_flag == 1) {
744 port->break_flag = 2;
745 sci_schedule_break_timer(port);
747 port->break_flag = 0;
749 sci_port_disable(port);
752 static int sci_handle_errors(struct uart_port *port)
755 unsigned short status = serial_port_in(port, SCxSR);
756 struct tty_port *tport = &port->state->port;
757 struct sci_port *s = to_sci_port(port);
760 * Handle overruns, if supported.
762 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
763 if (status & (1 << s->cfg->overrun_bit)) {
764 port->icount.overrun++;
767 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
770 dev_notice(port->dev, "overrun error");
774 if (status & SCxSR_FER(port)) {
775 if (sci_rxd_in(port) == 0) {
776 /* Notify of BREAK */
777 struct sci_port *sci_port = to_sci_port(port);
779 if (!sci_port->break_flag) {
782 sci_port->break_flag = 1;
783 sci_schedule_break_timer(sci_port);
785 /* Do sysrq handling. */
786 if (uart_handle_break(port))
789 dev_dbg(port->dev, "BREAK detected\n");
791 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
797 port->icount.frame++;
799 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
802 dev_notice(port->dev, "frame error\n");
806 if (status & SCxSR_PER(port)) {
808 port->icount.parity++;
810 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
813 dev_notice(port->dev, "parity error");
817 tty_flip_buffer_push(tport);
822 static int sci_handle_fifo_overrun(struct uart_port *port)
824 struct tty_port *tport = &port->state->port;
825 struct sci_port *s = to_sci_port(port);
826 struct plat_sci_reg *reg;
829 reg = sci_getreg(port, SCLSR);
833 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
834 serial_port_out(port, SCLSR, 0);
836 port->icount.overrun++;
838 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
839 tty_flip_buffer_push(tport);
841 dev_notice(port->dev, "overrun error\n");
848 static int sci_handle_breaks(struct uart_port *port)
851 unsigned short status = serial_port_in(port, SCxSR);
852 struct tty_port *tport = &port->state->port;
853 struct sci_port *s = to_sci_port(port);
855 if (uart_handle_break(port))
858 if (!s->break_flag && status & SCxSR_BRK(port)) {
859 #if defined(CONFIG_CPU_SH3)
866 /* Notify of BREAK */
867 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
870 dev_dbg(port->dev, "BREAK detected\n");
874 tty_flip_buffer_push(tport);
876 copied += sci_handle_fifo_overrun(port);
881 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
883 #ifdef CONFIG_SERIAL_SH_SCI_DMA
884 struct uart_port *port = ptr;
885 struct sci_port *s = to_sci_port(port);
888 u16 scr = serial_port_in(port, SCSCR);
889 u16 ssr = serial_port_in(port, SCxSR);
891 /* Disable future Rx interrupts */
892 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
893 disable_irq_nosync(irq);
898 serial_port_out(port, SCSCR, scr);
899 /* Clear current interrupt */
900 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
901 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
902 jiffies, s->rx_timeout);
903 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
909 /* I think sci_receive_chars has to be called irrespective
910 * of whether the I_IXOFF is set, otherwise, how is the interrupt
913 sci_receive_chars(ptr);
918 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
920 struct uart_port *port = ptr;
923 spin_lock_irqsave(&port->lock, flags);
924 sci_transmit_chars(port);
925 spin_unlock_irqrestore(&port->lock, flags);
930 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
932 struct uart_port *port = ptr;
935 if (port->type == PORT_SCI) {
936 if (sci_handle_errors(port)) {
937 /* discard character in rx buffer */
938 serial_port_in(port, SCxSR);
939 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
942 sci_handle_fifo_overrun(port);
943 sci_rx_interrupt(irq, ptr);
946 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
948 /* Kick the transmission */
949 sci_tx_interrupt(irq, ptr);
954 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
956 struct uart_port *port = ptr;
959 sci_handle_breaks(port);
960 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
965 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
968 * Not all ports (such as SCIFA) will support REIE. Rather than
969 * special-casing the port type, we check the port initialization
970 * IRQ enable mask to see whether the IRQ is desired at all. If
971 * it's unset, it's logically inferred that there's no point in
974 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
977 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
979 unsigned short ssr_status, scr_status, err_enabled;
980 struct uart_port *port = ptr;
981 struct sci_port *s = to_sci_port(port);
982 irqreturn_t ret = IRQ_NONE;
984 ssr_status = serial_port_in(port, SCxSR);
985 scr_status = serial_port_in(port, SCSCR);
986 err_enabled = scr_status & port_rx_irq_mask(port);
989 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
991 ret = sci_tx_interrupt(irq, ptr);
994 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
997 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
998 (scr_status & SCSCR_RIE))
999 ret = sci_rx_interrupt(irq, ptr);
1001 /* Error Interrupt */
1002 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1003 ret = sci_er_interrupt(irq, ptr);
1005 /* Break Interrupt */
1006 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1007 ret = sci_br_interrupt(irq, ptr);
1013 * Here we define a transition notifier so that we can update all of our
1014 * ports' baud rate when the peripheral clock changes.
1016 static int sci_notifier(struct notifier_block *self,
1017 unsigned long phase, void *p)
1019 struct sci_port *sci_port;
1020 unsigned long flags;
1022 sci_port = container_of(self, struct sci_port, freq_transition);
1024 if ((phase == CPUFREQ_POSTCHANGE) ||
1025 (phase == CPUFREQ_RESUMECHANGE)) {
1026 struct uart_port *port = &sci_port->port;
1028 spin_lock_irqsave(&port->lock, flags);
1029 port->uartclk = clk_get_rate(sci_port->iclk);
1030 spin_unlock_irqrestore(&port->lock, flags);
1036 static struct sci_irq_desc {
1038 irq_handler_t handler;
1039 } sci_irq_desc[] = {
1041 * Split out handlers, the default case.
1045 .handler = sci_er_interrupt,
1050 .handler = sci_rx_interrupt,
1055 .handler = sci_tx_interrupt,
1060 .handler = sci_br_interrupt,
1064 * Special muxed handler.
1068 .handler = sci_mpxed_interrupt,
1072 static int sci_request_irq(struct sci_port *port)
1074 struct uart_port *up = &port->port;
1077 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1078 struct sci_irq_desc *desc;
1081 if (SCIx_IRQ_IS_MUXED(port)) {
1085 irq = port->cfg->irqs[i];
1088 * Certain port types won't support all of the
1089 * available interrupt sources.
1095 desc = sci_irq_desc + i;
1096 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1097 dev_name(up->dev), desc->desc);
1098 if (!port->irqstr[j]) {
1099 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1104 ret = request_irq(irq, desc->handler, up->irqflags,
1105 port->irqstr[j], port);
1106 if (unlikely(ret)) {
1107 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1116 free_irq(port->cfg->irqs[i], port);
1120 kfree(port->irqstr[j]);
1125 static void sci_free_irq(struct sci_port *port)
1130 * Intentionally in reverse order so we iterate over the muxed
1133 for (i = 0; i < SCIx_NR_IRQS; i++) {
1134 unsigned int irq = port->cfg->irqs[i];
1137 * Certain port types won't support all of the available
1138 * interrupt sources.
1143 free_irq(port->cfg->irqs[i], port);
1144 kfree(port->irqstr[i]);
1146 if (SCIx_IRQ_IS_MUXED(port)) {
1147 /* If there's only one IRQ, we're done. */
1153 static const char *sci_gpio_names[SCIx_NR_FNS] = {
1154 "sck", "rxd", "txd", "cts", "rts",
1157 static const char *sci_gpio_str(unsigned int index)
1159 return sci_gpio_names[index];
1162 static void sci_init_gpios(struct sci_port *port)
1164 struct uart_port *up = &port->port;
1170 for (i = 0; i < SCIx_NR_FNS; i++) {
1174 if (!port->cfg->gpios[i])
1177 desc = sci_gpio_str(i);
1179 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1180 dev_name(up->dev), desc);
1183 * If we've failed the allocation, we can still continue
1184 * on with a NULL string.
1186 if (!port->gpiostr[i])
1187 dev_notice(up->dev, "%s string allocation failure\n",
1190 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1191 if (unlikely(ret != 0)) {
1192 dev_notice(up->dev, "failed %s gpio request\n", desc);
1195 * If we can't get the GPIO for whatever reason,
1196 * no point in keeping the verbose string around.
1198 kfree(port->gpiostr[i]);
1203 static void sci_free_gpios(struct sci_port *port)
1207 for (i = 0; i < SCIx_NR_FNS; i++)
1208 if (port->cfg->gpios[i]) {
1209 gpio_free(port->cfg->gpios[i]);
1210 kfree(port->gpiostr[i]);
1214 static unsigned int sci_tx_empty(struct uart_port *port)
1216 unsigned short status = serial_port_in(port, SCxSR);
1217 unsigned short in_tx_fifo = sci_txfill(port);
1219 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1223 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1224 * CTS/RTS is supported in hardware by at least one port and controlled
1225 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1226 * handled via the ->init_pins() op, which is a bit of a one-way street,
1227 * lacking any ability to defer pin control -- this will later be
1228 * converted over to the GPIO framework).
1230 * Other modes (such as loopback) are supported generically on certain
1231 * port types, but not others. For these it's sufficient to test for the
1232 * existence of the support register and simply ignore the port type.
1234 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1236 if (mctrl & TIOCM_LOOP) {
1237 struct plat_sci_reg *reg;
1240 * Standard loopback mode for SCFCR ports.
1242 reg = sci_getreg(port, SCFCR);
1244 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1248 static unsigned int sci_get_mctrl(struct uart_port *port)
1251 * CTS/RTS is handled in hardware when supported, while nothing
1252 * else is wired up. Keep it simple and simply assert DSR/CAR.
1254 return TIOCM_DSR | TIOCM_CAR;
1257 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1258 static void sci_dma_tx_complete(void *arg)
1260 struct sci_port *s = arg;
1261 struct uart_port *port = &s->port;
1262 struct circ_buf *xmit = &port->state->xmit;
1263 unsigned long flags;
1265 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1267 spin_lock_irqsave(&port->lock, flags);
1269 xmit->tail += sg_dma_len(&s->sg_tx);
1270 xmit->tail &= UART_XMIT_SIZE - 1;
1272 port->icount.tx += sg_dma_len(&s->sg_tx);
1274 async_tx_ack(s->desc_tx);
1277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1278 uart_write_wakeup(port);
1280 if (!uart_circ_empty(xmit)) {
1282 schedule_work(&s->work_tx);
1284 s->cookie_tx = -EINVAL;
1285 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1286 u16 ctrl = serial_port_in(port, SCSCR);
1287 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1291 spin_unlock_irqrestore(&port->lock, flags);
1294 /* Locking: called with port lock held */
1295 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1297 struct uart_port *port = &s->port;
1298 struct tty_port *tport = &port->state->port;
1299 int i, active, room;
1301 room = tty_buffer_request_room(tport, count);
1303 if (s->active_rx == s->cookie_rx[0]) {
1305 } else if (s->active_rx == s->cookie_rx[1]) {
1308 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1313 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1318 for (i = 0; i < room; i++)
1319 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1322 port->icount.rx += room;
1327 static void sci_dma_rx_complete(void *arg)
1329 struct sci_port *s = arg;
1330 struct uart_port *port = &s->port;
1331 unsigned long flags;
1334 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1336 spin_lock_irqsave(&port->lock, flags);
1338 count = sci_dma_rx_push(s, s->buf_len_rx);
1340 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1342 spin_unlock_irqrestore(&port->lock, flags);
1345 tty_flip_buffer_push(&port->state->port);
1347 schedule_work(&s->work_rx);
1350 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1352 struct dma_chan *chan = s->chan_rx;
1353 struct uart_port *port = &s->port;
1356 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1357 dma_release_channel(chan);
1358 if (sg_dma_address(&s->sg_rx[0]))
1359 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1360 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1365 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1367 struct dma_chan *chan = s->chan_tx;
1368 struct uart_port *port = &s->port;
1371 s->cookie_tx = -EINVAL;
1372 dma_release_channel(chan);
1377 static void sci_submit_rx(struct sci_port *s)
1379 struct dma_chan *chan = s->chan_rx;
1382 for (i = 0; i < 2; i++) {
1383 struct scatterlist *sg = &s->sg_rx[i];
1384 struct dma_async_tx_descriptor *desc;
1386 desc = dmaengine_prep_slave_sg(chan,
1387 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1390 s->desc_rx[i] = desc;
1391 desc->callback = sci_dma_rx_complete;
1392 desc->callback_param = s;
1393 s->cookie_rx[i] = desc->tx_submit(desc);
1396 if (!desc || s->cookie_rx[i] < 0) {
1398 async_tx_ack(s->desc_rx[0]);
1399 s->cookie_rx[0] = -EINVAL;
1403 s->cookie_rx[i] = -EINVAL;
1405 dev_warn(s->port.dev,
1406 "failed to re-start DMA, using PIO\n");
1407 sci_rx_dma_release(s, true);
1410 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1411 s->cookie_rx[i], i);
1414 s->active_rx = s->cookie_rx[0];
1416 dma_async_issue_pending(chan);
1419 static void work_fn_rx(struct work_struct *work)
1421 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1422 struct uart_port *port = &s->port;
1423 struct dma_async_tx_descriptor *desc;
1426 if (s->active_rx == s->cookie_rx[0]) {
1428 } else if (s->active_rx == s->cookie_rx[1]) {
1431 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1434 desc = s->desc_rx[new];
1436 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1438 /* Handle incomplete DMA receive */
1439 struct dma_chan *chan = s->chan_rx;
1440 struct shdma_desc *sh_desc = container_of(desc,
1441 struct shdma_desc, async_tx);
1442 unsigned long flags;
1445 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1446 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1447 sh_desc->partial, sh_desc->cookie);
1449 spin_lock_irqsave(&port->lock, flags);
1450 count = sci_dma_rx_push(s, sh_desc->partial);
1451 spin_unlock_irqrestore(&port->lock, flags);
1454 tty_flip_buffer_push(&port->state->port);
1461 s->cookie_rx[new] = desc->tx_submit(desc);
1462 if (s->cookie_rx[new] < 0) {
1463 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1464 sci_rx_dma_release(s, true);
1468 s->active_rx = s->cookie_rx[!new];
1470 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1471 s->cookie_rx[new], new, s->active_rx);
1474 static void work_fn_tx(struct work_struct *work)
1476 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1477 struct dma_async_tx_descriptor *desc;
1478 struct dma_chan *chan = s->chan_tx;
1479 struct uart_port *port = &s->port;
1480 struct circ_buf *xmit = &port->state->xmit;
1481 struct scatterlist *sg = &s->sg_tx;
1485 * Port xmit buffer is already mapped, and it is one page... Just adjust
1486 * offsets and lengths. Since it is a circular buffer, we have to
1487 * transmit till the end, and then the rest. Take the port lock to get a
1488 * consistent xmit buffer state.
1490 spin_lock_irq(&port->lock);
1491 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1492 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1494 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1495 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1496 spin_unlock_irq(&port->lock);
1498 BUG_ON(!sg_dma_len(sg));
1500 desc = dmaengine_prep_slave_sg(chan,
1501 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1502 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1505 sci_tx_dma_release(s, true);
1509 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1511 spin_lock_irq(&port->lock);
1513 desc->callback = sci_dma_tx_complete;
1514 desc->callback_param = s;
1515 spin_unlock_irq(&port->lock);
1516 s->cookie_tx = desc->tx_submit(desc);
1517 if (s->cookie_tx < 0) {
1518 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1520 sci_tx_dma_release(s, true);
1524 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1525 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1527 dma_async_issue_pending(chan);
1531 static void sci_start_tx(struct uart_port *port)
1533 struct sci_port *s = to_sci_port(port);
1534 unsigned short ctrl;
1536 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1537 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1538 u16 new, scr = serial_port_in(port, SCSCR);
1542 new = scr & ~0x8000;
1544 serial_port_out(port, SCSCR, new);
1547 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1550 schedule_work(&s->work_tx);
1554 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1555 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1556 ctrl = serial_port_in(port, SCSCR);
1557 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1561 static void sci_stop_tx(struct uart_port *port)
1563 unsigned short ctrl;
1565 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1566 ctrl = serial_port_in(port, SCSCR);
1568 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1573 serial_port_out(port, SCSCR, ctrl);
1576 static void sci_start_rx(struct uart_port *port)
1578 unsigned short ctrl;
1580 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1582 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1585 serial_port_out(port, SCSCR, ctrl);
1588 static void sci_stop_rx(struct uart_port *port)
1590 unsigned short ctrl;
1592 ctrl = serial_port_in(port, SCSCR);
1594 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1597 ctrl &= ~port_rx_irq_mask(port);
1599 serial_port_out(port, SCSCR, ctrl);
1602 static void sci_enable_ms(struct uart_port *port)
1605 * Not supported by hardware, always a nop.
1609 static void sci_break_ctl(struct uart_port *port, int break_state)
1611 struct sci_port *s = to_sci_port(port);
1612 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1613 unsigned short scscr, scsptr;
1615 /* check wheter the port has SCSPTR */
1618 * Not supported by hardware. Most parts couple break and rx
1619 * interrupts together, with break detection always enabled.
1624 scsptr = serial_port_in(port, SCSPTR);
1625 scscr = serial_port_in(port, SCSCR);
1627 if (break_state == -1) {
1628 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1631 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1635 serial_port_out(port, SCSPTR, scsptr);
1636 serial_port_out(port, SCSCR, scscr);
1639 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1640 static bool filter(struct dma_chan *chan, void *slave)
1642 struct sh_dmae_slave *param = slave;
1644 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1645 param->shdma_slave.slave_id);
1647 chan->private = ¶m->shdma_slave;
1651 static void rx_timer_fn(unsigned long arg)
1653 struct sci_port *s = (struct sci_port *)arg;
1654 struct uart_port *port = &s->port;
1655 u16 scr = serial_port_in(port, SCSCR);
1657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1659 enable_irq(s->cfg->irqs[1]);
1661 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1662 dev_dbg(port->dev, "DMA Rx timed out\n");
1663 schedule_work(&s->work_rx);
1666 static void sci_request_dma(struct uart_port *port)
1668 struct sci_port *s = to_sci_port(port);
1669 struct sh_dmae_slave *param;
1670 struct dma_chan *chan;
1671 dma_cap_mask_t mask;
1674 dev_dbg(port->dev, "%s: port %d\n", __func__,
1677 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1681 dma_cap_set(DMA_SLAVE, mask);
1683 param = &s->param_tx;
1685 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1686 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1688 s->cookie_tx = -EINVAL;
1689 chan = dma_request_channel(mask, filter, param);
1690 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1693 sg_init_table(&s->sg_tx, 1);
1694 /* UART circular tx buffer is an aligned page. */
1695 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1696 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1697 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1698 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1700 sci_tx_dma_release(s, false);
1702 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1703 sg_dma_len(&s->sg_tx),
1704 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1706 s->sg_len_tx = nent;
1708 INIT_WORK(&s->work_tx, work_fn_tx);
1711 param = &s->param_rx;
1713 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1714 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1716 chan = dma_request_channel(mask, filter, param);
1717 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1725 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1726 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1727 &dma[0], GFP_KERNEL);
1731 "failed to allocate dma buffer, using PIO\n");
1732 sci_rx_dma_release(s, true);
1736 buf[1] = buf[0] + s->buf_len_rx;
1737 dma[1] = dma[0] + s->buf_len_rx;
1739 for (i = 0; i < 2; i++) {
1740 struct scatterlist *sg = &s->sg_rx[i];
1742 sg_init_table(sg, 1);
1743 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1744 (int)buf[i] & ~PAGE_MASK);
1745 sg_dma_address(sg) = dma[i];
1748 INIT_WORK(&s->work_rx, work_fn_rx);
1749 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1755 static void sci_free_dma(struct uart_port *port)
1757 struct sci_port *s = to_sci_port(port);
1760 sci_tx_dma_release(s, false);
1762 sci_rx_dma_release(s, false);
1765 static inline void sci_request_dma(struct uart_port *port)
1769 static inline void sci_free_dma(struct uart_port *port)
1774 static int sci_startup(struct uart_port *port)
1776 struct sci_port *s = to_sci_port(port);
1777 unsigned long flags;
1780 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1782 ret = sci_request_irq(s);
1783 if (unlikely(ret < 0))
1786 sci_request_dma(port);
1788 spin_lock_irqsave(&port->lock, flags);
1791 spin_unlock_irqrestore(&port->lock, flags);
1796 static void sci_shutdown(struct uart_port *port)
1798 struct sci_port *s = to_sci_port(port);
1799 unsigned long flags;
1801 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1803 spin_lock_irqsave(&port->lock, flags);
1806 spin_unlock_irqrestore(&port->lock, flags);
1812 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1817 return ((freq + 16 * bps) / (16 * bps) - 1);
1819 return ((freq + 16 * bps) / (32 * bps) - 1);
1821 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1823 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1825 return (((freq * 1000 / 32) / bps) - 1);
1828 /* Warn, but use a safe default */
1831 return ((freq + 16 * bps) / (32 * bps) - 1);
1834 /* calculate sample rate, BRR, and clock select for HSCIF */
1835 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1836 int *brr, unsigned int *srr,
1840 int min_err = 1000; /* 100% */
1842 /* Find the combination of sample rate and clock select with the
1843 smallest deviation from the desired baud rate. */
1844 for (sr = 8; sr <= 32; sr++) {
1845 for (c = 0; c <= 3; c++) {
1846 /* integerized formulas from HSCIF documentation */
1847 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1848 if (br < 0 || br > 255)
1850 err = freq / ((br + 1) * bps * sr *
1851 (1 << (2 * c + 1)) / 1000) - 1000;
1852 if (min_err > err) {
1861 if (min_err == 1000) {
1870 static void sci_reset(struct uart_port *port)
1872 struct plat_sci_reg *reg;
1873 unsigned int status;
1876 status = serial_port_in(port, SCxSR);
1877 } while (!(status & SCxSR_TEND(port)));
1879 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1881 reg = sci_getreg(port, SCFCR);
1883 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1886 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1887 struct ktermios *old)
1889 struct sci_port *s = to_sci_port(port);
1890 struct plat_sci_reg *reg;
1891 unsigned int baud, smr_val, max_baud, cks = 0;
1893 unsigned int srr = 15;
1896 * earlyprintk comes here early on with port->uartclk set to zero.
1897 * the clock framework is not up and running at this point so here
1898 * we assume that 115200 is the maximum baud rate. please note that
1899 * the baud rate is not programmed during earlyprintk - it is assumed
1900 * that the previous boot loader has enabled required clocks and
1901 * setup the baud rate generator hardware for us already.
1903 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1905 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1906 if (likely(baud && port->uartclk)) {
1907 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1908 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1911 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1913 for (cks = 0; t >= 256 && cks <= 3; cks++)
1922 smr_val = serial_port_in(port, SCSMR) & 3;
1924 if ((termios->c_cflag & CSIZE) == CS7)
1926 if (termios->c_cflag & PARENB)
1928 if (termios->c_cflag & PARODD)
1930 if (termios->c_cflag & CSTOPB)
1933 uart_update_timeout(port, termios->c_cflag, baud);
1935 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1936 __func__, smr_val, cks, t, s->cfg->scscr);
1939 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1940 serial_port_out(port, SCBRR, t);
1941 reg = sci_getreg(port, HSSRR);
1943 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1944 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1946 serial_port_out(port, SCSMR, smr_val);
1948 sci_init_pins(port, termios->c_cflag);
1950 reg = sci_getreg(port, SCFCR);
1952 unsigned short ctrl = serial_port_in(port, SCFCR);
1954 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1955 if (termios->c_cflag & CRTSCTS)
1962 * As we've done a sci_reset() above, ensure we don't
1963 * interfere with the FIFOs while toggling MCE. As the
1964 * reset values could still be set, simply mask them out.
1966 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1968 serial_port_out(port, SCFCR, ctrl);
1971 serial_port_out(port, SCSCR, s->cfg->scscr);
1973 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1975 * Calculate delay for 1.5 DMA buffers: see
1976 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1977 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1978 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1979 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1980 * sizes), but it has been found out experimentally, that this is not
1981 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1982 * as a minimum seem to work perfectly.
1985 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1988 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1989 s->rx_timeout * 1000 / HZ, port->timeout);
1990 if (s->rx_timeout < msecs_to_jiffies(20))
1991 s->rx_timeout = msecs_to_jiffies(20);
1995 if ((termios->c_cflag & CREAD) != 0)
1998 sci_port_disable(s);
2001 static void sci_pm(struct uart_port *port, unsigned int state,
2002 unsigned int oldstate)
2004 struct sci_port *sci_port = to_sci_port(port);
2008 sci_port_disable(sci_port);
2011 sci_port_enable(sci_port);
2016 static const char *sci_type(struct uart_port *port)
2018 switch (port->type) {
2036 static inline unsigned long sci_port_size(struct uart_port *port)
2039 * Pick an arbitrary size that encapsulates all of the base
2040 * registers by default. This can be optimized later, or derived
2041 * from platform resource data at such a time that ports begin to
2042 * behave more erratically.
2044 if (port->type == PORT_HSCIF)
2050 static int sci_remap_port(struct uart_port *port)
2052 unsigned long size = sci_port_size(port);
2055 * Nothing to do if there's already an established membase.
2060 if (port->flags & UPF_IOREMAP) {
2061 port->membase = ioremap_nocache(port->mapbase, size);
2062 if (unlikely(!port->membase)) {
2063 dev_err(port->dev, "can't remap port#%d\n", port->line);
2068 * For the simple (and majority of) cases where we don't
2069 * need to do any remapping, just cast the cookie
2072 port->membase = (void __iomem *)port->mapbase;
2078 static void sci_release_port(struct uart_port *port)
2080 if (port->flags & UPF_IOREMAP) {
2081 iounmap(port->membase);
2082 port->membase = NULL;
2085 release_mem_region(port->mapbase, sci_port_size(port));
2088 static int sci_request_port(struct uart_port *port)
2090 unsigned long size = sci_port_size(port);
2091 struct resource *res;
2094 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2095 if (unlikely(res == NULL))
2098 ret = sci_remap_port(port);
2099 if (unlikely(ret != 0)) {
2100 release_resource(res);
2107 static void sci_config_port(struct uart_port *port, int flags)
2109 if (flags & UART_CONFIG_TYPE) {
2110 struct sci_port *sport = to_sci_port(port);
2112 port->type = sport->cfg->type;
2113 sci_request_port(port);
2117 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2119 struct sci_port *s = to_sci_port(port);
2121 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
2123 if (ser->baud_base < 2400)
2124 /* No paper tape reader for Mitch.. */
2130 static struct uart_ops sci_uart_ops = {
2131 .tx_empty = sci_tx_empty,
2132 .set_mctrl = sci_set_mctrl,
2133 .get_mctrl = sci_get_mctrl,
2134 .start_tx = sci_start_tx,
2135 .stop_tx = sci_stop_tx,
2136 .stop_rx = sci_stop_rx,
2137 .enable_ms = sci_enable_ms,
2138 .break_ctl = sci_break_ctl,
2139 .startup = sci_startup,
2140 .shutdown = sci_shutdown,
2141 .set_termios = sci_set_termios,
2144 .release_port = sci_release_port,
2145 .request_port = sci_request_port,
2146 .config_port = sci_config_port,
2147 .verify_port = sci_verify_port,
2148 #ifdef CONFIG_CONSOLE_POLL
2149 .poll_get_char = sci_poll_get_char,
2150 .poll_put_char = sci_poll_put_char,
2154 static int sci_init_single(struct platform_device *dev,
2155 struct sci_port *sci_port,
2157 struct plat_sci_port *p)
2159 struct uart_port *port = &sci_port->port;
2164 port->ops = &sci_uart_ops;
2165 port->iotype = UPIO_MEM;
2170 port->fifosize = 256;
2173 port->fifosize = 128;
2176 port->fifosize = 64;
2179 port->fifosize = 16;
2186 if (p->regtype == SCIx_PROBE_REGTYPE) {
2187 ret = sci_probe_regmap(p);
2193 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2194 if (IS_ERR(sci_port->iclk)) {
2195 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2196 if (IS_ERR(sci_port->iclk)) {
2197 dev_err(&dev->dev, "can't get iclk\n");
2198 return PTR_ERR(sci_port->iclk);
2203 * The function clock is optional, ignore it if we can't
2206 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2207 if (IS_ERR(sci_port->fclk))
2208 sci_port->fclk = NULL;
2210 port->dev = &dev->dev;
2212 sci_init_gpios(sci_port);
2214 pm_runtime_enable(&dev->dev);
2217 sci_port->break_timer.data = (unsigned long)sci_port;
2218 sci_port->break_timer.function = sci_break_timer;
2219 init_timer(&sci_port->break_timer);
2222 * Establish some sensible defaults for the error detection.
2225 p->error_mask = (p->type == PORT_SCI) ?
2226 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2229 * Establish sensible defaults for the overrun detection, unless
2230 * the part has explicitly disabled support for it.
2232 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2233 if (p->type == PORT_SCI)
2235 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2241 * Make the error mask inclusive of overrun detection, if
2244 p->error_mask |= (1 << p->overrun_bit);
2247 port->mapbase = p->mapbase;
2248 port->type = p->type;
2249 port->flags = p->flags;
2250 port->regshift = p->regshift;
2253 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2254 * for the multi-IRQ ports, which is where we are primarily
2255 * concerned with the shutdown path synchronization.
2257 * For the muxed case there's nothing more to do.
2259 port->irq = p->irqs[SCIx_RXI_IRQ];
2262 port->serial_in = sci_serial_in;
2263 port->serial_out = sci_serial_out;
2265 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2266 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2267 p->dma_slave_tx, p->dma_slave_rx);
2272 static void sci_cleanup_single(struct sci_port *port)
2274 sci_free_gpios(port);
2276 clk_put(port->iclk);
2277 clk_put(port->fclk);
2279 pm_runtime_disable(port->port.dev);
2282 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2283 static void serial_console_putchar(struct uart_port *port, int ch)
2285 sci_poll_put_char(port, ch);
2289 * Print a string to the serial port trying not to disturb
2290 * any possible real use of the port...
2292 static void serial_console_write(struct console *co, const char *s,
2295 struct sci_port *sci_port = &sci_ports[co->index];
2296 struct uart_port *port = &sci_port->port;
2297 unsigned short bits, ctrl;
2298 unsigned long flags;
2301 local_irq_save(flags);
2304 else if (oops_in_progress)
2305 locked = spin_trylock(&port->lock);
2307 spin_lock(&port->lock);
2309 /* first save the SCSCR then disable the interrupts */
2310 ctrl = serial_port_in(port, SCSCR);
2311 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2313 uart_console_write(port, s, count, serial_console_putchar);
2315 /* wait until fifo is empty and last bit has been transmitted */
2316 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2317 while ((serial_port_in(port, SCxSR) & bits) != bits)
2320 /* restore the SCSCR */
2321 serial_port_out(port, SCSCR, ctrl);
2324 spin_unlock(&port->lock);
2325 local_irq_restore(flags);
2328 static int serial_console_setup(struct console *co, char *options)
2330 struct sci_port *sci_port;
2331 struct uart_port *port;
2339 * Refuse to handle any bogus ports.
2341 if (co->index < 0 || co->index >= SCI_NPORTS)
2344 sci_port = &sci_ports[co->index];
2345 port = &sci_port->port;
2348 * Refuse to handle uninitialized ports.
2353 ret = sci_remap_port(port);
2354 if (unlikely(ret != 0))
2358 uart_parse_options(options, &baud, &parity, &bits, &flow);
2360 return uart_set_options(port, co, baud, parity, bits, flow);
2363 static struct console serial_console = {
2365 .device = uart_console_device,
2366 .write = serial_console_write,
2367 .setup = serial_console_setup,
2368 .flags = CON_PRINTBUFFER,
2370 .data = &sci_uart_driver,
2373 static struct console early_serial_console = {
2374 .name = "early_ttySC",
2375 .write = serial_console_write,
2376 .flags = CON_PRINTBUFFER,
2380 static char early_serial_buf[32];
2382 static int sci_probe_earlyprintk(struct platform_device *pdev)
2384 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2386 if (early_serial_console.data)
2389 early_serial_console.index = pdev->id;
2391 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2393 serial_console_setup(&early_serial_console, early_serial_buf);
2395 if (!strstr(early_serial_buf, "keep"))
2396 early_serial_console.flags |= CON_BOOT;
2398 register_console(&early_serial_console);
2402 #define SCI_CONSOLE (&serial_console)
2405 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2410 #define SCI_CONSOLE NULL
2412 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2414 static char banner[] __initdata =
2415 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
2417 static struct uart_driver sci_uart_driver = {
2418 .owner = THIS_MODULE,
2419 .driver_name = "sci",
2420 .dev_name = "ttySC",
2422 .minor = SCI_MINOR_START,
2424 .cons = SCI_CONSOLE,
2427 static int sci_remove(struct platform_device *dev)
2429 struct sci_port *port = platform_get_drvdata(dev);
2431 cpufreq_unregister_notifier(&port->freq_transition,
2432 CPUFREQ_TRANSITION_NOTIFIER);
2434 uart_remove_one_port(&sci_uart_driver, &port->port);
2436 sci_cleanup_single(port);
2442 static const struct of_device_id of_sci_match[] = {
2443 { .compatible = "renesas,sci-SCI-uart",
2444 .data = (void *)PORT_SCI },
2445 { .compatible = "renesas,sci-SCIF-uart",
2446 .data = (void *)PORT_SCIF },
2447 { .compatible = "renesas,sci-IRDA-uart",
2448 .data = (void *)PORT_IRDA },
2449 { .compatible = "renesas,sci-SCIFA-uart",
2450 .data = (void *)PORT_SCIFA },
2451 { .compatible = "renesas,sci-SCIFB-uart",
2452 .data = (void *)PORT_SCIFB },
2455 MODULE_DEVICE_TABLE(of, of_sci_match);
2457 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
2460 struct plat_sci_port *p;
2461 struct device_node *np = pdev->dev.of_node;
2462 const struct of_device_id *match;
2463 struct resource *res;
2467 match = of_match_node(of_sci_match, pdev->dev.of_node);
2468 if (!match || !match->data) {
2469 dev_err(&pdev->dev, "OF match error\n");
2473 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2475 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2479 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2481 dev_err(&pdev->dev, "failed to get I/O memory\n");
2484 p->mapbase = res->start;
2486 for (i = 0; i < SCIx_NR_IRQS; i++) {
2487 irq = platform_get_irq(pdev, i);
2489 dev_err(&pdev->dev, "failed to get irq data %d\n", i);
2495 prop = of_get_property(np, "cell-index", NULL);
2497 dev_err(&pdev->dev, "required DT prop cell-index missing\n");
2500 *dev_id = be32_to_cpup(prop);
2502 prop = of_get_property(np, "renesas,scscr", NULL);
2504 dev_err(&pdev->dev, "required DT prop scscr missing\n");
2507 p->scscr = be32_to_cpup(prop);
2509 prop = of_get_property(np, "renesas,scbrr-algo-id", NULL);
2511 dev_err(&pdev->dev, "required DT prop scbrr-algo-id missing\n");
2514 val = be32_to_cpup(prop);
2515 if (val <= SCBRR_ALGO_INVALID || val >= SCBRR_NR_ALGOS) {
2516 dev_err(&pdev->dev, "DT prop scbrr-algo-id out of range\n");
2519 p->scbrr_algo_id = val;
2521 p->flags = UPF_IOREMAP;
2522 if (of_get_property(np, "renesas,autoconf", NULL))
2523 p->flags |= UPF_BOOT_AUTOCONF;
2525 prop = of_get_property(np, "renesas,regtype", NULL);
2527 val = be32_to_cpup(prop);
2528 if (val < SCIx_PROBE_REGTYPE || val >= SCIx_NR_REGTYPES) {
2529 dev_err(&pdev->dev, "DT prop regtype out of range\n");
2535 p->type = (unsigned int)match->data;
2540 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
2545 #endif /* CONFIG_OF */
2547 static int sci_probe_single(struct platform_device *dev,
2549 struct plat_sci_port *p,
2550 struct sci_port *sciport)
2555 if (unlikely(index >= SCI_NPORTS)) {
2556 dev_notice(&dev->dev, "Attempting to register port "
2557 "%d when only %d are available.\n",
2558 index+1, SCI_NPORTS);
2559 dev_notice(&dev->dev, "Consider bumping "
2560 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2564 ret = sci_init_single(dev, sciport, index, p);
2568 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2570 sci_cleanup_single(sciport);
2577 static int sci_probe(struct platform_device *dev)
2579 struct plat_sci_port *p;
2580 struct sci_port *sp;
2581 int ret, dev_id = dev->id;
2584 * If we've come here via earlyprintk initialization, head off to
2585 * the special early probe. We don't have sufficient device state
2586 * to make it beyond this yet.
2588 if (is_early_platform_device(dev))
2589 return sci_probe_earlyprintk(dev);
2591 if (dev->dev.of_node)
2592 p = sci_parse_dt(dev, &dev_id);
2594 p = dev_get_platdata(&dev->dev);
2597 dev_err(&dev->dev, "no setup data supplied\n");
2601 sp = &sci_ports[dev_id];
2602 platform_set_drvdata(dev, sp);
2604 ret = sci_probe_single(dev, dev_id, p, sp);
2608 sp->freq_transition.notifier_call = sci_notifier;
2610 ret = cpufreq_register_notifier(&sp->freq_transition,
2611 CPUFREQ_TRANSITION_NOTIFIER);
2612 if (unlikely(ret < 0)) {
2613 sci_cleanup_single(sp);
2617 #ifdef CONFIG_SH_STANDARD_BIOS
2618 sh_bios_gdb_detach();
2624 static int sci_suspend(struct device *dev)
2626 struct sci_port *sport = dev_get_drvdata(dev);
2629 uart_suspend_port(&sci_uart_driver, &sport->port);
2634 static int sci_resume(struct device *dev)
2636 struct sci_port *sport = dev_get_drvdata(dev);
2639 uart_resume_port(&sci_uart_driver, &sport->port);
2644 static const struct dev_pm_ops sci_dev_pm_ops = {
2645 .suspend = sci_suspend,
2646 .resume = sci_resume,
2649 static struct platform_driver sci_driver = {
2651 .remove = sci_remove,
2654 .owner = THIS_MODULE,
2655 .pm = &sci_dev_pm_ops,
2656 .of_match_table = of_match_ptr(of_sci_match),
2660 static int __init sci_init(void)
2666 ret = uart_register_driver(&sci_uart_driver);
2667 if (likely(ret == 0)) {
2668 ret = platform_driver_register(&sci_driver);
2670 uart_unregister_driver(&sci_uart_driver);
2676 static void __exit sci_exit(void)
2678 platform_driver_unregister(&sci_driver);
2679 uart_unregister_driver(&sci_uart_driver);
2682 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2683 early_platform_init_buffer("earlyprintk", &sci_driver,
2684 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2686 module_init(sci_init);
2687 module_exit(sci_exit);
2689 MODULE_LICENSE("GPL");
2690 MODULE_ALIAS("platform:sh-sci");
2691 MODULE_AUTHOR("Paul Mundt");
2692 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");