2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
98 int irqs[SCIx_NR_IRQS];
99 char *irqstr[SCIx_NR_IRQS];
101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 dma_cookie_t cookie_tx;
106 dma_cookie_t cookie_rx[2];
107 dma_cookie_t active_rx;
108 dma_addr_t tx_dma_addr;
109 unsigned int tx_dma_len;
110 struct scatterlist sg_rx[2];
113 struct work_struct work_tx;
114 struct timer_list rx_timer;
115 unsigned int rx_timeout;
118 struct notifier_block freq_transition;
121 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
123 static struct sci_port sci_ports[SCI_NPORTS];
124 static struct uart_driver sci_uart_driver;
126 static inline struct sci_port *
127 to_sci_port(struct uart_port *uart)
129 return container_of(uart, struct sci_port, port);
132 struct plat_sci_reg {
136 /* Helper for invalidating specific entries of an inherited map. */
137 #define sci_reg_invalid { .offset = 0, .size = 0 }
139 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
140 [SCIx_PROBE_REGTYPE] = {
141 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
145 * Common SCI definitions, dependent on the port's regshift
148 [SCIx_SCI_REGTYPE] = {
149 [SCSMR] = { 0x00, 8 },
150 [SCBRR] = { 0x01, 8 },
151 [SCSCR] = { 0x02, 8 },
152 [SCxTDR] = { 0x03, 8 },
153 [SCxSR] = { 0x04, 8 },
154 [SCxRDR] = { 0x05, 8 },
155 [SCFCR] = sci_reg_invalid,
156 [SCFDR] = sci_reg_invalid,
157 [SCTFDR] = sci_reg_invalid,
158 [SCRFDR] = sci_reg_invalid,
159 [SCSPTR] = sci_reg_invalid,
160 [SCLSR] = sci_reg_invalid,
161 [HSSRR] = sci_reg_invalid,
162 [SCPCR] = sci_reg_invalid,
163 [SCPDR] = sci_reg_invalid,
167 * Common definitions for legacy IrDA ports, dependent on
170 [SCIx_IRDA_REGTYPE] = {
171 [SCSMR] = { 0x00, 8 },
172 [SCBRR] = { 0x01, 8 },
173 [SCSCR] = { 0x02, 8 },
174 [SCxTDR] = { 0x03, 8 },
175 [SCxSR] = { 0x04, 8 },
176 [SCxRDR] = { 0x05, 8 },
177 [SCFCR] = { 0x06, 8 },
178 [SCFDR] = { 0x07, 16 },
179 [SCTFDR] = sci_reg_invalid,
180 [SCRFDR] = sci_reg_invalid,
181 [SCSPTR] = sci_reg_invalid,
182 [SCLSR] = sci_reg_invalid,
183 [HSSRR] = sci_reg_invalid,
184 [SCPCR] = sci_reg_invalid,
185 [SCPDR] = sci_reg_invalid,
189 * Common SCIFA definitions.
191 [SCIx_SCIFA_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x20, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x24, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = { 0x1c, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 [HSSRR] = sci_reg_invalid,
205 [SCPCR] = { 0x30, 16 },
206 [SCPDR] = { 0x34, 16 },
210 * Common SCIFB definitions.
212 [SCIx_SCIFB_REGTYPE] = {
213 [SCSMR] = { 0x00, 16 },
214 [SCBRR] = { 0x04, 8 },
215 [SCSCR] = { 0x08, 16 },
216 [SCxTDR] = { 0x40, 8 },
217 [SCxSR] = { 0x14, 16 },
218 [SCxRDR] = { 0x60, 8 },
219 [SCFCR] = { 0x18, 16 },
220 [SCFDR] = sci_reg_invalid,
221 [SCTFDR] = { 0x38, 16 },
222 [SCRFDR] = { 0x3c, 16 },
223 [SCSPTR] = sci_reg_invalid,
224 [SCLSR] = sci_reg_invalid,
225 [HSSRR] = sci_reg_invalid,
226 [SCPCR] = { 0x30, 16 },
227 [SCPDR] = { 0x34, 16 },
231 * Common SH-2(A) SCIF definitions for ports with FIFO data
234 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
235 [SCSMR] = { 0x00, 16 },
236 [SCBRR] = { 0x04, 8 },
237 [SCSCR] = { 0x08, 16 },
238 [SCxTDR] = { 0x0c, 8 },
239 [SCxSR] = { 0x10, 16 },
240 [SCxRDR] = { 0x14, 8 },
241 [SCFCR] = { 0x18, 16 },
242 [SCFDR] = { 0x1c, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = { 0x20, 16 },
246 [SCLSR] = { 0x24, 16 },
247 [HSSRR] = sci_reg_invalid,
248 [SCPCR] = sci_reg_invalid,
249 [SCPDR] = sci_reg_invalid,
253 * Common SH-3 SCIF definitions.
255 [SCIx_SH3_SCIF_REGTYPE] = {
256 [SCSMR] = { 0x00, 8 },
257 [SCBRR] = { 0x02, 8 },
258 [SCSCR] = { 0x04, 8 },
259 [SCxTDR] = { 0x06, 8 },
260 [SCxSR] = { 0x08, 16 },
261 [SCxRDR] = { 0x0a, 8 },
262 [SCFCR] = { 0x0c, 8 },
263 [SCFDR] = { 0x0e, 16 },
264 [SCTFDR] = sci_reg_invalid,
265 [SCRFDR] = sci_reg_invalid,
266 [SCSPTR] = sci_reg_invalid,
267 [SCLSR] = sci_reg_invalid,
268 [HSSRR] = sci_reg_invalid,
269 [SCPCR] = sci_reg_invalid,
270 [SCPDR] = sci_reg_invalid,
274 * Common SH-4(A) SCIF(B) definitions.
276 [SCIx_SH4_SCIF_REGTYPE] = {
277 [SCSMR] = { 0x00, 16 },
278 [SCBRR] = { 0x04, 8 },
279 [SCSCR] = { 0x08, 16 },
280 [SCxTDR] = { 0x0c, 8 },
281 [SCxSR] = { 0x10, 16 },
282 [SCxRDR] = { 0x14, 8 },
283 [SCFCR] = { 0x18, 16 },
284 [SCFDR] = { 0x1c, 16 },
285 [SCTFDR] = sci_reg_invalid,
286 [SCRFDR] = sci_reg_invalid,
287 [SCSPTR] = { 0x20, 16 },
288 [SCLSR] = { 0x24, 16 },
289 [HSSRR] = sci_reg_invalid,
290 [SCPCR] = sci_reg_invalid,
291 [SCPDR] = sci_reg_invalid,
295 * Common HSCIF definitions.
297 [SCIx_HSCIF_REGTYPE] = {
298 [SCSMR] = { 0x00, 16 },
299 [SCBRR] = { 0x04, 8 },
300 [SCSCR] = { 0x08, 16 },
301 [SCxTDR] = { 0x0c, 8 },
302 [SCxSR] = { 0x10, 16 },
303 [SCxRDR] = { 0x14, 8 },
304 [SCFCR] = { 0x18, 16 },
305 [SCFDR] = { 0x1c, 16 },
306 [SCTFDR] = sci_reg_invalid,
307 [SCRFDR] = sci_reg_invalid,
308 [SCSPTR] = { 0x20, 16 },
309 [SCLSR] = { 0x24, 16 },
310 [HSSRR] = { 0x40, 16 },
311 [SCPCR] = sci_reg_invalid,
312 [SCPDR] = sci_reg_invalid,
316 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
319 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x04, 8 },
322 [SCSCR] = { 0x08, 16 },
323 [SCxTDR] = { 0x0c, 8 },
324 [SCxSR] = { 0x10, 16 },
325 [SCxRDR] = { 0x14, 8 },
326 [SCFCR] = { 0x18, 16 },
327 [SCFDR] = { 0x1c, 16 },
328 [SCTFDR] = sci_reg_invalid,
329 [SCRFDR] = sci_reg_invalid,
330 [SCSPTR] = sci_reg_invalid,
331 [SCLSR] = { 0x24, 16 },
332 [HSSRR] = sci_reg_invalid,
333 [SCPCR] = sci_reg_invalid,
334 [SCPDR] = sci_reg_invalid,
338 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
341 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
342 [SCSMR] = { 0x00, 16 },
343 [SCBRR] = { 0x04, 8 },
344 [SCSCR] = { 0x08, 16 },
345 [SCxTDR] = { 0x0c, 8 },
346 [SCxSR] = { 0x10, 16 },
347 [SCxRDR] = { 0x14, 8 },
348 [SCFCR] = { 0x18, 16 },
349 [SCFDR] = { 0x1c, 16 },
350 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
351 [SCRFDR] = { 0x20, 16 },
352 [SCSPTR] = { 0x24, 16 },
353 [SCLSR] = { 0x28, 16 },
354 [HSSRR] = sci_reg_invalid,
355 [SCPCR] = sci_reg_invalid,
356 [SCPDR] = sci_reg_invalid,
360 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
363 [SCIx_SH7705_SCIF_REGTYPE] = {
364 [SCSMR] = { 0x00, 16 },
365 [SCBRR] = { 0x04, 8 },
366 [SCSCR] = { 0x08, 16 },
367 [SCxTDR] = { 0x20, 8 },
368 [SCxSR] = { 0x14, 16 },
369 [SCxRDR] = { 0x24, 8 },
370 [SCFCR] = { 0x18, 16 },
371 [SCFDR] = { 0x1c, 16 },
372 [SCTFDR] = sci_reg_invalid,
373 [SCRFDR] = sci_reg_invalid,
374 [SCSPTR] = sci_reg_invalid,
375 [SCLSR] = sci_reg_invalid,
376 [HSSRR] = sci_reg_invalid,
377 [SCPCR] = sci_reg_invalid,
378 [SCPDR] = sci_reg_invalid,
382 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
385 * The "offset" here is rather misleading, in that it refers to an enum
386 * value relative to the port mapping rather than the fixed offset
387 * itself, which needs to be manually retrieved from the platform's
388 * register map for the given port.
390 static unsigned int sci_serial_in(struct uart_port *p, int offset)
392 const struct plat_sci_reg *reg = sci_getreg(p, offset);
395 return ioread8(p->membase + (reg->offset << p->regshift));
396 else if (reg->size == 16)
397 return ioread16(p->membase + (reg->offset << p->regshift));
399 WARN(1, "Invalid register access\n");
404 static void sci_serial_out(struct uart_port *p, int offset, int value)
406 const struct plat_sci_reg *reg = sci_getreg(p, offset);
409 iowrite8(value, p->membase + (reg->offset << p->regshift));
410 else if (reg->size == 16)
411 iowrite16(value, p->membase + (reg->offset << p->regshift));
413 WARN(1, "Invalid register access\n");
416 static int sci_probe_regmap(struct plat_sci_port *cfg)
420 cfg->regtype = SCIx_SCI_REGTYPE;
423 cfg->regtype = SCIx_IRDA_REGTYPE;
426 cfg->regtype = SCIx_SCIFA_REGTYPE;
429 cfg->regtype = SCIx_SCIFB_REGTYPE;
433 * The SH-4 is a bit of a misnomer here, although that's
434 * where this particular port layout originated. This
435 * configuration (or some slight variation thereof)
436 * remains the dominant model for all SCIFs.
438 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
441 cfg->regtype = SCIx_HSCIF_REGTYPE;
444 pr_err("Can't probe register map for given port\n");
451 static void sci_port_enable(struct sci_port *sci_port)
453 if (!sci_port->port.dev)
456 pm_runtime_get_sync(sci_port->port.dev);
458 clk_prepare_enable(sci_port->fclk);
459 sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
462 static void sci_port_disable(struct sci_port *sci_port)
464 if (!sci_port->port.dev)
467 /* Cancel the break timer to ensure that the timer handler will not try
468 * to access the hardware with clocks and power disabled. Reset the
469 * break flag to make the break debouncing state machine ready for the
472 del_timer_sync(&sci_port->break_timer);
473 sci_port->break_flag = 0;
475 clk_disable_unprepare(sci_port->fclk);
477 pm_runtime_put_sync(sci_port->port.dev);
480 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
483 * Not all ports (such as SCIFA) will support REIE. Rather than
484 * special-casing the port type, we check the port initialization
485 * IRQ enable mask to see whether the IRQ is desired at all. If
486 * it's unset, it's logically inferred that there's no point in
489 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
492 static void sci_start_tx(struct uart_port *port)
494 struct sci_port *s = to_sci_port(port);
497 #ifdef CONFIG_SERIAL_SH_SCI_DMA
498 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
499 u16 new, scr = serial_port_in(port, SCSCR);
501 new = scr | SCSCR_TDRQE;
503 new = scr & ~SCSCR_TDRQE;
505 serial_port_out(port, SCSCR, new);
508 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
509 dma_submit_error(s->cookie_tx)) {
511 schedule_work(&s->work_tx);
515 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
516 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
517 ctrl = serial_port_in(port, SCSCR);
518 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
522 static void sci_stop_tx(struct uart_port *port)
526 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
527 ctrl = serial_port_in(port, SCSCR);
529 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
530 ctrl &= ~SCSCR_TDRQE;
534 serial_port_out(port, SCSCR, ctrl);
537 static void sci_start_rx(struct uart_port *port)
541 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
544 ctrl &= ~SCSCR_RDRQE;
546 serial_port_out(port, SCSCR, ctrl);
549 static void sci_stop_rx(struct uart_port *port)
553 ctrl = serial_port_in(port, SCSCR);
555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
556 ctrl &= ~SCSCR_RDRQE;
558 ctrl &= ~port_rx_irq_mask(port);
560 serial_port_out(port, SCSCR, ctrl);
563 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
565 if (port->type == PORT_SCI) {
566 /* Just store the mask */
567 serial_port_out(port, SCxSR, mask);
568 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
569 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
570 /* Only clear the status bits we want to clear */
571 serial_port_out(port, SCxSR,
572 serial_port_in(port, SCxSR) & mask);
574 /* Store the mask, clear parity/framing errors */
575 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
579 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
581 #ifdef CONFIG_CONSOLE_POLL
582 static int sci_poll_get_char(struct uart_port *port)
584 unsigned short status;
588 status = serial_port_in(port, SCxSR);
589 if (status & SCxSR_ERRORS(port)) {
590 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
596 if (!(status & SCxSR_RDxF(port)))
599 c = serial_port_in(port, SCxRDR);
602 serial_port_in(port, SCxSR);
603 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
609 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
611 unsigned short status;
614 status = serial_port_in(port, SCxSR);
615 } while (!(status & SCxSR_TDxE(port)));
617 serial_port_out(port, SCxTDR, c);
618 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
620 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
622 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
624 struct sci_port *s = to_sci_port(port);
625 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
628 * Use port-specific handler if provided.
630 if (s->cfg->ops && s->cfg->ops->init_pins) {
631 s->cfg->ops->init_pins(port, cflag);
636 * For the generic path SCSPTR is necessary. Bail out if that's
642 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
643 ((!(cflag & CRTSCTS)))) {
644 unsigned short status;
646 status = serial_port_in(port, SCSPTR);
647 status &= ~SCSPTR_CTSIO;
648 status |= SCSPTR_RTSIO;
649 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
653 static int sci_txfill(struct uart_port *port)
655 const struct plat_sci_reg *reg;
657 reg = sci_getreg(port, SCTFDR);
659 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
661 reg = sci_getreg(port, SCFDR);
663 return serial_port_in(port, SCFDR) >> 8;
665 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
668 static int sci_txroom(struct uart_port *port)
670 return port->fifosize - sci_txfill(port);
673 static int sci_rxfill(struct uart_port *port)
675 const struct plat_sci_reg *reg;
677 reg = sci_getreg(port, SCRFDR);
679 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
681 reg = sci_getreg(port, SCFDR);
683 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
685 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
689 * SCI helper for checking the state of the muxed port/RXD pins.
691 static inline int sci_rxd_in(struct uart_port *port)
693 struct sci_port *s = to_sci_port(port);
695 if (s->cfg->port_reg <= 0)
698 /* Cast for ARM damage */
699 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
702 /* ********************************************************************** *
703 * the interrupt related routines *
704 * ********************************************************************** */
706 static void sci_transmit_chars(struct uart_port *port)
708 struct circ_buf *xmit = &port->state->xmit;
709 unsigned int stopped = uart_tx_stopped(port);
710 unsigned short status;
714 status = serial_port_in(port, SCxSR);
715 if (!(status & SCxSR_TDxE(port))) {
716 ctrl = serial_port_in(port, SCSCR);
717 if (uart_circ_empty(xmit))
721 serial_port_out(port, SCSCR, ctrl);
725 count = sci_txroom(port);
733 } else if (!uart_circ_empty(xmit) && !stopped) {
734 c = xmit->buf[xmit->tail];
735 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
740 serial_port_out(port, SCxTDR, c);
743 } while (--count > 0);
745 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
747 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
748 uart_write_wakeup(port);
749 if (uart_circ_empty(xmit)) {
752 ctrl = serial_port_in(port, SCSCR);
754 if (port->type != PORT_SCI) {
755 serial_port_in(port, SCxSR); /* Dummy read */
756 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
760 serial_port_out(port, SCSCR, ctrl);
764 /* On SH3, SCIF may read end-of-break as a space->mark char */
765 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
767 static void sci_receive_chars(struct uart_port *port)
769 struct sci_port *sci_port = to_sci_port(port);
770 struct tty_port *tport = &port->state->port;
771 int i, count, copied = 0;
772 unsigned short status;
775 status = serial_port_in(port, SCxSR);
776 if (!(status & SCxSR_RDxF(port)))
780 /* Don't copy more bytes than there is room for in the buffer */
781 count = tty_buffer_request_room(tport, sci_rxfill(port));
783 /* If for any reason we can't copy more data, we're done! */
787 if (port->type == PORT_SCI) {
788 char c = serial_port_in(port, SCxRDR);
789 if (uart_handle_sysrq_char(port, c) ||
790 sci_port->break_flag)
793 tty_insert_flip_char(tport, c, TTY_NORMAL);
795 for (i = 0; i < count; i++) {
796 char c = serial_port_in(port, SCxRDR);
798 status = serial_port_in(port, SCxSR);
799 #if defined(CONFIG_CPU_SH3)
800 /* Skip "chars" during break */
801 if (sci_port->break_flag) {
803 (status & SCxSR_FER(port))) {
808 /* Nonzero => end-of-break */
809 dev_dbg(port->dev, "debounce<%02x>\n", c);
810 sci_port->break_flag = 0;
817 #endif /* CONFIG_CPU_SH3 */
818 if (uart_handle_sysrq_char(port, c)) {
823 /* Store data and status */
824 if (status & SCxSR_FER(port)) {
826 port->icount.frame++;
827 dev_notice(port->dev, "frame error\n");
828 } else if (status & SCxSR_PER(port)) {
830 port->icount.parity++;
831 dev_notice(port->dev, "parity error\n");
835 tty_insert_flip_char(tport, c, flag);
839 serial_port_in(port, SCxSR); /* dummy read */
840 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
843 port->icount.rx += count;
847 /* Tell the rest of the system the news. New characters! */
848 tty_flip_buffer_push(tport);
850 serial_port_in(port, SCxSR); /* dummy read */
851 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
855 #define SCI_BREAK_JIFFIES (HZ/20)
858 * The sci generates interrupts during the break,
859 * 1 per millisecond or so during the break period, for 9600 baud.
860 * So dont bother disabling interrupts.
861 * But dont want more than 1 break event.
862 * Use a kernel timer to periodically poll the rx line until
863 * the break is finished.
865 static inline void sci_schedule_break_timer(struct sci_port *port)
867 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
870 /* Ensure that two consecutive samples find the break over. */
871 static void sci_break_timer(unsigned long data)
873 struct sci_port *port = (struct sci_port *)data;
875 if (sci_rxd_in(&port->port) == 0) {
876 port->break_flag = 1;
877 sci_schedule_break_timer(port);
878 } else if (port->break_flag == 1) {
880 port->break_flag = 2;
881 sci_schedule_break_timer(port);
883 port->break_flag = 0;
886 static int sci_handle_errors(struct uart_port *port)
889 unsigned short status = serial_port_in(port, SCxSR);
890 struct tty_port *tport = &port->state->port;
891 struct sci_port *s = to_sci_port(port);
893 /* Handle overruns */
894 if (status & s->overrun_mask) {
895 port->icount.overrun++;
898 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
901 dev_notice(port->dev, "overrun error\n");
904 if (status & SCxSR_FER(port)) {
905 if (sci_rxd_in(port) == 0) {
906 /* Notify of BREAK */
907 struct sci_port *sci_port = to_sci_port(port);
909 if (!sci_port->break_flag) {
912 sci_port->break_flag = 1;
913 sci_schedule_break_timer(sci_port);
915 /* Do sysrq handling. */
916 if (uart_handle_break(port))
919 dev_dbg(port->dev, "BREAK detected\n");
921 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
927 port->icount.frame++;
929 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
932 dev_notice(port->dev, "frame error\n");
936 if (status & SCxSR_PER(port)) {
938 port->icount.parity++;
940 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
943 dev_notice(port->dev, "parity error\n");
947 tty_flip_buffer_push(tport);
952 static int sci_handle_fifo_overrun(struct uart_port *port)
954 struct tty_port *tport = &port->state->port;
955 struct sci_port *s = to_sci_port(port);
956 const struct plat_sci_reg *reg;
960 reg = sci_getreg(port, s->overrun_reg);
964 status = serial_port_in(port, s->overrun_reg);
965 if (status & s->overrun_mask) {
966 status &= ~s->overrun_mask;
967 serial_port_out(port, s->overrun_reg, status);
969 port->icount.overrun++;
971 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
972 tty_flip_buffer_push(tport);
974 dev_dbg(port->dev, "overrun error\n");
981 static int sci_handle_breaks(struct uart_port *port)
984 unsigned short status = serial_port_in(port, SCxSR);
985 struct tty_port *tport = &port->state->port;
986 struct sci_port *s = to_sci_port(port);
988 if (uart_handle_break(port))
991 if (!s->break_flag && status & SCxSR_BRK(port)) {
992 #if defined(CONFIG_CPU_SH3)
999 /* Notify of BREAK */
1000 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1003 dev_dbg(port->dev, "BREAK detected\n");
1007 tty_flip_buffer_push(tport);
1009 copied += sci_handle_fifo_overrun(port);
1014 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1015 static void sci_dma_tx_complete(void *arg)
1017 struct sci_port *s = arg;
1018 struct uart_port *port = &s->port;
1019 struct circ_buf *xmit = &port->state->xmit;
1020 unsigned long flags;
1022 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1024 spin_lock_irqsave(&port->lock, flags);
1026 xmit->tail += s->tx_dma_len;
1027 xmit->tail &= UART_XMIT_SIZE - 1;
1029 port->icount.tx += s->tx_dma_len;
1031 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1032 uart_write_wakeup(port);
1034 if (!uart_circ_empty(xmit)) {
1036 schedule_work(&s->work_tx);
1038 s->cookie_tx = -EINVAL;
1039 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1040 u16 ctrl = serial_port_in(port, SCSCR);
1041 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1045 spin_unlock_irqrestore(&port->lock, flags);
1048 /* Locking: called with port lock held */
1049 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1051 struct uart_port *port = &s->port;
1052 struct tty_port *tport = &port->state->port;
1055 copied = tty_insert_flip_string(tport, buf, count);
1056 if (copied < count) {
1057 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1059 port->icount.buf_overrun++;
1062 port->icount.rx += copied;
1067 static int sci_dma_rx_find_active(struct sci_port *s)
1071 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1072 if (s->active_rx == s->cookie_rx[i])
1075 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1080 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1082 struct dma_chan *chan = s->chan_rx;
1083 struct uart_port *port = &s->port;
1084 unsigned long flags;
1086 spin_lock_irqsave(&port->lock, flags);
1088 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1089 spin_unlock_irqrestore(&port->lock, flags);
1090 dmaengine_terminate_all(chan);
1091 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1092 sg_dma_address(&s->sg_rx[0]));
1093 dma_release_channel(chan);
1098 static void sci_dma_rx_complete(void *arg)
1100 struct sci_port *s = arg;
1101 struct dma_chan *chan = s->chan_rx;
1102 struct uart_port *port = &s->port;
1103 struct dma_async_tx_descriptor *desc;
1104 unsigned long flags;
1105 int active, count = 0;
1107 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1110 spin_lock_irqsave(&port->lock, flags);
1112 active = sci_dma_rx_find_active(s);
1114 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1116 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1119 tty_flip_buffer_push(&port->state->port);
1121 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1123 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1127 desc->callback = sci_dma_rx_complete;
1128 desc->callback_param = s;
1129 s->cookie_rx[active] = dmaengine_submit(desc);
1130 if (dma_submit_error(s->cookie_rx[active]))
1133 s->active_rx = s->cookie_rx[!active];
1135 dma_async_issue_pending(chan);
1137 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1138 __func__, s->cookie_rx[active], active, s->active_rx);
1139 spin_unlock_irqrestore(&port->lock, flags);
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1145 sci_rx_dma_release(s, true);
1148 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1150 struct dma_chan *chan = s->chan_tx;
1151 struct uart_port *port = &s->port;
1152 unsigned long flags;
1154 spin_lock_irqsave(&port->lock, flags);
1156 s->cookie_tx = -EINVAL;
1157 spin_unlock_irqrestore(&port->lock, flags);
1158 dmaengine_terminate_all(chan);
1159 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1161 dma_release_channel(chan);
1166 static void sci_submit_rx(struct sci_port *s)
1168 struct dma_chan *chan = s->chan_rx;
1171 for (i = 0; i < 2; i++) {
1172 struct scatterlist *sg = &s->sg_rx[i];
1173 struct dma_async_tx_descriptor *desc;
1175 desc = dmaengine_prep_slave_sg(chan,
1176 sg, 1, DMA_DEV_TO_MEM,
1177 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1181 desc->callback = sci_dma_rx_complete;
1182 desc->callback_param = s;
1183 s->cookie_rx[i] = dmaengine_submit(desc);
1184 if (dma_submit_error(s->cookie_rx[i]))
1187 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1188 s->cookie_rx[i], i);
1191 s->active_rx = s->cookie_rx[0];
1193 dma_async_issue_pending(chan);
1198 dmaengine_terminate_all(chan);
1199 for (i = 0; i < 2; i++)
1200 s->cookie_rx[i] = -EINVAL;
1201 s->active_rx = -EINVAL;
1202 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1203 sci_rx_dma_release(s, true);
1206 static void work_fn_tx(struct work_struct *work)
1208 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1209 struct dma_async_tx_descriptor *desc;
1210 struct dma_chan *chan = s->chan_tx;
1211 struct uart_port *port = &s->port;
1212 struct circ_buf *xmit = &port->state->xmit;
1217 * Port xmit buffer is already mapped, and it is one page... Just adjust
1218 * offsets and lengths. Since it is a circular buffer, we have to
1219 * transmit till the end, and then the rest. Take the port lock to get a
1220 * consistent xmit buffer state.
1222 spin_lock_irq(&port->lock);
1223 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1224 s->tx_dma_len = min_t(unsigned int,
1225 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1226 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1227 spin_unlock_irq(&port->lock);
1229 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1231 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1233 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1235 sci_tx_dma_release(s, true);
1239 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1242 spin_lock_irq(&port->lock);
1243 desc->callback = sci_dma_tx_complete;
1244 desc->callback_param = s;
1245 spin_unlock_irq(&port->lock);
1246 s->cookie_tx = dmaengine_submit(desc);
1247 if (dma_submit_error(s->cookie_tx)) {
1248 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1250 sci_tx_dma_release(s, true);
1254 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1255 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1257 dma_async_issue_pending(chan);
1260 static void rx_timer_fn(unsigned long arg)
1262 struct sci_port *s = (struct sci_port *)arg;
1263 struct dma_chan *chan = s->chan_rx;
1264 struct uart_port *port = &s->port;
1265 struct dma_tx_state state;
1266 enum dma_status status;
1267 unsigned long flags;
1272 spin_lock_irqsave(&port->lock, flags);
1274 dev_dbg(port->dev, "DMA Rx timed out\n");
1276 active = sci_dma_rx_find_active(s);
1278 spin_unlock_irqrestore(&port->lock, flags);
1282 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1283 if (status == DMA_COMPLETE) {
1284 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1285 s->active_rx, active);
1286 spin_unlock_irqrestore(&port->lock, flags);
1288 /* Let packet complete handler take care of the packet */
1292 dmaengine_pause(chan);
1295 * sometimes DMA transfer doesn't stop even if it is stopped and
1296 * data keeps on coming until transaction is complete so check
1297 * for DMA_COMPLETE again
1298 * Let packet complete handler take care of the packet
1300 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1301 if (status == DMA_COMPLETE) {
1302 spin_unlock_irqrestore(&port->lock, flags);
1303 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1307 /* Handle incomplete DMA receive */
1308 dmaengine_terminate_all(s->chan_rx);
1309 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1310 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1314 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1316 tty_flip_buffer_push(&port->state->port);
1319 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1322 /* Direct new serial port interrupts back to CPU */
1323 scr = serial_port_in(port, SCSCR);
1324 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1325 scr &= ~SCSCR_RDRQE;
1326 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1328 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1330 spin_unlock_irqrestore(&port->lock, flags);
1333 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1334 enum dma_transfer_direction dir,
1337 dma_cap_mask_t mask;
1338 struct dma_chan *chan;
1339 struct dma_slave_config cfg;
1343 dma_cap_set(DMA_SLAVE, mask);
1345 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1346 (void *)(unsigned long)id, port->dev,
1347 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1350 "dma_request_slave_channel_compat failed\n");
1354 memset(&cfg, 0, sizeof(cfg));
1355 cfg.direction = dir;
1356 if (dir == DMA_MEM_TO_DEV) {
1357 cfg.dst_addr = port->mapbase +
1358 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1359 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1361 cfg.src_addr = port->mapbase +
1362 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1363 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1366 ret = dmaengine_slave_config(chan, &cfg);
1368 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1369 dma_release_channel(chan);
1376 static void sci_request_dma(struct uart_port *port)
1378 struct sci_port *s = to_sci_port(port);
1379 struct dma_chan *chan;
1381 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1383 if (!port->dev->of_node &&
1384 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1387 s->cookie_tx = -EINVAL;
1388 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1389 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1392 /* UART circular tx buffer is an aligned page. */
1393 s->tx_dma_addr = dma_map_single(chan->device->dev,
1394 port->state->xmit.buf,
1397 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1398 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1399 dma_release_channel(chan);
1402 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1403 __func__, UART_XMIT_SIZE,
1404 port->state->xmit.buf, &s->tx_dma_addr);
1407 INIT_WORK(&s->work_tx, work_fn_tx);
1410 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1411 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1419 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1420 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1424 "Failed to allocate Rx dma buffer, using PIO\n");
1425 dma_release_channel(chan);
1430 for (i = 0; i < 2; i++) {
1431 struct scatterlist *sg = &s->sg_rx[i];
1433 sg_init_table(sg, 1);
1435 sg_dma_address(sg) = dma;
1436 sg->length = s->buf_len_rx;
1438 buf += s->buf_len_rx;
1439 dma += s->buf_len_rx;
1442 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1444 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1449 static void sci_free_dma(struct uart_port *port)
1451 struct sci_port *s = to_sci_port(port);
1454 sci_tx_dma_release(s, false);
1456 sci_rx_dma_release(s, false);
1459 static inline void sci_request_dma(struct uart_port *port)
1463 static inline void sci_free_dma(struct uart_port *port)
1468 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1470 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1471 struct uart_port *port = ptr;
1472 struct sci_port *s = to_sci_port(port);
1475 u16 scr = serial_port_in(port, SCSCR);
1476 u16 ssr = serial_port_in(port, SCxSR);
1478 /* Disable future Rx interrupts */
1479 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1480 disable_irq_nosync(irq);
1486 serial_port_out(port, SCSCR, scr);
1487 /* Clear current interrupt */
1488 serial_port_out(port, SCxSR,
1489 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1490 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1491 jiffies, s->rx_timeout);
1492 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1498 /* I think sci_receive_chars has to be called irrespective
1499 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1502 sci_receive_chars(ptr);
1507 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1509 struct uart_port *port = ptr;
1510 unsigned long flags;
1512 spin_lock_irqsave(&port->lock, flags);
1513 sci_transmit_chars(port);
1514 spin_unlock_irqrestore(&port->lock, flags);
1519 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1521 struct uart_port *port = ptr;
1522 struct sci_port *s = to_sci_port(port);
1525 if (port->type == PORT_SCI) {
1526 if (sci_handle_errors(port)) {
1527 /* discard character in rx buffer */
1528 serial_port_in(port, SCxSR);
1529 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1532 sci_handle_fifo_overrun(port);
1534 sci_receive_chars(ptr);
1537 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1539 /* Kick the transmission */
1541 sci_tx_interrupt(irq, ptr);
1546 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1548 struct uart_port *port = ptr;
1551 sci_handle_breaks(port);
1552 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1557 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1559 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1560 struct uart_port *port = ptr;
1561 struct sci_port *s = to_sci_port(port);
1562 irqreturn_t ret = IRQ_NONE;
1564 ssr_status = serial_port_in(port, SCxSR);
1565 scr_status = serial_port_in(port, SCSCR);
1566 if (s->overrun_reg == SCxSR)
1567 orer_status = ssr_status;
1569 if (sci_getreg(port, s->overrun_reg)->size)
1570 orer_status = serial_port_in(port, s->overrun_reg);
1573 err_enabled = scr_status & port_rx_irq_mask(port);
1576 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1578 ret = sci_tx_interrupt(irq, ptr);
1581 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1584 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1585 (scr_status & SCSCR_RIE))
1586 ret = sci_rx_interrupt(irq, ptr);
1588 /* Error Interrupt */
1589 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1590 ret = sci_er_interrupt(irq, ptr);
1592 /* Break Interrupt */
1593 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1594 ret = sci_br_interrupt(irq, ptr);
1596 /* Overrun Interrupt */
1597 if (orer_status & s->overrun_mask) {
1598 sci_handle_fifo_overrun(port);
1606 * Here we define a transition notifier so that we can update all of our
1607 * ports' baud rate when the peripheral clock changes.
1609 static int sci_notifier(struct notifier_block *self,
1610 unsigned long phase, void *p)
1612 struct sci_port *sci_port;
1613 unsigned long flags;
1615 sci_port = container_of(self, struct sci_port, freq_transition);
1617 if (phase == CPUFREQ_POSTCHANGE) {
1618 struct uart_port *port = &sci_port->port;
1620 spin_lock_irqsave(&port->lock, flags);
1621 port->uartclk = clk_get_rate(sci_port->fclk);
1622 spin_unlock_irqrestore(&port->lock, flags);
1628 static const struct sci_irq_desc {
1630 irq_handler_t handler;
1631 } sci_irq_desc[] = {
1633 * Split out handlers, the default case.
1637 .handler = sci_er_interrupt,
1642 .handler = sci_rx_interrupt,
1647 .handler = sci_tx_interrupt,
1652 .handler = sci_br_interrupt,
1656 * Special muxed handler.
1660 .handler = sci_mpxed_interrupt,
1664 static int sci_request_irq(struct sci_port *port)
1666 struct uart_port *up = &port->port;
1669 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1670 const struct sci_irq_desc *desc;
1673 if (SCIx_IRQ_IS_MUXED(port)) {
1677 irq = port->irqs[i];
1680 * Certain port types won't support all of the
1681 * available interrupt sources.
1683 if (unlikely(irq < 0))
1687 desc = sci_irq_desc + i;
1688 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1689 dev_name(up->dev), desc->desc);
1690 if (!port->irqstr[j])
1693 ret = request_irq(irq, desc->handler, up->irqflags,
1694 port->irqstr[j], port);
1695 if (unlikely(ret)) {
1696 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1705 free_irq(port->irqs[i], port);
1709 kfree(port->irqstr[j]);
1714 static void sci_free_irq(struct sci_port *port)
1719 * Intentionally in reverse order so we iterate over the muxed
1722 for (i = 0; i < SCIx_NR_IRQS; i++) {
1723 int irq = port->irqs[i];
1726 * Certain port types won't support all of the available
1727 * interrupt sources.
1729 if (unlikely(irq < 0))
1732 free_irq(port->irqs[i], port);
1733 kfree(port->irqstr[i]);
1735 if (SCIx_IRQ_IS_MUXED(port)) {
1736 /* If there's only one IRQ, we're done. */
1742 static unsigned int sci_tx_empty(struct uart_port *port)
1744 unsigned short status = serial_port_in(port, SCxSR);
1745 unsigned short in_tx_fifo = sci_txfill(port);
1747 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1751 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1752 * CTS/RTS is supported in hardware by at least one port and controlled
1753 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1754 * handled via the ->init_pins() op, which is a bit of a one-way street,
1755 * lacking any ability to defer pin control -- this will later be
1756 * converted over to the GPIO framework).
1758 * Other modes (such as loopback) are supported generically on certain
1759 * port types, but not others. For these it's sufficient to test for the
1760 * existence of the support register and simply ignore the port type.
1762 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1764 if (mctrl & TIOCM_LOOP) {
1765 const struct plat_sci_reg *reg;
1768 * Standard loopback mode for SCFCR ports.
1770 reg = sci_getreg(port, SCFCR);
1772 serial_port_out(port, SCFCR,
1773 serial_port_in(port, SCFCR) |
1778 static unsigned int sci_get_mctrl(struct uart_port *port)
1781 * CTS/RTS is handled in hardware when supported, while nothing
1782 * else is wired up. Keep it simple and simply assert DSR/CAR.
1784 return TIOCM_DSR | TIOCM_CAR;
1787 static void sci_break_ctl(struct uart_port *port, int break_state)
1789 struct sci_port *s = to_sci_port(port);
1790 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1791 unsigned short scscr, scsptr;
1793 /* check wheter the port has SCSPTR */
1796 * Not supported by hardware. Most parts couple break and rx
1797 * interrupts together, with break detection always enabled.
1802 scsptr = serial_port_in(port, SCSPTR);
1803 scscr = serial_port_in(port, SCSCR);
1805 if (break_state == -1) {
1806 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1809 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1813 serial_port_out(port, SCSPTR, scsptr);
1814 serial_port_out(port, SCSCR, scscr);
1817 static int sci_startup(struct uart_port *port)
1819 struct sci_port *s = to_sci_port(port);
1820 unsigned long flags;
1823 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1825 ret = sci_request_irq(s);
1826 if (unlikely(ret < 0))
1829 sci_request_dma(port);
1831 spin_lock_irqsave(&port->lock, flags);
1834 spin_unlock_irqrestore(&port->lock, flags);
1839 static void sci_shutdown(struct uart_port *port)
1841 struct sci_port *s = to_sci_port(port);
1842 unsigned long flags;
1844 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1846 spin_lock_irqsave(&port->lock, flags);
1849 spin_unlock_irqrestore(&port->lock, flags);
1851 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1853 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1855 del_timer_sync(&s->rx_timer);
1863 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1866 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1869 /* calculate sample rate, BRR, and clock select for HSCIF */
1870 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, int *brr,
1871 unsigned int *srr, unsigned int *cks)
1873 int sr, c, br, err, recv_margin;
1874 int min_err = 1000; /* 100% */
1875 int recv_max_margin = 0;
1877 /* Find the combination of sample rate and clock select with the
1878 smallest deviation from the desired baud rate. */
1879 for (sr = 8; sr <= 32; sr++) {
1880 for (c = 0; c <= 3; c++) {
1881 /* integerized formulas from HSCIF documentation */
1882 br = DIV_ROUND_CLOSEST(freq, (sr *
1883 (1 << (2 * c + 1)) * bps)) - 1;
1884 br = clamp(br, 0, 255);
1885 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1886 (1 << (2 * c + 1)) / 1000)) -
1889 * M: Receive margin (%)
1890 * N: Ratio of bit rate to clock (N = sampling rate)
1891 * D: Clock duty (D = 0 to 1.0)
1892 * L: Frame length (L = 9 to 12)
1893 * F: Absolute value of clock frequency deviation
1895 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1896 * (|D - 0.5| / N * (1 + F))|
1897 * NOTE: Usually, treat D for 0.5, F is 0 by this
1900 recv_margin = abs((500 -
1901 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1902 if (abs(min_err) > abs(err)) {
1904 recv_max_margin = recv_margin;
1905 } else if ((min_err == err) &&
1906 (recv_margin > recv_max_margin))
1907 recv_max_margin = recv_margin;
1917 if (min_err == 1000) {
1926 static void sci_reset(struct uart_port *port)
1928 const struct plat_sci_reg *reg;
1929 unsigned int status;
1932 status = serial_port_in(port, SCxSR);
1933 } while (!(status & SCxSR_TEND(port)));
1935 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1937 reg = sci_getreg(port, SCFCR);
1939 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1942 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1943 struct ktermios *old)
1945 struct sci_port *s = to_sci_port(port);
1946 const struct plat_sci_reg *reg;
1947 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1949 unsigned int srr = 15;
1951 if ((termios->c_cflag & CSIZE) == CS7)
1952 smr_val |= SCSMR_CHR;
1953 if (termios->c_cflag & PARENB)
1954 smr_val |= SCSMR_PE;
1955 if (termios->c_cflag & PARODD)
1956 smr_val |= SCSMR_PE | SCSMR_ODD;
1957 if (termios->c_cflag & CSTOPB)
1958 smr_val |= SCSMR_STOP;
1961 * earlyprintk comes here early on with port->uartclk set to zero.
1962 * the clock framework is not up and running at this point so here
1963 * we assume that 115200 is the maximum baud rate. please note that
1964 * the baud rate is not programmed during earlyprintk - it is assumed
1965 * that the previous boot loader has enabled required clocks and
1966 * setup the baud rate generator hardware for us already.
1968 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1970 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1971 if (likely(baud && port->uartclk)) {
1972 if (s->cfg->type == PORT_HSCIF) {
1973 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1976 t = sci_scbrr_calc(s, baud, port->uartclk);
1977 for (cks = 0; t >= 256 && cks <= 3; cks++)
1986 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1988 uart_update_timeout(port, termios->c_cflag, baud);
1990 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1991 __func__, smr_val, cks, t, s->cfg->scscr);
1994 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1995 serial_port_out(port, SCBRR, t);
1996 reg = sci_getreg(port, HSSRR);
1998 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1999 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
2001 serial_port_out(port, SCSMR, smr_val);
2003 sci_init_pins(port, termios->c_cflag);
2005 reg = sci_getreg(port, SCFCR);
2007 unsigned short ctrl = serial_port_in(port, SCFCR);
2009 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2010 if (termios->c_cflag & CRTSCTS)
2017 * As we've done a sci_reset() above, ensure we don't
2018 * interfere with the FIFOs while toggling MCE. As the
2019 * reset values could still be set, simply mask them out.
2021 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2023 serial_port_out(port, SCFCR, ctrl);
2026 serial_port_out(port, SCSCR, s->cfg->scscr);
2028 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2030 * Calculate delay for 2 DMA buffers (4 FIFO).
2031 * See serial_core.c::uart_update_timeout().
2032 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2033 * function calculates 1 jiffie for the data plus 5 jiffies for the
2034 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2035 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2036 * value obtained by this formula is too small. Therefore, if the value
2037 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2042 /* byte size and parity */
2043 switch (termios->c_cflag & CSIZE) {
2058 if (termios->c_cflag & CSTOPB)
2060 if (termios->c_cflag & PARENB)
2062 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2064 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2065 s->rx_timeout * 1000 / HZ, port->timeout);
2066 if (s->rx_timeout < msecs_to_jiffies(20))
2067 s->rx_timeout = msecs_to_jiffies(20);
2071 if ((termios->c_cflag & CREAD) != 0)
2074 sci_port_disable(s);
2077 static void sci_pm(struct uart_port *port, unsigned int state,
2078 unsigned int oldstate)
2080 struct sci_port *sci_port = to_sci_port(port);
2083 case UART_PM_STATE_OFF:
2084 sci_port_disable(sci_port);
2087 sci_port_enable(sci_port);
2092 static const char *sci_type(struct uart_port *port)
2094 switch (port->type) {
2112 static int sci_remap_port(struct uart_port *port)
2114 struct sci_port *sport = to_sci_port(port);
2117 * Nothing to do if there's already an established membase.
2122 if (port->flags & UPF_IOREMAP) {
2123 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2124 if (unlikely(!port->membase)) {
2125 dev_err(port->dev, "can't remap port#%d\n", port->line);
2130 * For the simple (and majority of) cases where we don't
2131 * need to do any remapping, just cast the cookie
2134 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2140 static void sci_release_port(struct uart_port *port)
2142 struct sci_port *sport = to_sci_port(port);
2144 if (port->flags & UPF_IOREMAP) {
2145 iounmap(port->membase);
2146 port->membase = NULL;
2149 release_mem_region(port->mapbase, sport->reg_size);
2152 static int sci_request_port(struct uart_port *port)
2154 struct resource *res;
2155 struct sci_port *sport = to_sci_port(port);
2158 res = request_mem_region(port->mapbase, sport->reg_size,
2159 dev_name(port->dev));
2160 if (unlikely(res == NULL)) {
2161 dev_err(port->dev, "request_mem_region failed.");
2165 ret = sci_remap_port(port);
2166 if (unlikely(ret != 0)) {
2167 release_resource(res);
2174 static void sci_config_port(struct uart_port *port, int flags)
2176 if (flags & UART_CONFIG_TYPE) {
2177 struct sci_port *sport = to_sci_port(port);
2179 port->type = sport->cfg->type;
2180 sci_request_port(port);
2184 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2186 if (ser->baud_base < 2400)
2187 /* No paper tape reader for Mitch.. */
2193 static struct uart_ops sci_uart_ops = {
2194 .tx_empty = sci_tx_empty,
2195 .set_mctrl = sci_set_mctrl,
2196 .get_mctrl = sci_get_mctrl,
2197 .start_tx = sci_start_tx,
2198 .stop_tx = sci_stop_tx,
2199 .stop_rx = sci_stop_rx,
2200 .break_ctl = sci_break_ctl,
2201 .startup = sci_startup,
2202 .shutdown = sci_shutdown,
2203 .set_termios = sci_set_termios,
2206 .release_port = sci_release_port,
2207 .request_port = sci_request_port,
2208 .config_port = sci_config_port,
2209 .verify_port = sci_verify_port,
2210 #ifdef CONFIG_CONSOLE_POLL
2211 .poll_get_char = sci_poll_get_char,
2212 .poll_put_char = sci_poll_put_char,
2216 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2218 /* Get the SCI functional clock. It's called "fck" on ARM. */
2219 sci_port->fclk = clk_get(dev, "fck");
2220 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2221 return -EPROBE_DEFER;
2222 if (!IS_ERR(sci_port->fclk))
2226 * But it used to be called "sci_ick", and we need to maintain DT
2227 * backward compatibility.
2229 sci_port->fclk = clk_get(dev, "sci_ick");
2230 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2231 return -EPROBE_DEFER;
2232 if (!IS_ERR(sci_port->fclk))
2235 /* SH has historically named the clock "sci_fck". */
2236 sci_port->fclk = clk_get(dev, "sci_fck");
2237 if (!IS_ERR(sci_port->fclk))
2241 * Not all SH platforms declare a clock lookup entry for SCI devices,
2242 * in which case we need to get the global "peripheral_clk" clock.
2244 sci_port->fclk = clk_get(dev, "peripheral_clk");
2245 if (!IS_ERR(sci_port->fclk))
2248 dev_err(dev, "failed to get functional clock\n");
2249 return PTR_ERR(sci_port->fclk);
2252 static int sci_init_single(struct platform_device *dev,
2253 struct sci_port *sci_port, unsigned int index,
2254 struct plat_sci_port *p, bool early)
2256 struct uart_port *port = &sci_port->port;
2257 const struct resource *res;
2263 port->ops = &sci_uart_ops;
2264 port->iotype = UPIO_MEM;
2267 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2271 port->mapbase = res->start;
2272 sci_port->reg_size = resource_size(res);
2274 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2275 sci_port->irqs[i] = platform_get_irq(dev, i);
2277 /* The SCI generates several interrupts. They can be muxed together or
2278 * connected to different interrupt lines. In the muxed case only one
2279 * interrupt resource is specified. In the non-muxed case three or four
2280 * interrupt resources are specified, as the BRI interrupt is optional.
2282 if (sci_port->irqs[0] < 0)
2285 if (sci_port->irqs[1] < 0) {
2286 sci_port->irqs[1] = sci_port->irqs[0];
2287 sci_port->irqs[2] = sci_port->irqs[0];
2288 sci_port->irqs[3] = sci_port->irqs[0];
2291 if (p->regtype == SCIx_PROBE_REGTYPE) {
2292 ret = sci_probe_regmap(p);
2299 port->fifosize = 256;
2300 sci_port->overrun_reg = SCxSR;
2301 sci_port->overrun_mask = SCIFA_ORER;
2302 sci_port->sampling_rate = 16;
2305 port->fifosize = 128;
2306 sci_port->overrun_reg = SCLSR;
2307 sci_port->overrun_mask = SCLSR_ORER;
2308 sci_port->sampling_rate = 0;
2311 port->fifosize = 64;
2312 sci_port->overrun_reg = SCxSR;
2313 sci_port->overrun_mask = SCIFA_ORER;
2314 sci_port->sampling_rate = 16;
2317 port->fifosize = 16;
2318 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2319 sci_port->overrun_reg = SCxSR;
2320 sci_port->overrun_mask = SCIFA_ORER;
2321 sci_port->sampling_rate = 16;
2323 sci_port->overrun_reg = SCLSR;
2324 sci_port->overrun_mask = SCLSR_ORER;
2325 sci_port->sampling_rate = 32;
2330 sci_port->overrun_reg = SCxSR;
2331 sci_port->overrun_mask = SCI_ORER;
2332 sci_port->sampling_rate = 32;
2336 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2337 * match the SoC datasheet, this should be investigated. Let platform
2338 * data override the sampling rate for now.
2340 if (p->sampling_rate)
2341 sci_port->sampling_rate = p->sampling_rate;
2344 ret = sci_init_clocks(sci_port, &dev->dev);
2348 port->dev = &dev->dev;
2350 pm_runtime_enable(&dev->dev);
2353 sci_port->break_timer.data = (unsigned long)sci_port;
2354 sci_port->break_timer.function = sci_break_timer;
2355 init_timer(&sci_port->break_timer);
2358 * Establish some sensible defaults for the error detection.
2360 if (p->type == PORT_SCI) {
2361 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2362 sci_port->error_clear = SCI_ERROR_CLEAR;
2364 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2365 sci_port->error_clear = SCIF_ERROR_CLEAR;
2369 * Make the error mask inclusive of overrun detection, if
2372 if (sci_port->overrun_reg == SCxSR) {
2373 sci_port->error_mask |= sci_port->overrun_mask;
2374 sci_port->error_clear &= ~sci_port->overrun_mask;
2377 port->type = p->type;
2378 port->flags = UPF_FIXED_PORT | p->flags;
2379 port->regshift = p->regshift;
2382 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2383 * for the multi-IRQ ports, which is where we are primarily
2384 * concerned with the shutdown path synchronization.
2386 * For the muxed case there's nothing more to do.
2388 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2391 port->serial_in = sci_serial_in;
2392 port->serial_out = sci_serial_out;
2394 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2395 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2396 p->dma_slave_tx, p->dma_slave_rx);
2401 static void sci_cleanup_single(struct sci_port *port)
2403 clk_put(port->fclk);
2405 pm_runtime_disable(port->port.dev);
2408 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2409 static void serial_console_putchar(struct uart_port *port, int ch)
2411 sci_poll_put_char(port, ch);
2415 * Print a string to the serial port trying not to disturb
2416 * any possible real use of the port...
2418 static void serial_console_write(struct console *co, const char *s,
2421 struct sci_port *sci_port = &sci_ports[co->index];
2422 struct uart_port *port = &sci_port->port;
2423 unsigned short bits, ctrl;
2424 unsigned long flags;
2427 local_irq_save(flags);
2430 else if (oops_in_progress)
2431 locked = spin_trylock(&port->lock);
2433 spin_lock(&port->lock);
2435 /* first save the SCSCR then disable the interrupts */
2436 ctrl = serial_port_in(port, SCSCR);
2437 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2439 uart_console_write(port, s, count, serial_console_putchar);
2441 /* wait until fifo is empty and last bit has been transmitted */
2442 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2443 while ((serial_port_in(port, SCxSR) & bits) != bits)
2446 /* restore the SCSCR */
2447 serial_port_out(port, SCSCR, ctrl);
2450 spin_unlock(&port->lock);
2451 local_irq_restore(flags);
2454 static int serial_console_setup(struct console *co, char *options)
2456 struct sci_port *sci_port;
2457 struct uart_port *port;
2465 * Refuse to handle any bogus ports.
2467 if (co->index < 0 || co->index >= SCI_NPORTS)
2470 sci_port = &sci_ports[co->index];
2471 port = &sci_port->port;
2474 * Refuse to handle uninitialized ports.
2479 ret = sci_remap_port(port);
2480 if (unlikely(ret != 0))
2484 uart_parse_options(options, &baud, &parity, &bits, &flow);
2486 return uart_set_options(port, co, baud, parity, bits, flow);
2489 static struct console serial_console = {
2491 .device = uart_console_device,
2492 .write = serial_console_write,
2493 .setup = serial_console_setup,
2494 .flags = CON_PRINTBUFFER,
2496 .data = &sci_uart_driver,
2499 static struct console early_serial_console = {
2500 .name = "early_ttySC",
2501 .write = serial_console_write,
2502 .flags = CON_PRINTBUFFER,
2506 static char early_serial_buf[32];
2508 static int sci_probe_earlyprintk(struct platform_device *pdev)
2510 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2512 if (early_serial_console.data)
2515 early_serial_console.index = pdev->id;
2517 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2519 serial_console_setup(&early_serial_console, early_serial_buf);
2521 if (!strstr(early_serial_buf, "keep"))
2522 early_serial_console.flags |= CON_BOOT;
2524 register_console(&early_serial_console);
2528 #define SCI_CONSOLE (&serial_console)
2531 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2536 #define SCI_CONSOLE NULL
2538 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2540 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2542 static struct uart_driver sci_uart_driver = {
2543 .owner = THIS_MODULE,
2544 .driver_name = "sci",
2545 .dev_name = "ttySC",
2547 .minor = SCI_MINOR_START,
2549 .cons = SCI_CONSOLE,
2552 static int sci_remove(struct platform_device *dev)
2554 struct sci_port *port = platform_get_drvdata(dev);
2556 cpufreq_unregister_notifier(&port->freq_transition,
2557 CPUFREQ_TRANSITION_NOTIFIER);
2559 uart_remove_one_port(&sci_uart_driver, &port->port);
2561 sci_cleanup_single(port);
2566 struct sci_port_info {
2568 unsigned int regtype;
2571 static const struct of_device_id of_sci_match[] = {
2573 .compatible = "renesas,scif",
2574 .data = &(const struct sci_port_info) {
2576 .regtype = SCIx_SH4_SCIF_REGTYPE,
2579 .compatible = "renesas,scifa",
2580 .data = &(const struct sci_port_info) {
2582 .regtype = SCIx_SCIFA_REGTYPE,
2585 .compatible = "renesas,scifb",
2586 .data = &(const struct sci_port_info) {
2588 .regtype = SCIx_SCIFB_REGTYPE,
2591 .compatible = "renesas,hscif",
2592 .data = &(const struct sci_port_info) {
2594 .regtype = SCIx_HSCIF_REGTYPE,
2597 .compatible = "renesas,sci",
2598 .data = &(const struct sci_port_info) {
2600 .regtype = SCIx_SCI_REGTYPE,
2606 MODULE_DEVICE_TABLE(of, of_sci_match);
2608 static struct plat_sci_port *
2609 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2611 struct device_node *np = pdev->dev.of_node;
2612 const struct of_device_id *match;
2613 const struct sci_port_info *info;
2614 struct plat_sci_port *p;
2617 if (!IS_ENABLED(CONFIG_OF) || !np)
2620 match = of_match_node(of_sci_match, np);
2626 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2630 /* Get the line number from the aliases node. */
2631 id = of_alias_get_id(np, "serial");
2633 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2639 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2640 p->type = info->type;
2641 p->regtype = info->regtype;
2642 p->scscr = SCSCR_RE | SCSCR_TE;
2647 static int sci_probe_single(struct platform_device *dev,
2649 struct plat_sci_port *p,
2650 struct sci_port *sciport)
2655 if (unlikely(index >= SCI_NPORTS)) {
2656 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2657 index+1, SCI_NPORTS);
2658 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2662 ret = sci_init_single(dev, sciport, index, p, false);
2666 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2668 sci_cleanup_single(sciport);
2675 static int sci_probe(struct platform_device *dev)
2677 struct plat_sci_port *p;
2678 struct sci_port *sp;
2679 unsigned int dev_id;
2683 * If we've come here via earlyprintk initialization, head off to
2684 * the special early probe. We don't have sufficient device state
2685 * to make it beyond this yet.
2687 if (is_early_platform_device(dev))
2688 return sci_probe_earlyprintk(dev);
2690 if (dev->dev.of_node) {
2691 p = sci_parse_dt(dev, &dev_id);
2695 p = dev->dev.platform_data;
2697 dev_err(&dev->dev, "no platform data supplied\n");
2704 sp = &sci_ports[dev_id];
2705 platform_set_drvdata(dev, sp);
2707 ret = sci_probe_single(dev, dev_id, p, sp);
2711 sp->freq_transition.notifier_call = sci_notifier;
2713 ret = cpufreq_register_notifier(&sp->freq_transition,
2714 CPUFREQ_TRANSITION_NOTIFIER);
2715 if (unlikely(ret < 0)) {
2716 uart_remove_one_port(&sci_uart_driver, &sp->port);
2717 sci_cleanup_single(sp);
2721 #ifdef CONFIG_SH_STANDARD_BIOS
2722 sh_bios_gdb_detach();
2728 static __maybe_unused int sci_suspend(struct device *dev)
2730 struct sci_port *sport = dev_get_drvdata(dev);
2733 uart_suspend_port(&sci_uart_driver, &sport->port);
2738 static __maybe_unused int sci_resume(struct device *dev)
2740 struct sci_port *sport = dev_get_drvdata(dev);
2743 uart_resume_port(&sci_uart_driver, &sport->port);
2748 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2750 static struct platform_driver sci_driver = {
2752 .remove = sci_remove,
2755 .pm = &sci_dev_pm_ops,
2756 .of_match_table = of_match_ptr(of_sci_match),
2760 static int __init sci_init(void)
2764 pr_info("%s\n", banner);
2766 ret = uart_register_driver(&sci_uart_driver);
2767 if (likely(ret == 0)) {
2768 ret = platform_driver_register(&sci_driver);
2770 uart_unregister_driver(&sci_uart_driver);
2776 static void __exit sci_exit(void)
2778 platform_driver_unregister(&sci_driver);
2779 uart_unregister_driver(&sci_uart_driver);
2782 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2783 early_platform_init_buffer("earlyprintk", &sci_driver,
2784 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2786 module_init(sci_init);
2787 module_exit(sci_exit);
2789 MODULE_LICENSE("GPL");
2790 MODULE_ALIAS("platform:sh-sci");
2791 MODULE_AUTHOR("Paul Mundt");
2792 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");