drivers/tty/serial/sunsab.c

   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/setup.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47 #include <linux/sunserialcore.h>
  48
  49 #include "sunsab.h"
  50
  51 struct uart_sunsab_port {
  52         struct uart_port                port;           /* Generic UART port    */
  53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  54         unsigned long                   irqflags;       /* IRQ state flags      */
  55         int                             dsr;            /* Current DSR state    */
  56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  57         unsigned int                    tec_timeout;    /* likewise             */
  58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  62         unsigned int                    gis_shift;
  63         int                             type;           /* SAB82532 version     */
  64
  65         /* Setting configuration bits while the transmitter is active
  66          * can cause garbage characters to get emitted by the chip.
  67          * Therefore, we cache such writes here and do the real register
  68          * write the next time the transmitter becomes idle.
  69          */
  70         unsigned int                    cached_ebrg;
  71         unsigned char                   cached_mode;
  72         unsigned char                   cached_pvr;
  73         unsigned char                   cached_dafo;
  74 };
  75
  76 /*
  77  * This assumes you have a 29.4912 MHz clock for your UART.
  78  */
  79 #define SAB_BASE_BAUD ( 29491200 / 16 )
  80
  81 static char *sab82532_version[16] = {
  82         "V1.0", "V2.0", "V3.2", "V(0x03)",
  83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  86 };
  87
  88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  90
  91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  92 #define SAB82532_XMIT_FIFO_SIZE 32
  93
  94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  95 {
  96         int timeout = up->tec_timeout;
  97
  98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  99                 udelay(1);
 100 }
 101
 102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 103 {
 104         int timeout = up->cec_timeout;
 105
 106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 107                 udelay(1);
 108 }
 109
 110 static struct tty_struct *
 111 receive_chars(struct uart_sunsab_port *up,
 112               union sab82532_irq_status *stat)
 113 {
 114         struct tty_port *port = NULL;
 115         struct tty_struct *tty = NULL;
 116         unsigned char buf[32];
 117         int saw_console_brk = 0;
 118         int free_fifo = 0;
 119         int count = 0;
 120         int i;
 121
 122         if (up->port.state != NULL) {           /* Unopened serial console */
 123                 port = &up->port.state->port;
 124                 tty = port->tty;
 125         }
 126
 127         /* Read number of BYTES (Character + Status) available. */
 128         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 129                 count = SAB82532_RECV_FIFO_SIZE;
 130                 free_fifo++;
 131         }
 132
 133         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 134                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 135                 free_fifo++;
 136         }
 137
 138         /* Issue a FIFO read command in case we where idle. */
 139         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 140                 sunsab_cec_wait(up);
 141                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 142                 return tty;
 143         }
 144
 145         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 146                 free_fifo++;
 147
 148         /* Read the FIFO. */
 149         for (i = 0; i < count; i++)
 150                 buf[i] = readb(&up->regs->r.rfifo[i]);
 151
 152         /* Issue Receive Message Complete command. */
 153         if (free_fifo) {
 154                 sunsab_cec_wait(up);
 155                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 156         }
 157
 158         /* Count may be zero for BRK, so we check for it here */
 159         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 160             (up->port.line == up->port.cons->index))
 161                 saw_console_brk = 1;
 162
 163         for (i = 0; i < count; i++) {
 164                 unsigned char ch = buf[i], flag;
 165
 166                 flag = TTY_NORMAL;
 167                 up->port.icount.rx++;
 168
 169                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 170                                                 SAB82532_ISR0_FERR |
 171                                                 SAB82532_ISR0_RFO)) ||
 172                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 173                         /*
 174                          * For statistics only
 175                          */
 176                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 177                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 178                                                      SAB82532_ISR0_FERR);
 179                                 up->port.icount.brk++;
 180                                 /*
 181                                  * We do the SysRQ and SAK checking
 182                                  * here because otherwise the break
 183                                  * may get masked by ignore_status_mask
 184                                  * or read_status_mask.
 185                                  */
 186                                 if (uart_handle_break(&up->port))
 187                                         continue;
 188                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 189                                 up->port.icount.parity++;
 190                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 191                                 up->port.icount.frame++;
 192                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 193                                 up->port.icount.overrun++;
 194
 195                         /*
 196                          * Mask off conditions which should be ingored.
 197                          */
 198                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 199                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 200
 201                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 202                                 flag = TTY_BREAK;
 203                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 204                                 flag = TTY_PARITY;
 205                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 206                                 flag = TTY_FRAME;
 207                 }
 208
 209                 if (uart_handle_sysrq_char(&up->port, ch))
 210                         continue;
 211
 212                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 213                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 214                         tty_insert_flip_char(port, ch, flag);
 215                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 216                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
 217         }
 218
 219         if (saw_console_brk)
 220                 sun_do_break();
 221
 222         return tty;
 223 }
 224
 225 static void sunsab_stop_tx(struct uart_port *);
 226 static void sunsab_tx_idle(struct uart_sunsab_port *);
 227
 228 static void transmit_chars(struct uart_sunsab_port *up,
 229                            union sab82532_irq_status *stat)
 230 {
 231         struct circ_buf *xmit = &up->port.state->xmit;
 232         int i;
 233
 234         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 235                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 236                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 237                 set_bit(SAB82532_ALLS, &up->irqflags);
 238         }
 239
 240 #if 0 /* bde@nwlink.com says this check causes problems */
 241         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 242                 return;
 243 #endif
 244
 245         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 246                 return;
 247
 248         set_bit(SAB82532_XPR, &up->irqflags);
 249         sunsab_tx_idle(up);
 250
 251         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 252                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 253                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 254                 return;
 255         }
 256
 257         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 258         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 259         clear_bit(SAB82532_ALLS, &up->irqflags);
 260
 261         /* Stuff 32 bytes into Transmit FIFO. */
 262         clear_bit(SAB82532_XPR, &up->irqflags);
 263         for (i = 0; i < up->port.fifosize; i++) {
 264                 writeb(xmit->buf[xmit->tail],
 265                        &up->regs->w.xfifo[i]);
 266                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 267                 up->port.icount.tx++;
 268                 if (uart_circ_empty(xmit))
 269                         break;
 270         }
 271
 272         /* Issue a Transmit Frame command. */
 273         sunsab_cec_wait(up);
 274         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 275
 276         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 277                 uart_write_wakeup(&up->port);
 278
 279         if (uart_circ_empty(xmit))
 280                 sunsab_stop_tx(&up->port);
 281 }
 282
 283 static void check_status(struct uart_sunsab_port *up,
 284                          union sab82532_irq_status *stat)
 285 {
 286         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 287                 uart_handle_dcd_change(&up->port,
 288                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 289
 290         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 291                 uart_handle_cts_change(&up->port,
 292                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 293
 294         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 295                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 296                 up->port.icount.dsr++;
 297         }
 298
 299         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 300 }
 301
 302 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 303 {
 304         struct uart_sunsab_port *up = dev_id;
 305         struct tty_struct *tty;
 306         union sab82532_irq_status status;
 307         unsigned long flags;
 308         unsigned char gis;
 309
 310         spin_lock_irqsave(&up->port.lock, flags);
 311
 312         status.stat = 0;
 313         gis = readb(&up->regs->r.gis) >> up->gis_shift;
 314         if (gis & 1)
 315                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 316         if (gis & 2)
 317                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 318
 319         tty = NULL;
 320         if (status.stat) {
 321                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 322                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 323                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 324                         tty = receive_chars(up, &status);
 325                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 326                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 327                         check_status(up, &status);
 328                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 329                         transmit_chars(up, &status);
 330         }
 331
 332         spin_unlock_irqrestore(&up->port.lock, flags);
 333
 334         if (tty)
 335                 tty_flip_buffer_push(tty);
 336
 337         return IRQ_HANDLED;
 338 }
 339
 340 /* port->lock is not held.  */
 341 static unsigned int sunsab_tx_empty(struct uart_port *port)
 342 {
 343         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 344         int ret;
 345
 346         /* Do not need a lock for a state test like this.  */
 347         if (test_bit(SAB82532_ALLS, &up->irqflags))
 348                 ret = TIOCSER_TEMT;
 349         else
 350                 ret = 0;
 351
 352         return ret;
 353 }
 354
 355 /* port->lock held by caller.  */
 356 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 357 {
 358         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 359
 360         if (mctrl & TIOCM_RTS) {
 361                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 362                 up->cached_mode |= SAB82532_MODE_RTS;
 363         } else {
 364                 up->cached_mode |= (SAB82532_MODE_FRTS |
 365                                     SAB82532_MODE_RTS);
 366         }
 367         if (mctrl & TIOCM_DTR) {
 368                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 369         } else {
 370                 up->cached_pvr |= up->pvr_dtr_bit;
 371         }
 372
 373         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 374         if (test_bit(SAB82532_XPR, &up->irqflags))
 375                 sunsab_tx_idle(up);
 376 }
 377
 378 /* port->lock is held by caller and interrupts are disabled.  */
 379 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 380 {
 381         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 382         unsigned char val;
 383         unsigned int result;
 384
 385         result = 0;
 386
 387         val = readb(&up->regs->r.pvr);
 388         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 389
 390         val = readb(&up->regs->r.vstr);
 391         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 392
 393         val = readb(&up->regs->r.star);
 394         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 395
 396         return result;
 397 }
 398
 399 /* port->lock held by caller.  */
 400 static void sunsab_stop_tx(struct uart_port *port)
 401 {
 402         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 403
 404         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 405         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 406 }
 407
 408 /* port->lock held by caller.  */
 409 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 410 {
 411         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 412                 u8 tmp;
 413
 414                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 415                 writeb(up->cached_mode, &up->regs->rw.mode);
 416                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 417                 writeb(up->cached_dafo, &up->regs->w.dafo);
 418
 419                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 420                 tmp = readb(&up->regs->rw.ccr2);
 421                 tmp &= ~0xc0;
 422                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 423                 writeb(tmp, &up->regs->rw.ccr2);
 424         }
 425 }
 426
 427 /* port->lock held by caller.  */
 428 static void sunsab_start_tx(struct uart_port *port)
 429 {
 430         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 431         struct circ_buf *xmit = &up->port.state->xmit;
 432         int i;
 433
 434         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 435         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 436
 437         if (!test_bit(SAB82532_XPR, &up->irqflags))
 438                 return;
 439
 440         clear_bit(SAB82532_ALLS, &up->irqflags);
 441         clear_bit(SAB82532_XPR, &up->irqflags);
 442
 443         for (i = 0; i < up->port.fifosize; i++) {
 444                 writeb(xmit->buf[xmit->tail],
 445                        &up->regs->w.xfifo[i]);
 446                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 447                 up->port.icount.tx++;
 448                 if (uart_circ_empty(xmit))
 449                         break;
 450         }
 451
 452         /* Issue a Transmit Frame command.  */
 453         sunsab_cec_wait(up);
 454         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 455 }
 456
 457 /* port->lock is not held.  */
 458 static void sunsab_send_xchar(struct uart_port *port, char ch)
 459 {
 460         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 461         unsigned long flags;
 462
 463         spin_lock_irqsave(&up->port.lock, flags);
 464
 465         sunsab_tec_wait(up);
 466         writeb(ch, &up->regs->w.tic);
 467
 468         spin_unlock_irqrestore(&up->port.lock, flags);
 469 }
 470
 471 /* port->lock held by caller.  */
 472 static void sunsab_stop_rx(struct uart_port *port)
 473 {
 474         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 475
 476         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
 477         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 478 }
 479
 480 /* port->lock held by caller.  */
 481 static void sunsab_enable_ms(struct uart_port *port)
 482 {
 483         /* For now we always receive these interrupts.  */
 484 }
 485
 486 /* port->lock is not held.  */
 487 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 488 {
 489         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 490         unsigned long flags;
 491         unsigned char val;
 492
 493         spin_lock_irqsave(&up->port.lock, flags);
 494
 495         val = up->cached_dafo;
 496         if (break_state)
 497                 val |= SAB82532_DAFO_XBRK;
 498         else
 499                 val &= ~SAB82532_DAFO_XBRK;
 500         up->cached_dafo = val;
 501
 502         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 503         if (test_bit(SAB82532_XPR, &up->irqflags))
 504                 sunsab_tx_idle(up);
 505
 506         spin_unlock_irqrestore(&up->port.lock, flags);
 507 }
 508
 509 /* port->lock is not held.  */
 510 static int sunsab_startup(struct uart_port *port)
 511 {
 512         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 513         unsigned long flags;
 514         unsigned char tmp;
 515         int err = request_irq(up->port.irq, sunsab_interrupt,
 516                               IRQF_SHARED, "sab", up);
 517         if (err)
 518                 return err;
 519
 520         spin_lock_irqsave(&up->port.lock, flags);
 521
 522         /*
 523          * Wait for any commands or immediate characters
 524          */
 525         sunsab_cec_wait(up);
 526         sunsab_tec_wait(up);
 527
 528         /*
 529          * Clear the FIFO buffers.
 530          */
 531         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 532         sunsab_cec_wait(up);
 533         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 534
 535         /*
 536          * Clear the interrupt registers.
 537          */
 538         (void) readb(&up->regs->r.isr0);
 539         (void) readb(&up->regs->r.isr1);
 540
 541         /*
 542          * Now, initialize the UART
 543          */
 544         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 545         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 546                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 547         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 548         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 549                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 550         writeb(0, &up->regs->w.ccr3);
 551         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 552         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 553                            SAB82532_MODE_RAC);
 554         writeb(up->cached_mode, &up->regs->w.mode);
 555         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 556
 557         tmp = readb(&up->regs->rw.ccr0);
 558         tmp |= SAB82532_CCR0_PU;        /* power-up */
 559         writeb(tmp, &up->regs->rw.ccr0);
 560
 561         /*
 562          * Finally, enable interrupts
 563          */
 564         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 565                                SAB82532_IMR0_PLLA);
 566         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 567         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 568                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 569                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 570                                SAB82532_IMR1_XPR);
 571         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 572         set_bit(SAB82532_ALLS, &up->irqflags);
 573         set_bit(SAB82532_XPR, &up->irqflags);
 574
 575         spin_unlock_irqrestore(&up->port.lock, flags);
 576
 577         return 0;
 578 }
 579
 580 /* port->lock is not held.  */
 581 static void sunsab_shutdown(struct uart_port *port)
 582 {
 583         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 584         unsigned long flags;
 585
 586         spin_lock_irqsave(&up->port.lock, flags);
 587
 588         /* Disable Interrupts */
 589         up->interrupt_mask0 = 0xff;
 590         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 591         up->interrupt_mask1 = 0xff;
 592         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 593
 594         /* Disable break condition */
 595         up->cached_dafo = readb(&up->regs->rw.dafo);
 596         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 597         writeb(up->cached_dafo, &up->regs->rw.dafo);
 598
 599         /* Disable Receiver */
 600         up->cached_mode &= ~SAB82532_MODE_RAC;
 601         writeb(up->cached_mode, &up->regs->rw.mode);
 602
 603         /*
 604          * XXX FIXME
 605          *
 606          * If the chip is powered down here the system hangs/crashes during
 607          * reboot or shutdown.  This needs to be investigated further,
 608          * similar behaviour occurs in 2.4 when the driver is configured
 609          * as a module only.  One hint may be that data is sometimes
 610          * transmitted at 9600 baud during shutdown (regardless of the
 611          * speed the chip was configured for when the port was open).
 612          */
 613 #if 0
 614         /* Power Down */
 615         tmp = readb(&up->regs->rw.ccr0);
 616         tmp &= ~SAB82532_CCR0_PU;
 617         writeb(tmp, &up->regs->rw.ccr0);
 618 #endif
 619
 620         spin_unlock_irqrestore(&up->port.lock, flags);
 621         free_irq(up->port.irq, up);
 622 }
 623
 624 /*
 625  * This is used to figure out the divisor speeds.
 626  *
 627  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 628  *
 629  * with               0 <= N < 64 and 0 <= M < 16
 630  */
 631
 632 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 633 {
 634         int     n, m;
 635
 636         if (baud == 0) {
 637                 *n_ret = 0;
 638                 *m_ret = 0;
 639                 return;
 640         }
 641
 642         /*
 643          * We scale numbers by 10 so that we get better accuracy
 644          * without having to use floating point.  Here we increment m
 645          * until n is within the valid range.
 646          */
 647         n = (SAB_BASE_BAUD * 10) / baud;
 648         m = 0;
 649         while (n >= 640) {
 650                 n = n / 2;
 651                 m++;
 652         }
 653         n = (n+5) / 10;
 654         /*
 655          * We try very hard to avoid speeds with M == 0 since they may
 656          * not work correctly for XTAL frequences above 10 MHz.
 657          */
 658         if ((m == 0) && ((n & 1) == 0)) {
 659                 n = n / 2;
 660                 m++;
 661         }
 662         *n_ret = n - 1;
 663         *m_ret = m;
 664 }
 665
 666 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 667 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 668                                   unsigned int iflag, unsigned int baud,
 669                                   unsigned int quot)
 670 {
 671         unsigned char dafo;
 672         int bits, n, m;
 673
 674         /* Byte size and parity */
 675         switch (cflag & CSIZE) {
 676               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 677               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 678               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 679               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 680               /* Never happens, but GCC is too dumb to figure it out */
 681               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 682         }
 683
 684         if (cflag & CSTOPB) {
 685                 dafo |= SAB82532_DAFO_STOP;
 686                 bits++;
 687         }
 688
 689         if (cflag & PARENB) {
 690                 dafo |= SAB82532_DAFO_PARE;
 691                 bits++;
 692         }
 693
 694         if (cflag & PARODD) {
 695                 dafo |= SAB82532_DAFO_PAR_ODD;
 696         } else {
 697                 dafo |= SAB82532_DAFO_PAR_EVEN;
 698         }
 699         up->cached_dafo = dafo;
 700
 701         calc_ebrg(baud, &n, &m);
 702
 703         up->cached_ebrg = n | (m << 6);
 704
 705         up->tec_timeout = (10 * 1000000) / baud;
 706         up->cec_timeout = up->tec_timeout >> 2;
 707
 708         /* CTS flow control flags */
 709         /* We encode read_status_mask and ignore_status_mask like so:
 710          *
 711          * ---------------------
 712          * | ... | ISR1 | ISR0 |
 713          * ---------------------
 714          *  ..    15   8 7    0
 715          */
 716
 717         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 718                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 719                                      SAB82532_ISR0_CDSC);
 720         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 721                                       SAB82532_ISR1_ALLS |
 722                                       SAB82532_ISR1_XPR) << 8;
 723         if (iflag & INPCK)
 724                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 725                                               SAB82532_ISR0_FERR);
 726         if (iflag & (BRKINT | PARMRK))
 727                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 728
 729         /*
 730          * Characteres to ignore
 731          */
 732         up->port.ignore_status_mask = 0;
 733         if (iflag & IGNPAR)
 734                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 735                                                 SAB82532_ISR0_FERR);
 736         if (iflag & IGNBRK) {
 737                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 738                 /*
 739                  * If we're ignoring parity and break indicators,
 740                  * ignore overruns too (for real raw support).
 741                  */
 742                 if (iflag & IGNPAR)
 743                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 744         }
 745
 746         /*
 747          * ignore all characters if CREAD is not set
 748          */
 749         if ((cflag & CREAD) == 0)
 750                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 751                                                 SAB82532_ISR0_TCD);
 752
 753         uart_update_timeout(&up->port, cflag,
 754                             (up->port.uartclk / (16 * quot)));
 755
 756         /* Now schedule a register update when the chip's
 757          * transmitter is idle.
 758          */
 759         up->cached_mode |= SAB82532_MODE_RAC;
 760         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 761         if (test_bit(SAB82532_XPR, &up->irqflags))
 762                 sunsab_tx_idle(up);
 763 }
 764
 765 /* port->lock is not held.  */
 766 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 767                                struct ktermios *old)
 768 {
 769         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 770         unsigned long flags;
 771         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 772         unsigned int quot = uart_get_divisor(port, baud);
 773
 774         spin_lock_irqsave(&up->port.lock, flags);
 775         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 776         spin_unlock_irqrestore(&up->port.lock, flags);
 777 }
 778
 779 static const char *sunsab_type(struct uart_port *port)
 780 {
 781         struct uart_sunsab_port *up = (void *)port;
 782         static char buf[36];
 783
 784         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 785         return buf;
 786 }
 787
 788 static void sunsab_release_port(struct uart_port *port)
 789 {
 790 }
 791
 792 static int sunsab_request_port(struct uart_port *port)
 793 {
 794         return 0;
 795 }
 796
 797 static void sunsab_config_port(struct uart_port *port, int flags)
 798 {
 799 }
 800
 801 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 802 {
 803         return -EINVAL;
 804 }
 805
 806 static struct uart_ops sunsab_pops = {
 807         .tx_empty       = sunsab_tx_empty,
 808         .set_mctrl      = sunsab_set_mctrl,
 809         .get_mctrl      = sunsab_get_mctrl,
 810         .stop_tx        = sunsab_stop_tx,
 811         .start_tx       = sunsab_start_tx,
 812         .send_xchar     = sunsab_send_xchar,
 813         .stop_rx        = sunsab_stop_rx,
 814         .enable_ms      = sunsab_enable_ms,
 815         .break_ctl      = sunsab_break_ctl,
 816         .startup        = sunsab_startup,
 817         .shutdown       = sunsab_shutdown,
 818         .set_termios    = sunsab_set_termios,
 819         .type           = sunsab_type,
 820         .release_port   = sunsab_release_port,
 821         .request_port   = sunsab_request_port,
 822         .config_port    = sunsab_config_port,
 823         .verify_port    = sunsab_verify_port,
 824 };
 825
 826 static struct uart_driver sunsab_reg = {
 827         .owner                  = THIS_MODULE,
 828         .driver_name            = "sunsab",
 829         .dev_name               = "ttyS",
 830         .major                  = TTY_MAJOR,
 831 };
 832
 833 static struct uart_sunsab_port *sunsab_ports;
 834
 835 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 836
 837 static void sunsab_console_putchar(struct uart_port *port, int c)
 838 {
 839         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 840
 841         sunsab_tec_wait(up);
 842         writeb(c, &up->regs->w.tic);
 843 }
 844
 845 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 846 {
 847         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 848         unsigned long flags;
 849         int locked = 1;
 850
 851         local_irq_save(flags);
 852         if (up->port.sysrq) {
 853                 locked = 0;
 854         } else if (oops_in_progress) {
 855                 locked = spin_trylock(&up->port.lock);
 856         } else
 857                 spin_lock(&up->port.lock);
 858
 859         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 860         sunsab_tec_wait(up);
 861
 862         if (locked)
 863                 spin_unlock(&up->port.lock);
 864         local_irq_restore(flags);
 865 }
 866
 867 static int sunsab_console_setup(struct console *con, char *options)
 868 {
 869         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 870         unsigned long flags;
 871         unsigned int baud, quot;
 872
 873         /*
 874          * The console framework calls us for each and every port
 875          * registered. Defer the console setup until the requested
 876          * port has been properly discovered. A bit of a hack,
 877          * though...
 878          */
 879         if (up->port.type != PORT_SUNSAB)
 880                 return -1;
 881
 882         printk("Console: ttyS%d (SAB82532)\n",
 883                (sunsab_reg.minor - 64) + con->index);
 884
 885         sunserial_console_termios(con, up->port.dev->of_node);
 886
 887         switch (con->cflag & CBAUD) {
 888         case B150: baud = 150; break;
 889         case B300: baud = 300; break;
 890         case B600: baud = 600; break;
 891         case B1200: baud = 1200; break;
 892         case B2400: baud = 2400; break;
 893         case B4800: baud = 4800; break;
 894         default: case B9600: baud = 9600; break;
 895         case B19200: baud = 19200; break;
 896         case B38400: baud = 38400; break;
 897         case B57600: baud = 57600; break;
 898         case B115200: baud = 115200; break;
 899         case B230400: baud = 230400; break;
 900         case B460800: baud = 460800; break;
 901         };
 902
 903         /*
 904          * Temporary fix.
 905          */
 906         spin_lock_init(&up->port.lock);
 907
 908         /*
 909          * Initialize the hardware
 910          */
 911         sunsab_startup(&up->port);
 912
 913         spin_lock_irqsave(&up->port.lock, flags);
 914
 915         /*
 916          * Finally, enable interrupts
 917          */
 918         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 919                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 920         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 921         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 922                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 923                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 924                                 SAB82532_IMR1_XPR;
 925         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 926
 927         quot = uart_get_divisor(&up->port, baud);
 928         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 929         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 930
 931         spin_unlock_irqrestore(&up->port.lock, flags);
 932
 933         return 0;
 934 }
 935
 936 static struct console sunsab_console = {
 937         .name   =       "ttyS",
 938         .write  =       sunsab_console_write,
 939         .device =       uart_console_device,
 940         .setup  =       sunsab_console_setup,
 941         .flags  =       CON_PRINTBUFFER,
 942         .index  =       -1,
 943         .data   =       &sunsab_reg,
 944 };
 945
 946 static inline struct console *SUNSAB_CONSOLE(void)
 947 {
 948         return &sunsab_console;
 949 }
 950 #else
 951 #define SUNSAB_CONSOLE()        (NULL)
 952 #define sunsab_console_init()   do { } while (0)
 953 #endif
 954
 955 static int sunsab_init_one(struct uart_sunsab_port *up,
 956                                      struct platform_device *op,
 957                                      unsigned long offset,
 958                                      int line)
 959 {
 960         up->port.line = line;
 961         up->port.dev = &op->dev;
 962
 963         up->port.mapbase = op->resource[0].start + offset;
 964         up->port.membase = of_ioremap(&op->resource[0], offset,
 965                                       sizeof(union sab82532_async_regs),
 966                                       "sab");
 967         if (!up->port.membase)
 968                 return -ENOMEM;
 969         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
 970
 971         up->port.irq = op->archdata.irqs[0];
 972
 973         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
 974         up->port.iotype = UPIO_MEM;
 975
 976         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
 977
 978         up->port.ops = &sunsab_pops;
 979         up->port.type = PORT_SUNSAB;
 980         up->port.uartclk = SAB_BASE_BAUD;
 981
 982         up->type = readb(&up->regs->r.vstr) & 0x0f;
 983         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
 984         writeb(0xff, &up->regs->w.pim);
 985         if ((up->port.line & 0x1) == 0) {
 986                 up->pvr_dsr_bit = (1 << 0);
 987                 up->pvr_dtr_bit = (1 << 1);
 988                 up->gis_shift = 2;
 989         } else {
 990                 up->pvr_dsr_bit = (1 << 3);
 991                 up->pvr_dtr_bit = (1 << 2);
 992                 up->gis_shift = 0;
 993         }
 994         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
 995         writeb(up->cached_pvr, &up->regs->w.pvr);
 996         up->cached_mode = readb(&up->regs->rw.mode);
 997         up->cached_mode |= SAB82532_MODE_FRTS;
 998         writeb(up->cached_mode, &up->regs->rw.mode);
 999         up->cached_mode |= SAB82532_MODE_RTS;
1000         writeb(up->cached_mode, &up->regs->rw.mode);
1001
1002         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1003         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1004
1005         return 0;
1006 }
1007
1008 static int sab_probe(struct platform_device *op)
1009 {
1010         static int inst;
1011         struct uart_sunsab_port *up;
1012         int err;
1013
1014         up = &sunsab_ports[inst * 2];
1015
1016         err = sunsab_init_one(&up[0], op,
1017                               0,
1018                               (inst * 2) + 0);
1019         if (err)
1020                 goto out;
1021
1022         err = sunsab_init_one(&up[1], op,
1023                               sizeof(union sab82532_async_regs),
1024                               (inst * 2) + 1);
1025         if (err)
1026                 goto out1;
1027
1028         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1029                                 &sunsab_reg, up[0].port.line,
1030                                 false);
1031
1032         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1033                                 &sunsab_reg, up[1].port.line,
1034                                 false);
1035
1036         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1037         if (err)
1038                 goto out2;
1039
1040         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1041         if (err)
1042                 goto out3;
1043
1044         dev_set_drvdata(&op->dev, &up[0]);
1045
1046         inst++;
1047
1048         return 0;
1049
1050 out3:
1051         uart_remove_one_port(&sunsab_reg, &up[0].port);
1052 out2:
1053         of_iounmap(&op->resource[0],
1054                    up[1].port.membase,
1055                    sizeof(union sab82532_async_regs));
1056 out1:
1057         of_iounmap(&op->resource[0],
1058                    up[0].port.membase,
1059                    sizeof(union sab82532_async_regs));
1060 out:
1061         return err;
1062 }
1063
1064 static int sab_remove(struct platform_device *op)
1065 {
1066         struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1067
1068         uart_remove_one_port(&sunsab_reg, &up[1].port);
1069         uart_remove_one_port(&sunsab_reg, &up[0].port);
1070         of_iounmap(&op->resource[0],
1071                    up[1].port.membase,
1072                    sizeof(union sab82532_async_regs));
1073         of_iounmap(&op->resource[0],
1074                    up[0].port.membase,
1075                    sizeof(union sab82532_async_regs));
1076
1077         dev_set_drvdata(&op->dev, NULL);
1078
1079         return 0;
1080 }
1081
1082 static const struct of_device_id sab_match[] = {
1083         {
1084                 .name = "se",
1085         },
1086         {
1087                 .name = "serial",
1088                 .compatible = "sab82532",
1089         },
1090         {},
1091 };
1092 MODULE_DEVICE_TABLE(of, sab_match);
1093
1094 static struct platform_driver sab_driver = {
1095         .driver = {
1096                 .name = "sab",
1097                 .owner = THIS_MODULE,
1098                 .of_match_table = sab_match,
1099         },
1100         .probe          = sab_probe,
1101         .remove         = sab_remove,
1102 };
1103
1104 static int __init sunsab_init(void)
1105 {
1106         struct device_node *dp;
1107         int err;
1108         int num_channels = 0;
1109
1110         for_each_node_by_name(dp, "se")
1111                 num_channels += 2;
1112         for_each_node_by_name(dp, "serial") {
1113                 if (of_device_is_compatible(dp, "sab82532"))
1114                         num_channels += 2;
1115         }
1116
1117         if (num_channels) {
1118                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1119                                        num_channels, GFP_KERNEL);
1120                 if (!sunsab_ports)
1121                         return -ENOMEM;
1122
1123                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1124                 if (err) {
1125                         kfree(sunsab_ports);
1126                         sunsab_ports = NULL;
1127
1128                         return err;
1129                 }
1130         }
1131
1132         return platform_driver_register(&sab_driver);
1133 }
1134
1135 static void __exit sunsab_exit(void)
1136 {
1137         platform_driver_unregister(&sab_driver);
1138         if (sunsab_reg.nr) {
1139                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1140         }
1141
1142         kfree(sunsab_ports);
1143         sunsab_ports = NULL;
1144 }
1145
1146 module_init(sunsab_init);
1147 module_exit(sunsab_exit);
1148
1149 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1150 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1151 MODULE_LICENSE("GPL");