drivers/tty/serial/sunsab.c

   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/setup.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47 #include <linux/sunserialcore.h>
  48
  49 #include "sunsab.h"
  50
  51 struct uart_sunsab_port {
  52         struct uart_port                port;           /* Generic UART port    */
  53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  54         unsigned long                   irqflags;       /* IRQ state flags      */
  55         int                             dsr;            /* Current DSR state    */
  56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  57         unsigned int                    tec_timeout;    /* likewise             */
  58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  62         unsigned int                    gis_shift;
  63         int                             type;           /* SAB82532 version     */
  64
  65         /* Setting configuration bits while the transmitter is active
  66          * can cause garbage characters to get emitted by the chip.
  67          * Therefore, we cache such writes here and do the real register
  68          * write the next time the transmitter becomes idle.
  69          */
  70         unsigned int                    cached_ebrg;
  71         unsigned char                   cached_mode;
  72         unsigned char                   cached_pvr;
  73         unsigned char                   cached_dafo;
  74 };
  75
  76 /*
  77  * This assumes you have a 29.4912 MHz clock for your UART.
  78  */
  79 #define SAB_BASE_BAUD ( 29491200 / 16 )
  80
  81 static char *sab82532_version[16] = {
  82         "V1.0", "V2.0", "V3.2", "V(0x03)",
  83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  86 };
  87
  88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  90
  91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  92 #define SAB82532_XMIT_FIFO_SIZE 32
  93
  94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  95 {
  96         int timeout = up->tec_timeout;
  97
  98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  99                 udelay(1);
 100 }
 101
 102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 103 {
 104         int timeout = up->cec_timeout;
 105
 106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 107                 udelay(1);
 108 }
 109
 110 static struct tty_port *
 111 receive_chars(struct uart_sunsab_port *up,
 112               union sab82532_irq_status *stat)
 113 {
 114         struct tty_port *port = NULL;
 115         unsigned char buf[32];
 116         int saw_console_brk = 0;
 117         int free_fifo = 0;
 118         int count = 0;
 119         int i;
 120
 121         if (up->port.state != NULL)             /* Unopened serial console */
 122                 port = &up->port.state->port;
 123
 124         /* Read number of BYTES (Character + Status) available. */
 125         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 126                 count = SAB82532_RECV_FIFO_SIZE;
 127                 free_fifo++;
 128         }
 129
 130         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 131                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 132                 free_fifo++;
 133         }
 134
 135         /* Issue a FIFO read command in case we where idle. */
 136         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 137                 sunsab_cec_wait(up);
 138                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 139                 return port;
 140         }
 141
 142         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 143                 free_fifo++;
 144
 145         /* Read the FIFO. */
 146         for (i = 0; i < count; i++)
 147                 buf[i] = readb(&up->regs->r.rfifo[i]);
 148
 149         /* Issue Receive Message Complete command. */
 150         if (free_fifo) {
 151                 sunsab_cec_wait(up);
 152                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 153         }
 154
 155         /* Count may be zero for BRK, so we check for it here */
 156         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 157             (up->port.line == up->port.cons->index))
 158                 saw_console_brk = 1;
 159
 160         if (count == 0) {
 161                 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 162                         stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 163                                              SAB82532_ISR0_FERR);
 164                         up->port.icount.brk++;
 165                         uart_handle_break(&up->port);
 166                 }
 167         }
 168
 169         for (i = 0; i < count; i++) {
 170                 unsigned char ch = buf[i], flag;
 171
 172                 flag = TTY_NORMAL;
 173                 up->port.icount.rx++;
 174
 175                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 176                                                 SAB82532_ISR0_FERR |
 177                                                 SAB82532_ISR0_RFO)) ||
 178                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 179                         /*
 180                          * For statistics only
 181                          */
 182                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 183                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 184                                                      SAB82532_ISR0_FERR);
 185                                 up->port.icount.brk++;
 186                                 /*
 187                                  * We do the SysRQ and SAK checking
 188                                  * here because otherwise the break
 189                                  * may get masked by ignore_status_mask
 190                                  * or read_status_mask.
 191                                  */
 192                                 if (uart_handle_break(&up->port))
 193                                         continue;
 194                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 195                                 up->port.icount.parity++;
 196                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 197                                 up->port.icount.frame++;
 198                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 199                                 up->port.icount.overrun++;
 200
 201                         /*
 202                          * Mask off conditions which should be ingored.
 203                          */
 204                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 205                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 206
 207                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 208                                 flag = TTY_BREAK;
 209                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 210                                 flag = TTY_PARITY;
 211                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 212                                 flag = TTY_FRAME;
 213                 }
 214
 215                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
 216                         continue;
 217
 218                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 219                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 220                         tty_insert_flip_char(port, ch, flag);
 221                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 222                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
 223         }
 224
 225         if (saw_console_brk)
 226                 sun_do_break();
 227
 228         return port;
 229 }
 230
 231 static void sunsab_stop_tx(struct uart_port *);
 232 static void sunsab_tx_idle(struct uart_sunsab_port *);
 233
 234 static void transmit_chars(struct uart_sunsab_port *up,
 235                            union sab82532_irq_status *stat)
 236 {
 237         struct circ_buf *xmit = &up->port.state->xmit;
 238         int i;
 239
 240         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 241                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 242                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 243                 set_bit(SAB82532_ALLS, &up->irqflags);
 244         }
 245
 246 #if 0 /* bde@nwlink.com says this check causes problems */
 247         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 248                 return;
 249 #endif
 250
 251         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 252                 return;
 253
 254         set_bit(SAB82532_XPR, &up->irqflags);
 255         sunsab_tx_idle(up);
 256
 257         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 258                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 259                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 260                 return;
 261         }
 262
 263         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 264         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 265         clear_bit(SAB82532_ALLS, &up->irqflags);
 266
 267         /* Stuff 32 bytes into Transmit FIFO. */
 268         clear_bit(SAB82532_XPR, &up->irqflags);
 269         for (i = 0; i < up->port.fifosize; i++) {
 270                 writeb(xmit->buf[xmit->tail],
 271                        &up->regs->w.xfifo[i]);
 272                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 273                 up->port.icount.tx++;
 274                 if (uart_circ_empty(xmit))
 275                         break;
 276         }
 277
 278         /* Issue a Transmit Frame command. */
 279         sunsab_cec_wait(up);
 280         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 281
 282         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 283                 uart_write_wakeup(&up->port);
 284
 285         if (uart_circ_empty(xmit))
 286                 sunsab_stop_tx(&up->port);
 287 }
 288
 289 static void check_status(struct uart_sunsab_port *up,
 290                          union sab82532_irq_status *stat)
 291 {
 292         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 293                 uart_handle_dcd_change(&up->port,
 294                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 295
 296         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 297                 uart_handle_cts_change(&up->port,
 298                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 299
 300         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 301                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 302                 up->port.icount.dsr++;
 303         }
 304
 305         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 306 }
 307
 308 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 309 {
 310         struct uart_sunsab_port *up = dev_id;
 311         struct tty_port *port = NULL;
 312         union sab82532_irq_status status;
 313         unsigned long flags;
 314         unsigned char gis;
 315
 316         spin_lock_irqsave(&up->port.lock, flags);
 317
 318         status.stat = 0;
 319         gis = readb(&up->regs->r.gis) >> up->gis_shift;
 320         if (gis & 1)
 321                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 322         if (gis & 2)
 323                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 324
 325         if (status.stat) {
 326                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 327                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 328                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 329                         port = receive_chars(up, &status);
 330                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 331                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 332                         check_status(up, &status);
 333                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 334                         transmit_chars(up, &status);
 335         }
 336
 337         spin_unlock_irqrestore(&up->port.lock, flags);
 338
 339         if (port)
 340                 tty_flip_buffer_push(port);
 341
 342         return IRQ_HANDLED;
 343 }
 344
 345 /* port->lock is not held.  */
 346 static unsigned int sunsab_tx_empty(struct uart_port *port)
 347 {
 348         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 349         int ret;
 350
 351         /* Do not need a lock for a state test like this.  */
 352         if (test_bit(SAB82532_ALLS, &up->irqflags))
 353                 ret = TIOCSER_TEMT;
 354         else
 355                 ret = 0;
 356
 357         return ret;
 358 }
 359
 360 /* port->lock held by caller.  */
 361 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 362 {
 363         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 364
 365         if (mctrl & TIOCM_RTS) {
 366                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 367                 up->cached_mode |= SAB82532_MODE_RTS;
 368         } else {
 369                 up->cached_mode |= (SAB82532_MODE_FRTS |
 370                                     SAB82532_MODE_RTS);
 371         }
 372         if (mctrl & TIOCM_DTR) {
 373                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 374         } else {
 375                 up->cached_pvr |= up->pvr_dtr_bit;
 376         }
 377
 378         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 379         if (test_bit(SAB82532_XPR, &up->irqflags))
 380                 sunsab_tx_idle(up);
 381 }
 382
 383 /* port->lock is held by caller and interrupts are disabled.  */
 384 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 385 {
 386         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 387         unsigned char val;
 388         unsigned int result;
 389
 390         result = 0;
 391
 392         val = readb(&up->regs->r.pvr);
 393         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 394
 395         val = readb(&up->regs->r.vstr);
 396         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 397
 398         val = readb(&up->regs->r.star);
 399         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 400
 401         return result;
 402 }
 403
 404 /* port->lock held by caller.  */
 405 static void sunsab_stop_tx(struct uart_port *port)
 406 {
 407         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 408
 409         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 410         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 411 }
 412
 413 /* port->lock held by caller.  */
 414 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 415 {
 416         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 417                 u8 tmp;
 418
 419                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 420                 writeb(up->cached_mode, &up->regs->rw.mode);
 421                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 422                 writeb(up->cached_dafo, &up->regs->w.dafo);
 423
 424                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 425                 tmp = readb(&up->regs->rw.ccr2);
 426                 tmp &= ~0xc0;
 427                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 428                 writeb(tmp, &up->regs->rw.ccr2);
 429         }
 430 }
 431
 432 /* port->lock held by caller.  */
 433 static void sunsab_start_tx(struct uart_port *port)
 434 {
 435         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 436         struct circ_buf *xmit = &up->port.state->xmit;
 437         int i;
 438
 439         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 440                 return;
 441
 442         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 443         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 444
 445         if (!test_bit(SAB82532_XPR, &up->irqflags))
 446                 return;
 447
 448         clear_bit(SAB82532_ALLS, &up->irqflags);
 449         clear_bit(SAB82532_XPR, &up->irqflags);
 450
 451         for (i = 0; i < up->port.fifosize; i++) {
 452                 writeb(xmit->buf[xmit->tail],
 453                        &up->regs->w.xfifo[i]);
 454                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 455                 up->port.icount.tx++;
 456                 if (uart_circ_empty(xmit))
 457                         break;
 458         }
 459
 460         /* Issue a Transmit Frame command.  */
 461         sunsab_cec_wait(up);
 462         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 463 }
 464
 465 /* port->lock is not held.  */
 466 static void sunsab_send_xchar(struct uart_port *port, char ch)
 467 {
 468         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 469         unsigned long flags;
 470
 471         if (ch == __DISABLED_CHAR)
 472                 return;
 473
 474         spin_lock_irqsave(&up->port.lock, flags);
 475
 476         sunsab_tec_wait(up);
 477         writeb(ch, &up->regs->w.tic);
 478
 479         spin_unlock_irqrestore(&up->port.lock, flags);
 480 }
 481
 482 /* port->lock held by caller.  */
 483 static void sunsab_stop_rx(struct uart_port *port)
 484 {
 485         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 486
 487         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
 488         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 489 }
 490
 491 /* port->lock is not held.  */
 492 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 493 {
 494         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 495         unsigned long flags;
 496         unsigned char val;
 497
 498         spin_lock_irqsave(&up->port.lock, flags);
 499
 500         val = up->cached_dafo;
 501         if (break_state)
 502                 val |= SAB82532_DAFO_XBRK;
 503         else
 504                 val &= ~SAB82532_DAFO_XBRK;
 505         up->cached_dafo = val;
 506
 507         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 508         if (test_bit(SAB82532_XPR, &up->irqflags))
 509                 sunsab_tx_idle(up);
 510
 511         spin_unlock_irqrestore(&up->port.lock, flags);
 512 }
 513
 514 /* port->lock is not held.  */
 515 static int sunsab_startup(struct uart_port *port)
 516 {
 517         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 518         unsigned long flags;
 519         unsigned char tmp;
 520         int err = request_irq(up->port.irq, sunsab_interrupt,
 521                               IRQF_SHARED, "sab", up);
 522         if (err)
 523                 return err;
 524
 525         spin_lock_irqsave(&up->port.lock, flags);
 526
 527         /*
 528          * Wait for any commands or immediate characters
 529          */
 530         sunsab_cec_wait(up);
 531         sunsab_tec_wait(up);
 532
 533         /*
 534          * Clear the FIFO buffers.
 535          */
 536         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 537         sunsab_cec_wait(up);
 538         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 539
 540         /*
 541          * Clear the interrupt registers.
 542          */
 543         (void) readb(&up->regs->r.isr0);
 544         (void) readb(&up->regs->r.isr1);
 545
 546         /*
 547          * Now, initialize the UART
 548          */
 549         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 550         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 551                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 552         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 553         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 554                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 555         writeb(0, &up->regs->w.ccr3);
 556         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 557         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 558                            SAB82532_MODE_RAC);
 559         writeb(up->cached_mode, &up->regs->w.mode);
 560         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 561
 562         tmp = readb(&up->regs->rw.ccr0);
 563         tmp |= SAB82532_CCR0_PU;        /* power-up */
 564         writeb(tmp, &up->regs->rw.ccr0);
 565
 566         /*
 567          * Finally, enable interrupts
 568          */
 569         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 570                                SAB82532_IMR0_PLLA);
 571         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 572         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 573                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 574                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 575                                SAB82532_IMR1_XPR);
 576         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 577         set_bit(SAB82532_ALLS, &up->irqflags);
 578         set_bit(SAB82532_XPR, &up->irqflags);
 579
 580         spin_unlock_irqrestore(&up->port.lock, flags);
 581
 582         return 0;
 583 }
 584
 585 /* port->lock is not held.  */
 586 static void sunsab_shutdown(struct uart_port *port)
 587 {
 588         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 589         unsigned long flags;
 590
 591         spin_lock_irqsave(&up->port.lock, flags);
 592
 593         /* Disable Interrupts */
 594         up->interrupt_mask0 = 0xff;
 595         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 596         up->interrupt_mask1 = 0xff;
 597         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 598
 599         /* Disable break condition */
 600         up->cached_dafo = readb(&up->regs->rw.dafo);
 601         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 602         writeb(up->cached_dafo, &up->regs->rw.dafo);
 603
 604         /* Disable Receiver */
 605         up->cached_mode &= ~SAB82532_MODE_RAC;
 606         writeb(up->cached_mode, &up->regs->rw.mode);
 607
 608         /*
 609          * XXX FIXME
 610          *
 611          * If the chip is powered down here the system hangs/crashes during
 612          * reboot or shutdown.  This needs to be investigated further,
 613          * similar behaviour occurs in 2.4 when the driver is configured
 614          * as a module only.  One hint may be that data is sometimes
 615          * transmitted at 9600 baud during shutdown (regardless of the
 616          * speed the chip was configured for when the port was open).
 617          */
 618 #if 0
 619         /* Power Down */
 620         tmp = readb(&up->regs->rw.ccr0);
 621         tmp &= ~SAB82532_CCR0_PU;
 622         writeb(tmp, &up->regs->rw.ccr0);
 623 #endif
 624
 625         spin_unlock_irqrestore(&up->port.lock, flags);
 626         free_irq(up->port.irq, up);
 627 }
 628
 629 /*
 630  * This is used to figure out the divisor speeds.
 631  *
 632  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 633  *
 634  * with               0 <= N < 64 and 0 <= M < 16
 635  */
 636
 637 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 638 {
 639         int     n, m;
 640
 641         if (baud == 0) {
 642                 *n_ret = 0;
 643                 *m_ret = 0;
 644                 return;
 645         }
 646
 647         /*
 648          * We scale numbers by 10 so that we get better accuracy
 649          * without having to use floating point.  Here we increment m
 650          * until n is within the valid range.
 651          */
 652         n = (SAB_BASE_BAUD * 10) / baud;
 653         m = 0;
 654         while (n >= 640) {
 655                 n = n / 2;
 656                 m++;
 657         }
 658         n = (n+5) / 10;
 659         /*
 660          * We try very hard to avoid speeds with M == 0 since they may
 661          * not work correctly for XTAL frequences above 10 MHz.
 662          */
 663         if ((m == 0) && ((n & 1) == 0)) {
 664                 n = n / 2;
 665                 m++;
 666         }
 667         *n_ret = n - 1;
 668         *m_ret = m;
 669 }
 670
 671 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 672 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 673                                   unsigned int iflag, unsigned int baud,
 674                                   unsigned int quot)
 675 {
 676         unsigned char dafo;
 677         int bits, n, m;
 678
 679         /* Byte size and parity */
 680         switch (cflag & CSIZE) {
 681               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 682               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 683               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 684               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 685               /* Never happens, but GCC is too dumb to figure it out */
 686               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 687         }
 688
 689         if (cflag & CSTOPB) {
 690                 dafo |= SAB82532_DAFO_STOP;
 691                 bits++;
 692         }
 693
 694         if (cflag & PARENB) {
 695                 dafo |= SAB82532_DAFO_PARE;
 696                 bits++;
 697         }
 698
 699         if (cflag & PARODD) {
 700                 dafo |= SAB82532_DAFO_PAR_ODD;
 701         } else {
 702                 dafo |= SAB82532_DAFO_PAR_EVEN;
 703         }
 704         up->cached_dafo = dafo;
 705
 706         calc_ebrg(baud, &n, &m);
 707
 708         up->cached_ebrg = n | (m << 6);
 709
 710         up->tec_timeout = (10 * 1000000) / baud;
 711         up->cec_timeout = up->tec_timeout >> 2;
 712
 713         /* CTS flow control flags */
 714         /* We encode read_status_mask and ignore_status_mask like so:
 715          *
 716          * ---------------------
 717          * | ... | ISR1 | ISR0 |
 718          * ---------------------
 719          *  ..    15   8 7    0
 720          */
 721
 722         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 723                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 724                                      SAB82532_ISR0_CDSC);
 725         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 726                                       SAB82532_ISR1_ALLS |
 727                                       SAB82532_ISR1_XPR) << 8;
 728         if (iflag & INPCK)
 729                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 730                                               SAB82532_ISR0_FERR);
 731         if (iflag & (IGNBRK | BRKINT | PARMRK))
 732                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 733
 734         /*
 735          * Characteres to ignore
 736          */
 737         up->port.ignore_status_mask = 0;
 738         if (iflag & IGNPAR)
 739                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 740                                                 SAB82532_ISR0_FERR);
 741         if (iflag & IGNBRK) {
 742                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 743                 /*
 744                  * If we're ignoring parity and break indicators,
 745                  * ignore overruns too (for real raw support).
 746                  */
 747                 if (iflag & IGNPAR)
 748                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 749         }
 750
 751         /*
 752          * ignore all characters if CREAD is not set
 753          */
 754         if ((cflag & CREAD) == 0)
 755                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 756                                                 SAB82532_ISR0_TCD);
 757
 758         uart_update_timeout(&up->port, cflag,
 759                             (up->port.uartclk / (16 * quot)));
 760
 761         /* Now schedule a register update when the chip's
 762          * transmitter is idle.
 763          */
 764         up->cached_mode |= SAB82532_MODE_RAC;
 765         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 766         if (test_bit(SAB82532_XPR, &up->irqflags))
 767                 sunsab_tx_idle(up);
 768 }
 769
 770 /* port->lock is not held.  */
 771 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 772                                struct ktermios *old)
 773 {
 774         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 775         unsigned long flags;
 776         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 777         unsigned int quot = uart_get_divisor(port, baud);
 778
 779         spin_lock_irqsave(&up->port.lock, flags);
 780         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 781         spin_unlock_irqrestore(&up->port.lock, flags);
 782 }
 783
 784 static const char *sunsab_type(struct uart_port *port)
 785 {
 786         struct uart_sunsab_port *up = (void *)port;
 787         static char buf[36];
 788
 789         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 790         return buf;
 791 }
 792
 793 static void sunsab_release_port(struct uart_port *port)
 794 {
 795 }
 796
 797 static int sunsab_request_port(struct uart_port *port)
 798 {
 799         return 0;
 800 }
 801
 802 static void sunsab_config_port(struct uart_port *port, int flags)
 803 {
 804 }
 805
 806 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 807 {
 808         return -EINVAL;
 809 }
 810
 811 static struct uart_ops sunsab_pops = {
 812         .tx_empty       = sunsab_tx_empty,
 813         .set_mctrl      = sunsab_set_mctrl,
 814         .get_mctrl      = sunsab_get_mctrl,
 815         .stop_tx        = sunsab_stop_tx,
 816         .start_tx       = sunsab_start_tx,
 817         .send_xchar     = sunsab_send_xchar,
 818         .stop_rx        = sunsab_stop_rx,
 819         .break_ctl      = sunsab_break_ctl,
 820         .startup        = sunsab_startup,
 821         .shutdown       = sunsab_shutdown,
 822         .set_termios    = sunsab_set_termios,
 823         .type           = sunsab_type,
 824         .release_port   = sunsab_release_port,
 825         .request_port   = sunsab_request_port,
 826         .config_port    = sunsab_config_port,
 827         .verify_port    = sunsab_verify_port,
 828 };
 829
 830 static struct uart_driver sunsab_reg = {
 831         .owner                  = THIS_MODULE,
 832         .driver_name            = "sunsab",
 833         .dev_name               = "ttyS",
 834         .major                  = TTY_MAJOR,
 835 };
 836
 837 static struct uart_sunsab_port *sunsab_ports;
 838
 839 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 840
 841 static void sunsab_console_putchar(struct uart_port *port, int c)
 842 {
 843         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 844
 845         sunsab_tec_wait(up);
 846         writeb(c, &up->regs->w.tic);
 847 }
 848
 849 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 850 {
 851         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 852         unsigned long flags;
 853         int locked = 1;
 854
 855         if (up->port.sysrq || oops_in_progress)
 856                 locked = spin_trylock_irqsave(&up->port.lock, flags);
 857         else
 858                 spin_lock_irqsave(&up->port.lock, flags);
 859
 860         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 861         sunsab_tec_wait(up);
 862
 863         if (locked)
 864                 spin_unlock_irqrestore(&up->port.lock, flags);
 865 }
 866
 867 static int sunsab_console_setup(struct console *con, char *options)
 868 {
 869         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 870         unsigned long flags;
 871         unsigned int baud, quot;
 872
 873         /*
 874          * The console framework calls us for each and every port
 875          * registered. Defer the console setup until the requested
 876          * port has been properly discovered. A bit of a hack,
 877          * though...
 878          */
 879         if (up->port.type != PORT_SUNSAB)
 880                 return -1;
 881
 882         printk("Console: ttyS%d (SAB82532)\n",
 883                (sunsab_reg.minor - 64) + con->index);
 884
 885         sunserial_console_termios(con, up->port.dev->of_node);
 886
 887         switch (con->cflag & CBAUD) {
 888         case B150: baud = 150; break;
 889         case B300: baud = 300; break;
 890         case B600: baud = 600; break;
 891         case B1200: baud = 1200; break;
 892         case B2400: baud = 2400; break;
 893         case B4800: baud = 4800; break;
 894         default: case B9600: baud = 9600; break;
 895         case B19200: baud = 19200; break;
 896         case B38400: baud = 38400; break;
 897         case B57600: baud = 57600; break;
 898         case B115200: baud = 115200; break;
 899         case B230400: baud = 230400; break;
 900         case B460800: baud = 460800; break;
 901         }
 902
 903         /*
 904          * Temporary fix.
 905          */
 906         spin_lock_init(&up->port.lock);
 907
 908         /*
 909          * Initialize the hardware
 910          */
 911         sunsab_startup(&up->port);
 912
 913         spin_lock_irqsave(&up->port.lock, flags);
 914
 915         /*
 916          * Finally, enable interrupts
 917          */
 918         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 919                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 920         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 921         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 922                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 923                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 924                                 SAB82532_IMR1_XPR;
 925         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 926
 927         quot = uart_get_divisor(&up->port, baud);
 928         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 929         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 930
 931         spin_unlock_irqrestore(&up->port.lock, flags);
 932
 933         return 0;
 934 }
 935
 936 static struct console sunsab_console = {
 937         .name   =       "ttyS",
 938         .write  =       sunsab_console_write,
 939         .device =       uart_console_device,
 940         .setup  =       sunsab_console_setup,
 941         .flags  =       CON_PRINTBUFFER,
 942         .index  =       -1,
 943         .data   =       &sunsab_reg,
 944 };
 945
 946 static inline struct console *SUNSAB_CONSOLE(void)
 947 {
 948         return &sunsab_console;
 949 }
 950 #else
 951 #define SUNSAB_CONSOLE()        (NULL)
 952 #define sunsab_console_init()   do { } while (0)
 953 #endif
 954
 955 static int sunsab_init_one(struct uart_sunsab_port *up,
 956                                      struct platform_device *op,
 957                                      unsigned long offset,
 958                                      int line)
 959 {
 960         up->port.line = line;
 961         up->port.dev = &op->dev;
 962
 963         up->port.mapbase = op->resource[0].start + offset;
 964         up->port.membase = of_ioremap(&op->resource[0], offset,
 965                                       sizeof(union sab82532_async_regs),
 966                                       "sab");
 967         if (!up->port.membase)
 968                 return -ENOMEM;
 969         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
 970
 971         up->port.irq = op->archdata.irqs[0];
 972
 973         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
 974         up->port.iotype = UPIO_MEM;
 975
 976         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
 977
 978         up->port.ops = &sunsab_pops;
 979         up->port.type = PORT_SUNSAB;
 980         up->port.uartclk = SAB_BASE_BAUD;
 981
 982         up->type = readb(&up->regs->r.vstr) & 0x0f;
 983         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
 984         writeb(0xff, &up->regs->w.pim);
 985         if ((up->port.line & 0x1) == 0) {
 986                 up->pvr_dsr_bit = (1 << 0);
 987                 up->pvr_dtr_bit = (1 << 1);
 988                 up->gis_shift = 2;
 989         } else {
 990                 up->pvr_dsr_bit = (1 << 3);
 991                 up->pvr_dtr_bit = (1 << 2);
 992                 up->gis_shift = 0;
 993         }
 994         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
 995         writeb(up->cached_pvr, &up->regs->w.pvr);
 996         up->cached_mode = readb(&up->regs->rw.mode);
 997         up->cached_mode |= SAB82532_MODE_FRTS;
 998         writeb(up->cached_mode, &up->regs->rw.mode);
 999         up->cached_mode |= SAB82532_MODE_RTS;
1000         writeb(up->cached_mode, &up->regs->rw.mode);
1001
1002         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1003         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1004
1005         return 0;
1006 }
1007
1008 static int sab_probe(struct platform_device *op)
1009 {
1010         static int inst;
1011         struct uart_sunsab_port *up;
1012         int err;
1013
1014         up = &sunsab_ports[inst * 2];
1015
1016         err = sunsab_init_one(&up[0], op,
1017                               0,
1018                               (inst * 2) + 0);
1019         if (err)
1020                 goto out;
1021
1022         err = sunsab_init_one(&up[1], op,
1023                               sizeof(union sab82532_async_regs),
1024                               (inst * 2) + 1);
1025         if (err)
1026                 goto out1;
1027
1028         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1029                                 &sunsab_reg, up[0].port.line,
1030                                 false);
1031
1032         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1033                                 &sunsab_reg, up[1].port.line,
1034                                 false);
1035
1036         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1037         if (err)
1038                 goto out2;
1039
1040         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1041         if (err)
1042                 goto out3;
1043
1044         platform_set_drvdata(op, &up[0]);
1045
1046         inst++;
1047
1048         return 0;
1049
1050 out3:
1051         uart_remove_one_port(&sunsab_reg, &up[0].port);
1052 out2:
1053         of_iounmap(&op->resource[0],
1054                    up[1].port.membase,
1055                    sizeof(union sab82532_async_regs));
1056 out1:
1057         of_iounmap(&op->resource[0],
1058                    up[0].port.membase,
1059                    sizeof(union sab82532_async_regs));
1060 out:
1061         return err;
1062 }
1063
1064 static int sab_remove(struct platform_device *op)
1065 {
1066         struct uart_sunsab_port *up = platform_get_drvdata(op);
1067
1068         uart_remove_one_port(&sunsab_reg, &up[1].port);
1069         uart_remove_one_port(&sunsab_reg, &up[0].port);
1070         of_iounmap(&op->resource[0],
1071                    up[1].port.membase,
1072                    sizeof(union sab82532_async_regs));
1073         of_iounmap(&op->resource[0],
1074                    up[0].port.membase,
1075                    sizeof(union sab82532_async_regs));
1076
1077         return 0;
1078 }
1079
1080 static const struct of_device_id sab_match[] = {
1081         {
1082                 .name = "se",
1083         },
1084         {
1085                 .name = "serial",
1086                 .compatible = "sab82532",
1087         },
1088         {},
1089 };
1090 MODULE_DEVICE_TABLE(of, sab_match);
1091
1092 static struct platform_driver sab_driver = {
1093         .driver = {
1094                 .name = "sab",
1095                 .owner = THIS_MODULE,
1096                 .of_match_table = sab_match,
1097         },
1098         .probe          = sab_probe,
1099         .remove         = sab_remove,
1100 };
1101
1102 static int __init sunsab_init(void)
1103 {
1104         struct device_node *dp;
1105         int err;
1106         int num_channels = 0;
1107
1108         for_each_node_by_name(dp, "se")
1109                 num_channels += 2;
1110         for_each_node_by_name(dp, "serial") {
1111                 if (of_device_is_compatible(dp, "sab82532"))
1112                         num_channels += 2;
1113         }
1114
1115         if (num_channels) {
1116                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1117                                        num_channels, GFP_KERNEL);
1118                 if (!sunsab_ports)
1119                         return -ENOMEM;
1120
1121                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1122                 if (err) {
1123                         kfree(sunsab_ports);
1124                         sunsab_ports = NULL;
1125
1126                         return err;
1127                 }
1128         }
1129
1130         return platform_driver_register(&sab_driver);
1131 }
1132
1133 static void __exit sunsab_exit(void)
1134 {
1135         platform_driver_unregister(&sab_driver);
1136         if (sunsab_reg.nr) {
1137                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1138         }
1139
1140         kfree(sunsab_ports);
1141         sunsab_ports = NULL;
1142 }
1143
1144 module_init(sunsab_init);
1145 module_exit(sunsab_exit);
1146
1147 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1148 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1149 MODULE_LICENSE("GPL");