2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
34 #define CDNS_UART_TTY_NAME "ttyPS"
35 #define CDNS_UART_NAME "xuartps"
36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38 #define CDNS_UART_NR_PORTS 2
39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40 #define CDNS_UART_REGISTER_SPACE 0x1000
42 /* Rx Trigger level */
43 static int rx_trigger_level = 56;
44 module_param(rx_trigger_level, uint, S_IRUGO);
45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
48 static int rx_timeout = 10;
49 module_param(rx_timeout, uint, S_IRUGO);
50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
52 /* Register offsets for the UART. */
53 #define CDNS_UART_CR 0x00 /* Control Register */
54 #define CDNS_UART_MR 0x04 /* Mode Register */
55 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
56 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
59 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64 #define CDNS_UART_SR 0x2C /* Channel Status */
65 #define CDNS_UART_FIFO 0x30 /* FIFO */
66 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
72 /* Control Register Bit Definitions */
73 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
93 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
97 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
107 * Interrupt Registers:
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
115 * All four registers have the same bit definitions.
117 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
119 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
129 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_PARITY | CDNS_UART_IXR_FRAMING | \
130 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_RXTRIG | \
133 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
134 #define CDNS_UART_IXR_BRK 0x80000000
137 * Modem Control register:
138 * The read/write Modem Control register controls the interface with the modem
139 * or data set, or a peripheral device emulating a modem.
141 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
142 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
143 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
146 * Channel Status Register:
147 * The channel status register (CSR) is provided to enable the control logic
148 * to monitor the status of bits in the channel interrupt status register,
149 * even if these are masked out by the interrupt mask register.
151 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
152 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
153 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
154 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
156 /* baud dividers min/max values */
157 #define CDNS_UART_BDIV_MIN 4
158 #define CDNS_UART_BDIV_MAX 255
159 #define CDNS_UART_CD_MAX 65535
162 * struct cdns_uart - device data
163 * @port: Pointer to the UART port
164 * @uartclk: Reference clock
166 * @baud: Current baud rate
167 * @clk_rate_change_nb: Notifier block for clock changes
170 struct uart_port *port;
174 struct notifier_block clk_rate_change_nb;
176 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
179 static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
182 * There is no hardware break detection, so we interpret framing
183 * error with all-zeros data as a break sequence. Most of the time,
184 * there's another non-zero byte at the end of the sequence.
186 if (isrstatus & CDNS_UART_IXR_FRAMING) {
187 while (!(readl(port->membase + CDNS_UART_SR) &
188 CDNS_UART_SR_RXEMPTY)) {
189 if (!readl(port->membase + CDNS_UART_FIFO)) {
190 port->read_status_mask |= CDNS_UART_IXR_BRK;
191 isrstatus &= ~CDNS_UART_IXR_FRAMING;
194 writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR);
197 /* drop byte with parity error if IGNPAR specified */
198 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
199 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
201 isrstatus &= port->read_status_mask;
202 isrstatus &= ~port->ignore_status_mask;
204 if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG)))
207 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) {
209 char status = TTY_NORMAL;
211 data = readl(port->membase + CDNS_UART_FIFO);
213 /* Non-NULL byte after BREAK is garbage (99%) */
214 if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) {
215 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
217 if (uart_handle_break(port))
221 if (uart_handle_sysrq_char(port, data))
226 if (isrstatus & CDNS_UART_IXR_PARITY) {
227 port->icount.parity++;
229 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
230 port->icount.frame++;
232 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
233 port->icount.overrun++;
236 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
239 tty_flip_buffer_push(&port->state->port);
242 static void cdns_uart_handle_tx(struct uart_port *port)
244 unsigned int numbytes;
246 if (uart_circ_empty(&port->state->xmit)) {
247 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
251 numbytes = port->fifosize;
252 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
253 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
255 * Get the data from the UART circular buffer
256 * and write it to the cdns_uart's TX_FIFO
259 writel(port->state->xmit.buf[port->state->xmit.tail],
260 port->membase + CDNS_UART_FIFO);
264 * Adjust the tail of the UART buffer and wrap
265 * the buffer if it reaches limit.
267 port->state->xmit.tail =
268 (port->state->xmit.tail + 1) & (UART_XMIT_SIZE - 1);
273 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(port);
278 * cdns_uart_isr - Interrupt handler
280 * @dev_id: Id of the port
284 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
286 struct uart_port *port = (struct uart_port *)dev_id;
288 unsigned int isrstatus;
290 spin_lock_irqsave(&port->lock, flags);
292 /* Read the interrupt status register to determine which
293 * interrupt(s) is/are active.
295 isrstatus = readl(port->membase + CDNS_UART_ISR);
297 if (isrstatus & CDNS_UART_RX_IRQS)
298 cdns_uart_handle_rx(port, isrstatus);
300 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY)
301 cdns_uart_handle_tx(port);
303 writel(isrstatus, port->membase + CDNS_UART_ISR);
305 /* be sure to release the lock and tty before leaving */
306 spin_unlock_irqrestore(&port->lock, flags);
312 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
313 * @clk: UART module input clock
314 * @baud: Desired baud rate
315 * @rbdiv: BDIV value (return value)
316 * @rcd: CD value (return value)
317 * @div8: Value for clk_sel bit in mod (return value)
318 * Return: baud rate, requested baud when possible, or actual baud when there
319 * was too much error, zero if no valid divisors are found.
321 * Formula to obtain baud rate is
322 * baud_tx/rx rate = clk/CD * (BDIV + 1)
323 * input_clk = (Uart User Defined Clock or Apb Clock)
324 * depends on UCLKEN in MR Reg
325 * clk = input_clk or input_clk/8;
326 * depends on CLKS in MR reg
327 * CD and BDIV depends on values in
328 * baud rate generate register
329 * baud rate clock divisor register
331 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
332 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
335 unsigned int calc_baud;
336 unsigned int bestbaud = 0;
337 unsigned int bauderror;
338 unsigned int besterror = ~0;
340 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
347 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
348 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
349 if (cd < 1 || cd > CDNS_UART_CD_MAX)
352 calc_baud = clk / (cd * (bdiv + 1));
354 if (baud > calc_baud)
355 bauderror = baud - calc_baud;
357 bauderror = calc_baud - baud;
359 if (besterror > bauderror) {
362 bestbaud = calc_baud;
363 besterror = bauderror;
366 /* use the values when percent error is acceptable */
367 if (((besterror * 100) / baud) < 3)
374 * cdns_uart_set_baud_rate - Calculate and set the baud rate
375 * @port: Handle to the uart port structure
376 * @baud: Baud rate to set
377 * Return: baud rate, requested baud when possible, or actual baud when there
378 * was too much error, zero if no valid divisors are found.
380 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
383 unsigned int calc_baud;
384 u32 cd = 0, bdiv = 0;
387 struct cdns_uart *cdns_uart = port->private_data;
389 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
392 /* Write new divisors to hardware */
393 mreg = readl(port->membase + CDNS_UART_MR);
395 mreg |= CDNS_UART_MR_CLKSEL;
397 mreg &= ~CDNS_UART_MR_CLKSEL;
398 writel(mreg, port->membase + CDNS_UART_MR);
399 writel(cd, port->membase + CDNS_UART_BAUDGEN);
400 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
401 cdns_uart->baud = baud;
406 #ifdef CONFIG_COMMON_CLK
408 * cdns_uart_clk_notitifer_cb - Clock notifier callback
409 * @nb: Notifier block
410 * @event: Notify event
411 * @data: Notifier data
412 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
414 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
415 unsigned long event, void *data)
418 struct uart_port *port;
420 struct clk_notifier_data *ndata = data;
421 unsigned long flags = 0;
422 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
424 port = cdns_uart->port;
429 case PRE_RATE_CHANGE:
435 * Find out if current baud-rate can be achieved with new clock
438 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
439 &bdiv, &cd, &div8)) {
440 dev_warn(port->dev, "clock rate change rejected\n");
444 spin_lock_irqsave(&cdns_uart->port->lock, flags);
446 /* Disable the TX and RX to set baud rate */
447 ctrl_reg = readl(port->membase + CDNS_UART_CR);
448 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
449 writel(ctrl_reg, port->membase + CDNS_UART_CR);
451 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
455 case POST_RATE_CHANGE:
457 * Set clk dividers to generate correct baud with new clock
461 spin_lock_irqsave(&cdns_uart->port->lock, flags);
464 port->uartclk = ndata->new_rate;
466 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
469 case ABORT_RATE_CHANGE:
471 spin_lock_irqsave(&cdns_uart->port->lock, flags);
473 /* Set TX/RX Reset */
474 ctrl_reg = readl(port->membase + CDNS_UART_CR);
475 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
476 writel(ctrl_reg, port->membase + CDNS_UART_CR);
478 while (readl(port->membase + CDNS_UART_CR) &
479 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
483 * Clear the RX disable and TX disable bits and then set the TX
484 * enable bit and RX enable bit to enable the transmitter and
487 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
488 ctrl_reg = readl(port->membase + CDNS_UART_CR);
489 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
490 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
491 writel(ctrl_reg, port->membase + CDNS_UART_CR);
493 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
503 * cdns_uart_start_tx - Start transmitting bytes
504 * @port: Handle to the uart port structure
506 static void cdns_uart_start_tx(struct uart_port *port)
510 if (uart_tx_stopped(port))
514 * Set the TX enable bit and clear the TX disable bit to enable the
517 status = readl(port->membase + CDNS_UART_CR);
518 status &= ~CDNS_UART_CR_TX_DIS;
519 status |= CDNS_UART_CR_TX_EN;
520 writel(status, port->membase + CDNS_UART_CR);
522 if (uart_circ_empty(&port->state->xmit))
525 cdns_uart_handle_tx(port);
527 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
528 /* Enable the TX Empty interrupt */
529 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
533 * cdns_uart_stop_tx - Stop TX
534 * @port: Handle to the uart port structure
536 static void cdns_uart_stop_tx(struct uart_port *port)
540 regval = readl(port->membase + CDNS_UART_CR);
541 regval |= CDNS_UART_CR_TX_DIS;
542 /* Disable the transmitter */
543 writel(regval, port->membase + CDNS_UART_CR);
547 * cdns_uart_stop_rx - Stop RX
548 * @port: Handle to the uart port structure
550 static void cdns_uart_stop_rx(struct uart_port *port)
554 /* Disable RX IRQs */
555 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
557 /* Disable the receiver */
558 regval = readl(port->membase + CDNS_UART_CR);
559 regval |= CDNS_UART_CR_RX_DIS;
560 writel(regval, port->membase + CDNS_UART_CR);
564 * cdns_uart_tx_empty - Check whether TX is empty
565 * @port: Handle to the uart port structure
567 * Return: TIOCSER_TEMT on success, 0 otherwise
569 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
573 status = readl(port->membase + CDNS_UART_SR) &
574 CDNS_UART_SR_TXEMPTY;
575 return status ? TIOCSER_TEMT : 0;
579 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
580 * transmitting char breaks
581 * @port: Handle to the uart port structure
582 * @ctl: Value based on which start or stop decision is taken
584 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
589 spin_lock_irqsave(&port->lock, flags);
591 status = readl(port->membase + CDNS_UART_CR);
594 writel(CDNS_UART_CR_STARTBRK | status,
595 port->membase + CDNS_UART_CR);
597 if ((status & CDNS_UART_CR_STOPBRK) == 0)
598 writel(CDNS_UART_CR_STOPBRK | status,
599 port->membase + CDNS_UART_CR);
601 spin_unlock_irqrestore(&port->lock, flags);
605 * cdns_uart_set_termios - termios operations, handling data length, parity,
606 * stop bits, flow control, baud rate
607 * @port: Handle to the uart port structure
608 * @termios: Handle to the input termios structure
609 * @old: Values of the previously saved termios structure
611 static void cdns_uart_set_termios(struct uart_port *port,
612 struct ktermios *termios, struct ktermios *old)
614 unsigned int cval = 0;
615 unsigned int baud, minbaud, maxbaud;
617 unsigned int ctrl_reg, mode_reg;
619 spin_lock_irqsave(&port->lock, flags);
621 /* Wait for the transmit FIFO to empty before making changes */
622 if (!(readl(port->membase + CDNS_UART_CR) &
623 CDNS_UART_CR_TX_DIS)) {
624 while (!(readl(port->membase + CDNS_UART_SR) &
625 CDNS_UART_SR_TXEMPTY)) {
630 /* Disable the TX and RX to set baud rate */
631 ctrl_reg = readl(port->membase + CDNS_UART_CR);
632 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
633 writel(ctrl_reg, port->membase + CDNS_UART_CR);
636 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
637 * min and max baud should be calculated here based on port->uartclk.
638 * this way we get a valid baud and can safely call set_baud()
640 minbaud = port->uartclk /
641 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
642 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
643 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
644 baud = cdns_uart_set_baud_rate(port, baud);
645 if (tty_termios_baud_rate(termios))
646 tty_termios_encode_baud_rate(termios, baud, baud);
648 /* Update the per-port timeout. */
649 uart_update_timeout(port, termios->c_cflag, baud);
651 /* Set TX/RX Reset */
652 ctrl_reg = readl(port->membase + CDNS_UART_CR);
653 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
654 writel(ctrl_reg, port->membase + CDNS_UART_CR);
657 * Clear the RX disable and TX disable bits and then set the TX enable
658 * bit and RX enable bit to enable the transmitter and receiver.
660 ctrl_reg = readl(port->membase + CDNS_UART_CR);
661 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
662 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
663 writel(ctrl_reg, port->membase + CDNS_UART_CR);
665 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
667 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
668 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
669 port->ignore_status_mask = 0;
671 if (termios->c_iflag & INPCK)
672 port->read_status_mask |= CDNS_UART_IXR_PARITY |
673 CDNS_UART_IXR_FRAMING;
675 if (termios->c_iflag & IGNPAR)
676 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
677 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
679 /* ignore all characters if CREAD is not set */
680 if ((termios->c_cflag & CREAD) == 0)
681 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
682 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
683 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
685 mode_reg = readl(port->membase + CDNS_UART_MR);
687 /* Handling Data Size */
688 switch (termios->c_cflag & CSIZE) {
690 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
693 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
697 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
698 termios->c_cflag &= ~CSIZE;
699 termios->c_cflag |= CS8;
703 /* Handling Parity and Stop Bits length */
704 if (termios->c_cflag & CSTOPB)
705 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
707 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
709 if (termios->c_cflag & PARENB) {
710 /* Mark or Space parity */
711 if (termios->c_cflag & CMSPAR) {
712 if (termios->c_cflag & PARODD)
713 cval |= CDNS_UART_MR_PARITY_MARK;
715 cval |= CDNS_UART_MR_PARITY_SPACE;
717 if (termios->c_cflag & PARODD)
718 cval |= CDNS_UART_MR_PARITY_ODD;
720 cval |= CDNS_UART_MR_PARITY_EVEN;
723 cval |= CDNS_UART_MR_PARITY_NONE;
725 cval |= mode_reg & 1;
726 writel(cval, port->membase + CDNS_UART_MR);
728 spin_unlock_irqrestore(&port->lock, flags);
732 * cdns_uart_startup - Called when an application opens a cdns_uart port
733 * @port: Handle to the uart port structure
735 * Return: 0 on success, negative errno otherwise
737 static int cdns_uart_startup(struct uart_port *port)
741 unsigned int status = 0;
743 spin_lock_irqsave(&port->lock, flags);
745 /* Disable the TX and RX */
746 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
747 port->membase + CDNS_UART_CR);
749 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
752 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
753 port->membase + CDNS_UART_CR);
756 * Clear the RX disable bit and then set the RX enable bit to enable
759 status = readl(port->membase + CDNS_UART_CR);
760 status &= CDNS_UART_CR_RX_DIS;
761 status |= CDNS_UART_CR_RX_EN;
762 writel(status, port->membase + CDNS_UART_CR);
764 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
767 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
768 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
769 port->membase + CDNS_UART_MR);
772 * Set the RX FIFO Trigger level to use most of the FIFO, but it
773 * can be tuned with a module parameter
775 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
778 * Receive Timeout register is enabled but it
779 * can be tuned with a module parameter
781 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
783 /* Clear out any pending interrupts before enabling them */
784 writel(readl(port->membase + CDNS_UART_ISR),
785 port->membase + CDNS_UART_ISR);
787 spin_unlock_irqrestore(&port->lock, flags);
789 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
791 dev_err(port->dev, "request_irq '%d' failed with %d\n",
796 /* Set the Interrupt Registers with desired interrupts */
797 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
803 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
804 * @port: Handle to the uart port structure
806 static void cdns_uart_shutdown(struct uart_port *port)
811 spin_lock_irqsave(&port->lock, flags);
813 /* Disable interrupts */
814 status = readl(port->membase + CDNS_UART_IMR);
815 writel(status, port->membase + CDNS_UART_IDR);
816 writel(0xffffffff, port->membase + CDNS_UART_ISR);
818 /* Disable the TX and RX */
819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
820 port->membase + CDNS_UART_CR);
822 spin_unlock_irqrestore(&port->lock, flags);
824 free_irq(port->irq, port);
828 * cdns_uart_type - Set UART type to cdns_uart port
829 * @port: Handle to the uart port structure
831 * Return: string on success, NULL otherwise
833 static const char *cdns_uart_type(struct uart_port *port)
835 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
839 * cdns_uart_verify_port - Verify the port params
840 * @port: Handle to the uart port structure
841 * @ser: Handle to the structure whose members are compared
843 * Return: 0 on success, negative errno otherwise.
845 static int cdns_uart_verify_port(struct uart_port *port,
846 struct serial_struct *ser)
848 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
850 if (port->irq != ser->irq)
852 if (ser->io_type != UPIO_MEM)
854 if (port->iobase != ser->port)
862 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
863 * called when the driver adds a cdns_uart port via
864 * uart_add_one_port()
865 * @port: Handle to the uart port structure
867 * Return: 0 on success, negative errno otherwise.
869 static int cdns_uart_request_port(struct uart_port *port)
871 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
876 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
877 if (!port->membase) {
878 dev_err(port->dev, "Unable to map registers\n");
879 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
886 * cdns_uart_release_port - Release UART port
887 * @port: Handle to the uart port structure
889 * Release the memory region attached to a cdns_uart port. Called when the
890 * driver removes a cdns_uart port via uart_remove_one_port().
892 static void cdns_uart_release_port(struct uart_port *port)
894 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
895 iounmap(port->membase);
896 port->membase = NULL;
900 * cdns_uart_config_port - Configure UART port
901 * @port: Handle to the uart port structure
904 static void cdns_uart_config_port(struct uart_port *port, int flags)
906 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
907 port->type = PORT_XUARTPS;
911 * cdns_uart_get_mctrl - Get the modem control state
912 * @port: Handle to the uart port structure
914 * Return: the modem control state
916 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
918 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
921 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
925 val = readl(port->membase + CDNS_UART_MODEMCR);
927 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
929 if (mctrl & TIOCM_RTS)
930 val |= CDNS_UART_MODEMCR_RTS;
931 if (mctrl & TIOCM_DTR)
932 val |= CDNS_UART_MODEMCR_DTR;
934 writel(val, port->membase + CDNS_UART_MODEMCR);
937 #ifdef CONFIG_CONSOLE_POLL
938 static int cdns_uart_poll_get_char(struct uart_port *port)
943 spin_lock_irqsave(&port->lock, flags);
945 /* Check if FIFO is empty */
946 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
948 else /* Read a character */
949 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
951 spin_unlock_irqrestore(&port->lock, flags);
956 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
960 spin_lock_irqsave(&port->lock, flags);
962 /* Wait until FIFO is empty */
963 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
966 /* Write a character */
967 writel(c, port->membase + CDNS_UART_FIFO);
969 /* Wait until FIFO is empty */
970 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
973 spin_unlock_irqrestore(&port->lock, flags);
979 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
980 unsigned int oldstate)
982 struct cdns_uart *cdns_uart = port->private_data;
985 case UART_PM_STATE_OFF:
986 clk_disable(cdns_uart->uartclk);
987 clk_disable(cdns_uart->pclk);
990 clk_enable(cdns_uart->pclk);
991 clk_enable(cdns_uart->uartclk);
996 static struct uart_ops cdns_uart_ops = {
997 .set_mctrl = cdns_uart_set_mctrl,
998 .get_mctrl = cdns_uart_get_mctrl,
999 .start_tx = cdns_uart_start_tx,
1000 .stop_tx = cdns_uart_stop_tx,
1001 .stop_rx = cdns_uart_stop_rx,
1002 .tx_empty = cdns_uart_tx_empty,
1003 .break_ctl = cdns_uart_break_ctl,
1004 .set_termios = cdns_uart_set_termios,
1005 .startup = cdns_uart_startup,
1006 .shutdown = cdns_uart_shutdown,
1008 .type = cdns_uart_type,
1009 .verify_port = cdns_uart_verify_port,
1010 .request_port = cdns_uart_request_port,
1011 .release_port = cdns_uart_release_port,
1012 .config_port = cdns_uart_config_port,
1013 #ifdef CONFIG_CONSOLE_POLL
1014 .poll_get_char = cdns_uart_poll_get_char,
1015 .poll_put_char = cdns_uart_poll_put_char,
1019 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1022 * cdns_uart_get_port - Configure the port from platform device resource info
1025 * Return: a pointer to a uart_port or NULL for failure
1027 static struct uart_port *cdns_uart_get_port(int id)
1029 struct uart_port *port;
1031 /* Try the given port id if failed use default method */
1032 if (cdns_uart_port[id].mapbase != 0) {
1033 /* Find the next unused port */
1034 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1035 if (cdns_uart_port[id].mapbase == 0)
1039 if (id >= CDNS_UART_NR_PORTS)
1042 port = &cdns_uart_port[id];
1044 /* At this point, we've got an empty uart_port struct, initialize it */
1045 spin_lock_init(&port->lock);
1046 port->membase = NULL;
1048 port->type = PORT_UNKNOWN;
1049 port->iotype = UPIO_MEM32;
1050 port->flags = UPF_BOOT_AUTOCONF;
1051 port->ops = &cdns_uart_ops;
1052 port->fifosize = CDNS_UART_FIFO_SIZE;
1058 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1060 * cdns_uart_console_wait_tx - Wait for the TX to be full
1061 * @port: Handle to the uart port structure
1063 static void cdns_uart_console_wait_tx(struct uart_port *port)
1065 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1070 * cdns_uart_console_putchar - write the character to the FIFO buffer
1071 * @port: Handle to the uart port structure
1072 * @ch: Character to be written
1074 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1076 cdns_uart_console_wait_tx(port);
1077 writel(ch, port->membase + CDNS_UART_FIFO);
1080 static void __init cdns_early_write(struct console *con, const char *s,
1083 struct earlycon_device *dev = con->data;
1085 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1088 static int __init cdns_early_console_setup(struct earlycon_device *device,
1091 if (!device->port.membase)
1094 device->con->write = cdns_early_write;
1098 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1099 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1100 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1103 * cdns_uart_console_write - perform write operation
1104 * @co: Console handle
1105 * @s: Pointer to character array
1106 * @count: No of characters
1108 static void cdns_uart_console_write(struct console *co, const char *s,
1111 struct uart_port *port = &cdns_uart_port[co->index];
1112 unsigned long flags;
1113 unsigned int imr, ctrl;
1118 else if (oops_in_progress)
1119 locked = spin_trylock_irqsave(&port->lock, flags);
1121 spin_lock_irqsave(&port->lock, flags);
1123 /* save and disable interrupt */
1124 imr = readl(port->membase + CDNS_UART_IMR);
1125 writel(imr, port->membase + CDNS_UART_IDR);
1128 * Make sure that the tx part is enabled. Set the TX enable bit and
1129 * clear the TX disable bit to enable the transmitter.
1131 ctrl = readl(port->membase + CDNS_UART_CR);
1132 ctrl &= ~CDNS_UART_CR_TX_DIS;
1133 ctrl |= CDNS_UART_CR_TX_EN;
1134 writel(ctrl, port->membase + CDNS_UART_CR);
1136 uart_console_write(port, s, count, cdns_uart_console_putchar);
1137 cdns_uart_console_wait_tx(port);
1139 writel(ctrl, port->membase + CDNS_UART_CR);
1141 /* restore interrupt state */
1142 writel(imr, port->membase + CDNS_UART_IER);
1145 spin_unlock_irqrestore(&port->lock, flags);
1149 * cdns_uart_console_setup - Initialize the uart to default config
1150 * @co: Console handle
1151 * @options: Initial settings of uart
1153 * Return: 0 on success, negative errno otherwise.
1155 static int __init cdns_uart_console_setup(struct console *co, char *options)
1157 struct uart_port *port = &cdns_uart_port[co->index];
1163 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1166 if (!port->membase) {
1167 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1173 uart_parse_options(options, &baud, &parity, &bits, &flow);
1175 return uart_set_options(port, co, baud, parity, bits, flow);
1178 static struct uart_driver cdns_uart_uart_driver;
1180 static struct console cdns_uart_console = {
1181 .name = CDNS_UART_TTY_NAME,
1182 .write = cdns_uart_console_write,
1183 .device = uart_console_device,
1184 .setup = cdns_uart_console_setup,
1185 .flags = CON_PRINTBUFFER,
1186 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1187 .data = &cdns_uart_uart_driver,
1191 * cdns_uart_console_init - Initialization call
1193 * Return: 0 on success, negative errno otherwise
1195 static int __init cdns_uart_console_init(void)
1197 register_console(&cdns_uart_console);
1201 console_initcall(cdns_uart_console_init);
1203 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1205 static struct uart_driver cdns_uart_uart_driver = {
1206 .owner = THIS_MODULE,
1207 .driver_name = CDNS_UART_NAME,
1208 .dev_name = CDNS_UART_TTY_NAME,
1209 .major = CDNS_UART_MAJOR,
1210 .minor = CDNS_UART_MINOR,
1211 .nr = CDNS_UART_NR_PORTS,
1212 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1213 .cons = &cdns_uart_console,
1217 #ifdef CONFIG_PM_SLEEP
1219 * cdns_uart_suspend - suspend event
1220 * @device: Pointer to the device structure
1224 static int cdns_uart_suspend(struct device *device)
1226 struct uart_port *port = dev_get_drvdata(device);
1227 struct tty_struct *tty;
1228 struct device *tty_dev;
1231 /* Get the tty which could be NULL so don't assume it's valid */
1232 tty = tty_port_tty_get(&port->state->port);
1235 may_wake = device_may_wakeup(tty_dev);
1240 * Call the API provided in serial_core.c file which handles
1243 uart_suspend_port(&cdns_uart_uart_driver, port);
1244 if (console_suspend_enabled && !may_wake) {
1245 struct cdns_uart *cdns_uart = port->private_data;
1247 clk_disable(cdns_uart->uartclk);
1248 clk_disable(cdns_uart->pclk);
1250 unsigned long flags = 0;
1252 spin_lock_irqsave(&port->lock, flags);
1253 /* Empty the receive FIFO 1st before making changes */
1254 while (!(readl(port->membase + CDNS_UART_SR) &
1255 CDNS_UART_SR_RXEMPTY))
1256 readl(port->membase + CDNS_UART_FIFO);
1257 /* set RX trigger level to 1 */
1258 writel(1, port->membase + CDNS_UART_RXWM);
1259 /* disable RX timeout interrups */
1260 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1261 spin_unlock_irqrestore(&port->lock, flags);
1268 * cdns_uart_resume - Resume after a previous suspend
1269 * @device: Pointer to the device structure
1273 static int cdns_uart_resume(struct device *device)
1275 struct uart_port *port = dev_get_drvdata(device);
1276 unsigned long flags = 0;
1278 struct tty_struct *tty;
1279 struct device *tty_dev;
1282 /* Get the tty which could be NULL so don't assume it's valid */
1283 tty = tty_port_tty_get(&port->state->port);
1286 may_wake = device_may_wakeup(tty_dev);
1290 if (console_suspend_enabled && !may_wake) {
1291 struct cdns_uart *cdns_uart = port->private_data;
1293 clk_enable(cdns_uart->pclk);
1294 clk_enable(cdns_uart->uartclk);
1296 spin_lock_irqsave(&port->lock, flags);
1298 /* Set TX/RX Reset */
1299 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1300 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1301 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1302 while (readl(port->membase + CDNS_UART_CR) &
1303 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1306 /* restore rx timeout value */
1307 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1309 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1310 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1311 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1312 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1314 spin_unlock_irqrestore(&port->lock, flags);
1316 spin_lock_irqsave(&port->lock, flags);
1317 /* restore original rx trigger level */
1318 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1319 /* enable RX timeout interrupt */
1320 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1321 spin_unlock_irqrestore(&port->lock, flags);
1324 return uart_resume_port(&cdns_uart_uart_driver, port);
1326 #endif /* ! CONFIG_PM_SLEEP */
1328 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1332 * cdns_uart_probe - Platform driver probe
1333 * @pdev: Pointer to the platform device structure
1335 * Return: 0 on success, negative errno otherwise
1337 static int cdns_uart_probe(struct platform_device *pdev)
1340 struct uart_port *port;
1341 struct resource *res;
1342 struct cdns_uart *cdns_uart_data;
1344 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1346 if (!cdns_uart_data)
1349 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1350 if (IS_ERR(cdns_uart_data->pclk)) {
1351 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1352 if (!IS_ERR(cdns_uart_data->pclk))
1353 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1355 if (IS_ERR(cdns_uart_data->pclk)) {
1356 dev_err(&pdev->dev, "pclk clock not found.\n");
1357 return PTR_ERR(cdns_uart_data->pclk);
1360 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1361 if (IS_ERR(cdns_uart_data->uartclk)) {
1362 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1363 if (!IS_ERR(cdns_uart_data->uartclk))
1364 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1366 if (IS_ERR(cdns_uart_data->uartclk)) {
1367 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1368 return PTR_ERR(cdns_uart_data->uartclk);
1371 rc = clk_prepare(cdns_uart_data->pclk);
1373 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1376 rc = clk_prepare(cdns_uart_data->uartclk);
1378 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1379 goto err_out_clk_dis_pclk;
1382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1385 goto err_out_clk_disable;
1388 irq = platform_get_irq(pdev, 0);
1391 goto err_out_clk_disable;
1394 #ifdef CONFIG_COMMON_CLK
1395 cdns_uart_data->clk_rate_change_nb.notifier_call =
1396 cdns_uart_clk_notifier_cb;
1397 if (clk_notifier_register(cdns_uart_data->uartclk,
1398 &cdns_uart_data->clk_rate_change_nb))
1399 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1401 /* Look for a serialN alias */
1402 id = of_alias_get_id(pdev->dev.of_node, "serial");
1406 /* Initialize the port structure */
1407 port = cdns_uart_get_port(id);
1410 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1412 goto err_out_notif_unreg;
1416 * Register the port.
1417 * This function also registers this device with the tty layer
1418 * and triggers invocation of the config_port() entry point.
1420 port->mapbase = res->start;
1422 port->dev = &pdev->dev;
1423 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1424 port->private_data = cdns_uart_data;
1425 cdns_uart_data->port = port;
1426 platform_set_drvdata(pdev, port);
1428 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1431 "uart_add_one_port() failed; err=%i\n", rc);
1432 goto err_out_notif_unreg;
1437 err_out_notif_unreg:
1438 #ifdef CONFIG_COMMON_CLK
1439 clk_notifier_unregister(cdns_uart_data->uartclk,
1440 &cdns_uart_data->clk_rate_change_nb);
1442 err_out_clk_disable:
1443 clk_unprepare(cdns_uart_data->uartclk);
1444 err_out_clk_dis_pclk:
1445 clk_unprepare(cdns_uart_data->pclk);
1451 * cdns_uart_remove - called when the platform driver is unregistered
1452 * @pdev: Pointer to the platform device structure
1454 * Return: 0 on success, negative errno otherwise
1456 static int cdns_uart_remove(struct platform_device *pdev)
1458 struct uart_port *port = platform_get_drvdata(pdev);
1459 struct cdns_uart *cdns_uart_data = port->private_data;
1462 /* Remove the cdns_uart port from the serial core */
1463 #ifdef CONFIG_COMMON_CLK
1464 clk_notifier_unregister(cdns_uart_data->uartclk,
1465 &cdns_uart_data->clk_rate_change_nb);
1467 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1469 clk_unprepare(cdns_uart_data->uartclk);
1470 clk_unprepare(cdns_uart_data->pclk);
1474 /* Match table for of_platform binding */
1475 static const struct of_device_id cdns_uart_of_match[] = {
1476 { .compatible = "xlnx,xuartps", },
1477 { .compatible = "cdns,uart-r1p8", },
1480 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1482 static struct platform_driver cdns_uart_platform_driver = {
1483 .probe = cdns_uart_probe,
1484 .remove = cdns_uart_remove,
1486 .name = CDNS_UART_NAME,
1487 .of_match_table = cdns_uart_of_match,
1488 .pm = &cdns_uart_dev_pm_ops,
1492 static int __init cdns_uart_init(void)
1496 /* Register the cdns_uart driver with the serial core */
1497 retval = uart_register_driver(&cdns_uart_uart_driver);
1501 /* Register the platform driver */
1502 retval = platform_driver_register(&cdns_uart_platform_driver);
1504 uart_unregister_driver(&cdns_uart_uart_driver);
1509 static void __exit cdns_uart_exit(void)
1511 /* Unregister the platform driver */
1512 platform_driver_unregister(&cdns_uart_platform_driver);
1514 /* Unregister the cdns_uart driver */
1515 uart_unregister_driver(&cdns_uart_uart_driver);
1518 module_init(cdns_uart_init);
1519 module_exit(cdns_uart_exit);
1521 MODULE_DESCRIPTION("Driver for Cadence UART");
1522 MODULE_AUTHOR("Xilinx Inc.");
1523 MODULE_LICENSE("GPL");