2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
45 * - Suspend & Remote Wakeup
47 #include <linux/delay.h>
48 #include <linux/device.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/phy/phy.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/idr.h>
54 #include <linux/interrupt.h>
56 #include <linux/kernel.h>
57 #include <linux/slab.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/usb/ch9.h>
60 #include <linux/usb/gadget.h>
61 #include <linux/usb/otg.h>
62 #include <linux/usb/chipidea.h>
63 #include <linux/usb/of.h>
65 #include <linux/phy.h>
66 #include <linux/regulator/consumer.h>
76 /* Controller register map */
77 static const u8 ci_regs_nolpm[] = {
78 [CAP_CAPLENGTH] = 0x00U,
79 [CAP_HCCPARAMS] = 0x08U,
80 [CAP_DCCPARAMS] = 0x24U,
81 [CAP_TESTMODE] = 0x38U,
85 [OP_DEVICEADDR] = 0x14U,
86 [OP_ENDPTLISTADDR] = 0x18U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
99 static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
112 [OP_USBMODE] = 0xC8U,
113 [OP_ENDPTSETUPSTAT] = 0xD8U,
114 [OP_ENDPTPRIME] = 0xDCU,
115 [OP_ENDPTFLUSH] = 0xE0U,
116 [OP_ENDPTSTAT] = 0xE4U,
117 [OP_ENDPTCOMPLETE] = 0xE8U,
118 [OP_ENDPTCTRL] = 0xECU,
121 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
125 for (i = 0; i < OP_ENDPTCTRL; i++)
126 ci->hw_bank.regmap[i] =
127 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
128 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
130 for (; i <= OP_LAST; i++)
131 ci->hw_bank.regmap[i] = ci->hw_bank.op +
132 4 * (i - OP_ENDPTCTRL) +
134 ? ci_regs_lpm[OP_ENDPTCTRL]
135 : ci_regs_nolpm[OP_ENDPTCTRL]);
141 * hw_read_intr_enable: returns interrupt enable register
143 * @ci: the controller
145 * This function returns register data
147 u32 hw_read_intr_enable(struct ci_hdrc *ci)
149 return hw_read(ci, OP_USBINTR, ~0);
153 * hw_read_intr_status: returns interrupt status register
155 * @ci: the controller
157 * This function returns register data
159 u32 hw_read_intr_status(struct ci_hdrc *ci)
161 return hw_read(ci, OP_USBSTS, ~0);
165 * hw_port_test_set: writes port test mode (execute without interruption)
168 * This function returns an error code
170 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
172 const u8 TEST_MODE_MAX = 7;
174 if (mode > TEST_MODE_MAX)
177 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
182 * hw_port_test_get: reads port test mode value
184 * @ci: the controller
186 * This function returns port test mode value
188 u8 hw_port_test_get(struct ci_hdrc *ci)
190 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
193 static void hw_wait_phy_stable(void)
196 * The phy needs some delay to output the stable status from low
197 * power mode. And for OTGSC, the status inputs are debounced
198 * using a 1 ms time constant, so, delay 2ms for controller to get
199 * the stable status, like vbus and id when the phy leaves low power.
201 usleep_range(2000, 2500);
204 /* The PHY enters/leaves low power mode */
205 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
207 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
208 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
211 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
212 PORTSC_PHCD(ci->hw_bank.lpm));
213 else if (!enable && lpm)
214 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
218 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
222 /* bank is a module variable */
223 ci->hw_bank.abs = base;
225 ci->hw_bank.cap = ci->hw_bank.abs;
226 ci->hw_bank.cap += ci->platdata->capoffset;
227 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
229 hw_alloc_regmap(ci, false);
230 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
231 __ffs(HCCPARAMS_LEN);
232 ci->hw_bank.lpm = reg;
234 hw_alloc_regmap(ci, !!reg);
235 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
236 ci->hw_bank.size += OP_LAST;
237 ci->hw_bank.size /= sizeof(u32);
239 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
240 __ffs(DCCPARAMS_DEN);
241 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
243 if (ci->hw_ep_max > ENDPT_MAX)
246 ci_hdrc_enter_lpm(ci, false);
248 /* Disable all interrupts bits */
249 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
251 /* Clear all interrupts status bits*/
252 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
254 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
255 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
257 /* setup lock mode ? */
259 /* ENDPTSETUPSTAT is '0' by default */
261 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
266 static void hw_phymode_configure(struct ci_hdrc *ci)
268 u32 portsc, lpm, sts = 0;
270 switch (ci->platdata->phy_mode) {
271 case USBPHY_INTERFACE_MODE_UTMI:
272 portsc = PORTSC_PTS(PTS_UTMI);
273 lpm = DEVLC_PTS(PTS_UTMI);
275 case USBPHY_INTERFACE_MODE_UTMIW:
276 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
277 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
279 case USBPHY_INTERFACE_MODE_ULPI:
280 portsc = PORTSC_PTS(PTS_ULPI);
281 lpm = DEVLC_PTS(PTS_ULPI);
283 case USBPHY_INTERFACE_MODE_SERIAL:
284 portsc = PORTSC_PTS(PTS_SERIAL);
285 lpm = DEVLC_PTS(PTS_SERIAL);
288 case USBPHY_INTERFACE_MODE_HSIC:
289 portsc = PORTSC_PTS(PTS_HSIC);
290 lpm = DEVLC_PTS(PTS_HSIC);
296 if (ci->hw_bank.lpm) {
297 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
299 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
301 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
303 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
308 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
310 * @ci: the controller
312 * This function returns an error code if the phy failed to init
314 static int _ci_usb_phy_init(struct ci_hdrc *ci)
319 ret = phy_init(ci->phy);
323 ret = phy_power_on(ci->phy);
329 ret = usb_phy_init(ci->usb_phy);
336 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
338 * @ci: the controller
340 static void ci_usb_phy_exit(struct ci_hdrc *ci)
343 phy_power_off(ci->phy);
346 usb_phy_shutdown(ci->usb_phy);
351 * ci_usb_phy_init: initialize phy according to different phy type
352 * @ci: the controller
354 * This function returns an error code if usb_phy_init has failed
356 static int ci_usb_phy_init(struct ci_hdrc *ci)
360 switch (ci->platdata->phy_mode) {
361 case USBPHY_INTERFACE_MODE_UTMI:
362 case USBPHY_INTERFACE_MODE_UTMIW:
363 case USBPHY_INTERFACE_MODE_HSIC:
364 ret = _ci_usb_phy_init(ci);
366 hw_wait_phy_stable();
369 hw_phymode_configure(ci);
371 case USBPHY_INTERFACE_MODE_ULPI:
372 case USBPHY_INTERFACE_MODE_SERIAL:
373 hw_phymode_configure(ci);
374 ret = _ci_usb_phy_init(ci);
379 ret = _ci_usb_phy_init(ci);
381 hw_wait_phy_stable();
388 * hw_controller_reset: do controller reset
389 * @ci: the controller
391 * This function returns an error code
393 static int hw_controller_reset(struct ci_hdrc *ci)
397 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
398 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
408 * hw_device_reset: resets chip (execute without interruption)
409 * @ci: the controller
411 * This function returns an error code
413 int hw_device_reset(struct ci_hdrc *ci)
417 /* should flush & stop before reset */
418 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
419 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
421 ret = hw_controller_reset(ci);
423 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
427 if (ci->platdata->notify_event)
428 ci->platdata->notify_event(ci,
429 CI_HDRC_CONTROLLER_RESET_EVENT);
431 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
434 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
436 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
438 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
441 /* USBMODE should be configured step by step */
442 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
443 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
445 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
447 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
448 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
449 pr_err("lpm = %i", ci->hw_bank.lpm);
457 * hw_wait_reg: wait the register value
459 * Sometimes, it needs to wait register value before going on.
460 * Eg, when switch to device mode, the vbus value should be lower
461 * than OTGSC_BSV before connects to host.
463 * @ci: the controller
464 * @reg: register index
466 * @value: the bit value to wait
467 * @timeout_ms: timeout in millisecond
469 * This function returns an error code if timeout
471 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
472 u32 value, unsigned int timeout_ms)
474 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
476 while (hw_read(ci, reg, mask) != value) {
477 if (time_after(jiffies, elapse)) {
478 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
488 static irqreturn_t ci_irq(int irq, void *data)
490 struct ci_hdrc *ci = data;
491 irqreturn_t ret = IRQ_NONE;
495 disable_irq_nosync(irq);
496 ci->wakeup_int = true;
497 pm_runtime_get(ci->dev);
502 otgsc = hw_read_otgsc(ci, ~0);
503 if (ci_otg_is_fsm_mode(ci)) {
504 ret = ci_otg_fsm_irq(ci);
505 if (ret == IRQ_HANDLED)
511 * Handle id change interrupt, it indicates device/host function
514 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
516 /* Clear ID change irq status */
517 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
518 ci_otg_queue_work(ci);
523 * Handle vbus change interrupt, it indicates device connection
524 * and disconnection events.
526 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
527 ci->b_sess_valid_event = true;
529 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
530 ci_otg_queue_work(ci);
534 /* Handle device/host interrupt */
535 if (ci->role != CI_ROLE_END)
536 ret = ci_role(ci)->irq(ci);
541 static int ci_get_platdata(struct device *dev,
542 struct ci_hdrc_platform_data *platdata)
544 if (!platdata->phy_mode)
545 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
547 if (!platdata->dr_mode)
548 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
550 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
551 platdata->dr_mode = USB_DR_MODE_OTG;
553 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
554 /* Get the vbus regulator */
555 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
556 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
557 return -EPROBE_DEFER;
558 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
559 /* no vbus regulator is needed */
560 platdata->reg_vbus = NULL;
561 } else if (IS_ERR(platdata->reg_vbus)) {
562 dev_err(dev, "Getting regulator error: %ld\n",
563 PTR_ERR(platdata->reg_vbus));
564 return PTR_ERR(platdata->reg_vbus);
566 /* Get TPL support */
567 if (!platdata->tpl_support)
568 platdata->tpl_support =
569 of_usb_host_tpl_support(dev->of_node);
572 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
573 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
578 static DEFINE_IDA(ci_ida);
580 struct platform_device *ci_hdrc_add_device(struct device *dev,
581 struct resource *res, int nres,
582 struct ci_hdrc_platform_data *platdata)
584 struct platform_device *pdev;
587 ret = ci_get_platdata(dev, platdata);
591 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
595 pdev = platform_device_alloc("ci_hdrc", id);
601 pdev->dev.parent = dev;
602 pdev->dev.dma_mask = dev->dma_mask;
603 pdev->dev.dma_parms = dev->dma_parms;
604 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
606 ret = platform_device_add_resources(pdev, res, nres);
610 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
614 ret = platform_device_add(pdev);
621 platform_device_put(pdev);
623 ida_simple_remove(&ci_ida, id);
626 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
628 void ci_hdrc_remove_device(struct platform_device *pdev)
631 platform_device_unregister(pdev);
632 ida_simple_remove(&ci_ida, id);
634 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
636 static inline void ci_role_destroy(struct ci_hdrc *ci)
638 ci_hdrc_gadget_destroy(ci);
639 ci_hdrc_host_destroy(ci);
641 ci_hdrc_otg_destroy(ci);
644 static void ci_get_otg_capable(struct ci_hdrc *ci)
646 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
649 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
650 DCCPARAMS_DC | DCCPARAMS_HC)
651 == (DCCPARAMS_DC | DCCPARAMS_HC));
653 dev_dbg(ci->dev, "It is OTG capable controller\n");
656 static int ci_hdrc_probe(struct platform_device *pdev)
658 struct device *dev = &pdev->dev;
660 struct resource *res;
663 enum usb_dr_mode dr_mode;
665 if (!dev_get_platdata(dev)) {
666 dev_err(dev, "platform data missing\n");
670 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
671 base = devm_ioremap_resource(dev, res);
673 return PTR_ERR(base);
675 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
680 ci->platdata = dev_get_platdata(dev);
681 ci->imx28_write_fix = !!(ci->platdata->flags &
682 CI_HDRC_IMX28_WRITE_FIX);
683 ci->supports_runtime_pm = !!(ci->platdata->flags &
684 CI_HDRC_SUPPORTS_RUNTIME_PM);
686 ret = hw_device_init(ci, base);
688 dev_err(dev, "can't initialize hardware\n");
692 if (ci->platdata->phy) {
693 ci->phy = ci->platdata->phy;
694 } else if (ci->platdata->usb_phy) {
695 ci->usb_phy = ci->platdata->usb_phy;
697 ci->phy = devm_phy_get(dev->parent, "usb-phy");
698 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
700 /* if both generic PHY and USB PHY layers aren't enabled */
701 if (PTR_ERR(ci->phy) == -ENOSYS &&
702 PTR_ERR(ci->usb_phy) == -ENXIO)
705 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
706 return -EPROBE_DEFER;
710 else if (IS_ERR(ci->usb_phy))
714 ret = ci_usb_phy_init(ci);
716 dev_err(dev, "unable to init phy: %d\n", ret);
720 ci->hw_bank.phys = res->start;
722 ci->irq = platform_get_irq(pdev, 0);
724 dev_err(dev, "missing IRQ\n");
729 ci_get_otg_capable(ci);
731 dr_mode = ci->platdata->dr_mode;
732 /* initialize role(s) before the interrupt is requested */
733 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
734 ret = ci_hdrc_host_init(ci);
736 dev_info(dev, "doesn't support host\n");
739 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
740 ret = ci_hdrc_gadget_init(ci);
742 dev_info(dev, "doesn't support gadget\n");
745 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
746 dev_err(dev, "no supported roles\n");
751 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
752 /* Disable and clear all OTG irq */
753 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
754 OTGSC_INT_STATUS_BITS);
755 ret = ci_hdrc_otg_init(ci);
757 dev_err(dev, "init otg fails, ret = %d\n", ret);
762 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
764 ci->role = ci_otg_role(ci);
765 /* Enable ID change irq */
766 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
769 * If the controller is not OTG capable, but support
770 * role switch, the defalt role is gadget, and the
771 * user can switch it through debugfs.
773 ci->role = CI_ROLE_GADGET;
776 ci->role = ci->roles[CI_ROLE_HOST]
781 /* only update vbus status for peripheral */
782 if (ci->role == CI_ROLE_GADGET)
783 ci_handle_vbus_change(ci);
785 if (!ci_otg_is_fsm_mode(ci)) {
786 ret = ci_role_start(ci, ci->role);
788 dev_err(dev, "can't start %s role\n",
794 platform_set_drvdata(pdev, ci);
795 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
796 ci->platdata->name, ci);
800 if (ci->supports_runtime_pm) {
801 pm_runtime_set_active(&pdev->dev);
802 pm_runtime_enable(&pdev->dev);
803 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
804 pm_runtime_mark_last_busy(ci->dev);
805 pm_runtime_use_autosuspend(&pdev->dev);
808 if (ci_otg_is_fsm_mode(ci))
809 ci_hdrc_otg_fsm_start(ci);
811 ret = dbg_create_files(ci);
823 static int ci_hdrc_remove(struct platform_device *pdev)
825 struct ci_hdrc *ci = platform_get_drvdata(pdev);
827 if (ci->supports_runtime_pm) {
828 pm_runtime_get_sync(&pdev->dev);
829 pm_runtime_disable(&pdev->dev);
830 pm_runtime_put_noidle(&pdev->dev);
833 dbg_remove_files(ci);
835 ci_hdrc_enter_lpm(ci, true);
842 static void ci_controller_suspend(struct ci_hdrc *ci)
844 disable_irq(ci->irq);
845 ci_hdrc_enter_lpm(ci, true);
846 usb_phy_set_suspend(ci->usb_phy, 1);
851 static int ci_controller_resume(struct device *dev)
853 struct ci_hdrc *ci = dev_get_drvdata(dev);
855 dev_dbg(dev, "at %s\n", __func__);
862 ci_hdrc_enter_lpm(ci, false);
864 usb_phy_set_suspend(ci->usb_phy, 0);
865 usb_phy_set_wakeup(ci->usb_phy, false);
866 hw_wait_phy_stable();
870 if (ci->wakeup_int) {
871 ci->wakeup_int = false;
872 pm_runtime_mark_last_busy(ci->dev);
873 pm_runtime_put_autosuspend(ci->dev);
880 #ifdef CONFIG_PM_SLEEP
881 static int ci_suspend(struct device *dev)
883 struct ci_hdrc *ci = dev_get_drvdata(dev);
886 flush_workqueue(ci->wq);
888 * Controller needs to be active during suspend, otherwise the core
889 * may run resume when the parent is at suspend if other driver's
890 * suspend fails, it occurs before parent's suspend has not started,
891 * but the core suspend has finished.
894 pm_runtime_resume(dev);
901 ci_controller_suspend(ci);
906 static int ci_resume(struct device *dev)
908 struct ci_hdrc *ci = dev_get_drvdata(dev);
911 ret = ci_controller_resume(dev);
915 if (ci->supports_runtime_pm) {
916 pm_runtime_disable(dev);
917 pm_runtime_set_active(dev);
918 pm_runtime_enable(dev);
923 #endif /* CONFIG_PM_SLEEP */
925 static int ci_runtime_suspend(struct device *dev)
927 struct ci_hdrc *ci = dev_get_drvdata(dev);
929 dev_dbg(dev, "at %s\n", __func__);
936 usb_phy_set_wakeup(ci->usb_phy, true);
937 ci_controller_suspend(ci);
942 static int ci_runtime_resume(struct device *dev)
944 return ci_controller_resume(dev);
947 #endif /* CONFIG_PM */
948 static const struct dev_pm_ops ci_pm_ops = {
949 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
950 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
953 static struct platform_driver ci_hdrc_driver = {
954 .probe = ci_hdrc_probe,
955 .remove = ci_hdrc_remove,
962 module_platform_driver(ci_hdrc_driver);
964 MODULE_ALIAS("platform:ci_hdrc");
965 MODULE_LICENSE("GPL v2");
966 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
967 MODULE_DESCRIPTION("ChipIdea HDRC Driver");