2 * core.c - DesignWare HS OTG Controller common routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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7 * modification, are permitted provided that the following conditions
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19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/moduleparam.h>
45 #include <linux/spinlock.h>
46 #include <linux/interrupt.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
61 * dwc2_backup_host_registers() - Backup controller host registers.
62 * When suspending usb bus, registers needs to be backuped
63 * if controller power is disabled once suspended.
65 * @hsotg: Programming view of the DWC_otg controller
67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
69 struct dwc2_hregs_backup *hr;
72 dev_dbg(hsotg->dev, "%s\n", __func__);
74 /* Backup Host regs */
75 hr = &hsotg->hr_backup;
76 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
77 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
78 for (i = 0; i < hsotg->core_params->host_channels; ++i)
79 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
81 hr->hprt0 = dwc2_read_hprt0(hsotg);
82 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
89 * dwc2_restore_host_registers() - Restore controller host registers.
90 * When resuming usb bus, device registers needs to be restored
91 * if controller power were disabled.
93 * @hsotg: Programming view of the DWC_otg controller
95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
97 struct dwc2_hregs_backup *hr;
100 dev_dbg(hsotg->dev, "%s\n", __func__);
102 /* Restore host regs */
103 hr = &hsotg->hr_backup;
105 dev_err(hsotg->dev, "%s: no host registers to restore\n",
111 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
112 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
114 for (i = 0; i < hsotg->core_params->host_channels; ++i)
115 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
117 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
118 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
119 hsotg->frame_number = 0;
124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
131 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
132 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
134 * dwc2_backup_device_registers() - Backup controller device registers.
135 * When suspending usb bus, registers needs to be backuped
136 * if controller power is disabled once suspended.
138 * @hsotg: Programming view of the DWC_otg controller
140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
142 struct dwc2_dregs_backup *dr;
145 dev_dbg(hsotg->dev, "%s\n", __func__);
147 /* Backup dev regs */
148 dr = &hsotg->dr_backup;
150 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
151 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
152 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
153 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
154 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
156 for (i = 0; i < hsotg->num_of_eps; i++) {
158 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
160 /* Ensure DATA PID is correctly configured */
161 if (dr->diepctl[i] & DXEPCTL_DPID)
162 dr->diepctl[i] |= DXEPCTL_SETD1PID;
164 dr->diepctl[i] |= DXEPCTL_SETD0PID;
166 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
167 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
170 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
172 /* Ensure DATA PID is correctly configured */
173 if (dr->doepctl[i] & DXEPCTL_DPID)
174 dr->doepctl[i] |= DXEPCTL_SETD1PID;
176 dr->doepctl[i] |= DXEPCTL_SETD0PID;
178 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
179 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
186 * dwc2_restore_device_registers() - Restore controller device registers.
187 * When resuming usb bus, device registers needs to be restored
188 * if controller power were disabled.
190 * @hsotg: Programming view of the DWC_otg controller
192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
194 struct dwc2_dregs_backup *dr;
198 dev_dbg(hsotg->dev, "%s\n", __func__);
200 /* Restore dev regs */
201 dr = &hsotg->dr_backup;
203 dev_err(hsotg->dev, "%s: no device registers to restore\n",
209 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
210 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
211 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
212 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
213 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
215 for (i = 0; i < hsotg->num_of_eps; i++) {
217 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
218 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
219 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
221 /* Restore OUT EPs */
222 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
223 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
224 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
227 /* Set the Power-On Programming done bit */
228 dctl = dwc2_readl(hsotg->regs + DCTL);
229 dctl |= DCTL_PWRONPRGDONE;
230 dwc2_writel(dctl, hsotg->regs + DCTL);
235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
243 * dwc2_backup_global_registers() - Backup global controller registers.
244 * When suspending usb bus, registers needs to be backuped
245 * if controller power is disabled once suspended.
247 * @hsotg: Programming view of the DWC_otg controller
249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
251 struct dwc2_gregs_backup *gr;
254 /* Backup global regs */
255 gr = &hsotg->gr_backup;
257 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
258 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
259 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
260 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
261 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
262 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
263 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
264 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
265 for (i = 0; i < MAX_EPS_CHANNELS; i++)
266 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
273 * dwc2_restore_global_registers() - Restore controller global registers.
274 * When resuming usb bus, device registers needs to be restored
275 * if controller power were disabled.
277 * @hsotg: Programming view of the DWC_otg controller
279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
281 struct dwc2_gregs_backup *gr;
284 dev_dbg(hsotg->dev, "%s\n", __func__);
286 /* Restore global regs */
287 gr = &hsotg->gr_backup;
289 dev_err(hsotg->dev, "%s: no global registers to restore\n",
295 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
296 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
297 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
298 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
299 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
300 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
301 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
302 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
303 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
304 for (i = 0; i < MAX_EPS_CHANNELS; i++)
305 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
311 * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
313 * @hsotg: Programming view of the DWC_otg controller
314 * @restore: Controller registers need to be restored
316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
321 if (!hsotg->core_params->hibernation)
324 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
325 pcgcctl &= ~PCGCTL_STOPPCLK;
326 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
328 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
329 pcgcctl &= ~PCGCTL_PWRCLMP;
330 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
332 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
333 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
334 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
338 ret = dwc2_restore_global_registers(hsotg);
340 dev_err(hsotg->dev, "%s: failed to restore registers\n",
344 if (dwc2_is_host_mode(hsotg)) {
345 ret = dwc2_restore_host_registers(hsotg);
347 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
352 ret = dwc2_restore_device_registers(hsotg);
354 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
365 * dwc2_enter_hibernation() - Put controller in Partial Power Down.
367 * @hsotg: Programming view of the DWC_otg controller
369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
374 if (!hsotg->core_params->hibernation)
377 /* Backup all registers */
378 ret = dwc2_backup_global_registers(hsotg);
380 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
385 if (dwc2_is_host_mode(hsotg)) {
386 ret = dwc2_backup_host_registers(hsotg);
388 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
393 ret = dwc2_backup_device_registers(hsotg);
395 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
402 * Clear any pending interrupts since dwc2 will not be able to
403 * clear them after entering hibernation.
405 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
407 /* Put the controller in low power state */
408 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
410 pcgcctl |= PCGCTL_PWRCLMP;
411 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
414 pcgcctl |= PCGCTL_RSTPDWNMODULE;
415 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
418 pcgcctl |= PCGCTL_STOPPCLK;
419 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
425 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
426 * used in both device and host modes
428 * @hsotg: Programming view of the DWC_otg controller
430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
434 /* Clear any pending OTG Interrupts */
435 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
437 /* Clear any pending interrupts */
438 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
440 /* Enable the interrupts in the GINTMSK */
441 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
443 if (hsotg->core_params->dma_enable <= 0)
444 intmsk |= GINTSTS_RXFLVL;
445 if (hsotg->core_params->external_id_pin_ctl <= 0)
446 intmsk |= GINTSTS_CONIDSTSCHNG;
448 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
451 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
455 * Initializes the FSLSPClkSel field of the HCFG register depending on the
458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
462 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
463 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
464 hsotg->core_params->ulpi_fs_ls > 0) ||
465 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
467 val = HCFG_FSLSPCLKSEL_48_MHZ;
469 /* High speed PHY running at full speed or high speed */
470 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
473 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
474 hcfg = dwc2_readl(hsotg->regs + HCFG);
475 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
476 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
477 dwc2_writel(hcfg, hsotg->regs + HCFG);
481 * Do core a soft reset of the core. Be careful with this because it
482 * resets all the internal state machines of the core.
484 int dwc2_core_reset(struct dwc2_hsotg *hsotg)
489 dev_vdbg(hsotg->dev, "%s()\n", __func__);
491 /* Core Soft Reset */
492 greset = dwc2_readl(hsotg->regs + GRSTCTL);
493 greset |= GRSTCTL_CSFTRST;
494 dwc2_writel(greset, hsotg->regs + GRSTCTL);
497 greset = dwc2_readl(hsotg->regs + GRSTCTL);
500 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
504 } while (greset & GRSTCTL_CSFTRST);
506 /* Wait for AHB master IDLE state */
510 greset = dwc2_readl(hsotg->regs + GRSTCTL);
513 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
517 } while (!(greset & GRSTCTL_AHBIDLE));
523 * Force the mode of the controller.
525 * Forcing the mode is needed for two cases:
527 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
528 * controller to stay in a particular mode regardless of ID pin
529 * changes. We do this usually after a core reset.
531 * 2) During probe we want to read reset values of the hw
532 * configuration registers that are only available in either host or
533 * device mode. We may need to force the mode if the current mode does
534 * not allow us to access the register in the mode that we want.
536 * In either case it only makes sense to force the mode if the
537 * controller hardware is OTG capable.
539 * Checks are done in this function to determine whether doing a force
540 * would be valid or not.
542 * If a force is done, it requires a 25ms delay to take effect.
544 * Returns true if the mode was forced.
546 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
552 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
555 * Force mode has no effect if the hardware is not OTG.
557 if (!dwc2_hw_is_otg(hsotg))
561 * If dr_mode is either peripheral or host only, there is no
562 * need to ever force the mode to the opposite mode.
564 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
567 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
570 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
572 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
573 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
577 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
584 * Clears the force mode bits.
586 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
590 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
591 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
592 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
593 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
596 * NOTE: This long sleep is _very_ important, otherwise the core will
597 * not stay in host mode after a connector ID change!
603 * Sets or clears force mode based on the dr_mode parameter.
605 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
607 switch (hsotg->dr_mode) {
608 case USB_DR_MODE_HOST:
609 dwc2_force_mode(hsotg, true);
611 case USB_DR_MODE_PERIPHERAL:
612 dwc2_force_mode(hsotg, false);
614 case USB_DR_MODE_OTG:
615 dwc2_clear_force_mode(hsotg);
618 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
619 __func__, hsotg->dr_mode);
625 * Do core a soft reset of the core. Be careful with this because it
626 * resets all the internal state machines of the core.
628 * Additionally this will apply force mode as per the hsotg->dr_mode
631 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
635 retval = dwc2_core_reset(hsotg);
639 dwc2_force_dr_mode(hsotg);
643 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
649 * core_init() is now called on every switch so only call the
650 * following for the first time through
653 dev_dbg(hsotg->dev, "FS PHY selected\n");
655 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
656 if (!(usbcfg & GUSBCFG_PHYSEL)) {
657 usbcfg |= GUSBCFG_PHYSEL;
658 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
660 /* Reset after a PHY select */
661 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
665 "%s: Reset failed, aborting", __func__);
672 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
673 * do this on HNP Dev/Host mode switches (done in dev_init and
676 if (dwc2_is_host_mode(hsotg))
677 dwc2_init_fs_ls_pclk_sel(hsotg);
679 if (hsotg->core_params->i2c_enable > 0) {
680 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
682 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
683 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
684 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
685 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
687 /* Program GI2CCTL.I2CEn */
688 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
689 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
690 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
691 i2cctl &= ~GI2CCTL_I2CEN;
692 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
693 i2cctl |= GI2CCTL_I2CEN;
694 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
700 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
702 u32 usbcfg, usbcfg_old;
708 usbcfg = usbcfg_old = dwc2_readl(hsotg->regs + GUSBCFG);
711 * HS PHY parameters. These parameters are preserved during soft reset
712 * so only program the first time. Do a soft reset immediately after
715 switch (hsotg->core_params->phy_type) {
716 case DWC2_PHY_TYPE_PARAM_ULPI:
718 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
719 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
720 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
721 if (hsotg->core_params->phy_ulpi_ddr > 0)
722 usbcfg |= GUSBCFG_DDRSEL;
724 case DWC2_PHY_TYPE_PARAM_UTMI:
725 /* UTMI+ interface */
726 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
727 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
728 if (hsotg->core_params->phy_utmi_width == 16)
729 usbcfg |= GUSBCFG_PHYIF16;
732 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
736 if (usbcfg != usbcfg_old) {
737 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
739 /* Reset after setting the PHY parameters */
740 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
743 "%s: Reset failed, aborting", __func__);
751 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
756 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
757 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
758 /* If FS mode with FS PHY */
759 retval = dwc2_fs_phy_init(hsotg, select_phy);
764 retval = dwc2_hs_phy_init(hsotg, select_phy);
769 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
770 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
771 hsotg->core_params->ulpi_fs_ls > 0) {
772 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
773 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
774 usbcfg |= GUSBCFG_ULPI_FS_LS;
775 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
776 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
778 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
779 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
780 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
781 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
787 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
789 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
791 switch (hsotg->hw_params.arch) {
792 case GHWCFG2_EXT_DMA_ARCH:
793 dev_err(hsotg->dev, "External DMA Mode not supported\n");
796 case GHWCFG2_INT_DMA_ARCH:
797 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
798 if (hsotg->core_params->ahbcfg != -1) {
799 ahbcfg &= GAHBCFG_CTRL_MASK;
800 ahbcfg |= hsotg->core_params->ahbcfg &
805 case GHWCFG2_SLAVE_ONLY_ARCH:
807 dev_dbg(hsotg->dev, "Slave Only Mode\n");
811 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
812 hsotg->core_params->dma_enable,
813 hsotg->core_params->dma_desc_enable);
815 if (hsotg->core_params->dma_enable > 0) {
816 if (hsotg->core_params->dma_desc_enable > 0)
817 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
819 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
821 dev_dbg(hsotg->dev, "Using Slave mode\n");
822 hsotg->core_params->dma_desc_enable = 0;
825 if (hsotg->core_params->dma_enable > 0)
826 ahbcfg |= GAHBCFG_DMA_EN;
828 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
833 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
837 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
838 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
840 switch (hsotg->hw_params.op_mode) {
841 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
842 if (hsotg->core_params->otg_cap ==
843 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
844 usbcfg |= GUSBCFG_HNPCAP;
845 if (hsotg->core_params->otg_cap !=
846 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
847 usbcfg |= GUSBCFG_SRPCAP;
850 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
851 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
852 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
853 if (hsotg->core_params->otg_cap !=
854 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
855 usbcfg |= GUSBCFG_SRPCAP;
858 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
859 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
860 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
865 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
869 * dwc2_core_init() - Initializes the DWC_otg controller registers and
870 * prepares the core for device mode or host mode operation
872 * @hsotg: Programming view of the DWC_otg controller
873 * @initial_setup: If true then this is the first init for this instance.
875 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
880 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
882 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
884 /* Set ULPI External VBUS bit if needed */
885 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
886 if (hsotg->core_params->phy_ulpi_ext_vbus ==
887 DWC2_PHY_ULPI_EXTERNAL_VBUS)
888 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
890 /* Set external TS Dline pulsing bit if needed */
891 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
892 if (hsotg->core_params->ts_dline > 0)
893 usbcfg |= GUSBCFG_TERMSELDLPULSE;
895 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
898 * Reset the Controller
900 * We only need to reset the controller if this is a re-init.
901 * For the first init we know for sure that earlier code reset us (it
902 * needed to in order to properly detect various parameters).
904 if (!initial_setup) {
905 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
907 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
914 * This needs to happen in FS mode before any other programming occurs
916 retval = dwc2_phy_init(hsotg, initial_setup);
920 /* Program the GAHBCFG Register */
921 retval = dwc2_gahbcfg_init(hsotg);
925 /* Program the GUSBCFG register */
926 dwc2_gusbcfg_init(hsotg);
928 /* Program the GOTGCTL register */
929 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
930 otgctl &= ~GOTGCTL_OTGVER;
931 if (hsotg->core_params->otg_ver > 0)
932 otgctl |= GOTGCTL_OTGVER;
933 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
934 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
936 /* Clear the SRP success bit for FS-I2c */
937 hsotg->srp_success = 0;
939 /* Enable common interrupts */
940 dwc2_enable_common_interrupts(hsotg);
943 * Do device or host initialization based on mode during PCD and
946 if (dwc2_is_host_mode(hsotg)) {
947 dev_dbg(hsotg->dev, "Host Mode\n");
948 hsotg->op_state = OTG_STATE_A_HOST;
950 dev_dbg(hsotg->dev, "Device Mode\n");
951 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
958 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
960 * @hsotg: Programming view of DWC_otg controller
962 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
966 dev_dbg(hsotg->dev, "%s()\n", __func__);
968 /* Disable all interrupts */
969 dwc2_writel(0, hsotg->regs + GINTMSK);
970 dwc2_writel(0, hsotg->regs + HAINTMSK);
972 /* Enable the common interrupts */
973 dwc2_enable_common_interrupts(hsotg);
975 /* Enable host mode interrupts without disturbing common interrupts */
976 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
977 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
978 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
982 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
984 * @hsotg: Programming view of DWC_otg controller
986 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
988 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
990 /* Disable host mode interrupts without disturbing common interrupts */
991 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
992 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
993 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
997 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
998 * For system that have a total fifo depth that is smaller than the default
1001 * @hsotg: Programming view of DWC_otg controller
1003 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
1005 struct dwc2_core_params *params = hsotg->core_params;
1006 struct dwc2_hw_params *hw = &hsotg->hw_params;
1007 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
1009 total_fifo_size = hw->total_fifo_size;
1010 rxfsiz = params->host_rx_fifo_size;
1011 nptxfsiz = params->host_nperio_tx_fifo_size;
1012 ptxfsiz = params->host_perio_tx_fifo_size;
1015 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
1016 * allocation with support for high bandwidth endpoints. Synopsys
1017 * defines MPS(Max Packet size) for a periodic EP=1024, and for
1018 * non-periodic as 512.
1020 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
1022 * For Buffer DMA mode/Scatter Gather DMA mode
1023 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
1024 * with n = number of host channel.
1025 * 2 * ((1024/4) + 2) = 516
1027 rxfsiz = 516 + hw->host_channels;
1030 * min non-periodic tx fifo depth
1031 * 2 * (largest non-periodic USB packet used / 4)
1037 * min periodic tx fifo depth
1038 * (largest packet size*MC)/4
1039 * (1024 * 3)/4 = 768
1043 params->host_rx_fifo_size = rxfsiz;
1044 params->host_nperio_tx_fifo_size = nptxfsiz;
1045 params->host_perio_tx_fifo_size = ptxfsiz;
1049 * If the summation of RX, NPTX and PTX fifo sizes is still
1050 * bigger than the total_fifo_size, then we have a problem.
1052 * We won't be able to allocate as many endpoints. Right now,
1053 * we're just printing an error message, but ideally this FIFO
1054 * allocation algorithm would be improved in the future.
1056 * FIXME improve this FIFO allocation algorithm.
1058 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
1059 dev_err(hsotg->dev, "invalid fifo sizes\n");
1062 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
1064 struct dwc2_core_params *params = hsotg->core_params;
1065 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
1067 if (!params->enable_dynamic_fifo)
1070 dwc2_calculate_dynamic_fifo(hsotg);
1073 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
1074 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
1075 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
1076 grxfsiz |= params->host_rx_fifo_size <<
1077 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
1078 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
1079 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
1080 dwc2_readl(hsotg->regs + GRXFSIZ));
1082 /* Non-periodic Tx FIFO */
1083 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
1084 dwc2_readl(hsotg->regs + GNPTXFSIZ));
1085 nptxfsiz = params->host_nperio_tx_fifo_size <<
1086 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
1087 nptxfsiz |= params->host_rx_fifo_size <<
1088 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
1089 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
1090 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
1091 dwc2_readl(hsotg->regs + GNPTXFSIZ));
1093 /* Periodic Tx FIFO */
1094 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
1095 dwc2_readl(hsotg->regs + HPTXFSIZ));
1096 hptxfsiz = params->host_perio_tx_fifo_size <<
1097 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
1098 hptxfsiz |= (params->host_rx_fifo_size +
1099 params->host_nperio_tx_fifo_size) <<
1100 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
1101 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
1102 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
1103 dwc2_readl(hsotg->regs + HPTXFSIZ));
1105 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
1106 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
1108 * Global DFIFOCFG calculation for Host mode -
1109 * include RxFIFO, NPTXFIFO and HPTXFIFO
1111 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
1112 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
1113 dfifocfg |= (params->host_rx_fifo_size +
1114 params->host_nperio_tx_fifo_size +
1115 params->host_perio_tx_fifo_size) <<
1116 GDFIFOCFG_EPINFOBASE_SHIFT &
1117 GDFIFOCFG_EPINFOBASE_MASK;
1118 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
1123 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
1126 * @hsotg: Programming view of DWC_otg controller
1128 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
1129 * request queues. Host channels are reset to ensure that they are ready for
1130 * performing transfers.
1132 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
1134 u32 hcfg, hfir, otgctl;
1136 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
1138 /* Restart the Phy Clock */
1139 dwc2_writel(0, hsotg->regs + PCGCTL);
1141 /* Initialize Host Configuration Register */
1142 dwc2_init_fs_ls_pclk_sel(hsotg);
1143 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
1144 hcfg = dwc2_readl(hsotg->regs + HCFG);
1145 hcfg |= HCFG_FSLSSUPP;
1146 dwc2_writel(hcfg, hsotg->regs + HCFG);
1150 * This bit allows dynamic reloading of the HFIR register during
1151 * runtime. This bit needs to be programmed during initial configuration
1152 * and its value must not be changed during runtime.
1154 if (hsotg->core_params->reload_ctl > 0) {
1155 hfir = dwc2_readl(hsotg->regs + HFIR);
1156 hfir |= HFIR_RLDCTRL;
1157 dwc2_writel(hfir, hsotg->regs + HFIR);
1160 if (hsotg->core_params->dma_desc_enable > 0) {
1161 u32 op_mode = hsotg->hw_params.op_mode;
1162 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
1163 !hsotg->hw_params.dma_desc_enable ||
1164 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
1165 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
1166 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
1168 "Hardware does not support descriptor DMA mode -\n");
1170 "falling back to buffer DMA mode.\n");
1171 hsotg->core_params->dma_desc_enable = 0;
1173 hcfg = dwc2_readl(hsotg->regs + HCFG);
1174 hcfg |= HCFG_DESCDMA;
1175 dwc2_writel(hcfg, hsotg->regs + HCFG);
1179 /* Configure data FIFO sizes */
1180 dwc2_config_fifos(hsotg);
1182 /* TODO - check this */
1183 /* Clear Host Set HNP Enable in the OTG Control Register */
1184 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1185 otgctl &= ~GOTGCTL_HSTSETHNPEN;
1186 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1188 /* Make sure the FIFOs are flushed */
1189 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
1190 dwc2_flush_rx_fifo(hsotg);
1192 /* Clear Host Set HNP Enable in the OTG Control Register */
1193 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1194 otgctl &= ~GOTGCTL_HSTSETHNPEN;
1195 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1197 if (hsotg->core_params->dma_desc_enable <= 0) {
1198 int num_channels, i;
1201 /* Flush out any leftover queued requests */
1202 num_channels = hsotg->core_params->host_channels;
1203 for (i = 0; i < num_channels; i++) {
1204 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1205 hcchar &= ~HCCHAR_CHENA;
1206 hcchar |= HCCHAR_CHDIS;
1207 hcchar &= ~HCCHAR_EPDIR;
1208 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1211 /* Halt all channels to put them into a known state */
1212 for (i = 0; i < num_channels; i++) {
1215 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1216 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
1217 hcchar &= ~HCCHAR_EPDIR;
1218 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1219 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
1222 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1223 if (++count > 1000) {
1225 "Unable to clear enable on channel %d\n",
1230 } while (hcchar & HCCHAR_CHENA);
1234 /* Turn on the vbus power */
1235 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
1236 if (hsotg->op_state == OTG_STATE_A_HOST) {
1237 u32 hprt0 = dwc2_read_hprt0(hsotg);
1239 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
1240 !!(hprt0 & HPRT0_PWR));
1241 if (!(hprt0 & HPRT0_PWR)) {
1243 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1247 dwc2_enable_host_interrupts(hsotg);
1250 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
1251 struct dwc2_host_chan *chan)
1253 u32 hcintmsk = HCINTMSK_CHHLTD;
1255 switch (chan->ep_type) {
1256 case USB_ENDPOINT_XFER_CONTROL:
1257 case USB_ENDPOINT_XFER_BULK:
1258 dev_vdbg(hsotg->dev, "control/bulk\n");
1259 hcintmsk |= HCINTMSK_XFERCOMPL;
1260 hcintmsk |= HCINTMSK_STALL;
1261 hcintmsk |= HCINTMSK_XACTERR;
1262 hcintmsk |= HCINTMSK_DATATGLERR;
1263 if (chan->ep_is_in) {
1264 hcintmsk |= HCINTMSK_BBLERR;
1266 hcintmsk |= HCINTMSK_NAK;
1267 hcintmsk |= HCINTMSK_NYET;
1269 hcintmsk |= HCINTMSK_ACK;
1272 if (chan->do_split) {
1273 hcintmsk |= HCINTMSK_NAK;
1274 if (chan->complete_split)
1275 hcintmsk |= HCINTMSK_NYET;
1277 hcintmsk |= HCINTMSK_ACK;
1280 if (chan->error_state)
1281 hcintmsk |= HCINTMSK_ACK;
1284 case USB_ENDPOINT_XFER_INT:
1286 dev_vdbg(hsotg->dev, "intr\n");
1287 hcintmsk |= HCINTMSK_XFERCOMPL;
1288 hcintmsk |= HCINTMSK_NAK;
1289 hcintmsk |= HCINTMSK_STALL;
1290 hcintmsk |= HCINTMSK_XACTERR;
1291 hcintmsk |= HCINTMSK_DATATGLERR;
1292 hcintmsk |= HCINTMSK_FRMOVRUN;
1295 hcintmsk |= HCINTMSK_BBLERR;
1296 if (chan->error_state)
1297 hcintmsk |= HCINTMSK_ACK;
1298 if (chan->do_split) {
1299 if (chan->complete_split)
1300 hcintmsk |= HCINTMSK_NYET;
1302 hcintmsk |= HCINTMSK_ACK;
1306 case USB_ENDPOINT_XFER_ISOC:
1308 dev_vdbg(hsotg->dev, "isoc\n");
1309 hcintmsk |= HCINTMSK_XFERCOMPL;
1310 hcintmsk |= HCINTMSK_FRMOVRUN;
1311 hcintmsk |= HCINTMSK_ACK;
1313 if (chan->ep_is_in) {
1314 hcintmsk |= HCINTMSK_XACTERR;
1315 hcintmsk |= HCINTMSK_BBLERR;
1319 dev_err(hsotg->dev, "## Unknown EP type ##\n");
1323 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1325 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1328 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
1329 struct dwc2_host_chan *chan)
1331 u32 hcintmsk = HCINTMSK_CHHLTD;
1334 * For Descriptor DMA mode core halts the channel on AHB error.
1335 * Interrupt is not required.
1337 if (hsotg->core_params->dma_desc_enable <= 0) {
1339 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1340 hcintmsk |= HCINTMSK_AHBERR;
1343 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
1344 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1345 hcintmsk |= HCINTMSK_XFERCOMPL;
1348 if (chan->error_state && !chan->do_split &&
1349 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1351 dev_vdbg(hsotg->dev, "setting ACK\n");
1352 hcintmsk |= HCINTMSK_ACK;
1353 if (chan->ep_is_in) {
1354 hcintmsk |= HCINTMSK_DATATGLERR;
1355 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
1356 hcintmsk |= HCINTMSK_NAK;
1360 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1362 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1365 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
1366 struct dwc2_host_chan *chan)
1370 if (hsotg->core_params->dma_enable > 0) {
1372 dev_vdbg(hsotg->dev, "DMA enabled\n");
1373 dwc2_hc_enable_dma_ints(hsotg, chan);
1376 dev_vdbg(hsotg->dev, "DMA disabled\n");
1377 dwc2_hc_enable_slave_ints(hsotg, chan);
1380 /* Enable the top level host channel interrupt */
1381 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
1382 intmsk |= 1 << chan->hc_num;
1383 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
1385 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
1387 /* Make sure host channel interrupts are enabled */
1388 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
1389 intmsk |= GINTSTS_HCHINT;
1390 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
1392 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
1396 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
1397 * a specific endpoint
1399 * @hsotg: Programming view of DWC_otg controller
1400 * @chan: Information needed to initialize the host channel
1402 * The HCCHARn register is set up with the characteristics specified in chan.
1403 * Host channel interrupts that may need to be serviced while this transfer is
1404 * in progress are enabled.
1406 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1408 u8 hc_num = chan->hc_num;
1414 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1416 /* Clear old interrupt conditions for this host channel */
1417 hcintmsk = 0xffffffff;
1418 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1419 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
1421 /* Enable channel interrupts required for this transfer */
1422 dwc2_hc_enable_ints(hsotg, chan);
1425 * Program the HCCHARn register with the endpoint characteristics for
1426 * the current transfer
1428 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
1429 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
1431 hcchar |= HCCHAR_EPDIR;
1432 if (chan->speed == USB_SPEED_LOW)
1433 hcchar |= HCCHAR_LSPDDEV;
1434 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
1435 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
1436 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
1438 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
1441 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
1443 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
1445 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
1447 dev_vdbg(hsotg->dev, " Is In: %d\n",
1449 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
1450 chan->speed == USB_SPEED_LOW);
1451 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
1453 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
1457 /* Program the HCSPLT register for SPLITs */
1458 if (chan->do_split) {
1460 dev_vdbg(hsotg->dev,
1461 "Programming HC %d with split --> %s\n",
1463 chan->complete_split ? "CSPLIT" : "SSPLIT");
1464 if (chan->complete_split)
1465 hcsplt |= HCSPLT_COMPSPLT;
1466 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
1467 HCSPLT_XACTPOS_MASK;
1468 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
1469 HCSPLT_HUBADDR_MASK;
1470 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
1471 HCSPLT_PRTADDR_MASK;
1473 dev_vdbg(hsotg->dev, " comp split %d\n",
1474 chan->complete_split);
1475 dev_vdbg(hsotg->dev, " xact pos %d\n",
1477 dev_vdbg(hsotg->dev, " hub addr %d\n",
1479 dev_vdbg(hsotg->dev, " hub port %d\n",
1481 dev_vdbg(hsotg->dev, " is_in %d\n",
1483 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
1485 dev_vdbg(hsotg->dev, " xferlen %d\n",
1490 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
1494 * dwc2_hc_halt() - Attempts to halt a host channel
1496 * @hsotg: Controller register interface
1497 * @chan: Host channel to halt
1498 * @halt_status: Reason for halting the channel
1500 * This function should only be called in Slave mode or to abort a transfer in
1501 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
1502 * controller halts the channel when the transfer is complete or a condition
1503 * occurs that requires application intervention.
1505 * In slave mode, checks for a free request queue entry, then sets the Channel
1506 * Enable and Channel Disable bits of the Host Channel Characteristics
1507 * register of the specified channel to intiate the halt. If there is no free
1508 * request queue entry, sets only the Channel Disable bit of the HCCHARn
1509 * register to flush requests for this channel. In the latter case, sets a
1510 * flag to indicate that the host channel needs to be halted when a request
1511 * queue slot is open.
1513 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
1514 * HCCHARn register. The controller ensures there is space in the request
1515 * queue before submitting the halt request.
1517 * Some time may elapse before the core flushes any posted requests for this
1518 * host channel and halts. The Channel Halted interrupt handler completes the
1519 * deactivation of the host channel.
1521 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1522 enum dwc2_halt_status halt_status)
1524 u32 nptxsts, hptxsts, hcchar;
1527 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1528 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1529 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1531 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1532 halt_status == DWC2_HC_XFER_AHB_ERR) {
1534 * Disable all channel interrupts except Ch Halted. The QTD
1535 * and QH state associated with this transfer has been cleared
1536 * (in the case of URB_DEQUEUE), so the channel needs to be
1537 * shut down carefully to prevent crashes.
1539 u32 hcintmsk = HCINTMSK_CHHLTD;
1541 dev_vdbg(hsotg->dev, "dequeue/error\n");
1542 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1545 * Make sure no other interrupts besides halt are currently
1546 * pending. Handling another interrupt could cause a crash due
1547 * to the QTD and QH state.
1549 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1552 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1553 * even if the channel was already halted for some other
1556 chan->halt_status = halt_status;
1558 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1559 if (!(hcchar & HCCHAR_CHENA)) {
1561 * The channel is either already halted or it hasn't
1562 * started yet. In DMA mode, the transfer may halt if
1563 * it finishes normally or a condition occurs that
1564 * requires driver intervention. Don't want to halt
1565 * the channel again. In either Slave or DMA mode,
1566 * it's possible that the transfer has been assigned
1567 * to a channel, but not started yet when an URB is
1568 * dequeued. Don't want to halt a channel that hasn't
1574 if (chan->halt_pending) {
1576 * A halt has already been issued for this channel. This might
1577 * happen when a transfer is aborted by a higher level in
1580 dev_vdbg(hsotg->dev,
1581 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1582 __func__, chan->hc_num);
1586 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1588 /* No need to set the bit in DDMA for disabling the channel */
1589 /* TODO check it everywhere channel is disabled */
1590 if (hsotg->core_params->dma_desc_enable <= 0) {
1592 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1593 hcchar |= HCCHAR_CHENA;
1596 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1598 hcchar |= HCCHAR_CHDIS;
1600 if (hsotg->core_params->dma_enable <= 0) {
1602 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1603 hcchar |= HCCHAR_CHENA;
1605 /* Check for space in the request queue to issue the halt */
1606 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1607 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1608 dev_vdbg(hsotg->dev, "control/bulk\n");
1609 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1610 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1611 dev_vdbg(hsotg->dev, "Disabling channel\n");
1612 hcchar &= ~HCCHAR_CHENA;
1616 dev_vdbg(hsotg->dev, "isoc/intr\n");
1617 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1618 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1619 hsotg->queuing_high_bandwidth) {
1621 dev_vdbg(hsotg->dev, "Disabling channel\n");
1622 hcchar &= ~HCCHAR_CHENA;
1627 dev_vdbg(hsotg->dev, "DMA enabled\n");
1630 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1631 chan->halt_status = halt_status;
1633 if (hcchar & HCCHAR_CHENA) {
1635 dev_vdbg(hsotg->dev, "Channel enabled\n");
1636 chan->halt_pending = 1;
1637 chan->halt_on_queue = 0;
1640 dev_vdbg(hsotg->dev, "Channel disabled\n");
1641 chan->halt_on_queue = 1;
1645 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1647 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1649 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1650 chan->halt_pending);
1651 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1652 chan->halt_on_queue);
1653 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1659 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1661 * @hsotg: Programming view of DWC_otg controller
1662 * @chan: Identifies the host channel to clean up
1664 * This function is normally called after a transfer is done and the host
1665 * channel is being released
1667 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1671 chan->xfer_started = 0;
1674 * Clear channel interrupt enables and any unhandled channel interrupt
1677 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1678 hcintmsk = 0xffffffff;
1679 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1680 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1684 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1685 * which frame a periodic transfer should occur
1687 * @hsotg: Programming view of DWC_otg controller
1688 * @chan: Identifies the host channel to set up and its properties
1689 * @hcchar: Current value of the HCCHAR register for the specified host channel
1691 * This function has no effect on non-periodic transfers
1693 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1694 struct dwc2_host_chan *chan, u32 *hcchar)
1696 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1697 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1698 /* 1 if _next_ frame is odd, 0 if it's even */
1699 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1700 *hcchar |= HCCHAR_ODDFRM;
1704 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1706 /* Set up the initial PID for the transfer */
1707 if (chan->speed == USB_SPEED_HIGH) {
1708 if (chan->ep_is_in) {
1709 if (chan->multi_count == 1)
1710 chan->data_pid_start = DWC2_HC_PID_DATA0;
1711 else if (chan->multi_count == 2)
1712 chan->data_pid_start = DWC2_HC_PID_DATA1;
1714 chan->data_pid_start = DWC2_HC_PID_DATA2;
1716 if (chan->multi_count == 1)
1717 chan->data_pid_start = DWC2_HC_PID_DATA0;
1719 chan->data_pid_start = DWC2_HC_PID_MDATA;
1722 chan->data_pid_start = DWC2_HC_PID_DATA0;
1727 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1730 * @hsotg: Programming view of DWC_otg controller
1731 * @chan: Information needed to initialize the host channel
1733 * This function should only be called in Slave mode. For a channel associated
1734 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1735 * associated with a periodic EP, the periodic Tx FIFO is written.
1737 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1738 * the number of bytes written to the Tx FIFO.
1740 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1741 struct dwc2_host_chan *chan)
1744 u32 remaining_count;
1747 u32 __iomem *data_fifo;
1748 u32 *data_buf = (u32 *)chan->xfer_buf;
1751 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1753 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1755 remaining_count = chan->xfer_len - chan->xfer_count;
1756 if (remaining_count > chan->max_packet)
1757 byte_count = chan->max_packet;
1759 byte_count = remaining_count;
1761 dword_count = (byte_count + 3) / 4;
1763 if (((unsigned long)data_buf & 0x3) == 0) {
1764 /* xfer_buf is DWORD aligned */
1765 for (i = 0; i < dword_count; i++, data_buf++)
1766 dwc2_writel(*data_buf, data_fifo);
1768 /* xfer_buf is not DWORD aligned */
1769 for (i = 0; i < dword_count; i++, data_buf++) {
1770 u32 data = data_buf[0] | data_buf[1] << 8 |
1771 data_buf[2] << 16 | data_buf[3] << 24;
1772 dwc2_writel(data, data_fifo);
1776 chan->xfer_count += byte_count;
1777 chan->xfer_buf += byte_count;
1781 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1782 * channel and starts the transfer
1784 * @hsotg: Programming view of DWC_otg controller
1785 * @chan: Information needed to initialize the host channel. The xfer_len value
1786 * may be reduced to accommodate the max widths of the XferSize and
1787 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1788 * changed to reflect the final xfer_len value.
1790 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1791 * the caller must ensure that there is sufficient space in the request queue
1794 * For an OUT transfer in Slave mode, it loads a data packet into the
1795 * appropriate FIFO. If necessary, additional data packets are loaded in the
1798 * For an IN transfer in Slave mode, a data packet is requested. The data
1799 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1800 * additional data packets are requested in the Host ISR.
1802 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1803 * register along with a packet count of 1 and the channel is enabled. This
1804 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1805 * simply set to 0 since no data transfer occurs in this case.
1807 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1808 * all the information required to perform the subsequent data transfer. In
1809 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1810 * controller performs the entire PING protocol, then starts the data
1813 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1814 struct dwc2_host_chan *chan)
1816 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1817 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1824 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1826 if (chan->do_ping) {
1827 if (hsotg->core_params->dma_enable <= 0) {
1829 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1830 dwc2_hc_do_ping(hsotg, chan);
1831 chan->xfer_started = 1;
1835 dev_vdbg(hsotg->dev, "ping, DMA\n");
1836 hctsiz |= TSIZ_DOPNG;
1840 if (chan->do_split) {
1842 dev_vdbg(hsotg->dev, "split\n");
1845 if (chan->complete_split && !chan->ep_is_in)
1847 * For CSPLIT OUT Transfer, set the size to 0 so the
1848 * core doesn't expect any data written to the FIFO
1851 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1852 chan->xfer_len = chan->max_packet;
1853 else if (!chan->ep_is_in && chan->xfer_len > 188)
1854 chan->xfer_len = 188;
1856 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1859 /* For split set ec_mc for immediate retries */
1860 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1861 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1867 dev_vdbg(hsotg->dev, "no split\n");
1869 * Ensure that the transfer length and packet count will fit
1870 * in the widths allocated for them in the HCTSIZn register
1872 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1873 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1875 * Make sure the transfer size is no larger than one
1876 * (micro)frame's worth of data. (A check was done
1877 * when the periodic transfer was accepted to ensure
1878 * that a (micro)frame's worth of data can be
1879 * programmed into a channel.)
1881 u32 max_periodic_len =
1882 chan->multi_count * chan->max_packet;
1884 if (chan->xfer_len > max_periodic_len)
1885 chan->xfer_len = max_periodic_len;
1886 } else if (chan->xfer_len > max_hc_xfer_size) {
1888 * Make sure that xfer_len is a multiple of max packet
1892 max_hc_xfer_size - chan->max_packet + 1;
1895 if (chan->xfer_len > 0) {
1896 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1898 if (num_packets > max_hc_pkt_count) {
1899 num_packets = max_hc_pkt_count;
1900 chan->xfer_len = num_packets * chan->max_packet;
1903 /* Need 1 packet for transfer length of 0 */
1909 * Always program an integral # of max packets for IN
1912 chan->xfer_len = num_packets * chan->max_packet;
1914 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1915 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1917 * Make sure that the multi_count field matches the
1918 * actual transfer length
1920 chan->multi_count = num_packets;
1922 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1923 dwc2_set_pid_isoc(chan);
1925 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1928 /* The ec_mc gets the multi_count for non-split */
1929 ec_mc = chan->multi_count;
1932 chan->start_pkt_count = num_packets;
1933 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1934 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1935 TSIZ_SC_MC_PID_MASK;
1936 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1938 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1939 hctsiz, chan->hc_num);
1941 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1943 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1944 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1945 TSIZ_XFERSIZE_SHIFT);
1946 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1947 (hctsiz & TSIZ_PKTCNT_MASK) >>
1949 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1950 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1951 TSIZ_SC_MC_PID_SHIFT);
1954 if (hsotg->core_params->dma_enable > 0) {
1955 dma_addr_t dma_addr;
1957 if (chan->align_buf) {
1959 dev_vdbg(hsotg->dev, "align_buf\n");
1960 dma_addr = chan->align_buf;
1962 dma_addr = chan->xfer_dma;
1964 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1966 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1967 (unsigned long)dma_addr, chan->hc_num);
1970 /* Start the split */
1971 if (chan->do_split) {
1972 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1974 hcsplt |= HCSPLT_SPLTENA;
1975 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1978 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1979 hcchar &= ~HCCHAR_MULTICNT_MASK;
1980 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1981 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1983 if (hcchar & HCCHAR_CHDIS)
1984 dev_warn(hsotg->dev,
1985 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1986 __func__, chan->hc_num, hcchar);
1988 /* Set host channel enable after all other setup is complete */
1989 hcchar |= HCCHAR_CHENA;
1990 hcchar &= ~HCCHAR_CHDIS;
1993 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1994 (hcchar & HCCHAR_MULTICNT_MASK) >>
1995 HCCHAR_MULTICNT_SHIFT);
1997 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1999 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
2002 chan->xfer_started = 1;
2005 if (hsotg->core_params->dma_enable <= 0 &&
2006 !chan->ep_is_in && chan->xfer_len > 0)
2007 /* Load OUT packet into the appropriate Tx FIFO */
2008 dwc2_hc_write_packet(hsotg, chan);
2012 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
2013 * host channel and starts the transfer in Descriptor DMA mode
2015 * @hsotg: Programming view of DWC_otg controller
2016 * @chan: Information needed to initialize the host channel
2018 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
2019 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
2020 * with micro-frame bitmap.
2022 * Initializes HCDMA register with descriptor list address and CTD value then
2023 * starts the transfer via enabling the channel.
2025 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
2026 struct dwc2_host_chan *chan)
2032 hctsiz |= TSIZ_DOPNG;
2034 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2035 dwc2_set_pid_isoc(chan);
2037 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
2038 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
2039 TSIZ_SC_MC_PID_MASK;
2041 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
2042 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
2044 /* Non-zero only for high-speed interrupt endpoints */
2045 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
2048 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2050 dev_vdbg(hsotg->dev, " Start PID: %d\n",
2051 chan->data_pid_start);
2052 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
2055 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
2057 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
2058 chan->desc_list_sz, DMA_TO_DEVICE);
2060 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
2063 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
2064 &chan->desc_list_addr, chan->hc_num);
2066 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2067 hcchar &= ~HCCHAR_MULTICNT_MASK;
2068 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
2069 HCCHAR_MULTICNT_MASK;
2071 if (hcchar & HCCHAR_CHDIS)
2072 dev_warn(hsotg->dev,
2073 "%s: chdis set, channel %d, hcchar 0x%08x\n",
2074 __func__, chan->hc_num, hcchar);
2076 /* Set host channel enable after all other setup is complete */
2077 hcchar |= HCCHAR_CHENA;
2078 hcchar &= ~HCCHAR_CHDIS;
2081 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
2082 (hcchar & HCCHAR_MULTICNT_MASK) >>
2083 HCCHAR_MULTICNT_SHIFT);
2085 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2087 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
2090 chan->xfer_started = 1;
2095 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
2096 * a previous call to dwc2_hc_start_transfer()
2098 * @hsotg: Programming view of DWC_otg controller
2099 * @chan: Information needed to initialize the host channel
2101 * The caller must ensure there is sufficient space in the request queue and Tx
2102 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
2103 * the controller acts autonomously to complete transfers programmed to a host
2106 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2107 * if there is any data remaining to be queued. For an IN transfer, another
2108 * data packet is always requested. For the SETUP phase of a control transfer,
2109 * this function does nothing.
2111 * Return: 1 if a new request is queued, 0 if no more requests are required
2114 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
2115 struct dwc2_host_chan *chan)
2118 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2122 /* SPLITs always queue just once per channel */
2125 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
2126 /* SETUPs are queued only once since they can't be NAK'd */
2129 if (chan->ep_is_in) {
2131 * Always queue another request for other IN transfers. If
2132 * back-to-back INs are issued and NAKs are received for both,
2133 * the driver may still be processing the first NAK when the
2134 * second NAK is received. When the interrupt handler clears
2135 * the NAK interrupt for the first NAK, the second NAK will
2136 * not be seen. So we can't depend on the NAK interrupt
2137 * handler to requeue a NAK'd request. Instead, IN requests
2138 * are issued each time this function is called. When the
2139 * transfer completes, the extra requests for the channel will
2142 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2144 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
2145 hcchar |= HCCHAR_CHENA;
2146 hcchar &= ~HCCHAR_CHDIS;
2148 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
2150 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2157 if (chan->xfer_count < chan->xfer_len) {
2158 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2159 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2160 u32 hcchar = dwc2_readl(hsotg->regs +
2161 HCCHAR(chan->hc_num));
2163 dwc2_hc_set_even_odd_frame(hsotg, chan,
2167 /* Load OUT packet into the appropriate Tx FIFO */
2168 dwc2_hc_write_packet(hsotg, chan);
2177 * dwc2_hc_do_ping() - Starts a PING transfer
2179 * @hsotg: Programming view of DWC_otg controller
2180 * @chan: Information needed to initialize the host channel
2182 * This function should only be called in Slave mode. The Do Ping bit is set in
2183 * the HCTSIZ register, then the channel is enabled.
2185 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
2191 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2195 hctsiz = TSIZ_DOPNG;
2196 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
2197 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
2199 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2200 hcchar |= HCCHAR_CHENA;
2201 hcchar &= ~HCCHAR_CHDIS;
2202 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2206 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
2207 * the HFIR register according to PHY type and speed
2209 * @hsotg: Programming view of DWC_otg controller
2211 * NOTE: The caller can modify the value of the HFIR register only after the
2212 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
2215 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
2219 int clock = 60; /* default value */
2221 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2222 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2224 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
2225 !(usbcfg & GUSBCFG_PHYIF16))
2227 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
2228 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
2230 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2231 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2233 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2234 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
2236 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2237 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2239 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
2240 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
2242 if ((usbcfg & GUSBCFG_PHYSEL) &&
2243 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2246 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
2247 /* High speed case */
2251 return 1000 * clock;
2255 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
2258 * @core_if: Programming view of DWC_otg controller
2259 * @dest: Destination buffer for the packet
2260 * @bytes: Number of bytes to copy to the destination
2262 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
2264 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
2265 u32 *data_buf = (u32 *)dest;
2266 int word_count = (bytes + 3) / 4;
2270 * Todo: Account for the case where dest is not dword aligned. This
2271 * requires reading data from the FIFO into a u32 temp buffer, then
2272 * moving it into the data buffer.
2275 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
2277 for (i = 0; i < word_count; i++, data_buf++)
2278 *data_buf = dwc2_readl(fifo);
2282 * dwc2_dump_host_registers() - Prints the host registers
2284 * @hsotg: Programming view of DWC_otg controller
2286 * NOTE: This function will be removed once the peripheral controller code
2287 * is integrated and the driver is stable
2289 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
2295 dev_dbg(hsotg->dev, "Host Global Registers\n");
2296 addr = hsotg->regs + HCFG;
2297 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
2298 (unsigned long)addr, dwc2_readl(addr));
2299 addr = hsotg->regs + HFIR;
2300 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
2301 (unsigned long)addr, dwc2_readl(addr));
2302 addr = hsotg->regs + HFNUM;
2303 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
2304 (unsigned long)addr, dwc2_readl(addr));
2305 addr = hsotg->regs + HPTXSTS;
2306 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
2307 (unsigned long)addr, dwc2_readl(addr));
2308 addr = hsotg->regs + HAINT;
2309 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
2310 (unsigned long)addr, dwc2_readl(addr));
2311 addr = hsotg->regs + HAINTMSK;
2312 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
2313 (unsigned long)addr, dwc2_readl(addr));
2314 if (hsotg->core_params->dma_desc_enable > 0) {
2315 addr = hsotg->regs + HFLBADDR;
2316 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
2317 (unsigned long)addr, dwc2_readl(addr));
2320 addr = hsotg->regs + HPRT0;
2321 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
2322 (unsigned long)addr, dwc2_readl(addr));
2324 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2325 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
2326 addr = hsotg->regs + HCCHAR(i);
2327 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
2328 (unsigned long)addr, dwc2_readl(addr));
2329 addr = hsotg->regs + HCSPLT(i);
2330 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
2331 (unsigned long)addr, dwc2_readl(addr));
2332 addr = hsotg->regs + HCINT(i);
2333 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
2334 (unsigned long)addr, dwc2_readl(addr));
2335 addr = hsotg->regs + HCINTMSK(i);
2336 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
2337 (unsigned long)addr, dwc2_readl(addr));
2338 addr = hsotg->regs + HCTSIZ(i);
2339 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
2340 (unsigned long)addr, dwc2_readl(addr));
2341 addr = hsotg->regs + HCDMA(i);
2342 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
2343 (unsigned long)addr, dwc2_readl(addr));
2344 if (hsotg->core_params->dma_desc_enable > 0) {
2345 addr = hsotg->regs + HCDMAB(i);
2346 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
2347 (unsigned long)addr, dwc2_readl(addr));
2354 * dwc2_dump_global_registers() - Prints the core global registers
2356 * @hsotg: Programming view of DWC_otg controller
2358 * NOTE: This function will be removed once the peripheral controller code
2359 * is integrated and the driver is stable
2361 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
2366 dev_dbg(hsotg->dev, "Core Global Registers\n");
2367 addr = hsotg->regs + GOTGCTL;
2368 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
2369 (unsigned long)addr, dwc2_readl(addr));
2370 addr = hsotg->regs + GOTGINT;
2371 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
2372 (unsigned long)addr, dwc2_readl(addr));
2373 addr = hsotg->regs + GAHBCFG;
2374 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
2375 (unsigned long)addr, dwc2_readl(addr));
2376 addr = hsotg->regs + GUSBCFG;
2377 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
2378 (unsigned long)addr, dwc2_readl(addr));
2379 addr = hsotg->regs + GRSTCTL;
2380 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
2381 (unsigned long)addr, dwc2_readl(addr));
2382 addr = hsotg->regs + GINTSTS;
2383 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
2384 (unsigned long)addr, dwc2_readl(addr));
2385 addr = hsotg->regs + GINTMSK;
2386 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
2387 (unsigned long)addr, dwc2_readl(addr));
2388 addr = hsotg->regs + GRXSTSR;
2389 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
2390 (unsigned long)addr, dwc2_readl(addr));
2391 addr = hsotg->regs + GRXFSIZ;
2392 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
2393 (unsigned long)addr, dwc2_readl(addr));
2394 addr = hsotg->regs + GNPTXFSIZ;
2395 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
2396 (unsigned long)addr, dwc2_readl(addr));
2397 addr = hsotg->regs + GNPTXSTS;
2398 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
2399 (unsigned long)addr, dwc2_readl(addr));
2400 addr = hsotg->regs + GI2CCTL;
2401 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
2402 (unsigned long)addr, dwc2_readl(addr));
2403 addr = hsotg->regs + GPVNDCTL;
2404 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
2405 (unsigned long)addr, dwc2_readl(addr));
2406 addr = hsotg->regs + GGPIO;
2407 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
2408 (unsigned long)addr, dwc2_readl(addr));
2409 addr = hsotg->regs + GUID;
2410 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
2411 (unsigned long)addr, dwc2_readl(addr));
2412 addr = hsotg->regs + GSNPSID;
2413 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
2414 (unsigned long)addr, dwc2_readl(addr));
2415 addr = hsotg->regs + GHWCFG1;
2416 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
2417 (unsigned long)addr, dwc2_readl(addr));
2418 addr = hsotg->regs + GHWCFG2;
2419 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
2420 (unsigned long)addr, dwc2_readl(addr));
2421 addr = hsotg->regs + GHWCFG3;
2422 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
2423 (unsigned long)addr, dwc2_readl(addr));
2424 addr = hsotg->regs + GHWCFG4;
2425 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
2426 (unsigned long)addr, dwc2_readl(addr));
2427 addr = hsotg->regs + GLPMCFG;
2428 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
2429 (unsigned long)addr, dwc2_readl(addr));
2430 addr = hsotg->regs + GPWRDN;
2431 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
2432 (unsigned long)addr, dwc2_readl(addr));
2433 addr = hsotg->regs + GDFIFOCFG;
2434 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
2435 (unsigned long)addr, dwc2_readl(addr));
2436 addr = hsotg->regs + HPTXFSIZ;
2437 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
2438 (unsigned long)addr, dwc2_readl(addr));
2440 addr = hsotg->regs + PCGCTL;
2441 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
2442 (unsigned long)addr, dwc2_readl(addr));
2447 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
2449 * @hsotg: Programming view of DWC_otg controller
2450 * @num: Tx FIFO to flush
2452 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
2457 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
2459 greset = GRSTCTL_TXFFLSH;
2460 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
2461 dwc2_writel(greset, hsotg->regs + GRSTCTL);
2464 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2465 if (++count > 10000) {
2466 dev_warn(hsotg->dev,
2467 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
2469 dwc2_readl(hsotg->regs + GNPTXSTS));
2473 } while (greset & GRSTCTL_TXFFLSH);
2475 /* Wait for at least 3 PHY Clocks */
2480 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
2482 * @hsotg: Programming view of DWC_otg controller
2484 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
2489 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2491 greset = GRSTCTL_RXFFLSH;
2492 dwc2_writel(greset, hsotg->regs + GRSTCTL);
2495 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2496 if (++count > 10000) {
2497 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
2502 } while (greset & GRSTCTL_RXFFLSH);
2504 /* Wait for at least 3 PHY Clocks */
2508 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
2510 /* Parameter access functions */
2511 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
2516 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
2517 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
2520 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
2521 switch (hsotg->hw_params.op_mode) {
2522 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2523 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2524 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2525 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2532 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
2543 "%d invalid for otg_cap parameter. Check HW configuration.\n",
2545 switch (hsotg->hw_params.op_mode) {
2546 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2547 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
2549 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2550 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2551 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2552 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2555 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2558 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2561 hsotg->core_params->otg_cap = val;
2564 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2568 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
2576 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2578 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
2579 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2582 hsotg->core_params->dma_enable = val;
2585 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2589 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2590 !hsotg->hw_params.dma_desc_enable))
2598 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2600 val = (hsotg->core_params->dma_enable > 0 &&
2601 hsotg->hw_params.dma_desc_enable);
2602 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2605 hsotg->core_params->dma_desc_enable = val;
2608 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
2612 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2613 !hsotg->hw_params.dma_desc_enable))
2621 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
2623 val = (hsotg->core_params->dma_enable > 0 &&
2624 hsotg->hw_params.dma_desc_enable);
2627 hsotg->core_params->dma_desc_fs_enable = val;
2628 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
2631 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2634 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2637 "Wrong value for host_support_fs_low_power\n");
2639 "host_support_fs_low_power must be 0 or 1\n");
2643 "Setting host_support_fs_low_power to %d\n", val);
2646 hsotg->core_params->host_support_fs_ls_low_power = val;
2649 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2653 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
2661 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2663 val = hsotg->hw_params.enable_dynamic_fifo;
2664 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2667 hsotg->core_params->enable_dynamic_fifo = val;
2670 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2674 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
2680 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2682 val = hsotg->hw_params.host_rx_fifo_size;
2683 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2686 hsotg->core_params->host_rx_fifo_size = val;
2689 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2693 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
2699 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2701 val = hsotg->hw_params.host_nperio_tx_fifo_size;
2702 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2706 hsotg->core_params->host_nperio_tx_fifo_size = val;
2709 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2713 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
2719 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2721 val = hsotg->hw_params.host_perio_tx_fifo_size;
2722 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2726 hsotg->core_params->host_perio_tx_fifo_size = val;
2729 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2733 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
2739 "%d invalid for max_transfer_size. Check HW configuration.\n",
2741 val = hsotg->hw_params.max_transfer_size;
2742 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2745 hsotg->core_params->max_transfer_size = val;
2748 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2752 if (val < 15 || val > hsotg->hw_params.max_packet_count)
2758 "%d invalid for max_packet_count. Check HW configuration.\n",
2760 val = hsotg->hw_params.max_packet_count;
2761 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2764 hsotg->core_params->max_packet_count = val;
2767 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2771 if (val < 1 || val > hsotg->hw_params.host_channels)
2777 "%d invalid for host_channels. Check HW configuration.\n",
2779 val = hsotg->hw_params.host_channels;
2780 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2783 hsotg->core_params->host_channels = val;
2786 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2789 u32 hs_phy_type, fs_phy_type;
2791 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
2792 DWC2_PHY_TYPE_PARAM_ULPI)) {
2794 dev_err(hsotg->dev, "Wrong value for phy_type\n");
2795 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2801 hs_phy_type = hsotg->hw_params.hs_phy_type;
2802 fs_phy_type = hsotg->hw_params.fs_phy_type;
2803 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2804 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2805 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2807 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2808 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2809 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2811 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2812 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2818 "%d invalid for phy_type. Check HW configuration.\n",
2820 val = DWC2_PHY_TYPE_PARAM_FS;
2821 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2822 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2823 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2824 val = DWC2_PHY_TYPE_PARAM_UTMI;
2826 val = DWC2_PHY_TYPE_PARAM_ULPI;
2828 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2831 hsotg->core_params->phy_type = val;
2834 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2836 return hsotg->core_params->phy_type;
2839 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2843 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2845 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2846 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2851 if (val == DWC2_SPEED_PARAM_HIGH &&
2852 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2858 "%d invalid for speed parameter. Check HW configuration.\n",
2860 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2861 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2862 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2865 hsotg->core_params->speed = val;
2868 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2872 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2873 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2876 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2878 "host_ls_low_power_phy_clk must be 0 or 1\n");
2883 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2884 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2890 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2892 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2893 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2894 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2895 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2899 hsotg->core_params->host_ls_low_power_phy_clk = val;
2902 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2904 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2906 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2907 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2910 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2913 hsotg->core_params->phy_ulpi_ddr = val;
2916 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2918 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2921 "Wrong value for phy_ulpi_ext_vbus\n");
2923 "phy_ulpi_ext_vbus must be 0 or 1\n");
2926 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2929 hsotg->core_params->phy_ulpi_ext_vbus = val;
2932 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2936 switch (hsotg->hw_params.utmi_phy_data_width) {
2937 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
2940 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
2941 valid = (val == 16);
2943 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
2944 valid = (val == 8 || val == 16);
2951 "%d invalid for phy_utmi_width. Check HW configuration.\n",
2954 val = (hsotg->hw_params.utmi_phy_data_width ==
2955 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
2956 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2959 hsotg->core_params->phy_utmi_width = val;
2962 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2964 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2966 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2967 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2970 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2973 hsotg->core_params->ulpi_fs_ls = val;
2976 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2978 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2980 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2981 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2984 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2987 hsotg->core_params->ts_dline = val;
2990 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2994 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2996 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2997 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
3003 if (val == 1 && !(hsotg->hw_params.i2c_enable))
3009 "%d invalid for i2c_enable. Check HW configuration.\n",
3011 val = hsotg->hw_params.i2c_enable;
3012 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
3015 hsotg->core_params->i2c_enable = val;
3018 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
3022 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3025 "Wrong value for en_multiple_tx_fifo,\n");
3027 "en_multiple_tx_fifo must be 0 or 1\n");
3032 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
3038 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
3040 val = hsotg->hw_params.en_multiple_tx_fifo;
3041 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
3044 hsotg->core_params->en_multiple_tx_fifo = val;
3047 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
3051 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3054 "'%d' invalid for parameter reload_ctl\n", val);
3055 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
3060 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
3066 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
3068 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
3069 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
3072 hsotg->core_params->reload_ctl = val;
3075 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
3078 hsotg->core_params->ahbcfg = val;
3080 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
3081 GAHBCFG_HBSTLEN_SHIFT;
3084 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
3086 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3089 "'%d' invalid for parameter otg_ver\n", val);
3091 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
3094 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
3097 hsotg->core_params->otg_ver = val;
3100 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
3102 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3105 "'%d' invalid for parameter uframe_sched\n",
3107 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
3110 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
3113 hsotg->core_params->uframe_sched = val;
3116 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
3119 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3122 "'%d' invalid for parameter external_id_pin_ctl\n",
3124 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
3127 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
3130 hsotg->core_params->external_id_pin_ctl = val;
3133 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
3136 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3139 "'%d' invalid for parameter hibernation\n",
3141 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
3144 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
3147 hsotg->core_params->hibernation = val;
3151 * This function is called during module intialization to pass module parameters
3152 * for the DWC_otg core.
3154 void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
3155 const struct dwc2_core_params *params)
3157 dev_dbg(hsotg->dev, "%s()\n", __func__);
3159 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
3160 dwc2_set_param_dma_enable(hsotg, params->dma_enable);
3161 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
3162 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
3163 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
3164 params->host_support_fs_ls_low_power);
3165 dwc2_set_param_enable_dynamic_fifo(hsotg,
3166 params->enable_dynamic_fifo);
3167 dwc2_set_param_host_rx_fifo_size(hsotg,
3168 params->host_rx_fifo_size);
3169 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
3170 params->host_nperio_tx_fifo_size);
3171 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
3172 params->host_perio_tx_fifo_size);
3173 dwc2_set_param_max_transfer_size(hsotg,
3174 params->max_transfer_size);
3175 dwc2_set_param_max_packet_count(hsotg,
3176 params->max_packet_count);
3177 dwc2_set_param_host_channels(hsotg, params->host_channels);
3178 dwc2_set_param_phy_type(hsotg, params->phy_type);
3179 dwc2_set_param_speed(hsotg, params->speed);
3180 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
3181 params->host_ls_low_power_phy_clk);
3182 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
3183 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
3184 params->phy_ulpi_ext_vbus);
3185 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
3186 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
3187 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
3188 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
3189 dwc2_set_param_en_multiple_tx_fifo(hsotg,
3190 params->en_multiple_tx_fifo);
3191 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
3192 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
3193 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
3194 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
3195 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
3196 dwc2_set_param_hibernation(hsotg, params->hibernation);
3200 * Forces either host or device mode if the controller is not
3201 * currently in that mode.
3203 * Returns true if the mode was forced.
3205 static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
3207 if (host && dwc2_is_host_mode(hsotg))
3209 else if (!host && dwc2_is_device_mode(hsotg))
3212 return dwc2_force_mode(hsotg, host);
3216 * Gets host hardware parameters. Forces host mode if not currently in
3217 * host mode. Should be called immediately after a core soft reset in
3218 * order to get the reset values.
3220 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
3222 struct dwc2_hw_params *hw = &hsotg->hw_params;
3227 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3230 forced = dwc2_force_mode_if_needed(hsotg, true);
3232 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
3233 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
3234 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
3235 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
3238 dwc2_clear_force_mode(hsotg);
3240 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3241 FIFOSIZE_DEPTH_SHIFT;
3242 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3243 FIFOSIZE_DEPTH_SHIFT;
3247 * Gets device hardware parameters. Forces device mode if not
3248 * currently in device mode. Should be called immediately after a core
3249 * soft reset in order to get the reset values.
3251 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
3253 struct dwc2_hw_params *hw = &hsotg->hw_params;
3257 if (hsotg->dr_mode == USB_DR_MODE_HOST)
3260 forced = dwc2_force_mode_if_needed(hsotg, false);
3262 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
3263 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
3266 dwc2_clear_force_mode(hsotg);
3268 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3269 FIFOSIZE_DEPTH_SHIFT;
3273 * During device initialization, read various hardware configuration
3274 * registers and interpret the contents.
3276 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
3278 struct dwc2_hw_params *hw = &hsotg->hw_params;
3280 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
3284 * Attempt to ensure this device is really a DWC_otg Controller.
3285 * Read and verify the GSNPSID register contents. The value should be
3286 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
3287 * as in "OTG version 2.xx" or "OTG version 3.xx".
3289 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
3290 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
3291 (hw->snpsid & 0xfffff000) != 0x4f543000) {
3292 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
3297 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
3298 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
3299 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
3301 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
3302 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
3303 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
3304 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
3305 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
3307 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
3308 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
3309 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
3310 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
3311 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
3314 * Host specific hardware parameters. Reading these parameters
3315 * requires the controller to be in host mode. The mode will
3316 * be forced, if necessary, to read these values.
3318 dwc2_get_host_hwparams(hsotg);
3319 dwc2_get_dev_hwparams(hsotg);
3322 hw->dev_ep_dirs = hwcfg1;
3325 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
3326 GHWCFG2_OP_MODE_SHIFT;
3327 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
3328 GHWCFG2_ARCHITECTURE_SHIFT;
3329 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
3330 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
3331 GHWCFG2_NUM_HOST_CHAN_SHIFT);
3332 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
3333 GHWCFG2_HS_PHY_TYPE_SHIFT;
3334 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
3335 GHWCFG2_FS_PHY_TYPE_SHIFT;
3336 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
3337 GHWCFG2_NUM_DEV_EP_SHIFT;
3338 hw->nperio_tx_q_depth =
3339 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
3340 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
3341 hw->host_perio_tx_q_depth =
3342 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
3343 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
3344 hw->dev_token_q_depth =
3345 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
3346 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
3349 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
3350 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
3351 hw->max_transfer_size = (1 << (width + 11)) - 1;
3353 * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates
3354 * coherent buffers with this size, and if it's too large we can
3355 * exhaust the coherent DMA pool.
3357 if (hw->max_transfer_size > 65535)
3358 hw->max_transfer_size = 65535;
3359 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
3360 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
3361 hw->max_packet_count = (1 << (width + 4)) - 1;
3362 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
3363 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
3364 GHWCFG3_DFIFO_DEPTH_SHIFT;
3367 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
3368 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
3369 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
3370 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
3371 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
3372 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
3373 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
3376 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
3377 GRXFSIZ_DEPTH_SHIFT;
3379 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
3380 dev_dbg(hsotg->dev, " op_mode=%d\n",
3382 dev_dbg(hsotg->dev, " arch=%d\n",
3384 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
3385 hw->dma_desc_enable);
3386 dev_dbg(hsotg->dev, " power_optimized=%d\n",
3387 hw->power_optimized);
3388 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
3390 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
3392 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
3394 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
3395 hw->utmi_phy_data_width);
3396 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
3398 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
3399 hw->num_dev_perio_in_ep);
3400 dev_dbg(hsotg->dev, " host_channels=%d\n",
3402 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
3403 hw->max_transfer_size);
3404 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
3405 hw->max_packet_count);
3406 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
3407 hw->nperio_tx_q_depth);
3408 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
3409 hw->host_perio_tx_q_depth);
3410 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
3411 hw->dev_token_q_depth);
3412 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
3413 hw->enable_dynamic_fifo);
3414 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
3415 hw->en_multiple_tx_fifo);
3416 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
3417 hw->total_fifo_size);
3418 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
3419 hw->host_rx_fifo_size);
3420 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
3421 hw->host_nperio_tx_fifo_size);
3422 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
3423 hw->host_perio_tx_fifo_size);
3424 dev_dbg(hsotg->dev, "\n");
3430 * Sets all parameters to the given value.
3432 * Assumes that the dwc2_core_params struct contains only integers.
3434 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
3436 int *p = (int *)params;
3437 size_t size = sizeof(*params) / sizeof(*p);
3440 for (i = 0; i < size; i++)
3445 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
3447 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
3450 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
3452 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
3459 * dwc2_enable_global_interrupts() - Enables the controller's Global
3460 * Interrupt in the AHB Config register
3462 * @hsotg: Programming view of DWC_otg controller
3464 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
3466 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3468 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
3469 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3473 * dwc2_disable_global_interrupts() - Disables the controller's Global
3474 * Interrupt in the AHB Config register
3476 * @hsotg: Programming view of DWC_otg controller
3478 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
3480 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3482 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
3483 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3486 /* Returns the controller's GHWCFG2.OTG_MODE. */
3487 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
3489 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
3491 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
3492 GHWCFG2_OP_MODE_SHIFT;
3495 /* Returns true if the controller is capable of DRD. */
3496 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
3498 unsigned op_mode = dwc2_op_mode(hsotg);
3500 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
3501 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
3502 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
3505 /* Returns true if the controller is host-only. */
3506 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
3508 unsigned op_mode = dwc2_op_mode(hsotg);
3510 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
3511 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
3514 /* Returns true if the controller is device-only. */
3515 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
3517 unsigned op_mode = dwc2_op_mode(hsotg);
3519 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
3520 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
3523 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
3524 MODULE_AUTHOR("Synopsys, Inc.");
3525 MODULE_LICENSE("Dual BSD/GPL");