2 * core.h - DesignWare HS OTG Controller common declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #ifndef __DWC2_CORE_H__
38 #define __DWC2_CORE_H__
40 #include <linux/phy/phy.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/usb/gadget.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/phy.h>
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
54 #define DWC2_TRACE_SCHEDULER no_printk
55 #define DWC2_TRACE_SCHEDULER_VB no_printk
57 /* Detailed scheduler tracing, but won't overwhelm console */
58 #define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
62 /* Verbose scheduler tracing */
63 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
78 static inline u32 dwc2_readl(const void __iomem *addr)
80 u32 value = __raw_readl(addr);
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
90 static inline void dwc2_writel(u32 value, void __iomem *addr)
92 __raw_writel(value, addr);
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
100 #ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
105 /* Normal architectures just use readl/write */
106 static inline u32 dwc2_readl(const void __iomem *addr)
111 static inline void dwc2_writel(u32 value, void __iomem *addr)
115 #ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
121 /* Maximum number of Endpoints/HostChannels */
122 #define MAX_EPS_CHANNELS 16
124 /* dwc2-hsotg declarations */
125 static const char * const dwc2_hsotg_supply_names[] = {
126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
133 * Unfortunately there seems to be a limit of the amount of data that can
134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
135 * packets (which practically means 1 packet and 63 bytes of data) when the
138 * This means if we are wanting to move >127 bytes of data, we need to
139 * split the transactions up, but just doing one packet at a time does
140 * not work (this may be an implicit DATA0 PID on first packet of the
141 * transaction) and doing 2 packets is outside the controller's limits.
143 * If we try to lower the MPS size for EP0, then no transfers work properly
144 * for EP0, and the system will fail basic enumeration. As no cause for this
145 * has currently been found, we cannot support any large IN transfers for
148 #define EP0_MPS_LIMIT 64
151 struct dwc2_hsotg_req;
154 * struct dwc2_hsotg_ep - driver endpoint definition.
155 * @ep: The gadget layer representation of the endpoint.
156 * @name: The driver generated name for the endpoint.
157 * @queue: Queue of requests for this endpoint.
158 * @parent: Reference back to the parent device structure.
159 * @req: The current request that the endpoint is processing. This is
160 * used to indicate an request has been loaded onto the endpoint
161 * and has yet to be completed (maybe due to data move, or simply
162 * awaiting an ack from the core all the data has been completed).
163 * @debugfs: File entry for debugfs file for this endpoint.
164 * @lock: State lock to protect contents of endpoint.
165 * @dir_in: Set to true if this endpoint is of the IN direction, which
166 * means that it is sending data to the Host.
167 * @index: The index for the endpoint registers.
168 * @mc: Multi Count - number of transactions per microframe
169 * @interval - Interval for periodic endpoints, in frames or microframes.
170 * @name: The name array passed to the USB core.
171 * @halted: Set if the endpoint has been halted.
172 * @periodic: Set if this is a periodic ep, such as Interrupt
173 * @isochronous: Set if this is a isochronous ep
174 * @send_zlp: Set if we need to send a zero-length packet.
175 * @desc_list_dma: The DMA address of descriptor chain currently in use.
176 * @desc_list: Pointer to descriptor DMA chain head currently in use.
177 * @desc_count: Count of entries within the DMA descriptor chain of EP.
178 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
179 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
180 * @total_data: The total number of data bytes done.
181 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
182 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
183 * @last_load: The offset of data for the last start of request.
184 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
185 * @target_frame: Targeted frame num to setup next ISOC transfer
186 * @frame_overrun: Indicates SOF number overrun in DSTS
188 * This is the driver's state for each registered enpoint, allowing it
189 * to keep track of transactions that need doing. Each endpoint has a
190 * lock to protect the state, to try and avoid using an overall lock
191 * for the host controller as much as possible.
193 * For periodic IN endpoints, we have fifo_size and fifo_load to try
194 * and keep track of the amount of data in the periodic FIFO for each
195 * of these as we don't have a status register that tells us how much
196 * is in each of them. (note, this may actually be useless information
197 * as in shared-fifo mode periodic in acts like a single-frame packet
198 * buffer than a fifo)
200 struct dwc2_hsotg_ep {
202 struct list_head queue;
203 struct dwc2_hsotg *parent;
204 struct dwc2_hsotg_req *req;
205 struct dentry *debugfs;
207 unsigned long total_data;
208 unsigned int size_loaded;
209 unsigned int last_load;
210 unsigned int fifo_load;
211 unsigned short fifo_size;
212 unsigned short fifo_index;
214 unsigned char dir_in;
217 unsigned char interval;
219 unsigned int halted:1;
220 unsigned int periodic:1;
221 unsigned int isochronous:1;
222 unsigned int send_zlp:1;
223 unsigned int target_frame;
224 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
227 dma_addr_t desc_list_dma;
228 struct dwc2_dma_desc *desc_list;
231 unsigned char isoc_chain_num;
232 unsigned int next_desc;
238 * struct dwc2_hsotg_req - data transfer request
239 * @req: The USB gadget request
240 * @queue: The list of requests for the endpoint this is queued for.
241 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
243 struct dwc2_hsotg_req {
244 struct usb_request req;
245 struct list_head queue;
249 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
250 #define call_gadget(_hs, _entry) \
252 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
253 (_hs)->driver && (_hs)->driver->_entry) { \
254 spin_unlock(&_hs->lock); \
255 (_hs)->driver->_entry(&(_hs)->gadget); \
256 spin_lock(&_hs->lock); \
260 #define call_gadget(_hs, _entry) do {} while (0)
264 struct dwc2_host_chan;
268 DWC2_L0, /* On state */
269 DWC2_L1, /* LPM sleep state */
270 DWC2_L2, /* USB suspend state */
271 DWC2_L3, /* Off state */
275 * Gadget periodic tx fifo sizes as used by legacy driver
276 * EP0 is not included
278 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
279 768, 0, 0, 0, 0, 0, 0, 0}
281 /* Gadget ep0 states */
282 enum dwc2_ep0_state {
291 * struct dwc2_core_params - Parameters for configuring the core
293 * @otg_cap: Specifies the OTG capabilities.
294 * 0 - HNP and SRP capable
295 * 1 - SRP Only capable
296 * 2 - No HNP/SRP capable (always available)
297 * Defaults to best available option (0, 1, then 2)
298 * @otg_ver: OTG version supported
301 * @host_dma: Specifies whether to use slave or DMA mode for accessing
302 * the data FIFOs. The driver will automatically detect the
303 * value for this parameter if none is specified.
304 * 0 - Slave (always available)
305 * 1 - DMA (default, if available)
306 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
307 * address DMA mode or descriptor DMA mode for accessing
308 * the data FIFOs. The driver will automatically detect the
309 * value for this if none is specified.
311 * 1 - Descriptor DMA (default, if available)
312 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
313 * address DMA mode or descriptor DMA mode for accessing
314 * the data FIFOs in Full Speed mode only. The driver
315 * will automatically detect the value for this if none is
318 * 1 - Descriptor DMA in FS (default, if available)
319 * @speed: Specifies the maximum speed of operation in host and
320 * device mode. The actual speed depends on the speed of
321 * the attached device and the value of phy_type.
323 * (default when phy_type is UTMI+ or ULPI)
325 * (default when phy_type is Full Speed)
326 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
327 * 1 - Allow dynamic FIFO sizing (default, if available)
328 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
329 * are enabled for non-periodic IN endpoints in device
331 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
332 * dynamic FIFO sizing is enabled
334 * Actual maximum value is autodetected and also
336 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
337 * in host mode when dynamic FIFO sizing is enabled
339 * Actual maximum value is autodetected and also
341 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
342 * host mode when dynamic FIFO sizing is enabled
344 * Actual maximum value is autodetected and also
346 * @max_transfer_size: The maximum transfer size supported, in bytes
348 * Actual maximum value is autodetected and also
350 * @max_packet_count: The maximum number of packets in a transfer
352 * Actual maximum value is autodetected and also
354 * @host_channels: The number of host channel registers to use
356 * Actual maximum value is autodetected and also
358 * @phy_type: Specifies the type of PHY interface to use. By default,
359 * the driver will automatically detect the phy_type.
363 * Defaults to best available option (2, 1, then 0)
364 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
365 * is applicable for a phy_type of UTMI+ or ULPI. (For a
366 * ULPI phy_type, this parameter indicates the data width
367 * between the MAC and the ULPI Wrapper.) Also, this
368 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
369 * parameter was set to "8 and 16 bits", meaning that the
370 * core has been configured to work at either data path
372 * 8 or 16 (default 16 if available)
373 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
374 * data rate. This parameter is only applicable if phy_type
376 * 0 - single data rate ULPI interface with 8 bit wide
378 * 1 - double data rate ULPI interface with 4 bit wide
380 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
381 * external supply to drive the VBus
382 * 0 - Internal supply (default)
383 * 1 - External supply
384 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
385 * speed PHY. This parameter is only applicable if phy_type
389 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
392 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
393 * when attached to a Full Speed or Low Speed device in
395 * 0 - Don't support low power mode (default)
396 * 1 - Support low power mode
397 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
398 * when connected to a Low Speed device in host
399 * mode. This parameter is applicable only if
400 * host_support_fs_ls_low_power is enabled.
402 * (default when phy_type is UTMI+ or ULPI)
404 * (default when phy_type is Full Speed)
405 * @ts_dline: Enable Term Select Dline pulsing
408 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
409 * 0 - No (default for core < 2.92a)
410 * 1 - Yes (default for core >= 2.92a)
411 * @ahbcfg: This field allows the default value of the GAHBCFG
412 * register to be overridden
413 * -1 - GAHBCFG value will be set to 0x06
415 * all others - GAHBCFG value will be overridden with
417 * Not all bits can be controlled like this, the
418 * bits defined by GAHBCFG_CTRL_MASK are controlled
419 * by the driver and are ignored in this
420 * configuration value.
421 * @uframe_sched: True to enable the microframe scheduler
422 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
423 * Disable CONIDSTSCHNG controller interrupt in such
427 * @hibernation: Specifies whether the controller support hibernation.
428 * If hibernation is enabled, the controller will enter
429 * hibernation in both peripheral and host mode when
433 * @g_dma: Enables gadget dma usage (default: autodetect).
434 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
435 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
436 * DWORDS from 16-32768 (default: 2048 if
437 * possible, otherwise autodetect).
438 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
439 * DWORDS from 16-32768 (default: 1024 if
440 * possible, otherwise autodetect).
441 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
442 * mode. Each value corresponds to one EP
443 * starting from EP1 (max 15 values). Sizes are
444 * in DWORDS with possible values from from
445 * 16-32768 (default: 256, 256, 256, 256, 768,
446 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
448 * The following parameters may be specified when starting the module. These
449 * parameters define how the DWC_otg controller should be configured. A
450 * value of -1 (or any other out of range value) for any parameter means
451 * to read the value from hardware (if possible) or use the builtin
452 * default described above.
454 struct dwc2_core_params {
456 * Don't add any non-int members here, this will break
457 * dwc2_set_all_params!
460 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
461 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
462 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
466 int dma_desc_fs_enable;
468 #define DWC2_SPEED_PARAM_HIGH 0
469 #define DWC2_SPEED_PARAM_FULL 1
470 #define DWC2_SPEED_PARAM_LOW 2
472 int enable_dynamic_fifo;
473 int en_multiple_tx_fifo;
474 int host_rx_fifo_size;
475 int host_nperio_tx_fifo_size;
476 int host_perio_tx_fifo_size;
477 int max_transfer_size;
478 int max_packet_count;
481 #define DWC2_PHY_TYPE_PARAM_FS 0
482 #define DWC2_PHY_TYPE_PARAM_UTMI 1
483 #define DWC2_PHY_TYPE_PARAM_ULPI 2
487 int phy_ulpi_ext_vbus;
488 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0
489 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
493 int host_support_fs_ls_low_power;
494 int host_ls_low_power_phy_clk;
495 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
496 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
502 int external_id_pin_ctl;
506 * The following parameters are *only* set via device
507 * properties and cannot be set directly in this structure.
510 /* Host parameters */
513 /* Gadget parameters */
517 u16 g_np_tx_fifo_size;
518 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
522 * struct dwc2_hw_params - Autodetected parameters.
524 * These parameters are the various parameters read from hardware
525 * registers during initialization. They typically contain the best
526 * supported or maximum value that can be configured in the
527 * corresponding dwc2_core_params value.
529 * The values that are not in dwc2_core_params are documented below.
531 * @op_mode Mode of Operation
532 * 0 - HNP- and SRP-Capable OTG (Host & Device)
533 * 1 - SRP-Capable OTG (Host & Device)
534 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
535 * 3 - SRP-Capable Device
537 * 5 - SRP-Capable Host
543 * @power_optimized Are power optimizations enabled?
544 * @num_dev_ep Number of device endpoints available
545 * @num_dev_perio_in_ep Number of device periodic IN endpoints
547 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
550 * @host_perio_tx_q_depth
551 * Host Mode Periodic Request Queue Depth
554 * Non-Periodic Request Queue Depth
556 * @hs_phy_type High-speed PHY interface type
557 * 0 - High-speed interface not supported
561 * @fs_phy_type Full-speed PHY interface type
562 * 0 - Full speed interface not supported
563 * 1 - Dedicated full speed interface
564 * 2 - FS pins shared with UTMI+ pins
565 * 3 - FS pins shared with ULPI pins
566 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
567 * @utmi_phy_data_width UTMI+ PHY data width
571 * @snpsid: Value from SNPSID register
572 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
574 struct dwc2_hw_params {
577 unsigned dma_desc_enable:1;
578 unsigned enable_dynamic_fifo:1;
579 unsigned en_multiple_tx_fifo:1;
580 unsigned rx_fifo_size:16;
581 unsigned host_nperio_tx_fifo_size:16;
582 unsigned dev_nperio_tx_fifo_size:16;
583 unsigned host_perio_tx_fifo_size:16;
584 unsigned nperio_tx_q_depth:3;
585 unsigned host_perio_tx_q_depth:3;
586 unsigned dev_token_q_depth:5;
587 unsigned max_transfer_size:26;
588 unsigned max_packet_count:11;
589 unsigned host_channels:5;
590 unsigned hs_phy_type:2;
591 unsigned fs_phy_type:2;
592 unsigned i2c_enable:1;
593 unsigned num_dev_ep:4;
594 unsigned num_dev_perio_in_ep:4;
595 unsigned total_fifo_size:16;
596 unsigned power_optimized:1;
597 unsigned utmi_phy_data_width:2;
602 /* Size of control and EP0 buffers */
603 #define DWC2_CTRL_BUFF_SIZE 8
606 * struct dwc2_gregs_backup - Holds global registers state before entering partial
608 * @gotgctl: Backup of GOTGCTL register
609 * @gintmsk: Backup of GINTMSK register
610 * @gahbcfg: Backup of GAHBCFG register
611 * @gusbcfg: Backup of GUSBCFG register
612 * @grxfsiz: Backup of GRXFSIZ register
613 * @gnptxfsiz: Backup of GNPTXFSIZ register
614 * @gi2cctl: Backup of GI2CCTL register
615 * @hptxfsiz: Backup of HPTXFSIZ register
616 * @gdfifocfg: Backup of GDFIFOCFG register
617 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
618 * @gpwrdn: Backup of GPWRDN register
620 struct dwc2_gregs_backup {
631 u32 dtxfsiz[MAX_EPS_CHANNELS];
637 * struct dwc2_dregs_backup - Holds device registers state before entering partial
639 * @dcfg: Backup of DCFG register
640 * @dctl: Backup of DCTL register
641 * @daintmsk: Backup of DAINTMSK register
642 * @diepmsk: Backup of DIEPMSK register
643 * @doepmsk: Backup of DOEPMSK register
644 * @diepctl: Backup of DIEPCTL register
645 * @dieptsiz: Backup of DIEPTSIZ register
646 * @diepdma: Backup of DIEPDMA register
647 * @doepctl: Backup of DOEPCTL register
648 * @doeptsiz: Backup of DOEPTSIZ register
649 * @doepdma: Backup of DOEPDMA register
651 struct dwc2_dregs_backup {
657 u32 diepctl[MAX_EPS_CHANNELS];
658 u32 dieptsiz[MAX_EPS_CHANNELS];
659 u32 diepdma[MAX_EPS_CHANNELS];
660 u32 doepctl[MAX_EPS_CHANNELS];
661 u32 doeptsiz[MAX_EPS_CHANNELS];
662 u32 doepdma[MAX_EPS_CHANNELS];
667 * struct dwc2_hregs_backup - Holds host registers state before entering partial
669 * @hcfg: Backup of HCFG register
670 * @haintmsk: Backup of HAINTMSK register
671 * @hcintmsk: Backup of HCINTMSK register
672 * @hptr0: Backup of HPTR0 register
673 * @hfir: Backup of HFIR register
675 struct dwc2_hregs_backup {
678 u32 hcintmsk[MAX_EPS_CHANNELS];
685 * Constants related to high speed periodic scheduling
687 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
688 * reservation point of view it's assumed that the schedule goes right back to
689 * the beginning after the end of the schedule.
691 * What does that mean for scheduling things with a long interval? It means
692 * we'll reserve time for them in every possible microframe that they could
693 * ever be scheduled in. ...but we'll still only actually schedule them as
694 * often as they were requested.
696 * We keep our schedule in a "bitmap" structure. This simplifies having
697 * to keep track of and merge intervals: we just let the bitmap code do most
698 * of the heavy lifting. In a way scheduling is much like memory allocation.
700 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
701 * supposed to schedule for periodic transfers). That's according to spec.
703 * Note that though we only schedule 80% of each microframe, the bitmap that we
704 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
705 * space for each uFrame).
708 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
709 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
710 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
711 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
713 #define DWC2_US_PER_UFRAME 125
714 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
716 #define DWC2_HS_SCHEDULE_UFRAMES 8
717 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
718 DWC2_HS_PERIODIC_US_PER_UFRAME)
721 * Constants related to low speed scheduling
723 * For high speed we schedule every 1us. For low speed that's a bit overkill,
724 * so we make up a unit called a "slice" that's worth 25us. There are 40
725 * slices in a full frame and we can schedule 36 of those (90%) for periodic
728 * Our low speed schedule can be as short as 1 frame or could be longer. When
729 * we only schedule 1 frame it means that we'll need to reserve a time every
730 * frame even for things that only transfer very rarely, so something that runs
731 * every 2048 frames will get time reserved in every frame. Our low speed
732 * schedule can be longer and we'll be able to handle more overlap, but that
733 * will come at increased memory cost and increased time to schedule.
735 * Note: one other advantage of a short low speed schedule is that if we mess
736 * up and miss scheduling we can jump in and use any of the slots that we
737 * happened to reserve.
739 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
740 * the schedule. There will be one schedule per TT.
743 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
745 #define DWC2_US_PER_SLICE 25
746 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
748 #define DWC2_ROUND_US_TO_SLICE(us) \
749 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
752 #define DWC2_LS_PERIODIC_US_PER_FRAME \
754 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
755 (DWC2_LS_PERIODIC_US_PER_FRAME / \
758 #define DWC2_LS_SCHEDULE_FRAMES 1
759 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
760 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
763 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
764 * and periodic schedules
766 * These are common for both host and peripheral modes:
768 * @dev: The struct device pointer
769 * @regs: Pointer to controller regs
770 * @hw_params: Parameters that were autodetected from the
772 * @core_params: Parameters that define how the core should be configured
773 * @op_state: The operational State, during transitions (a_host=>
774 * a_peripheral and b_device=>b_host) this may not match
775 * the core, but allows the software to determine
777 * @dr_mode: Requested mode of operation, one of following:
778 * - USB_DR_MODE_PERIPHERAL
781 * @hcd_enabled Host mode sub-driver initialization indicator.
782 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
783 * @ll_hw_enabled Status of low-level hardware resources.
784 * @phy: The otg phy transceiver structure for phy control.
785 * @uphy: The otg phy transceiver structure for old USB phy control.
786 * @plat: The platform specific configuration data. This can be removed once
787 * all SoCs support usb transceiver.
788 * @supplies: Definition of USB power supplies
789 * @phyif: PHY interface width
790 * @lock: Spinlock that protects all the driver data structures
791 * @priv: Stores a pointer to the struct usb_hcd
792 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
793 * transfer are in process of being queued
794 * @srp_success: Stores status of SRP request in the case of a FS PHY
795 * with an I2C interface
796 * @wq_otg: Workqueue object used for handling of some interrupts
797 * @wf_otg: Work object for handling Connector ID Status Change
799 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
800 * @lx_state: Lx state of connected device
801 * @gregs_backup: Backup of global registers during suspend
802 * @dregs_backup: Backup of device registers during suspend
803 * @hregs_backup: Backup of host registers during suspend
805 * These are for host mode:
807 * @flags: Flags for handling root port state changes
808 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
809 * Transfers associated with these QHs are not currently
810 * assigned to a host channel.
811 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
812 * Transfers associated with these QHs are currently
813 * assigned to a host channel.
814 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
815 * non-periodic schedule
816 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
817 * list of QHs for periodic transfers that are _not_
818 * scheduled for the next frame. Each QH in the list has an
819 * interval counter that determines when it needs to be
820 * scheduled for execution. This scheduling mechanism
821 * allows only a simple calculation for periodic bandwidth
822 * used (i.e. must assume that all periodic transfers may
823 * need to execute in the same frame). However, it greatly
824 * simplifies scheduling and should be sufficient for the
825 * vast majority of OTG hosts, which need to connect to a
826 * small number of peripherals at one time. Items move from
827 * this list to periodic_sched_ready when the QH interval
828 * counter is 0 at SOF.
829 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
830 * the next frame, but have not yet been assigned to host
831 * channels. Items move from this list to
832 * periodic_sched_assigned as host channels become
833 * available during the current frame.
834 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
835 * frame that are assigned to host channels. Items move
836 * from this list to periodic_sched_queued as the
837 * transactions for the QH are queued to the DWC_otg
839 * @periodic_sched_queued: List of periodic QHs that have been queued for
840 * execution. Items move from this list to either
841 * periodic_sched_inactive or periodic_sched_ready when the
842 * channel associated with the transfer is released. If the
843 * interval for the QH is 1, the item moves to
844 * periodic_sched_ready because it must be rescheduled for
845 * the next frame. Otherwise, the item moves to
846 * periodic_sched_inactive.
847 * @split_order: List keeping track of channels doing splits, in order.
848 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
849 * This value is in microseconds per (micro)frame. The
850 * assumption is that all periodic transfers may occur in
851 * the same (micro)frame.
852 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
853 * host is in high speed mode; low speed schedules are
854 * stored elsewhere since we need one per TT.
855 * @frame_number: Frame number read from the core at SOF. The value ranges
856 * from 0 to HFNUM_MAX_FRNUM.
857 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
858 * SOF enable/disable.
859 * @free_hc_list: Free host channels in the controller. This is a list of
860 * struct dwc2_host_chan items.
861 * @periodic_channels: Number of host channels assigned to periodic transfers.
862 * Currently assuming that there is a dedicated host
863 * channel for each periodic transaction and at least one
864 * host channel is available for non-periodic transactions.
865 * @non_periodic_channels: Number of host channels assigned to non-periodic
867 * @available_host_channels Number of host channels available for the microframe
869 * @hc_ptr_array: Array of pointers to the host channel descriptors.
870 * Allows accessing a host channel descriptor given the
871 * host channel number. This is useful in interrupt
873 * @status_buf: Buffer used for data received during the status phase of
874 * a control transfer.
875 * @status_buf_dma: DMA address for status_buf
876 * @start_work: Delayed work for handling host A-cable connection
877 * @reset_work: Delayed work for handling a port reset
878 * @otg_port: OTG port number
879 * @frame_list: Frame list
880 * @frame_list_dma: Frame list DMA address
881 * @frame_list_sz: Frame list size
882 * @desc_gen_cache: Kmem cache for generic descriptors
883 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
885 * These are for peripheral mode:
887 * @driver: USB gadget driver
888 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
889 * @num_of_eps: Number of available EPs (excluding EP0)
890 * @debug_root: Root directrory for debugfs.
891 * @debug_file: Main status file for debugfs.
892 * @debug_testmode: Testmode status file for debugfs.
893 * @debug_fifo: FIFO status file for debugfs.
894 * @ep0_reply: Request used for ep0 reply.
895 * @ep0_buff: Buffer for EP0 reply data, if needed.
896 * @ctrl_buff: Buffer for EP0 control requests.
897 * @ctrl_req: Request for EP0 control packets.
898 * @ep0_state: EP0 control transfers state
899 * @test_mode: USB test mode requested by the host
900 * @setup_desc_dma: EP0 setup stage desc chain DMA address
901 * @setup_desc: EP0 setup stage desc chain pointer
902 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
903 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
904 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
905 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
906 * @eps: The endpoints being supplied to the gadget framework
911 /** Params detected from hardware */
912 struct dwc2_hw_params hw_params;
913 /** Params to actually use */
914 struct dwc2_core_params params;
915 enum usb_otg_state op_state;
916 enum usb_dr_mode dr_mode;
917 unsigned int hcd_enabled:1;
918 unsigned int gadget_enabled:1;
919 unsigned int ll_hw_enabled:1;
922 struct usb_phy *uphy;
923 struct dwc2_hsotg_plat *plat;
924 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
931 struct reset_control *reset;
933 unsigned int queuing_high_bandwidth:1;
934 unsigned int srp_success:1;
936 struct workqueue_struct *wq_otg;
937 struct work_struct wf_otg;
938 struct timer_list wkp_timer;
939 enum dwc2_lx_state lx_state;
940 struct dwc2_gregs_backup gr_backup;
941 struct dwc2_dregs_backup dr_backup;
942 struct dwc2_hregs_backup hr_backup;
944 struct dentry *debug_root;
945 struct debugfs_regset32 *regset;
947 /* DWC OTG HW Release versions */
948 #define DWC2_CORE_REV_2_71a 0x4f54271a
949 #define DWC2_CORE_REV_2_90a 0x4f54290a
950 #define DWC2_CORE_REV_2_92a 0x4f54292a
951 #define DWC2_CORE_REV_2_94a 0x4f54294a
952 #define DWC2_CORE_REV_3_00a 0x4f54300a
953 #define DWC2_CORE_REV_3_10a 0x4f54310a
954 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
955 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
957 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
958 union dwc2_hcd_internal_flags {
961 unsigned port_connect_status_change:1;
962 unsigned port_connect_status:1;
963 unsigned port_reset_change:1;
964 unsigned port_enable_change:1;
965 unsigned port_suspend_change:1;
966 unsigned port_over_current_change:1;
967 unsigned port_l1_change:1;
968 unsigned reserved:25;
972 struct list_head non_periodic_sched_inactive;
973 struct list_head non_periodic_sched_active;
974 struct list_head *non_periodic_qh_ptr;
975 struct list_head periodic_sched_inactive;
976 struct list_head periodic_sched_ready;
977 struct list_head periodic_sched_assigned;
978 struct list_head periodic_sched_queued;
979 struct list_head split_order;
981 unsigned long hs_periodic_bitmap[
982 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
984 u16 periodic_qh_count;
990 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
991 #define FRAME_NUM_ARRAY_SIZE 1000
992 u16 *frame_num_array;
993 u16 *last_frame_num_array;
995 int dumped_frame_num_array;
998 struct list_head free_hc_list;
999 int periodic_channels;
1000 int non_periodic_channels;
1001 int available_host_channels;
1002 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1004 dma_addr_t status_buf_dma;
1005 #define DWC2_HCD_STATUS_BUF_SIZE 64
1007 struct delayed_work start_work;
1008 struct delayed_work reset_work;
1011 dma_addr_t frame_list_dma;
1013 struct kmem_cache *desc_gen_cache;
1014 struct kmem_cache *desc_hsisoc_cache;
1020 u32 hfnum_7_samples_a;
1021 u64 hfnum_7_frrem_accum_a;
1022 u32 hfnum_0_samples_a;
1023 u64 hfnum_0_frrem_accum_a;
1024 u32 hfnum_other_samples_a;
1025 u64 hfnum_other_frrem_accum_a;
1027 u32 hfnum_7_samples_b;
1028 u64 hfnum_7_frrem_accum_b;
1029 u32 hfnum_0_samples_b;
1030 u64 hfnum_0_frrem_accum_b;
1031 u32 hfnum_other_samples_b;
1032 u64 hfnum_other_frrem_accum_b;
1034 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1036 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1037 /* Gadget structures */
1038 struct usb_gadget_driver *driver;
1040 unsigned int dedicated_fifos:1;
1041 unsigned char num_of_eps;
1044 struct usb_request *ep0_reply;
1045 struct usb_request *ctrl_req;
1048 enum dwc2_ep0_state ep0_state;
1051 dma_addr_t setup_desc_dma[2];
1052 struct dwc2_dma_desc *setup_desc[2];
1053 dma_addr_t ctrl_in_desc_dma;
1054 struct dwc2_dma_desc *ctrl_in_desc;
1055 dma_addr_t ctrl_out_desc_dma;
1056 struct dwc2_dma_desc *ctrl_out_desc;
1058 struct usb_gadget gadget;
1059 unsigned int enabled:1;
1060 unsigned int connected:1;
1061 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1062 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1063 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1066 /* Reasons for halting a host channel */
1067 enum dwc2_halt_status {
1068 DWC2_HC_XFER_NO_HALT_STATUS,
1069 DWC2_HC_XFER_COMPLETE,
1070 DWC2_HC_XFER_URB_COMPLETE,
1075 DWC2_HC_XFER_XACT_ERR,
1076 DWC2_HC_XFER_FRAME_OVERRUN,
1077 DWC2_HC_XFER_BABBLE_ERR,
1078 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1079 DWC2_HC_XFER_AHB_ERR,
1080 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1081 DWC2_HC_XFER_URB_DEQUEUE,
1084 /* Core version information */
1085 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1087 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1090 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1092 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1095 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1097 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1101 * The following functions support initialization of the core driver component
1102 * and the DWC_otg controller
1104 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
1105 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1106 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1107 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
1109 bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1110 void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
1111 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1113 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1116 * Common core Functions.
1117 * The following functions support managing the DWC_otg controller in either
1118 * device or host mode.
1120 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1121 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1122 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1124 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1125 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1127 /* This function should be called on every hardware interrupt. */
1128 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1130 /* The device ID match table */
1131 extern const struct of_device_id dwc2_of_match_table[];
1133 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1134 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1137 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1138 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1141 * The following functions check the controller's OTG operation mode
1142 * capability (GHWCFG2.OTG_MODE).
1144 * These functions can be used before the internal hsotg->hw_params
1145 * are read in and cached so they always read directly from the
1148 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1149 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1150 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1151 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1154 * Returns the mode of operation, host or device
1156 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1158 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1160 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1162 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1166 * Dump core registers and SPRAM
1168 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1169 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1170 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1173 * Return OTG version - either 1.3 or 2.0
1175 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1177 /* Gadget defines */
1178 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1179 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1180 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1181 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1182 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1183 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1185 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1186 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1187 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1188 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1189 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1190 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
1192 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1194 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1196 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1198 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1200 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1202 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1203 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1204 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1207 #define dwc2_is_device_connected(hsotg) (0)
1208 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1210 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1214 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1215 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1216 extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1217 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1218 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1219 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1220 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1221 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1223 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1225 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1228 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1229 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1230 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1231 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1232 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
1234 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1236 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1241 #endif /* __DWC2_CORE_H__ */