2 * core.h - DesignWare HS OTG Controller common declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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37 #ifndef __DWC2_CORE_H__
38 #define __DWC2_CORE_H__
40 #include <linux/phy/phy.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/usb/gadget.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/phy.h>
47 static inline u32 dwc2_readl(const void __iomem *addr)
49 u32 value = __raw_readl(addr);
51 /* In order to preserve endianness __raw_* operation is used. Therefore
52 * a barrier is needed to ensure IO access is not re-ordered across
59 static inline void dwc2_writel(u32 value, void __iomem *addr)
61 __raw_writel(value, addr);
64 * In order to preserve endianness __raw_* operation is used. Therefore
65 * a barrier is needed to ensure IO access is not re-ordered across
69 #ifdef DWC2_LOG_WRITES
70 pr_info("INFO:: wrote %08x to %p\n", value, addr);
74 /* Maximum number of Endpoints/HostChannels */
75 #define MAX_EPS_CHANNELS 16
77 /* dwc2-hsotg declarations */
78 static const char * const dwc2_hsotg_supply_names[] = {
79 "vusb_d", /* digital USB supply, 1.2V */
80 "vusb_a", /* analog USB supply, 1.1V */
86 * Unfortunately there seems to be a limit of the amount of data that can
87 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
88 * packets (which practically means 1 packet and 63 bytes of data) when the
91 * This means if we are wanting to move >127 bytes of data, we need to
92 * split the transactions up, but just doing one packet at a time does
93 * not work (this may be an implicit DATA0 PID on first packet of the
94 * transaction) and doing 2 packets is outside the controller's limits.
96 * If we try to lower the MPS size for EP0, then no transfers work properly
97 * for EP0, and the system will fail basic enumeration. As no cause for this
98 * has currently been found, we cannot support any large IN transfers for
101 #define EP0_MPS_LIMIT 64
104 struct dwc2_hsotg_req;
107 * struct dwc2_hsotg_ep - driver endpoint definition.
108 * @ep: The gadget layer representation of the endpoint.
109 * @name: The driver generated name for the endpoint.
110 * @queue: Queue of requests for this endpoint.
111 * @parent: Reference back to the parent device structure.
112 * @req: The current request that the endpoint is processing. This is
113 * used to indicate an request has been loaded onto the endpoint
114 * and has yet to be completed (maybe due to data move, or simply
115 * awaiting an ack from the core all the data has been completed).
116 * @debugfs: File entry for debugfs file for this endpoint.
117 * @lock: State lock to protect contents of endpoint.
118 * @dir_in: Set to true if this endpoint is of the IN direction, which
119 * means that it is sending data to the Host.
120 * @index: The index for the endpoint registers.
121 * @mc: Multi Count - number of transactions per microframe
122 * @interval - Interval for periodic endpoints
123 * @name: The name array passed to the USB core.
124 * @halted: Set if the endpoint has been halted.
125 * @periodic: Set if this is a periodic ep, such as Interrupt
126 * @isochronous: Set if this is a isochronous ep
127 * @send_zlp: Set if we need to send a zero-length packet.
128 * @total_data: The total number of data bytes done.
129 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
130 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
131 * @last_load: The offset of data for the last start of request.
132 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
134 * This is the driver's state for each registered enpoint, allowing it
135 * to keep track of transactions that need doing. Each endpoint has a
136 * lock to protect the state, to try and avoid using an overall lock
137 * for the host controller as much as possible.
139 * For periodic IN endpoints, we have fifo_size and fifo_load to try
140 * and keep track of the amount of data in the periodic FIFO for each
141 * of these as we don't have a status register that tells us how much
142 * is in each of them. (note, this may actually be useless information
143 * as in shared-fifo mode periodic in acts like a single-frame packet
144 * buffer than a fifo)
146 struct dwc2_hsotg_ep {
148 struct list_head queue;
149 struct dwc2_hsotg *parent;
150 struct dwc2_hsotg_req *req;
151 struct dentry *debugfs;
153 unsigned long total_data;
154 unsigned int size_loaded;
155 unsigned int last_load;
156 unsigned int fifo_load;
157 unsigned short fifo_size;
158 unsigned short fifo_index;
160 unsigned char dir_in;
163 unsigned char interval;
165 unsigned int halted:1;
166 unsigned int periodic:1;
167 unsigned int isochronous:1;
168 unsigned int send_zlp:1;
169 unsigned int has_correct_parity:1;
175 * struct dwc2_hsotg_req - data transfer request
176 * @req: The USB gadget request
177 * @queue: The list of requests for the endpoint this is queued for.
178 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
180 struct dwc2_hsotg_req {
181 struct usb_request req;
182 struct list_head queue;
186 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
187 #define call_gadget(_hs, _entry) \
189 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
190 (_hs)->driver && (_hs)->driver->_entry) { \
191 spin_unlock(&_hs->lock); \
192 (_hs)->driver->_entry(&(_hs)->gadget); \
193 spin_lock(&_hs->lock); \
197 #define call_gadget(_hs, _entry) do {} while (0)
201 struct dwc2_host_chan;
205 DWC2_L0, /* On state */
206 DWC2_L1, /* LPM sleep state */
207 DWC2_L2, /* USB suspend state */
208 DWC2_L3, /* Off state */
212 * Gadget periodic tx fifo sizes as used by legacy driver
213 * EP0 is not included
215 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
216 768, 0, 0, 0, 0, 0, 0, 0}
218 /* Gadget ep0 states */
219 enum dwc2_ep0_state {
228 * struct dwc2_core_params - Parameters for configuring the core
230 * @otg_cap: Specifies the OTG capabilities.
231 * 0 - HNP and SRP capable
232 * 1 - SRP Only capable
233 * 2 - No HNP/SRP capable (always available)
234 * Defaults to best available option (0, 1, then 2)
235 * @otg_ver: OTG version supported
238 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
239 * the data FIFOs. The driver will automatically detect the
240 * value for this parameter if none is specified.
241 * 0 - Slave (always available)
242 * 1 - DMA (default, if available)
243 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
244 * address DMA mode or descriptor DMA mode for accessing
245 * the data FIFOs. The driver will automatically detect the
246 * value for this if none is specified.
248 * 1 - Descriptor DMA (default, if available)
249 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
250 * address DMA mode or descriptor DMA mode for accessing
251 * the data FIFOs in Full Speed mode only. The driver
252 * will automatically detect the value for this if none is
255 * 1 - Descriptor DMA in FS (default, if available)
256 * @speed: Specifies the maximum speed of operation in host and
257 * device mode. The actual speed depends on the speed of
258 * the attached device and the value of phy_type.
260 * (default when phy_type is UTMI+ or ULPI)
262 * (default when phy_type is Full Speed)
263 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
264 * 1 - Allow dynamic FIFO sizing (default, if available)
265 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
267 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
268 * dynamic FIFO sizing is enabled
270 * Actual maximum value is autodetected and also
272 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
273 * in host mode when dynamic FIFO sizing is enabled
275 * Actual maximum value is autodetected and also
277 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
278 * host mode when dynamic FIFO sizing is enabled
280 * Actual maximum value is autodetected and also
282 * @max_transfer_size: The maximum transfer size supported, in bytes
284 * Actual maximum value is autodetected and also
286 * @max_packet_count: The maximum number of packets in a transfer
288 * Actual maximum value is autodetected and also
290 * @host_channels: The number of host channel registers to use
292 * Actual maximum value is autodetected and also
294 * @phy_type: Specifies the type of PHY interface to use. By default,
295 * the driver will automatically detect the phy_type.
299 * Defaults to best available option (2, 1, then 0)
300 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
301 * is applicable for a phy_type of UTMI+ or ULPI. (For a
302 * ULPI phy_type, this parameter indicates the data width
303 * between the MAC and the ULPI Wrapper.) Also, this
304 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
305 * parameter was set to "8 and 16 bits", meaning that the
306 * core has been configured to work at either data path
308 * 8 or 16 (default 16 if available)
309 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
310 * data rate. This parameter is only applicable if phy_type
312 * 0 - single data rate ULPI interface with 8 bit wide
314 * 1 - double data rate ULPI interface with 4 bit wide
316 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
317 * external supply to drive the VBus
318 * 0 - Internal supply (default)
319 * 1 - External supply
320 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
321 * speed PHY. This parameter is only applicable if phy_type
325 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
328 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
329 * when attached to a Full Speed or Low Speed device in
331 * 0 - Don't support low power mode (default)
332 * 1 - Support low power mode
333 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
334 * when connected to a Low Speed device in host
335 * mode. This parameter is applicable only if
336 * host_support_fs_ls_low_power is enabled.
338 * (default when phy_type is UTMI+ or ULPI)
340 * (default when phy_type is Full Speed)
341 * @ts_dline: Enable Term Select Dline pulsing
344 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
345 * 0 - No (default for core < 2.92a)
346 * 1 - Yes (default for core >= 2.92a)
347 * @ahbcfg: This field allows the default value of the GAHBCFG
348 * register to be overridden
349 * -1 - GAHBCFG value will be set to 0x06
351 * all others - GAHBCFG value will be overridden with
353 * Not all bits can be controlled like this, the
354 * bits defined by GAHBCFG_CTRL_MASK are controlled
355 * by the driver and are ignored in this
356 * configuration value.
357 * @uframe_sched: True to enable the microframe scheduler
358 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
359 * Disable CONIDSTSCHNG controller interrupt in such
363 * @hibernation: Specifies whether the controller support hibernation.
364 * If hibernation is enabled, the controller will enter
365 * hibernation in both peripheral and host mode when
370 * The following parameters may be specified when starting the module. These
371 * parameters define how the DWC_otg controller should be configured. A
372 * value of -1 (or any other out of range value) for any parameter means
373 * to read the value from hardware (if possible) or use the builtin
374 * default described above.
376 struct dwc2_core_params {
378 * Don't add any non-int members here, this will break
379 * dwc2_set_all_params!
385 int dma_desc_fs_enable;
387 int enable_dynamic_fifo;
388 int en_multiple_tx_fifo;
389 int host_rx_fifo_size;
390 int host_nperio_tx_fifo_size;
391 int host_perio_tx_fifo_size;
392 int max_transfer_size;
393 int max_packet_count;
398 int phy_ulpi_ext_vbus;
401 int host_support_fs_ls_low_power;
402 int host_ls_low_power_phy_clk;
407 int external_id_pin_ctl;
412 * struct dwc2_hw_params - Autodetected parameters.
414 * These parameters are the various parameters read from hardware
415 * registers during initialization. They typically contain the best
416 * supported or maximum value that can be configured in the
417 * corresponding dwc2_core_params value.
419 * The values that are not in dwc2_core_params are documented below.
421 * @op_mode Mode of Operation
422 * 0 - HNP- and SRP-Capable OTG (Host & Device)
423 * 1 - SRP-Capable OTG (Host & Device)
424 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
425 * 3 - SRP-Capable Device
427 * 5 - SRP-Capable Host
433 * @power_optimized Are power optimizations enabled?
434 * @num_dev_ep Number of device endpoints available
435 * @num_dev_perio_in_ep Number of device periodic IN endpoints
437 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
440 * @host_perio_tx_q_depth
441 * Host Mode Periodic Request Queue Depth
444 * Non-Periodic Request Queue Depth
446 * @hs_phy_type High-speed PHY interface type
447 * 0 - High-speed interface not supported
451 * @fs_phy_type Full-speed PHY interface type
452 * 0 - Full speed interface not supported
453 * 1 - Dedicated full speed interface
454 * 2 - FS pins shared with UTMI+ pins
455 * 3 - FS pins shared with ULPI pins
456 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
457 * @utmi_phy_data_width UTMI+ PHY data width
461 * @snpsid: Value from SNPSID register
462 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
464 struct dwc2_hw_params {
467 unsigned dma_desc_enable:1;
468 unsigned dma_desc_fs_enable:1;
469 unsigned enable_dynamic_fifo:1;
470 unsigned en_multiple_tx_fifo:1;
471 unsigned host_rx_fifo_size:16;
472 unsigned host_nperio_tx_fifo_size:16;
473 unsigned dev_nperio_tx_fifo_size:16;
474 unsigned host_perio_tx_fifo_size:16;
475 unsigned nperio_tx_q_depth:3;
476 unsigned host_perio_tx_q_depth:3;
477 unsigned dev_token_q_depth:5;
478 unsigned max_transfer_size:26;
479 unsigned max_packet_count:11;
480 unsigned host_channels:5;
481 unsigned hs_phy_type:2;
482 unsigned fs_phy_type:2;
483 unsigned i2c_enable:1;
484 unsigned num_dev_ep:4;
485 unsigned num_dev_perio_in_ep:4;
486 unsigned total_fifo_size:16;
487 unsigned power_optimized:1;
488 unsigned utmi_phy_data_width:2;
493 /* Size of control and EP0 buffers */
494 #define DWC2_CTRL_BUFF_SIZE 8
497 * struct dwc2_gregs_backup - Holds global registers state before entering partial
499 * @gotgctl: Backup of GOTGCTL register
500 * @gintmsk: Backup of GINTMSK register
501 * @gahbcfg: Backup of GAHBCFG register
502 * @gusbcfg: Backup of GUSBCFG register
503 * @grxfsiz: Backup of GRXFSIZ register
504 * @gnptxfsiz: Backup of GNPTXFSIZ register
505 * @gi2cctl: Backup of GI2CCTL register
506 * @hptxfsiz: Backup of HPTXFSIZ register
507 * @gdfifocfg: Backup of GDFIFOCFG register
508 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
509 * @gpwrdn: Backup of GPWRDN register
511 struct dwc2_gregs_backup {
522 u32 dtxfsiz[MAX_EPS_CHANNELS];
528 * struct dwc2_dregs_backup - Holds device registers state before entering partial
530 * @dcfg: Backup of DCFG register
531 * @dctl: Backup of DCTL register
532 * @daintmsk: Backup of DAINTMSK register
533 * @diepmsk: Backup of DIEPMSK register
534 * @doepmsk: Backup of DOEPMSK register
535 * @diepctl: Backup of DIEPCTL register
536 * @dieptsiz: Backup of DIEPTSIZ register
537 * @diepdma: Backup of DIEPDMA register
538 * @doepctl: Backup of DOEPCTL register
539 * @doeptsiz: Backup of DOEPTSIZ register
540 * @doepdma: Backup of DOEPDMA register
542 struct dwc2_dregs_backup {
548 u32 diepctl[MAX_EPS_CHANNELS];
549 u32 dieptsiz[MAX_EPS_CHANNELS];
550 u32 diepdma[MAX_EPS_CHANNELS];
551 u32 doepctl[MAX_EPS_CHANNELS];
552 u32 doeptsiz[MAX_EPS_CHANNELS];
553 u32 doepdma[MAX_EPS_CHANNELS];
558 * struct dwc2_hregs_backup - Holds host registers state before entering partial
560 * @hcfg: Backup of HCFG register
561 * @haintmsk: Backup of HAINTMSK register
562 * @hcintmsk: Backup of HCINTMSK register
563 * @hptr0: Backup of HPTR0 register
564 * @hfir: Backup of HFIR register
566 struct dwc2_hregs_backup {
569 u32 hcintmsk[MAX_EPS_CHANNELS];
576 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
577 * and periodic schedules
579 * These are common for both host and peripheral modes:
581 * @dev: The struct device pointer
582 * @regs: Pointer to controller regs
583 * @hw_params: Parameters that were autodetected from the
585 * @core_params: Parameters that define how the core should be configured
586 * @op_state: The operational State, during transitions (a_host=>
587 * a_peripheral and b_device=>b_host) this may not match
588 * the core, but allows the software to determine
590 * @dr_mode: Requested mode of operation, one of following:
591 * - USB_DR_MODE_PERIPHERAL
594 * @hcd_enabled Host mode sub-driver initialization indicator.
595 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
596 * @ll_hw_enabled Status of low-level hardware resources.
597 * @phy: The otg phy transceiver structure for phy control.
598 * @uphy: The otg phy transceiver structure for old USB phy control.
599 * @plat: The platform specific configuration data. This can be removed once
600 * all SoCs support usb transceiver.
601 * @supplies: Definition of USB power supplies
602 * @phyif: PHY interface width
603 * @lock: Spinlock that protects all the driver data structures
604 * @priv: Stores a pointer to the struct usb_hcd
605 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
606 * transfer are in process of being queued
607 * @srp_success: Stores status of SRP request in the case of a FS PHY
608 * with an I2C interface
609 * @wq_otg: Workqueue object used for handling of some interrupts
610 * @wf_otg: Work object for handling Connector ID Status Change
612 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
613 * @lx_state: Lx state of connected device
614 * @gregs_backup: Backup of global registers during suspend
615 * @dregs_backup: Backup of device registers during suspend
616 * @hregs_backup: Backup of host registers during suspend
618 * These are for host mode:
620 * @flags: Flags for handling root port state changes
621 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
622 * Transfers associated with these QHs are not currently
623 * assigned to a host channel.
624 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
625 * Transfers associated with these QHs are currently
626 * assigned to a host channel.
627 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
628 * non-periodic schedule
629 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
630 * list of QHs for periodic transfers that are _not_
631 * scheduled for the next frame. Each QH in the list has an
632 * interval counter that determines when it needs to be
633 * scheduled for execution. This scheduling mechanism
634 * allows only a simple calculation for periodic bandwidth
635 * used (i.e. must assume that all periodic transfers may
636 * need to execute in the same frame). However, it greatly
637 * simplifies scheduling and should be sufficient for the
638 * vast majority of OTG hosts, which need to connect to a
639 * small number of peripherals at one time. Items move from
640 * this list to periodic_sched_ready when the QH interval
641 * counter is 0 at SOF.
642 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
643 * the next frame, but have not yet been assigned to host
644 * channels. Items move from this list to
645 * periodic_sched_assigned as host channels become
646 * available during the current frame.
647 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
648 * frame that are assigned to host channels. Items move
649 * from this list to periodic_sched_queued as the
650 * transactions for the QH are queued to the DWC_otg
652 * @periodic_sched_queued: List of periodic QHs that have been queued for
653 * execution. Items move from this list to either
654 * periodic_sched_inactive or periodic_sched_ready when the
655 * channel associated with the transfer is released. If the
656 * interval for the QH is 1, the item moves to
657 * periodic_sched_ready because it must be rescheduled for
658 * the next frame. Otherwise, the item moves to
659 * periodic_sched_inactive.
660 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
661 * This value is in microseconds per (micro)frame. The
662 * assumption is that all periodic transfers may occur in
663 * the same (micro)frame.
664 * @frame_usecs: Internal variable used by the microframe scheduler
665 * @frame_number: Frame number read from the core at SOF. The value ranges
666 * from 0 to HFNUM_MAX_FRNUM.
667 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
668 * SOF enable/disable.
669 * @free_hc_list: Free host channels in the controller. This is a list of
670 * struct dwc2_host_chan items.
671 * @periodic_channels: Number of host channels assigned to periodic transfers.
672 * Currently assuming that there is a dedicated host
673 * channel for each periodic transaction and at least one
674 * host channel is available for non-periodic transactions.
675 * @non_periodic_channels: Number of host channels assigned to non-periodic
677 * @available_host_channels Number of host channels available for the microframe
679 * @hc_ptr_array: Array of pointers to the host channel descriptors.
680 * Allows accessing a host channel descriptor given the
681 * host channel number. This is useful in interrupt
683 * @status_buf: Buffer used for data received during the status phase of
684 * a control transfer.
685 * @status_buf_dma: DMA address for status_buf
686 * @start_work: Delayed work for handling host A-cable connection
687 * @reset_work: Delayed work for handling a port reset
688 * @otg_port: OTG port number
689 * @frame_list: Frame list
690 * @frame_list_dma: Frame list DMA address
691 * @frame_list_sz: Frame list size
692 * @desc_gen_cache: Kmem cache for generic descriptors
693 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
695 * These are for peripheral mode:
697 * @driver: USB gadget driver
698 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
699 * @num_of_eps: Number of available EPs (excluding EP0)
700 * @debug_root: Root directrory for debugfs.
701 * @debug_file: Main status file for debugfs.
702 * @debug_testmode: Testmode status file for debugfs.
703 * @debug_fifo: FIFO status file for debugfs.
704 * @ep0_reply: Request used for ep0 reply.
705 * @ep0_buff: Buffer for EP0 reply data, if needed.
706 * @ctrl_buff: Buffer for EP0 control requests.
707 * @ctrl_req: Request for EP0 control packets.
708 * @ep0_state: EP0 control transfers state
709 * @test_mode: USB test mode requested by the host
710 * @eps: The endpoints being supplied to the gadget framework
711 * @g_using_dma: Indicate if dma usage is enabled
712 * @g_rx_fifo_sz: Contains rx fifo size value
713 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
714 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
719 /** Params detected from hardware */
720 struct dwc2_hw_params hw_params;
721 /** Params to actually use */
722 struct dwc2_core_params *core_params;
723 enum usb_otg_state op_state;
724 enum usb_dr_mode dr_mode;
725 unsigned int hcd_enabled:1;
726 unsigned int gadget_enabled:1;
727 unsigned int ll_hw_enabled:1;
730 struct usb_phy *uphy;
731 struct dwc2_hsotg_plat *plat;
732 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
740 unsigned int queuing_high_bandwidth:1;
741 unsigned int srp_success:1;
743 struct workqueue_struct *wq_otg;
744 struct work_struct wf_otg;
745 struct timer_list wkp_timer;
746 enum dwc2_lx_state lx_state;
747 struct dwc2_gregs_backup gr_backup;
748 struct dwc2_dregs_backup dr_backup;
749 struct dwc2_hregs_backup hr_backup;
751 struct dentry *debug_root;
752 struct debugfs_regset32 *regset;
754 /* DWC OTG HW Release versions */
755 #define DWC2_CORE_REV_2_71a 0x4f54271a
756 #define DWC2_CORE_REV_2_90a 0x4f54290a
757 #define DWC2_CORE_REV_2_92a 0x4f54292a
758 #define DWC2_CORE_REV_2_94a 0x4f54294a
759 #define DWC2_CORE_REV_3_00a 0x4f54300a
761 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
762 union dwc2_hcd_internal_flags {
765 unsigned port_connect_status_change:1;
766 unsigned port_connect_status:1;
767 unsigned port_reset_change:1;
768 unsigned port_enable_change:1;
769 unsigned port_suspend_change:1;
770 unsigned port_over_current_change:1;
771 unsigned port_l1_change:1;
772 unsigned reserved:25;
776 struct list_head non_periodic_sched_inactive;
777 struct list_head non_periodic_sched_active;
778 struct list_head *non_periodic_qh_ptr;
779 struct list_head periodic_sched_inactive;
780 struct list_head periodic_sched_ready;
781 struct list_head periodic_sched_assigned;
782 struct list_head periodic_sched_queued;
786 u16 periodic_qh_count;
790 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
791 #define FRAME_NUM_ARRAY_SIZE 1000
793 u16 *frame_num_array;
794 u16 *last_frame_num_array;
796 int dumped_frame_num_array;
799 struct list_head free_hc_list;
800 int periodic_channels;
801 int non_periodic_channels;
802 int available_host_channels;
803 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
805 dma_addr_t status_buf_dma;
806 #define DWC2_HCD_STATUS_BUF_SIZE 64
808 struct delayed_work start_work;
809 struct delayed_work reset_work;
812 dma_addr_t frame_list_dma;
814 struct kmem_cache *desc_gen_cache;
815 struct kmem_cache *desc_hsisoc_cache;
821 u32 hfnum_7_samples_a;
822 u64 hfnum_7_frrem_accum_a;
823 u32 hfnum_0_samples_a;
824 u64 hfnum_0_frrem_accum_a;
825 u32 hfnum_other_samples_a;
826 u64 hfnum_other_frrem_accum_a;
828 u32 hfnum_7_samples_b;
829 u64 hfnum_7_frrem_accum_b;
830 u32 hfnum_0_samples_b;
831 u64 hfnum_0_frrem_accum_b;
832 u32 hfnum_other_samples_b;
833 u64 hfnum_other_frrem_accum_b;
835 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
837 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
838 /* Gadget structures */
839 struct usb_gadget_driver *driver;
841 unsigned int dedicated_fifos:1;
842 unsigned char num_of_eps;
845 struct usb_request *ep0_reply;
846 struct usb_request *ctrl_req;
849 enum dwc2_ep0_state ep0_state;
852 struct usb_gadget gadget;
853 unsigned int enabled:1;
854 unsigned int connected:1;
855 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
856 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
859 u32 g_np_g_tx_fifo_sz;
860 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
861 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
864 /* Reasons for halting a host channel */
865 enum dwc2_halt_status {
866 DWC2_HC_XFER_NO_HALT_STATUS,
867 DWC2_HC_XFER_COMPLETE,
868 DWC2_HC_XFER_URB_COMPLETE,
873 DWC2_HC_XFER_XACT_ERR,
874 DWC2_HC_XFER_FRAME_OVERRUN,
875 DWC2_HC_XFER_BABBLE_ERR,
876 DWC2_HC_XFER_DATA_TOGGLE_ERR,
877 DWC2_HC_XFER_AHB_ERR,
878 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
879 DWC2_HC_XFER_URB_DEQUEUE,
883 * The following functions support initialization of the core driver component
884 * and the DWC_otg controller
886 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
887 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
888 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
889 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
890 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
892 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
895 * Host core Functions.
896 * The following functions support managing the DWC_otg controller in host
899 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
900 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
901 enum dwc2_halt_status halt_status);
902 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
903 struct dwc2_host_chan *chan);
904 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
905 struct dwc2_host_chan *chan);
906 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
907 struct dwc2_host_chan *chan);
908 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
909 struct dwc2_host_chan *chan);
910 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
911 struct dwc2_host_chan *chan);
912 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
913 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
915 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
916 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
919 * Common core Functions.
920 * The following functions support managing the DWC_otg controller in either
921 * device or host mode.
923 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
924 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
925 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
927 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
928 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
929 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
931 /* This function should be called on every hardware interrupt. */
932 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
934 /* OTG Core Parameters */
937 * Specifies the OTG capabilities. The driver will automatically
938 * detect the value for this parameter if none is specified.
939 * 0 - HNP and SRP capable (default)
940 * 1 - SRP Only capable
941 * 2 - No HNP/SRP capable
943 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
944 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
945 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
946 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
949 * Specifies whether to use slave or DMA mode for accessing the data
950 * FIFOs. The driver will automatically detect the value for this
951 * parameter if none is specified.
953 * 1 - DMA (default, if available)
955 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
958 * When DMA mode is enabled specifies whether to use
959 * address DMA or DMA Descritor mode for accessing the data
960 * FIFOs in device mode. The driver will automatically detect
961 * the value for this parameter if none is specified.
963 * 1 - DMA Descriptor(default, if available)
965 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
968 * When DMA mode is enabled specifies whether to use
969 * address DMA or DMA Descritor mode with full speed devices
970 * for accessing the data FIFOs in host mode.
972 * 1 - FS DMA Descriptor(default, if available)
974 extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg,
978 * Specifies the maximum speed of operation in host and device mode.
979 * The actual speed depends on the speed of the attached device and
980 * the value of phy_type. The actual speed depends on the speed of the
982 * 0 - High Speed (default)
985 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
986 #define DWC2_SPEED_PARAM_HIGH 0
987 #define DWC2_SPEED_PARAM_FULL 1
990 * Specifies whether low power mode is supported when attached
991 * to a Full Speed or Low Speed device in host mode.
993 * 0 - Don't support low power mode (default)
994 * 1 - Support low power mode
996 extern void dwc2_set_param_host_support_fs_ls_low_power(
997 struct dwc2_hsotg *hsotg, int val);
1000 * Specifies the PHY clock rate in low power mode when connected to a
1001 * Low Speed device in host mode. This parameter is applicable only if
1002 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
1003 * then defaults to 6 MHZ otherwise 48 MHZ.
1008 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
1010 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
1011 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
1014 * 0 - Use cC FIFO size parameters
1015 * 1 - Allow dynamic FIFO sizing (default)
1017 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
1021 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
1022 * FIFO sizing is enabled.
1023 * 16 to 32768 (default 1024)
1025 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
1028 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
1029 * when Dynamic FIFO sizing is enabled in the core.
1030 * 16 to 32768 (default 256)
1032 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1036 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
1037 * FIFO sizing is enabled.
1038 * 16 to 32768 (default 256)
1040 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1044 * The maximum transfer size supported in bytes.
1045 * 2047 to 65,535 (default 65,535)
1047 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
1050 * The maximum number of packets in a transfer.
1051 * 15 to 511 (default 511)
1053 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
1056 * The number of host channel registers to use.
1057 * 1 to 16 (default 11)
1058 * Note: The FPGA configuration supports a maximum of 11 host channels.
1060 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
1063 * Specifies the type of PHY interface to use. By default, the driver
1064 * will automatically detect the phy_type.
1066 * 0 - Full Speed PHY
1067 * 1 - UTMI+ (default)
1070 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
1071 #define DWC2_PHY_TYPE_PARAM_FS 0
1072 #define DWC2_PHY_TYPE_PARAM_UTMI 1
1073 #define DWC2_PHY_TYPE_PARAM_ULPI 2
1076 * Specifies the UTMI+ Data Width. This parameter is
1077 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
1078 * PHY_TYPE, this parameter indicates the data width between
1079 * the MAC and the ULPI Wrapper.) Also, this parameter is
1080 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
1081 * to "8 and 16 bits", meaning that the core has been
1082 * configured to work at either data path width.
1084 * 8 or 16 bits (default 16)
1086 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
1089 * Specifies whether the ULPI operates at double or single
1090 * data rate. This parameter is only applicable if PHY_TYPE is
1093 * 0 - single data rate ULPI interface with 8 bit wide data
1095 * 1 - double data rate ULPI interface with 4 bit wide data
1098 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
1101 * Specifies whether to use the internal or external supply to
1102 * drive the vbus with a ULPI phy.
1104 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
1105 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0
1106 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
1109 * Specifies whether to use the I2Cinterface for full speed PHY. This
1110 * parameter is only applicable if PHY_TYPE is FS.
1114 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
1116 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
1118 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
1121 * Specifies whether dedicated transmit FIFOs are
1122 * enabled for non periodic IN endpoints in device mode
1126 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
1129 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
1131 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
1133 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
1135 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1136 const struct dwc2_core_params *params);
1138 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
1140 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1142 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1143 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1146 * The following functions check the controller's OTG operation mode
1147 * capability (GHWCFG2.OTG_MODE).
1149 * These functions can be used before the internal hsotg->hw_params
1150 * are read in and cached so they always read directly from the
1153 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1154 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1155 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1156 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1159 * Returns the mode of operation, host or device
1161 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1163 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1165 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1167 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1171 * Dump core registers and SPRAM
1173 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1174 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1175 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1178 * Return OTG version - either 1.3 or 2.0
1180 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1182 /* Gadget defines */
1183 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1184 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1185 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1186 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1187 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1188 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1190 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1191 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1192 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1193 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1195 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1197 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1199 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1201 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1203 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1205 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1206 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1207 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1210 #define dwc2_is_device_connected(hsotg) (0)
1213 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1214 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1215 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1216 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1217 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1219 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1221 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1222 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1223 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1224 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1225 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
1229 #endif /* __DWC2_CORE_H__ */