2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
40 return container_of(req, struct dwc2_hsotg_req, req);
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
50 return container_of(gadget, struct dwc2_hsotg, gadget);
53 static inline void __orr32(void __iomem *ptr, u32 val)
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
58 static inline void __bic32(void __iomem *ptr, u32 val)
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
67 return hsotg->eps_in[ep_index];
69 return hsotg->eps_out[ep_index];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
96 return hsotg->params.g_dma;
100 * using_desc_dma - return the descriptor DMA status of the driver.
101 * @hsotg: The driver state.
103 * Return true if we're using descriptor DMA.
105 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
107 return hsotg->params.g_dma_desc;
111 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
112 * @hs_ep: The endpoint
113 * @increment: The value to increment by
115 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
116 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
118 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
120 hs_ep->target_frame += hs_ep->interval;
121 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
122 hs_ep->frame_overrun = 1;
123 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
125 hs_ep->frame_overrun = 0;
130 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
131 * @hsotg: The device state
132 * @ints: A bitmask of the interrupts to enable
134 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
136 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
139 new_gsintmsk = gsintmsk | ints;
141 if (new_gsintmsk != gsintmsk) {
142 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
143 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
148 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
149 * @hsotg: The device state
150 * @ints: A bitmask of the interrupts to enable
152 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
154 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
157 new_gsintmsk = gsintmsk & ~ints;
159 if (new_gsintmsk != gsintmsk)
160 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
164 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
165 * @hsotg: The device state
166 * @ep: The endpoint index
167 * @dir_in: True if direction is in.
168 * @en: The enable value, true to enable
170 * Set or clear the mask for an individual endpoint's interrupt
173 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
174 unsigned int ep, unsigned int dir_in,
184 local_irq_save(flags);
185 daint = dwc2_readl(hsotg->regs + DAINTMSK);
190 dwc2_writel(daint, hsotg->regs + DAINTMSK);
191 local_irq_restore(flags);
195 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
196 * @hsotg: The device instance.
198 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
204 u32 *txfsz = hsotg->params.g_tx_fifo_size;
206 /* Reset fifo map if not correctly cleared during previous session */
207 WARN_ON(hsotg->fifo_map);
210 /* set RX/NPTX FIFO sizes */
211 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
212 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
213 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
214 hsotg->regs + GNPTXFSIZ);
217 * arange all the rest of the TX FIFOs, as some versions of this
218 * block have overlapping default addresses. This also ensures
219 * that if the settings have been changed, then they are set to
223 /* start at the end of the GNPTXFSIZ, rounded up */
224 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
227 * Configure fifos sizes from provided configuration and assign
228 * them to endpoints dynamically according to maxpacket size value of
231 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
235 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
236 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
237 "insufficient fifo memory");
240 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
241 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
244 dwc2_writel(hsotg->hw_params.total_fifo_size |
245 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
246 hsotg->regs + GDFIFOCFG);
248 * according to p428 of the design guide, we need to ensure that
249 * all fifos are flushed before continuing
252 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
253 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
255 /* wait until the fifos are both flushed */
258 val = dwc2_readl(hsotg->regs + GRSTCTL);
260 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
263 if (--timeout == 0) {
265 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
273 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
277 * @ep: USB endpoint to allocate request for.
278 * @flags: Allocation flags
280 * Allocate a new USB request structure appropriate for the specified endpoint
282 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
285 struct dwc2_hsotg_req *req;
287 req = kzalloc(sizeof(*req), flags);
291 INIT_LIST_HEAD(&req->queue);
297 * is_ep_periodic - return true if the endpoint is in periodic mode.
298 * @hs_ep: The endpoint to query.
300 * Returns true if the endpoint is in periodic mode, meaning it is being
301 * used for an Interrupt or ISO transfer.
303 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
305 return hs_ep->periodic;
309 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
310 * @hsotg: The device state.
311 * @hs_ep: The endpoint for the request
312 * @hs_req: The request being processed.
314 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
315 * of a request to ensure the buffer is ready for access by the caller.
317 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
318 struct dwc2_hsotg_ep *hs_ep,
319 struct dwc2_hsotg_req *hs_req)
321 struct usb_request *req = &hs_req->req;
323 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
327 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
328 * for Control endpoint
329 * @hsotg: The device state.
331 * This function will allocate 4 descriptor chains for EP 0: 2 for
332 * Setup stage, per one for IN and OUT data/status transactions.
334 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
336 hsotg->setup_desc[0] =
337 dmam_alloc_coherent(hsotg->dev,
338 sizeof(struct dwc2_dma_desc),
339 &hsotg->setup_desc_dma[0],
341 if (!hsotg->setup_desc[0])
344 hsotg->setup_desc[1] =
345 dmam_alloc_coherent(hsotg->dev,
346 sizeof(struct dwc2_dma_desc),
347 &hsotg->setup_desc_dma[1],
349 if (!hsotg->setup_desc[1])
352 hsotg->ctrl_in_desc =
353 dmam_alloc_coherent(hsotg->dev,
354 sizeof(struct dwc2_dma_desc),
355 &hsotg->ctrl_in_desc_dma,
357 if (!hsotg->ctrl_in_desc)
360 hsotg->ctrl_out_desc =
361 dmam_alloc_coherent(hsotg->dev,
362 sizeof(struct dwc2_dma_desc),
363 &hsotg->ctrl_out_desc_dma,
365 if (!hsotg->ctrl_out_desc)
375 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
376 * @hsotg: The controller state.
377 * @hs_ep: The endpoint we're going to write for.
378 * @hs_req: The request to write data for.
380 * This is called when the TxFIFO has some space in it to hold a new
381 * transmission and we have something to give it. The actual setup of
382 * the data size is done elsewhere, so all we have to do is to actually
385 * The return value is zero if there is more space (or nothing was done)
386 * otherwise -ENOSPC is returned if the FIFO space was used up.
388 * This routine is only needed for PIO
390 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
391 struct dwc2_hsotg_ep *hs_ep,
392 struct dwc2_hsotg_req *hs_req)
394 bool periodic = is_ep_periodic(hs_ep);
395 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
396 int buf_pos = hs_req->req.actual;
397 int to_write = hs_ep->size_loaded;
403 to_write -= (buf_pos - hs_ep->last_load);
405 /* if there's nothing to write, get out early */
409 if (periodic && !hsotg->dedicated_fifos) {
410 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
415 * work out how much data was loaded so we can calculate
416 * how much data is left in the fifo.
419 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
422 * if shared fifo, we cannot write anything until the
423 * previous data has been completely sent.
425 if (hs_ep->fifo_load != 0) {
426 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
430 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
432 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
434 /* how much of the data has moved */
435 size_done = hs_ep->size_loaded - size_left;
437 /* how much data is left in the fifo */
438 can_write = hs_ep->fifo_load - size_done;
439 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
440 __func__, can_write);
442 can_write = hs_ep->fifo_size - can_write;
443 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
444 __func__, can_write);
446 if (can_write <= 0) {
447 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
450 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
451 can_write = dwc2_readl(hsotg->regs +
452 DTXFSTS(hs_ep->fifo_index));
457 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
459 "%s: no queue slots available (0x%08x)\n",
462 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
466 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
467 can_write *= 4; /* fifo size is in 32bit quantities. */
470 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
472 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
473 __func__, gnptxsts, can_write, to_write, max_transfer);
476 * limit to 512 bytes of data, it seems at least on the non-periodic
477 * FIFO, requests of >512 cause the endpoint to get stuck with a
478 * fragment of the end of the transfer in it.
480 if (can_write > 512 && !periodic)
484 * limit the write to one max-packet size worth of data, but allow
485 * the transfer to return that it did not run out of fifo space
488 if (to_write > max_transfer) {
489 to_write = max_transfer;
491 /* it's needed only when we do not use dedicated fifos */
492 if (!hsotg->dedicated_fifos)
493 dwc2_hsotg_en_gsint(hsotg,
494 periodic ? GINTSTS_PTXFEMP :
498 /* see if we can write data */
500 if (to_write > can_write) {
501 to_write = can_write;
502 pkt_round = to_write % max_transfer;
505 * Round the write down to an
506 * exact number of packets.
508 * Note, we do not currently check to see if we can ever
509 * write a full packet or not to the FIFO.
513 to_write -= pkt_round;
516 * enable correct FIFO interrupt to alert us when there
520 /* it's needed only when we do not use dedicated fifos */
521 if (!hsotg->dedicated_fifos)
522 dwc2_hsotg_en_gsint(hsotg,
523 periodic ? GINTSTS_PTXFEMP :
527 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
528 to_write, hs_req->req.length, can_write, buf_pos);
533 hs_req->req.actual = buf_pos + to_write;
534 hs_ep->total_data += to_write;
537 hs_ep->fifo_load += to_write;
539 to_write = DIV_ROUND_UP(to_write, 4);
540 data = hs_req->req.buf + buf_pos;
542 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
544 return (to_write >= can_write) ? -ENOSPC : 0;
548 * get_ep_limit - get the maximum data legnth for this endpoint
549 * @hs_ep: The endpoint
551 * Return the maximum data that can be queued in one go on a given endpoint
552 * so that transfers that are too long can be split.
554 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
556 int index = hs_ep->index;
557 unsigned int maxsize;
561 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
562 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
566 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
571 /* we made the constant loading easier above by using +1 */
576 * constrain by packet count if maxpkts*pktsize is greater
577 * than the length register size.
580 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
581 maxsize = maxpkt * hs_ep->ep.maxpacket;
587 * dwc2_hsotg_read_frameno - read current frame number
588 * @hsotg: The device instance
590 * Return the current frame number
592 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
596 dsts = dwc2_readl(hsotg->regs + DSTS);
597 dsts &= DSTS_SOFFN_MASK;
598 dsts >>= DSTS_SOFFN_SHIFT;
604 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
605 * DMA descriptor chain prepared for specific endpoint
606 * @hs_ep: The endpoint
608 * Return the maximum data that can be queued in one go on a given endpoint
609 * depending on its descriptor chain capacity so that transfers that
610 * are too long can be split.
612 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
614 int is_isoc = hs_ep->isochronous;
615 unsigned int maxsize;
618 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
619 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
621 maxsize = DEV_DMA_NBYTES_LIMIT;
623 /* Above size of one descriptor was chosen, multiple it */
624 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
630 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
631 * @hs_ep: The endpoint
632 * @mask: RX/TX bytes mask to be defined
634 * Returns maximum data payload for one descriptor after analyzing endpoint
636 * DMA descriptor transfer bytes limit depends on EP type:
638 * Isochronous - descriptor rx/tx bytes bitfield limit,
639 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
640 * have concatenations from various descriptors within one packet.
642 * Selects corresponding mask for RX/TX bytes as well.
644 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
646 u32 mps = hs_ep->ep.maxpacket;
647 int dir_in = hs_ep->dir_in;
650 if (!hs_ep->index && !dir_in) {
652 *mask = DEV_DMA_NBYTES_MASK;
653 } else if (hs_ep->isochronous) {
655 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
656 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
658 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
659 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
662 desc_size = DEV_DMA_NBYTES_LIMIT;
663 *mask = DEV_DMA_NBYTES_MASK;
665 /* Round down desc_size to be mps multiple */
666 desc_size -= desc_size % mps;
673 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
674 * @hs_ep: The endpoint
675 * @dma_buff: DMA address to use
676 * @len: Length of the transfer
678 * This function will iterate over descriptor chain and fill its entries
679 * with corresponding information based on transfer data.
681 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
685 struct dwc2_hsotg *hsotg = hs_ep->parent;
686 int dir_in = hs_ep->dir_in;
687 struct dwc2_dma_desc *desc = hs_ep->desc_list;
688 u32 mps = hs_ep->ep.maxpacket;
694 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
696 hs_ep->desc_count = (len / maxsize) +
697 ((len % maxsize) ? 1 : 0);
699 hs_ep->desc_count = 1;
701 for (i = 0; i < hs_ep->desc_count; ++i) {
703 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
704 << DEV_DMA_BUFF_STS_SHIFT);
707 if (!hs_ep->index && !dir_in)
708 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
710 desc->status |= (maxsize <<
711 DEV_DMA_NBYTES_SHIFT & mask);
712 desc->buf = dma_buff + offset;
717 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
720 desc->status |= (len % mps) ? DEV_DMA_SHORT :
721 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
723 dev_err(hsotg->dev, "wrong len %d\n", len);
726 len << DEV_DMA_NBYTES_SHIFT & mask;
727 desc->buf = dma_buff + offset;
730 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
731 desc->status |= (DEV_DMA_BUFF_STS_HREADY
732 << DEV_DMA_BUFF_STS_SHIFT);
738 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
739 * @hs_ep: The isochronous endpoint.
740 * @dma_buff: usb requests dma buffer.
741 * @len: usb request transfer length.
743 * Finds out index of first free entry either in the bottom or up half of
744 * descriptor chain depend on which is under SW control and not processed
745 * by HW. Then fills that descriptor with the data of the arrived usb request,
746 * frame info, sets Last and IOC bits increments next_desc. If filled
747 * descriptor is not the first one, removes L bit from the previous descriptor
750 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
751 dma_addr_t dma_buff, unsigned int len)
753 struct dwc2_dma_desc *desc;
754 struct dwc2_hsotg *hsotg = hs_ep->parent;
759 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
761 dev_err(hsotg->dev, "wrong len %d\n", len);
766 * If SW has already filled half of chain, then return and wait for
767 * the other chain to be processed by HW.
769 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
772 /* Increment frame number by interval for IN */
774 dwc2_gadget_incr_frame_num(hs_ep);
776 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
779 /* Sanity check of calculated index */
780 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
781 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
782 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
786 desc = &hs_ep->desc_list[index];
788 /* Clear L bit of previous desc if more than one entries in the chain */
789 if (hs_ep->next_desc)
790 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
792 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
793 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
796 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
798 desc->buf = dma_buff;
799 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
800 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
803 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) &
804 DEV_DMA_ISOC_PID_MASK) |
805 ((len % hs_ep->ep.maxpacket) ?
807 ((hs_ep->target_frame <<
808 DEV_DMA_ISOC_FRNUM_SHIFT) &
809 DEV_DMA_ISOC_FRNUM_MASK);
812 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
813 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
815 /* Update index of last configured entry in the chain */
822 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
823 * @hs_ep: The isochronous endpoint.
825 * Prepare first descriptor chain for isochronous endpoints. Afterwards
826 * write DMA address to HW and enable the endpoint.
828 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
829 * to prepare second descriptor chain while first one is being processed by HW.
831 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
833 struct dwc2_hsotg *hsotg = hs_ep->parent;
834 struct dwc2_hsotg_req *hs_req, *treq;
835 int index = hs_ep->index;
841 if (list_empty(&hs_ep->queue)) {
842 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
846 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
847 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
850 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
855 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
856 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
858 /* write descriptor chain address to control register */
859 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
861 ctrl = dwc2_readl(hsotg->regs + depctl);
862 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
863 dwc2_writel(ctrl, hsotg->regs + depctl);
865 /* Switch ISOC descriptor chain number being processed by SW*/
866 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
867 hs_ep->next_desc = 0;
871 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
872 * @hsotg: The controller state.
873 * @hs_ep: The endpoint to process a request for
874 * @hs_req: The request to start.
875 * @continuing: True if we are doing more for the current request.
877 * Start the given request running by setting the endpoint registers
878 * appropriately, and writing any data to the FIFOs.
880 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
881 struct dwc2_hsotg_ep *hs_ep,
882 struct dwc2_hsotg_req *hs_req,
885 struct usb_request *ureq = &hs_req->req;
886 int index = hs_ep->index;
887 int dir_in = hs_ep->dir_in;
893 unsigned int packets;
895 unsigned int dma_reg;
898 if (hs_ep->req && !continuing) {
899 dev_err(hsotg->dev, "%s: active request\n", __func__);
902 } else if (hs_ep->req != hs_req && continuing) {
904 "%s: continue different req\n", __func__);
910 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
911 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
912 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
914 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
915 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
916 hs_ep->dir_in ? "in" : "out");
918 /* If endpoint is stalled, we will restart request later */
919 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
921 if (index && ctrl & DXEPCTL_STALL) {
922 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
926 length = ureq->length - ureq->actual;
927 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
928 ureq->length, ureq->actual);
930 if (!using_desc_dma(hsotg))
931 maxreq = get_ep_limit(hs_ep);
933 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
935 if (length > maxreq) {
936 int round = maxreq % hs_ep->ep.maxpacket;
938 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
939 __func__, length, maxreq, round);
941 /* round down to multiple of packets */
949 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
951 packets = 1; /* send one packet if length is zero. */
953 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
954 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
958 if (dir_in && index != 0)
959 if (hs_ep->isochronous)
960 epsize = DXEPTSIZ_MC(packets);
962 epsize = DXEPTSIZ_MC(1);
967 * zero length packet should be programmed on its own and should not
968 * be counted in DIEPTSIZ.PktCnt with other packets.
970 if (dir_in && ureq->zero && !continuing) {
971 /* Test if zlp is actually required. */
972 if ((ureq->length >= hs_ep->ep.maxpacket) &&
973 !(ureq->length % hs_ep->ep.maxpacket))
977 epsize |= DXEPTSIZ_PKTCNT(packets);
978 epsize |= DXEPTSIZ_XFERSIZE(length);
980 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
981 __func__, packets, length, ureq->length, epsize, epsize_reg);
983 /* store the request as the current one we're doing */
986 if (using_desc_dma(hsotg)) {
988 u32 mps = hs_ep->ep.maxpacket;
990 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
994 else if (length % mps)
995 length += (mps - (length % mps));
999 * If more data to send, adjust DMA for EP0 out data stage.
1000 * ureq->dma stays unchanged, hence increment it by already
1001 * passed passed data count before starting new transaction.
1003 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1005 offset = ureq->actual;
1007 /* Fill DDMA chain entries */
1008 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1011 /* write descriptor chain address to control register */
1012 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1014 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1015 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1017 /* write size / packets */
1018 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1020 if (using_dma(hsotg) && !continuing && (length != 0)) {
1022 * write DMA address to control register, buffer
1023 * already synced by dwc2_hsotg_ep_queue().
1026 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1028 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1029 __func__, &ureq->dma, dma_reg);
1033 if (hs_ep->isochronous && hs_ep->interval == 1) {
1034 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1035 dwc2_gadget_incr_frame_num(hs_ep);
1037 if (hs_ep->target_frame & 0x1)
1038 ctrl |= DXEPCTL_SETODDFR;
1040 ctrl |= DXEPCTL_SETEVENFR;
1043 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1045 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1047 /* For Setup request do not clear NAK */
1048 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1049 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1051 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1052 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1055 * set these, it seems that DMA support increments past the end
1056 * of the packet buffer so we need to calculate the length from
1059 hs_ep->size_loaded = length;
1060 hs_ep->last_load = ureq->actual;
1062 if (dir_in && !using_dma(hsotg)) {
1063 /* set these anyway, we may need them for non-periodic in */
1064 hs_ep->fifo_load = 0;
1066 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1070 * Note, trying to clear the NAK here causes problems with transmit
1071 * on the S3C6400 ending up with the TXFIFO becoming full.
1074 /* check ep is enabled */
1075 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1077 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1078 index, dwc2_readl(hsotg->regs + epctrl_reg));
1080 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1081 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1083 /* enable ep interrupts */
1084 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1088 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1089 * @hsotg: The device state.
1090 * @hs_ep: The endpoint the request is on.
1091 * @req: The request being processed.
1093 * We've been asked to queue a request, so ensure that the memory buffer
1094 * is correctly setup for DMA. If we've been passed an extant DMA address
1095 * then ensure the buffer has been synced to memory. If our buffer has no
1096 * DMA memory, then we map the memory and mark our request to allow us to
1097 * cleanup on completion.
1099 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1100 struct dwc2_hsotg_ep *hs_ep,
1101 struct usb_request *req)
1105 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1112 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1113 __func__, req->buf, req->length);
1118 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1119 struct dwc2_hsotg_ep *hs_ep,
1120 struct dwc2_hsotg_req *hs_req)
1122 void *req_buf = hs_req->req.buf;
1124 /* If dma is not being used or buffer is aligned */
1125 if (!using_dma(hsotg) || !((long)req_buf & 3))
1128 WARN_ON(hs_req->saved_req_buf);
1130 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1131 hs_ep->ep.name, req_buf, hs_req->req.length);
1133 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1134 if (!hs_req->req.buf) {
1135 hs_req->req.buf = req_buf;
1137 "%s: unable to allocate memory for bounce buffer\n",
1142 /* Save actual buffer */
1143 hs_req->saved_req_buf = req_buf;
1146 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1151 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1152 struct dwc2_hsotg_ep *hs_ep,
1153 struct dwc2_hsotg_req *hs_req)
1155 /* If dma is not being used or buffer was aligned */
1156 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1159 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1160 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1162 /* Copy data from bounce buffer on successful out transfer */
1163 if (!hs_ep->dir_in && !hs_req->req.status)
1164 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1165 hs_req->req.actual);
1167 /* Free bounce buffer */
1168 kfree(hs_req->req.buf);
1170 hs_req->req.buf = hs_req->saved_req_buf;
1171 hs_req->saved_req_buf = NULL;
1175 * dwc2_gadget_target_frame_elapsed - Checks target frame
1176 * @hs_ep: The driver endpoint to check
1178 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1179 * corresponding transfer.
1181 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1183 struct dwc2_hsotg *hsotg = hs_ep->parent;
1184 u32 target_frame = hs_ep->target_frame;
1185 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1186 bool frame_overrun = hs_ep->frame_overrun;
1188 if (!frame_overrun && current_frame >= target_frame)
1191 if (frame_overrun && current_frame >= target_frame &&
1192 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1199 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1200 * @hsotg: The driver state
1201 * @hs_ep: the ep descriptor chain is for
1203 * Called to update EP0 structure's pointers depend on stage of
1206 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1207 struct dwc2_hsotg_ep *hs_ep)
1209 switch (hsotg->ep0_state) {
1210 case DWC2_EP0_SETUP:
1211 case DWC2_EP0_STATUS_OUT:
1212 hs_ep->desc_list = hsotg->setup_desc[0];
1213 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1215 case DWC2_EP0_DATA_IN:
1216 case DWC2_EP0_STATUS_IN:
1217 hs_ep->desc_list = hsotg->ctrl_in_desc;
1218 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1220 case DWC2_EP0_DATA_OUT:
1221 hs_ep->desc_list = hsotg->ctrl_out_desc;
1222 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1225 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1233 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1236 struct dwc2_hsotg_req *hs_req = our_req(req);
1237 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1238 struct dwc2_hsotg *hs = hs_ep->parent;
1242 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1243 ep->name, req, req->length, req->buf, req->no_interrupt,
1244 req->zero, req->short_not_ok);
1246 /* Prevent new request submission when controller is suspended */
1247 if (hs->lx_state == DWC2_L2) {
1248 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
1253 /* initialise status of the request */
1254 INIT_LIST_HEAD(&hs_req->queue);
1256 req->status = -EINPROGRESS;
1258 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1262 /* if we're using DMA, sync the buffers as necessary */
1263 if (using_dma(hs)) {
1264 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1268 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1269 if (using_desc_dma(hs) && !hs_ep->index) {
1270 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1275 first = list_empty(&hs_ep->queue);
1276 list_add_tail(&hs_req->queue, &hs_ep->queue);
1279 * Handle DDMA isochronous transfers separately - just add new entry
1280 * to the half of descriptor chain that is not processed by HW.
1281 * Transfer will be started once SW gets either one of NAK or
1282 * OutTknEpDis interrupts.
1284 if (using_desc_dma(hs) && hs_ep->isochronous &&
1285 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1286 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1287 hs_req->req.length);
1289 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1295 if (!hs_ep->isochronous) {
1296 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1300 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1301 dwc2_gadget_incr_frame_num(hs_ep);
1303 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1304 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1309 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1312 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1313 struct dwc2_hsotg *hs = hs_ep->parent;
1314 unsigned long flags = 0;
1317 spin_lock_irqsave(&hs->lock, flags);
1318 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1319 spin_unlock_irqrestore(&hs->lock, flags);
1324 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1325 struct usb_request *req)
1327 struct dwc2_hsotg_req *hs_req = our_req(req);
1333 * dwc2_hsotg_complete_oursetup - setup completion callback
1334 * @ep: The endpoint the request was on.
1335 * @req: The request completed.
1337 * Called on completion of any requests the driver itself
1338 * submitted that need cleaning up.
1340 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1341 struct usb_request *req)
1343 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1344 struct dwc2_hsotg *hsotg = hs_ep->parent;
1346 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1348 dwc2_hsotg_ep_free_request(ep, req);
1352 * ep_from_windex - convert control wIndex value to endpoint
1353 * @hsotg: The driver state.
1354 * @windex: The control request wIndex field (in host order).
1356 * Convert the given wIndex into a pointer to an driver endpoint
1357 * structure, or return NULL if it is not a valid endpoint.
1359 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1362 struct dwc2_hsotg_ep *ep;
1363 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1364 int idx = windex & 0x7F;
1366 if (windex >= 0x100)
1369 if (idx > hsotg->num_of_eps)
1372 ep = index_to_ep(hsotg, idx, dir);
1374 if (idx && ep->dir_in != dir)
1381 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1382 * @hsotg: The driver state.
1383 * @testmode: requested usb test mode
1384 * Enable usb Test Mode requested by the Host.
1386 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1388 int dctl = dwc2_readl(hsotg->regs + DCTL);
1390 dctl &= ~DCTL_TSTCTL_MASK;
1397 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1402 dwc2_writel(dctl, hsotg->regs + DCTL);
1407 * dwc2_hsotg_send_reply - send reply to control request
1408 * @hsotg: The device state
1410 * @buff: Buffer for request
1411 * @length: Length of reply.
1413 * Create a request and queue it on the given endpoint. This is useful as
1414 * an internal method of sending replies to certain control requests, etc.
1416 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1417 struct dwc2_hsotg_ep *ep,
1421 struct usb_request *req;
1424 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1426 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1427 hsotg->ep0_reply = req;
1429 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1433 req->buf = hsotg->ep0_buff;
1434 req->length = length;
1436 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1440 req->complete = dwc2_hsotg_complete_oursetup;
1443 memcpy(req->buf, buff, length);
1445 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1447 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1455 * dwc2_hsotg_process_req_status - process request GET_STATUS
1456 * @hsotg: The device state
1457 * @ctrl: USB control request
1459 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1460 struct usb_ctrlrequest *ctrl)
1462 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1463 struct dwc2_hsotg_ep *ep;
1467 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1470 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1474 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1475 case USB_RECIP_DEVICE:
1477 * bit 0 => self powered
1478 * bit 1 => remote wakeup
1480 reply = cpu_to_le16(0);
1483 case USB_RECIP_INTERFACE:
1484 /* currently, the data result should be zero */
1485 reply = cpu_to_le16(0);
1488 case USB_RECIP_ENDPOINT:
1489 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1493 reply = cpu_to_le16(ep->halted ? 1 : 0);
1500 if (le16_to_cpu(ctrl->wLength) != 2)
1503 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1505 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1512 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1515 * get_ep_head - return the first request on the endpoint
1516 * @hs_ep: The controller endpoint to get
1518 * Get the first request on the endpoint.
1520 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1522 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1527 * dwc2_gadget_start_next_request - Starts next request from ep queue
1528 * @hs_ep: Endpoint structure
1530 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1531 * in its handler. Hence we need to unmask it here to be able to do
1532 * resynchronization.
1534 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1537 struct dwc2_hsotg *hsotg = hs_ep->parent;
1538 int dir_in = hs_ep->dir_in;
1539 struct dwc2_hsotg_req *hs_req;
1540 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1542 if (!list_empty(&hs_ep->queue)) {
1543 hs_req = get_ep_head(hs_ep);
1544 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1547 if (!hs_ep->isochronous)
1551 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1554 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1556 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1557 mask |= DOEPMSK_OUTTKNEPDISMSK;
1558 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1563 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1564 * @hsotg: The device state
1565 * @ctrl: USB control request
1567 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1568 struct usb_ctrlrequest *ctrl)
1570 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1571 struct dwc2_hsotg_req *hs_req;
1572 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1573 struct dwc2_hsotg_ep *ep;
1580 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1581 __func__, set ? "SET" : "CLEAR");
1583 wValue = le16_to_cpu(ctrl->wValue);
1584 wIndex = le16_to_cpu(ctrl->wIndex);
1585 recip = ctrl->bRequestType & USB_RECIP_MASK;
1588 case USB_RECIP_DEVICE:
1590 case USB_DEVICE_TEST_MODE:
1591 if ((wIndex & 0xff) != 0)
1596 hsotg->test_mode = wIndex >> 8;
1597 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1600 "%s: failed to send reply\n", __func__);
1609 case USB_RECIP_ENDPOINT:
1610 ep = ep_from_windex(hsotg, wIndex);
1612 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1618 case USB_ENDPOINT_HALT:
1619 halted = ep->halted;
1621 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1623 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1626 "%s: failed to send reply\n", __func__);
1631 * we have to complete all requests for ep if it was
1632 * halted, and the halt was cleared by CLEAR_FEATURE
1635 if (!set && halted) {
1637 * If we have request in progress,
1643 list_del_init(&hs_req->queue);
1644 if (hs_req->req.complete) {
1645 spin_unlock(&hsotg->lock);
1646 usb_gadget_giveback_request(
1647 &ep->ep, &hs_req->req);
1648 spin_lock(&hsotg->lock);
1652 /* If we have pending request, then start it */
1654 dwc2_gadget_start_next_request(ep);
1669 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1672 * dwc2_hsotg_stall_ep0 - stall ep0
1673 * @hsotg: The device state
1675 * Set stall for ep0 as response for setup request.
1677 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1679 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1683 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1684 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1687 * DxEPCTL_Stall will be cleared by EP once it has
1688 * taken effect, so no need to clear later.
1691 ctrl = dwc2_readl(hsotg->regs + reg);
1692 ctrl |= DXEPCTL_STALL;
1693 ctrl |= DXEPCTL_CNAK;
1694 dwc2_writel(ctrl, hsotg->regs + reg);
1697 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1698 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1701 * complete won't be called, so we enqueue
1702 * setup request here
1704 dwc2_hsotg_enqueue_setup(hsotg);
1708 * dwc2_hsotg_process_control - process a control request
1709 * @hsotg: The device state
1710 * @ctrl: The control request received
1712 * The controller has received the SETUP phase of a control request, and
1713 * needs to work out what to do next (and whether to pass it on to the
1716 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1717 struct usb_ctrlrequest *ctrl)
1719 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1724 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1725 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1726 ctrl->wIndex, ctrl->wLength);
1728 if (ctrl->wLength == 0) {
1730 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1731 } else if (ctrl->bRequestType & USB_DIR_IN) {
1733 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1736 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1739 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1740 switch (ctrl->bRequest) {
1741 case USB_REQ_SET_ADDRESS:
1742 hsotg->connected = 1;
1743 dcfg = dwc2_readl(hsotg->regs + DCFG);
1744 dcfg &= ~DCFG_DEVADDR_MASK;
1745 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1746 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1747 dwc2_writel(dcfg, hsotg->regs + DCFG);
1749 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1751 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1754 case USB_REQ_GET_STATUS:
1755 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1758 case USB_REQ_CLEAR_FEATURE:
1759 case USB_REQ_SET_FEATURE:
1760 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1765 /* as a fallback, try delivering it to the driver to deal with */
1767 if (ret == 0 && hsotg->driver) {
1768 spin_unlock(&hsotg->lock);
1769 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1770 spin_lock(&hsotg->lock);
1772 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1776 * the request is either unhandlable, or is not formatted correctly
1777 * so respond with a STALL for the status stage to indicate failure.
1781 dwc2_hsotg_stall_ep0(hsotg);
1785 * dwc2_hsotg_complete_setup - completion of a setup transfer
1786 * @ep: The endpoint the request was on.
1787 * @req: The request completed.
1789 * Called on completion of any requests the driver itself submitted for
1792 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1793 struct usb_request *req)
1795 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1796 struct dwc2_hsotg *hsotg = hs_ep->parent;
1798 if (req->status < 0) {
1799 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1803 spin_lock(&hsotg->lock);
1804 if (req->actual == 0)
1805 dwc2_hsotg_enqueue_setup(hsotg);
1807 dwc2_hsotg_process_control(hsotg, req->buf);
1808 spin_unlock(&hsotg->lock);
1812 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1813 * @hsotg: The device state.
1815 * Enqueue a request on EP0 if necessary to received any SETUP packets
1816 * received from the host.
1818 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1820 struct usb_request *req = hsotg->ctrl_req;
1821 struct dwc2_hsotg_req *hs_req = our_req(req);
1824 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1828 req->buf = hsotg->ctrl_buff;
1829 req->complete = dwc2_hsotg_complete_setup;
1831 if (!list_empty(&hs_req->queue)) {
1832 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1836 hsotg->eps_out[0]->dir_in = 0;
1837 hsotg->eps_out[0]->send_zlp = 0;
1838 hsotg->ep0_state = DWC2_EP0_SETUP;
1840 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1842 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1844 * Don't think there's much we can do other than watch the
1850 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1851 struct dwc2_hsotg_ep *hs_ep)
1854 u8 index = hs_ep->index;
1855 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1856 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1859 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1862 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1864 if (using_desc_dma(hsotg)) {
1865 /* Not specific buffer needed for ep0 ZLP */
1866 dma_addr_t dma = hs_ep->desc_list_dma;
1868 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1869 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1871 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1872 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1876 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1877 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1878 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1879 ctrl |= DXEPCTL_USBACTEP;
1880 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1884 * dwc2_hsotg_complete_request - complete a request given to us
1885 * @hsotg: The device state.
1886 * @hs_ep: The endpoint the request was on.
1887 * @hs_req: The request to complete.
1888 * @result: The result code (0 => Ok, otherwise errno)
1890 * The given request has finished, so call the necessary completion
1891 * if it has one and then look to see if we can start a new request
1894 * Note, expects the ep to already be locked as appropriate.
1896 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1897 struct dwc2_hsotg_ep *hs_ep,
1898 struct dwc2_hsotg_req *hs_req,
1902 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1906 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1907 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1910 * only replace the status if we've not already set an error
1911 * from a previous transaction
1914 if (hs_req->req.status == -EINPROGRESS)
1915 hs_req->req.status = result;
1917 if (using_dma(hsotg))
1918 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1920 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1923 list_del_init(&hs_req->queue);
1926 * call the complete request with the locks off, just in case the
1927 * request tries to queue more work for this endpoint.
1930 if (hs_req->req.complete) {
1931 spin_unlock(&hsotg->lock);
1932 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1933 spin_lock(&hsotg->lock);
1936 /* In DDMA don't need to proceed to starting of next ISOC request */
1937 if (using_desc_dma(hsotg) && hs_ep->isochronous)
1941 * Look to see if there is anything else to do. Note, the completion
1942 * of the previous request may have caused a new request to be started
1943 * so be careful when doing this.
1946 if (!hs_ep->req && result >= 0)
1947 dwc2_gadget_start_next_request(hs_ep);
1951 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
1952 * @hs_ep: The endpoint the request was on.
1954 * Get first request from the ep queue, determine descriptor on which complete
1955 * happened. SW based on isoc_chain_num discovers which half of the descriptor
1956 * chain is currently in use by HW, adjusts dma_address and calculates index
1957 * of completed descriptor based on the value of DEPDMA register. Update actual
1958 * length of request, giveback to gadget.
1960 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
1962 struct dwc2_hsotg *hsotg = hs_ep->parent;
1963 struct dwc2_hsotg_req *hs_req;
1964 struct usb_request *ureq;
1966 dma_addr_t dma_addr;
1972 hs_req = get_ep_head(hs_ep);
1974 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
1977 ureq = &hs_req->req;
1979 dma_addr = hs_ep->desc_list_dma;
1982 * If lower half of descriptor chain is currently use by SW,
1983 * that means higher half is being processed by HW, so shift
1984 * DMA address to higher half of descriptor chain.
1986 if (!hs_ep->isoc_chain_num)
1987 dma_addr += sizeof(struct dwc2_dma_desc) *
1988 (MAX_DMA_DESC_NUM_GENERIC / 2);
1990 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
1991 depdma = dwc2_readl(hsotg->regs + dma_reg);
1993 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
1994 desc_sts = hs_ep->desc_list[index].status;
1996 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
1997 DEV_DMA_ISOC_RX_NBYTES_MASK;
1998 ureq->actual = ureq->length -
1999 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
2001 /* Adjust actual length for ISOC Out if length is not align of 4 */
2002 if (!hs_ep->dir_in && ureq->length & 0x3)
2003 ureq->actual += 4 - (ureq->length & 0x3);
2005 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2009 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2010 * @hs_ep: The isochronous endpoint to be re-enabled.
2012 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2013 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2014 * was under SW control till HW was busy and restart the endpoint if needed.
2016 static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2018 struct dwc2_hsotg *hsotg = hs_ep->parent;
2022 u32 dma_addr = hs_ep->desc_list_dma;
2023 unsigned char index = hs_ep->index;
2025 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2026 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2028 ctrl = dwc2_readl(hsotg->regs + depctl);
2031 * EP was disabled if HW has processed last descriptor or BNA was set.
2032 * So restart ep if SW has prepared new descriptor chain in ep_queue
2033 * routine while HW was busy.
2035 if (!(ctrl & DXEPCTL_EPENA)) {
2036 if (!hs_ep->next_desc) {
2037 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2042 dma_addr += sizeof(struct dwc2_dma_desc) *
2043 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2044 hs_ep->isoc_chain_num;
2045 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2047 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2048 dwc2_writel(ctrl, hsotg->regs + depctl);
2050 /* Switch ISOC descriptor chain number being processed by SW*/
2051 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2052 hs_ep->next_desc = 0;
2054 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2060 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2061 * @hsotg: The device state.
2062 * @ep_idx: The endpoint index for the data
2063 * @size: The size of data in the fifo, in bytes
2065 * The FIFO status shows there is data to read from the FIFO for a given
2066 * endpoint, so sort out whether we need to read the data into a request
2067 * that has been made for that endpoint.
2069 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2071 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2072 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2073 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2079 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2083 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2084 __func__, size, ep_idx, epctl);
2086 /* dump the data from the FIFO, we've nothing we can do */
2087 for (ptr = 0; ptr < size; ptr += 4)
2088 (void)dwc2_readl(fifo);
2094 read_ptr = hs_req->req.actual;
2095 max_req = hs_req->req.length - read_ptr;
2097 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2098 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2100 if (to_read > max_req) {
2102 * more data appeared than we where willing
2103 * to deal with in this request.
2106 /* currently we don't deal this */
2110 hs_ep->total_data += to_read;
2111 hs_req->req.actual += to_read;
2112 to_read = DIV_ROUND_UP(to_read, 4);
2115 * note, we might over-write the buffer end by 3 bytes depending on
2116 * alignment of the data.
2118 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2122 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2123 * @hsotg: The device instance
2124 * @dir_in: If IN zlp
2126 * Generate a zero-length IN packet request for terminating a SETUP
2129 * Note, since we don't write any data to the TxFIFO, then it is
2130 * currently believed that we do not need to wait for any space in
2133 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2135 /* eps_out[0] is used in both directions */
2136 hsotg->eps_out[0]->dir_in = dir_in;
2137 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2139 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2142 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2147 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2148 if (ctrl & DXEPCTL_EOFRNUM)
2149 ctrl |= DXEPCTL_SETEVENFR;
2151 ctrl |= DXEPCTL_SETODDFR;
2152 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2156 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2157 * @hs_ep - The endpoint on which transfer went
2159 * Iterate over endpoints descriptor chain and get info on bytes remained
2160 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2162 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2164 struct dwc2_hsotg *hsotg = hs_ep->parent;
2165 unsigned int bytes_rem = 0;
2166 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2173 for (i = 0; i < hs_ep->desc_count; ++i) {
2174 status = desc->status;
2175 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2177 if (status & DEV_DMA_STS_MASK)
2178 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2179 i, status & DEV_DMA_STS_MASK);
2186 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2187 * @hsotg: The device instance
2188 * @epnum: The endpoint received from
2190 * The RXFIFO has delivered an OutDone event, which means that the data
2191 * transfer for an OUT endpoint has been completed, either by a short
2192 * packet or by the finish of a transfer.
2194 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2196 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2197 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2198 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2199 struct usb_request *req = &hs_req->req;
2200 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2204 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2208 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2209 dev_dbg(hsotg->dev, "zlp packet received\n");
2210 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2211 dwc2_hsotg_enqueue_setup(hsotg);
2215 if (using_desc_dma(hsotg))
2216 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2218 if (using_dma(hsotg)) {
2219 unsigned int size_done;
2222 * Calculate the size of the transfer by checking how much
2223 * is left in the endpoint size register and then working it
2224 * out from the amount we loaded for the transfer.
2226 * We need to do this as DMA pointers are always 32bit aligned
2227 * so may overshoot/undershoot the transfer.
2230 size_done = hs_ep->size_loaded - size_left;
2231 size_done += hs_ep->last_load;
2233 req->actual = size_done;
2236 /* if there is more request to do, schedule new transfer */
2237 if (req->actual < req->length && size_left == 0) {
2238 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2242 if (req->actual < req->length && req->short_not_ok) {
2243 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2244 __func__, req->actual, req->length);
2247 * todo - what should we return here? there's no one else
2248 * even bothering to check the status.
2252 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2253 if (!using_desc_dma(hsotg) && epnum == 0 &&
2254 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2255 /* Move to STATUS IN */
2256 dwc2_hsotg_ep0_zlp(hsotg, true);
2261 * Slave mode OUT transfers do not go through XferComplete so
2262 * adjust the ISOC parity here.
2264 if (!using_dma(hsotg)) {
2265 if (hs_ep->isochronous && hs_ep->interval == 1)
2266 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2267 else if (hs_ep->isochronous && hs_ep->interval > 1)
2268 dwc2_gadget_incr_frame_num(hs_ep);
2271 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2275 * dwc2_hsotg_handle_rx - RX FIFO has data
2276 * @hsotg: The device instance
2278 * The IRQ handler has detected that the RX FIFO has some data in it
2279 * that requires processing, so find out what is in there and do the
2282 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2283 * chunks, so if you have x packets received on an endpoint you'll get x
2284 * FIFO events delivered, each with a packet's worth of data in it.
2286 * When using DMA, we should not be processing events from the RXFIFO
2287 * as the actual data should be sent to the memory directly and we turn
2288 * on the completion interrupts to get notifications of transfer completion.
2290 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2292 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2293 u32 epnum, status, size;
2295 WARN_ON(using_dma(hsotg));
2297 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2298 status = grxstsr & GRXSTS_PKTSTS_MASK;
2300 size = grxstsr & GRXSTS_BYTECNT_MASK;
2301 size >>= GRXSTS_BYTECNT_SHIFT;
2303 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2304 __func__, grxstsr, size, epnum);
2306 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2307 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2308 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2311 case GRXSTS_PKTSTS_OUTDONE:
2312 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2313 dwc2_hsotg_read_frameno(hsotg));
2315 if (!using_dma(hsotg))
2316 dwc2_hsotg_handle_outdone(hsotg, epnum);
2319 case GRXSTS_PKTSTS_SETUPDONE:
2321 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2322 dwc2_hsotg_read_frameno(hsotg),
2323 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2325 * Call dwc2_hsotg_handle_outdone here if it was not called from
2326 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2327 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2329 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2330 dwc2_hsotg_handle_outdone(hsotg, epnum);
2333 case GRXSTS_PKTSTS_OUTRX:
2334 dwc2_hsotg_rx_data(hsotg, epnum, size);
2337 case GRXSTS_PKTSTS_SETUPRX:
2339 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2340 dwc2_hsotg_read_frameno(hsotg),
2341 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2343 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2345 dwc2_hsotg_rx_data(hsotg, epnum, size);
2349 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2352 dwc2_hsotg_dump(hsotg);
2358 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2359 * @mps: The maximum packet size in bytes.
2361 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2365 return D0EPCTL_MPS_64;
2367 return D0EPCTL_MPS_32;
2369 return D0EPCTL_MPS_16;
2371 return D0EPCTL_MPS_8;
2374 /* bad max packet size, warn and return invalid result */
2380 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2381 * @hsotg: The driver state.
2382 * @ep: The index number of the endpoint
2383 * @mps: The maximum packet size in bytes
2384 * @mc: The multicount value
2386 * Configure the maximum packet size for the given endpoint, updating
2387 * the hardware control registers to reflect this.
2389 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2390 unsigned int ep, unsigned int mps,
2391 unsigned int mc, unsigned int dir_in)
2393 struct dwc2_hsotg_ep *hs_ep;
2394 void __iomem *regs = hsotg->regs;
2397 hs_ep = index_to_ep(hsotg, ep, dir_in);
2402 u32 mps_bytes = mps;
2404 /* EP0 is a special case */
2405 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2408 hs_ep->ep.maxpacket = mps_bytes;
2416 hs_ep->ep.maxpacket = mps;
2420 reg = dwc2_readl(regs + DIEPCTL(ep));
2421 reg &= ~DXEPCTL_MPS_MASK;
2423 dwc2_writel(reg, regs + DIEPCTL(ep));
2425 reg = dwc2_readl(regs + DOEPCTL(ep));
2426 reg &= ~DXEPCTL_MPS_MASK;
2428 dwc2_writel(reg, regs + DOEPCTL(ep));
2434 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2438 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2439 * @hsotg: The driver state
2440 * @idx: The index for the endpoint (0..15)
2442 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2447 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2448 hsotg->regs + GRSTCTL);
2450 /* wait until the fifo is flushed */
2454 val = dwc2_readl(hsotg->regs + GRSTCTL);
2456 if ((val & (GRSTCTL_TXFFLSH)) == 0)
2459 if (--timeout == 0) {
2461 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2471 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2472 * @hsotg: The driver state
2473 * @hs_ep: The driver endpoint to check.
2475 * Check to see if there is a request that has data to send, and if so
2476 * make an attempt to write data into the FIFO.
2478 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2479 struct dwc2_hsotg_ep *hs_ep)
2481 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2483 if (!hs_ep->dir_in || !hs_req) {
2485 * if request is not enqueued, we disable interrupts
2486 * for endpoints, excepting ep0
2488 if (hs_ep->index != 0)
2489 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2494 if (hs_req->req.actual < hs_req->req.length) {
2495 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2497 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2504 * dwc2_hsotg_complete_in - complete IN transfer
2505 * @hsotg: The device state.
2506 * @hs_ep: The endpoint that has just completed.
2508 * An IN transfer has been completed, update the transfer's state and then
2509 * call the relevant completion routines.
2511 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2512 struct dwc2_hsotg_ep *hs_ep)
2514 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2515 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2516 int size_left, size_done;
2519 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2523 /* Finish ZLP handling for IN EP0 transactions */
2524 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2525 dev_dbg(hsotg->dev, "zlp packet sent\n");
2528 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2529 * changed to IN. Change back to complete OUT transfer request
2533 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2534 if (hsotg->test_mode) {
2537 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2539 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2541 dwc2_hsotg_stall_ep0(hsotg);
2545 dwc2_hsotg_enqueue_setup(hsotg);
2550 * Calculate the size of the transfer by checking how much is left
2551 * in the endpoint size register and then working it out from
2552 * the amount we loaded for the transfer.
2554 * We do this even for DMA, as the transfer may have incremented
2555 * past the end of the buffer (DMA transfers are always 32bit
2558 if (using_desc_dma(hsotg)) {
2559 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2561 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2564 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2567 size_done = hs_ep->size_loaded - size_left;
2568 size_done += hs_ep->last_load;
2570 if (hs_req->req.actual != size_done)
2571 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2572 __func__, hs_req->req.actual, size_done);
2574 hs_req->req.actual = size_done;
2575 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2576 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2578 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2579 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2580 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2584 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2585 if (hs_ep->send_zlp) {
2586 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2587 hs_ep->send_zlp = 0;
2588 /* transfer will be completed on next complete interrupt */
2592 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2593 /* Move to STATUS OUT */
2594 dwc2_hsotg_ep0_zlp(hsotg, false);
2598 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2602 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2603 * @hsotg: The device state.
2604 * @idx: Index of ep.
2605 * @dir_in: Endpoint direction 1-in 0-out.
2607 * Reads for endpoint with given index and direction, by masking
2608 * epint_reg with coresponding mask.
2610 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2611 unsigned int idx, int dir_in)
2613 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2614 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2619 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2620 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2621 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2622 mask |= DXEPINT_SETUP_RCVD;
2624 ints = dwc2_readl(hsotg->regs + epint_reg);
2630 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2631 * @hs_ep: The endpoint on which interrupt is asserted.
2633 * This interrupt indicates that the endpoint has been disabled per the
2634 * application's request.
2636 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2637 * in case of ISOC completes current request.
2639 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2640 * request starts it.
2642 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2644 struct dwc2_hsotg *hsotg = hs_ep->parent;
2645 struct dwc2_hsotg_req *hs_req;
2646 unsigned char idx = hs_ep->index;
2647 int dir_in = hs_ep->dir_in;
2648 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2649 int dctl = dwc2_readl(hsotg->regs + DCTL);
2651 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2654 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2656 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2658 if (hs_ep->isochronous) {
2659 dwc2_hsotg_complete_in(hsotg, hs_ep);
2663 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2664 int dctl = dwc2_readl(hsotg->regs + DCTL);
2666 dctl |= DCTL_CGNPINNAK;
2667 dwc2_writel(dctl, hsotg->regs + DCTL);
2672 if (dctl & DCTL_GOUTNAKSTS) {
2673 dctl |= DCTL_CGOUTNAK;
2674 dwc2_writel(dctl, hsotg->regs + DCTL);
2677 if (!hs_ep->isochronous)
2680 if (list_empty(&hs_ep->queue)) {
2681 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2687 hs_req = get_ep_head(hs_ep);
2689 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2691 dwc2_gadget_incr_frame_num(hs_ep);
2692 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2694 dwc2_gadget_start_next_request(hs_ep);
2698 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2699 * @hs_ep: The endpoint on which interrupt is asserted.
2701 * This is starting point for ISOC-OUT transfer, synchronization done with
2702 * first out token received from host while corresponding EP is disabled.
2704 * Device does not know initial frame in which out token will come. For this
2705 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2706 * getting this interrupt SW starts calculation for next transfer frame.
2708 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2710 struct dwc2_hsotg *hsotg = ep->parent;
2711 int dir_in = ep->dir_in;
2715 if (dir_in || !ep->isochronous)
2719 * Store frame in which irq was asserted here, as
2720 * it can change while completing request below.
2722 tmp = dwc2_hsotg_read_frameno(hsotg);
2724 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2726 if (using_desc_dma(hsotg)) {
2727 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2728 /* Start first ISO Out */
2729 ep->target_frame = tmp;
2730 dwc2_gadget_start_isoc_ddma(ep);
2735 if (ep->interval > 1 &&
2736 ep->target_frame == TARGET_FRAME_INITIAL) {
2740 dsts = dwc2_readl(hsotg->regs + DSTS);
2741 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2742 dwc2_gadget_incr_frame_num(ep);
2744 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2745 if (ep->target_frame & 0x1)
2746 ctrl |= DXEPCTL_SETODDFR;
2748 ctrl |= DXEPCTL_SETEVENFR;
2750 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2753 dwc2_gadget_start_next_request(ep);
2754 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2755 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2756 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2760 * dwc2_gadget_handle_nak - handle NAK interrupt
2761 * @hs_ep: The endpoint on which interrupt is asserted.
2763 * This is starting point for ISOC-IN transfer, synchronization done with
2764 * first IN token received from host while corresponding EP is disabled.
2766 * Device does not know when first one token will arrive from host. On first
2767 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2768 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2769 * sent in response to that as there was no data in FIFO. SW is basing on this
2770 * interrupt to obtain frame in which token has come and then based on the
2771 * interval calculates next frame for transfer.
2773 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2775 struct dwc2_hsotg *hsotg = hs_ep->parent;
2776 int dir_in = hs_ep->dir_in;
2778 if (!dir_in || !hs_ep->isochronous)
2781 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2782 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2784 if (using_desc_dma(hsotg)) {
2785 dwc2_gadget_start_isoc_ddma(hs_ep);
2789 if (hs_ep->interval > 1) {
2790 u32 ctrl = dwc2_readl(hsotg->regs +
2791 DIEPCTL(hs_ep->index));
2792 if (hs_ep->target_frame & 0x1)
2793 ctrl |= DXEPCTL_SETODDFR;
2795 ctrl |= DXEPCTL_SETEVENFR;
2797 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2800 dwc2_hsotg_complete_request(hsotg, hs_ep,
2801 get_ep_head(hs_ep), 0);
2804 dwc2_gadget_incr_frame_num(hs_ep);
2808 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2809 * @hsotg: The driver state
2810 * @idx: The index for the endpoint (0..15)
2811 * @dir_in: Set if this is an IN endpoint
2813 * Process and clear any interrupt pending for an individual endpoint
2815 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2818 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2819 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2820 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2821 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2825 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2826 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2828 /* Clear endpoint interrupts */
2829 dwc2_writel(ints, hsotg->regs + epint_reg);
2832 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2833 __func__, idx, dir_in ? "in" : "out");
2837 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2838 __func__, idx, dir_in ? "in" : "out", ints);
2840 /* Don't process XferCompl interrupt if it is a setup packet */
2841 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2842 ints &= ~DXEPINT_XFERCOMPL;
2845 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2846 * stage and xfercomplete was generated without SETUP phase done
2847 * interrupt. SW should parse received setup packet only after host's
2848 * exit from setup phase of control transfer.
2850 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2851 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2852 ints &= ~DXEPINT_XFERCOMPL;
2854 if (ints & DXEPINT_XFERCOMPL) {
2856 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2857 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2858 dwc2_readl(hsotg->regs + epsiz_reg));
2860 /* In DDMA handle isochronous requests separately */
2861 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2862 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2863 /* Try to start next isoc request */
2864 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2865 } else if (dir_in) {
2867 * We get OutDone from the FIFO, so we only
2868 * need to look at completing IN requests here
2869 * if operating slave mode
2871 if (hs_ep->isochronous && hs_ep->interval > 1)
2872 dwc2_gadget_incr_frame_num(hs_ep);
2874 dwc2_hsotg_complete_in(hsotg, hs_ep);
2875 if (ints & DXEPINT_NAKINTRPT)
2876 ints &= ~DXEPINT_NAKINTRPT;
2878 if (idx == 0 && !hs_ep->req)
2879 dwc2_hsotg_enqueue_setup(hsotg);
2880 } else if (using_dma(hsotg)) {
2882 * We're using DMA, we need to fire an OutDone here
2883 * as we ignore the RXFIFO.
2885 if (hs_ep->isochronous && hs_ep->interval > 1)
2886 dwc2_gadget_incr_frame_num(hs_ep);
2888 dwc2_hsotg_handle_outdone(hsotg, idx);
2892 if (ints & DXEPINT_EPDISBLD)
2893 dwc2_gadget_handle_ep_disabled(hs_ep);
2895 if (ints & DXEPINT_OUTTKNEPDIS)
2896 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2898 if (ints & DXEPINT_NAKINTRPT)
2899 dwc2_gadget_handle_nak(hs_ep);
2901 if (ints & DXEPINT_AHBERR)
2902 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2904 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2905 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2907 if (using_dma(hsotg) && idx == 0) {
2909 * this is the notification we've received a
2910 * setup packet. In non-DMA mode we'd get this
2911 * from the RXFIFO, instead we need to process
2918 dwc2_hsotg_handle_outdone(hsotg, 0);
2922 if (ints & DXEPINT_STSPHSERCVD) {
2923 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2925 /* Move to STATUS IN for DDMA */
2926 if (using_desc_dma(hsotg))
2927 dwc2_hsotg_ep0_zlp(hsotg, true);
2930 if (ints & DXEPINT_BACK2BACKSETUP)
2931 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2933 if (ints & DXEPINT_BNAINTR) {
2934 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2937 * Try to start next isoc request, if any.
2938 * Sometimes the endpoint remains enabled after BNA interrupt
2939 * assertion, which is not expected, hence we can enter here
2942 if (hs_ep->isochronous)
2943 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2946 if (dir_in && !hs_ep->isochronous) {
2947 /* not sure if this is important, but we'll clear it anyway */
2948 if (ints & DXEPINT_INTKNTXFEMP) {
2949 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2953 /* this probably means something bad is happening */
2954 if (ints & DXEPINT_INTKNEPMIS) {
2955 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2959 /* FIFO has space or is empty (see GAHBCFG) */
2960 if (hsotg->dedicated_fifos &&
2961 ints & DXEPINT_TXFEMP) {
2962 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2964 if (!using_dma(hsotg))
2965 dwc2_hsotg_trytx(hsotg, hs_ep);
2971 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2972 * @hsotg: The device state.
2974 * Handle updating the device settings after the enumeration phase has
2977 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2979 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2980 int ep0_mps = 0, ep_mps = 8;
2983 * This should signal the finish of the enumeration phase
2984 * of the USB handshaking, so we should now know what rate
2988 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2991 * note, since we're limited by the size of transfer on EP0, and
2992 * it seems IN transfers must be a even number of packets we do
2993 * not advertise a 64byte MPS on EP0.
2996 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2997 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2998 case DSTS_ENUMSPD_FS:
2999 case DSTS_ENUMSPD_FS48:
3000 hsotg->gadget.speed = USB_SPEED_FULL;
3001 ep0_mps = EP0_MPS_LIMIT;
3005 case DSTS_ENUMSPD_HS:
3006 hsotg->gadget.speed = USB_SPEED_HIGH;
3007 ep0_mps = EP0_MPS_LIMIT;
3011 case DSTS_ENUMSPD_LS:
3012 hsotg->gadget.speed = USB_SPEED_LOW;
3016 * note, we don't actually support LS in this driver at the
3017 * moment, and the documentation seems to imply that it isn't
3018 * supported by the PHYs on some of the devices.
3022 dev_info(hsotg->dev, "new device is %s\n",
3023 usb_speed_string(hsotg->gadget.speed));
3026 * we should now know the maximum packet size for an
3027 * endpoint, so set the endpoints to a default value.
3032 /* Initialize ep0 for both in and out directions */
3033 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3034 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3035 for (i = 1; i < hsotg->num_of_eps; i++) {
3036 if (hsotg->eps_in[i])
3037 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3039 if (hsotg->eps_out[i])
3040 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3045 /* ensure after enumeration our EP0 is active */
3047 dwc2_hsotg_enqueue_setup(hsotg);
3049 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3050 dwc2_readl(hsotg->regs + DIEPCTL0),
3051 dwc2_readl(hsotg->regs + DOEPCTL0));
3055 * kill_all_requests - remove all requests from the endpoint's queue
3056 * @hsotg: The device state.
3057 * @ep: The endpoint the requests may be on.
3058 * @result: The result code to use.
3060 * Go through the requests on the given endpoint and mark them
3061 * completed with the given result code.
3063 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3064 struct dwc2_hsotg_ep *ep,
3067 struct dwc2_hsotg_req *req, *treq;
3072 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3073 dwc2_hsotg_complete_request(hsotg, ep, req,
3076 if (!hsotg->dedicated_fifos)
3078 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3079 if (size < ep->fifo_size)
3080 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3084 * dwc2_hsotg_disconnect - disconnect service
3085 * @hsotg: The device state.
3087 * The device has been disconnected. Remove all current
3088 * transactions and signal the gadget driver that this
3091 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3095 if (!hsotg->connected)
3098 hsotg->connected = 0;
3099 hsotg->test_mode = 0;
3101 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3102 if (hsotg->eps_in[ep])
3103 kill_all_requests(hsotg, hsotg->eps_in[ep],
3105 if (hsotg->eps_out[ep])
3106 kill_all_requests(hsotg, hsotg->eps_out[ep],
3110 call_gadget(hsotg, disconnect);
3111 hsotg->lx_state = DWC2_L3;
3115 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3116 * @hsotg: The device state:
3117 * @periodic: True if this is a periodic FIFO interrupt
3119 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3121 struct dwc2_hsotg_ep *ep;
3124 /* look through for any more data to transmit */
3125 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3126 ep = index_to_ep(hsotg, epno, 1);
3134 if ((periodic && !ep->periodic) ||
3135 (!periodic && ep->periodic))
3138 ret = dwc2_hsotg_trytx(hsotg, ep);
3144 /* IRQ flags which will trigger a retry around the IRQ loop */
3145 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3150 * dwc2_hsotg_core_init - issue softreset to the core
3151 * @hsotg: The device state
3153 * Issue a soft reset to the core, and await the core finishing it.
3155 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3163 /* Kill any ep0 requests as controller will be reinitialized */
3164 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3167 if (dwc2_core_reset(hsotg, true))
3171 * we must now enable ep0 ready for host detection and then
3172 * set configuration.
3175 /* keep other bits untouched (so e.g. forced modes are not lost) */
3176 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3177 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3180 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3181 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3182 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3183 /* FS/LS Dedicated Transceiver Interface */
3184 usbcfg |= GUSBCFG_PHYSEL;
3186 /* set the PLL on, remove the HNP/SRP and set the PHY */
3187 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3188 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3189 (val << GUSBCFG_USBTRDTIM_SHIFT);
3191 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3193 dwc2_hsotg_init_fifo(hsotg);
3196 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3198 dcfg |= DCFG_EPMISCNT(1);
3200 switch (hsotg->params.speed) {
3201 case DWC2_SPEED_PARAM_LOW:
3202 dcfg |= DCFG_DEVSPD_LS;
3204 case DWC2_SPEED_PARAM_FULL:
3205 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3206 dcfg |= DCFG_DEVSPD_FS48;
3208 dcfg |= DCFG_DEVSPD_FS;
3211 dcfg |= DCFG_DEVSPD_HS;
3214 dwc2_writel(dcfg, hsotg->regs + DCFG);
3216 /* Clear any pending OTG interrupts */
3217 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3219 /* Clear any pending interrupts */
3220 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3221 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3222 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3223 GINTSTS_USBRST | GINTSTS_RESETDET |
3224 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3225 GINTSTS_USBSUSP | GINTSTS_WKUPINT;
3227 if (!using_desc_dma(hsotg))
3228 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3230 if (!hsotg->params.external_id_pin_ctl)
3231 intmsk |= GINTSTS_CONIDSTSCHNG;
3233 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3235 if (using_dma(hsotg)) {
3236 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3237 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
3238 hsotg->regs + GAHBCFG);
3240 /* Set DDMA mode support in the core if needed */
3241 if (using_desc_dma(hsotg))
3242 __orr32(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3245 dwc2_writel(((hsotg->dedicated_fifos) ?
3246 (GAHBCFG_NP_TXF_EMP_LVL |
3247 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3248 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3252 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3253 * when we have no data to transfer. Otherwise we get being flooded by
3257 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3258 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3259 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3260 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3261 hsotg->regs + DIEPMSK);
3264 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3265 * DMA mode we may need this and StsPhseRcvd.
3267 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3268 DOEPMSK_STSPHSERCVDMSK) : 0) |
3269 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3271 hsotg->regs + DOEPMSK);
3273 /* Enable BNA interrupt for DDMA */
3274 if (using_desc_dma(hsotg))
3275 __orr32(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3277 dwc2_writel(0, hsotg->regs + DAINTMSK);
3279 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3280 dwc2_readl(hsotg->regs + DIEPCTL0),
3281 dwc2_readl(hsotg->regs + DOEPCTL0));
3283 /* enable in and out endpoint interrupts */
3284 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3287 * Enable the RXFIFO when in slave mode, as this is how we collect
3288 * the data. In DMA mode, we get events from the FIFO but also
3289 * things we cannot process, so do not use it.
3291 if (!using_dma(hsotg))
3292 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3294 /* Enable interrupts for EP0 in and out */
3295 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3296 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3298 if (!is_usb_reset) {
3299 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3300 udelay(10); /* see openiboot */
3301 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3304 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3307 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3308 * writing to the EPCTL register..
3311 /* set to read 1 8byte packet */
3312 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3313 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3315 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3316 DXEPCTL_CNAK | DXEPCTL_EPENA |
3318 hsotg->regs + DOEPCTL0);
3320 /* enable, but don't activate EP0in */
3321 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3322 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3324 dwc2_hsotg_enqueue_setup(hsotg);
3326 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3327 dwc2_readl(hsotg->regs + DIEPCTL0),
3328 dwc2_readl(hsotg->regs + DOEPCTL0));
3330 /* clear global NAKs */
3331 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3333 val |= DCTL_SFTDISCON;
3334 __orr32(hsotg->regs + DCTL, val);
3336 /* must be at-least 3ms to allow bus to see disconnect */
3339 hsotg->lx_state = DWC2_L0;
3342 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3344 /* set the soft-disconnect bit */
3345 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3348 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3350 /* remove the soft-disconnect and let's go */
3351 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3355 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3356 * @hsotg: The device state:
3358 * This interrupt indicates one of the following conditions occurred while
3359 * transmitting an ISOC transaction.
3360 * - Corrupted IN Token for ISOC EP.
3361 * - Packet not complete in FIFO.
3363 * The following actions will be taken:
3364 * - Determine the EP
3365 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3367 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3369 struct dwc2_hsotg_ep *hs_ep;
3373 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3375 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3376 hs_ep = hsotg->eps_in[idx];
3377 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3378 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3379 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3380 epctrl |= DXEPCTL_SNAK;
3381 epctrl |= DXEPCTL_EPDIS;
3382 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3386 /* Clear interrupt */
3387 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3391 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3392 * @hsotg: The device state:
3394 * This interrupt indicates one of the following conditions occurred while
3395 * transmitting an ISOC transaction.
3396 * - Corrupted OUT Token for ISOC EP.
3397 * - Packet not complete in FIFO.
3399 * The following actions will be taken:
3400 * - Determine the EP
3401 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3403 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3408 struct dwc2_hsotg_ep *hs_ep;
3411 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3413 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3414 hs_ep = hsotg->eps_out[idx];
3415 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3416 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3417 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3418 /* Unmask GOUTNAKEFF interrupt */
3419 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3420 gintmsk |= GINTSTS_GOUTNAKEFF;
3421 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3423 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3424 if (!(gintsts & GINTSTS_GOUTNAKEFF))
3425 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3429 /* Clear interrupt */
3430 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3434 * dwc2_hsotg_irq - handle device interrupt
3435 * @irq: The IRQ number triggered
3436 * @pw: The pw value when registered the handler.
3438 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3440 struct dwc2_hsotg *hsotg = pw;
3441 int retry_count = 8;
3445 if (!dwc2_is_device_mode(hsotg))
3448 spin_lock(&hsotg->lock);
3450 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3451 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3453 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3454 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3458 if (gintsts & GINTSTS_RESETDET) {
3459 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3461 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3463 /* This event must be used only if controller is suspended */
3464 if (hsotg->lx_state == DWC2_L2) {
3465 dwc2_exit_hibernation(hsotg, true);
3466 hsotg->lx_state = DWC2_L0;
3470 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3471 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3472 u32 connected = hsotg->connected;
3474 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3475 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3476 dwc2_readl(hsotg->regs + GNPTXSTS));
3478 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3480 /* Report disconnection if it is not already done. */
3481 dwc2_hsotg_disconnect(hsotg);
3483 if (usb_status & GOTGCTL_BSESVLD && connected)
3484 dwc2_hsotg_core_init_disconnected(hsotg, true);
3487 if (gintsts & GINTSTS_ENUMDONE) {
3488 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3490 dwc2_hsotg_irq_enumdone(hsotg);
3493 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3494 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3495 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3496 u32 daint_out, daint_in;
3500 daint_out = daint >> DAINT_OUTEP_SHIFT;
3501 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3503 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3505 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3506 ep++, daint_out >>= 1) {
3508 dwc2_hsotg_epint(hsotg, ep, 0);
3511 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3512 ep++, daint_in >>= 1) {
3514 dwc2_hsotg_epint(hsotg, ep, 1);
3518 /* check both FIFOs */
3520 if (gintsts & GINTSTS_NPTXFEMP) {
3521 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3524 * Disable the interrupt to stop it happening again
3525 * unless one of these endpoint routines decides that
3526 * it needs re-enabling
3529 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3530 dwc2_hsotg_irq_fifoempty(hsotg, false);
3533 if (gintsts & GINTSTS_PTXFEMP) {
3534 dev_dbg(hsotg->dev, "PTxFEmp\n");
3536 /* See note in GINTSTS_NPTxFEmp */
3538 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3539 dwc2_hsotg_irq_fifoempty(hsotg, true);
3542 if (gintsts & GINTSTS_RXFLVL) {
3544 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3545 * we need to retry dwc2_hsotg_handle_rx if this is still
3549 dwc2_hsotg_handle_rx(hsotg);
3552 if (gintsts & GINTSTS_ERLYSUSP) {
3553 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3554 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3558 * these next two seem to crop-up occasionally causing the core
3559 * to shutdown the USB transfer, so try clearing them and logging
3563 if (gintsts & GINTSTS_GOUTNAKEFF) {
3567 struct dwc2_hsotg_ep *hs_ep;
3569 /* Mask this interrupt */
3570 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3571 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3572 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3574 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3575 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3576 hs_ep = hsotg->eps_out[idx];
3577 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3579 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3580 epctrl |= DXEPCTL_SNAK;
3581 epctrl |= DXEPCTL_EPDIS;
3582 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3586 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3589 if (gintsts & GINTSTS_GINNAKEFF) {
3590 dev_info(hsotg->dev, "GINNakEff triggered\n");
3592 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3594 dwc2_hsotg_dump(hsotg);
3597 if (gintsts & GINTSTS_INCOMPL_SOIN)
3598 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3600 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3601 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3604 * if we've had fifo events, we should try and go around the
3605 * loop again to see if there's any point in returning yet.
3608 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3611 spin_unlock(&hsotg->lock);
3616 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
3617 u32 bit, u32 timeout)
3621 for (i = 0; i < timeout; i++) {
3622 if (dwc2_readl(hs_otg->regs + reg) & bit)
3630 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3631 struct dwc2_hsotg_ep *hs_ep)
3636 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3637 DOEPCTL(hs_ep->index);
3638 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3639 DOEPINT(hs_ep->index);
3641 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3644 if (hs_ep->dir_in) {
3645 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3646 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3647 /* Wait for Nak effect */
3648 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3649 DXEPINT_INEPNAKEFF, 100))
3650 dev_warn(hsotg->dev,
3651 "%s: timeout DIEPINT.NAKEFF\n",
3654 __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3655 /* Wait for Nak effect */
3656 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3657 GINTSTS_GINNAKEFF, 100))
3658 dev_warn(hsotg->dev,
3659 "%s: timeout GINTSTS.GINNAKEFF\n",
3663 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3664 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3666 /* Wait for global nak to take effect */
3667 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3668 GINTSTS_GOUTNAKEFF, 100))
3669 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3674 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3676 /* Wait for ep to be disabled */
3677 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3678 dev_warn(hsotg->dev,
3679 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3681 /* Clear EPDISBLD interrupt */
3682 __orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3684 if (hs_ep->dir_in) {
3685 unsigned short fifo_index;
3687 if (hsotg->dedicated_fifos || hs_ep->periodic)
3688 fifo_index = hs_ep->fifo_index;
3693 dwc2_flush_tx_fifo(hsotg, fifo_index);
3695 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3696 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3697 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3700 /* Remove global NAKs */
3701 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3706 * dwc2_hsotg_ep_enable - enable the given endpoint
3707 * @ep: The USB endpint to configure
3708 * @desc: The USB endpoint descriptor to configure with.
3710 * This is called from the USB gadget code's usb_ep_enable().
3712 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3713 const struct usb_endpoint_descriptor *desc)
3715 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3716 struct dwc2_hsotg *hsotg = hs_ep->parent;
3717 unsigned long flags;
3718 unsigned int index = hs_ep->index;
3724 unsigned int dir_in;
3725 unsigned int i, val, size;
3729 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3730 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3731 desc->wMaxPacketSize, desc->bInterval);
3733 /* not to be called for EP0 */
3735 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3739 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3740 if (dir_in != hs_ep->dir_in) {
3741 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3745 mps = usb_endpoint_maxp(desc);
3746 mc = usb_endpoint_maxp_mult(desc);
3748 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3750 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3751 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3753 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3754 __func__, epctrl, epctrl_reg);
3756 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3757 if (using_desc_dma(hsotg)) {
3758 hs_ep->desc_list = dma_alloc_coherent(hsotg->dev,
3759 MAX_DMA_DESC_NUM_GENERIC *
3760 sizeof(struct dwc2_dma_desc),
3761 &hs_ep->desc_list_dma, GFP_ATOMIC);
3762 if (!hs_ep->desc_list) {
3768 spin_lock_irqsave(&hsotg->lock, flags);
3770 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3771 epctrl |= DXEPCTL_MPS(mps);
3774 * mark the endpoint as active, otherwise the core may ignore
3775 * transactions entirely for this endpoint
3777 epctrl |= DXEPCTL_USBACTEP;
3779 /* update the endpoint state */
3780 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3782 /* default, set to non-periodic */
3783 hs_ep->isochronous = 0;
3784 hs_ep->periodic = 0;
3786 hs_ep->interval = desc->bInterval;
3788 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3789 case USB_ENDPOINT_XFER_ISOC:
3790 epctrl |= DXEPCTL_EPTYPE_ISO;
3791 epctrl |= DXEPCTL_SETEVENFR;
3792 hs_ep->isochronous = 1;
3793 hs_ep->interval = 1 << (desc->bInterval - 1);
3794 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3795 hs_ep->isoc_chain_num = 0;
3796 hs_ep->next_desc = 0;
3798 hs_ep->periodic = 1;
3799 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3800 mask |= DIEPMSK_NAKMSK;
3801 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3803 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3804 mask |= DOEPMSK_OUTTKNEPDISMSK;
3805 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3809 case USB_ENDPOINT_XFER_BULK:
3810 epctrl |= DXEPCTL_EPTYPE_BULK;
3813 case USB_ENDPOINT_XFER_INT:
3815 hs_ep->periodic = 1;
3817 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3818 hs_ep->interval = 1 << (desc->bInterval - 1);
3820 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3823 case USB_ENDPOINT_XFER_CONTROL:
3824 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3829 * if the hardware has dedicated fifos, we must give each IN EP
3830 * a unique tx-fifo even if it is non-periodic.
3832 if (dir_in && hsotg->dedicated_fifos) {
3834 u32 fifo_size = UINT_MAX;
3836 size = hs_ep->ep.maxpacket * hs_ep->mc;
3837 for (i = 1; i < hsotg->num_of_eps; ++i) {
3838 if (hsotg->fifo_map & (1 << i))
3840 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3841 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3844 /* Search for smallest acceptable fifo */
3845 if (val < fifo_size) {
3852 "%s: No suitable fifo found\n", __func__);
3856 hsotg->fifo_map |= 1 << fifo_index;
3857 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3858 hs_ep->fifo_index = fifo_index;
3859 hs_ep->fifo_size = fifo_size;
3862 /* for non control endpoints, set PID to D0 */
3863 if (index && !hs_ep->isochronous)
3864 epctrl |= DXEPCTL_SETD0PID;
3866 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3869 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3870 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3871 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3873 /* enable the endpoint interrupt */
3874 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3877 spin_unlock_irqrestore(&hsotg->lock, flags);
3880 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3881 dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3882 sizeof(struct dwc2_dma_desc),
3883 hs_ep->desc_list, hs_ep->desc_list_dma);
3884 hs_ep->desc_list = NULL;
3891 * dwc2_hsotg_ep_disable - disable given endpoint
3892 * @ep: The endpoint to disable.
3894 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
3896 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3897 struct dwc2_hsotg *hsotg = hs_ep->parent;
3898 int dir_in = hs_ep->dir_in;
3899 int index = hs_ep->index;
3900 unsigned long flags;
3904 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
3906 if (ep == &hsotg->eps_out[0]->ep) {
3907 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3911 /* Remove DMA memory allocated for non-control Endpoints */
3912 if (using_desc_dma(hsotg)) {
3913 dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3914 sizeof(struct dwc2_dma_desc),
3915 hs_ep->desc_list, hs_ep->desc_list_dma);
3916 hs_ep->desc_list = NULL;
3919 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3921 spin_lock_irqsave(&hsotg->lock, flags);
3923 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3925 if (ctrl & DXEPCTL_EPENA)
3926 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3928 ctrl &= ~DXEPCTL_EPENA;
3929 ctrl &= ~DXEPCTL_USBACTEP;
3930 ctrl |= DXEPCTL_SNAK;
3932 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
3933 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
3935 /* disable endpoint interrupts */
3936 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
3938 /* terminate all requests with shutdown */
3939 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
3941 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
3942 hs_ep->fifo_index = 0;
3943 hs_ep->fifo_size = 0;
3945 spin_unlock_irqrestore(&hsotg->lock, flags);
3950 * on_list - check request is on the given endpoint
3951 * @ep: The endpoint to check.
3952 * @test: The request to test if it is on the endpoint.
3954 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
3956 struct dwc2_hsotg_req *req, *treq;
3958 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
3967 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
3968 * @ep: The endpoint to dequeue.
3969 * @req: The request to be removed from a queue.
3971 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
3973 struct dwc2_hsotg_req *hs_req = our_req(req);
3974 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3975 struct dwc2_hsotg *hs = hs_ep->parent;
3976 unsigned long flags;
3978 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
3980 spin_lock_irqsave(&hs->lock, flags);
3982 if (!on_list(hs_ep, hs_req)) {
3983 spin_unlock_irqrestore(&hs->lock, flags);
3987 /* Dequeue already started request */
3988 if (req == &hs_ep->req->req)
3989 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
3991 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
3992 spin_unlock_irqrestore(&hs->lock, flags);
3998 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
3999 * @ep: The endpoint to set halt.
4000 * @value: Set or unset the halt.
4001 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4002 * the endpoint is busy processing requests.
4004 * We need to stall the endpoint immediately if request comes from set_feature
4005 * protocol command handler.
4007 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4009 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4010 struct dwc2_hsotg *hs = hs_ep->parent;
4011 int index = hs_ep->index;
4016 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4020 dwc2_hsotg_stall_ep0(hs);
4023 "%s: can't clear halt on ep0\n", __func__);
4027 if (hs_ep->isochronous) {
4028 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4032 if (!now && value && !list_empty(&hs_ep->queue)) {
4033 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4038 if (hs_ep->dir_in) {
4039 epreg = DIEPCTL(index);
4040 epctl = dwc2_readl(hs->regs + epreg);
4043 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4044 if (epctl & DXEPCTL_EPENA)
4045 epctl |= DXEPCTL_EPDIS;
4047 epctl &= ~DXEPCTL_STALL;
4048 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4049 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4050 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4051 epctl |= DXEPCTL_SETD0PID;
4053 dwc2_writel(epctl, hs->regs + epreg);
4055 epreg = DOEPCTL(index);
4056 epctl = dwc2_readl(hs->regs + epreg);
4059 epctl |= DXEPCTL_STALL;
4061 epctl &= ~DXEPCTL_STALL;
4062 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4063 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4064 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4065 epctl |= DXEPCTL_SETD0PID;
4067 dwc2_writel(epctl, hs->regs + epreg);
4070 hs_ep->halted = value;
4076 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4077 * @ep: The endpoint to set halt.
4078 * @value: Set or unset the halt.
4080 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4082 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4083 struct dwc2_hsotg *hs = hs_ep->parent;
4084 unsigned long flags = 0;
4087 spin_lock_irqsave(&hs->lock, flags);
4088 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4089 spin_unlock_irqrestore(&hs->lock, flags);
4094 static struct usb_ep_ops dwc2_hsotg_ep_ops = {
4095 .enable = dwc2_hsotg_ep_enable,
4096 .disable = dwc2_hsotg_ep_disable,
4097 .alloc_request = dwc2_hsotg_ep_alloc_request,
4098 .free_request = dwc2_hsotg_ep_free_request,
4099 .queue = dwc2_hsotg_ep_queue_lock,
4100 .dequeue = dwc2_hsotg_ep_dequeue,
4101 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4102 /* note, don't believe we have any call for the fifo routines */
4106 * dwc2_hsotg_init - initialize the usb core
4107 * @hsotg: The driver state
4109 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4113 /* unmask subset of endpoint interrupts */
4115 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4116 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4117 hsotg->regs + DIEPMSK);
4119 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4120 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4121 hsotg->regs + DOEPMSK);
4123 dwc2_writel(0, hsotg->regs + DAINTMSK);
4125 /* Be in disconnected state until gadget is registered */
4126 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
4130 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4131 dwc2_readl(hsotg->regs + GRXFSIZ),
4132 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4134 dwc2_hsotg_init_fifo(hsotg);
4136 /* keep other bits untouched (so e.g. forced modes are not lost) */
4137 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4138 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4141 /* set the PLL on, remove the HNP/SRP and set the PHY */
4142 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4143 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4144 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4145 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4147 if (using_dma(hsotg))
4148 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4152 * dwc2_hsotg_udc_start - prepare the udc for work
4153 * @gadget: The usb gadget state
4154 * @driver: The usb gadget driver
4156 * Perform initialization to prepare udc device and driver
4159 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4160 struct usb_gadget_driver *driver)
4162 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4163 unsigned long flags;
4167 pr_err("%s: called with no device\n", __func__);
4172 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4176 if (driver->max_speed < USB_SPEED_FULL)
4177 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4179 if (!driver->setup) {
4180 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4184 WARN_ON(hsotg->driver);
4186 driver->driver.bus = NULL;
4187 hsotg->driver = driver;
4188 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4189 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4191 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4192 ret = dwc2_lowlevel_hw_enable(hsotg);
4197 if (!IS_ERR_OR_NULL(hsotg->uphy))
4198 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4200 spin_lock_irqsave(&hsotg->lock, flags);
4201 if (dwc2_hw_is_device(hsotg)) {
4202 dwc2_hsotg_init(hsotg);
4203 dwc2_hsotg_core_init_disconnected(hsotg, false);
4207 spin_unlock_irqrestore(&hsotg->lock, flags);
4209 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4214 hsotg->driver = NULL;
4219 * dwc2_hsotg_udc_stop - stop the udc
4220 * @gadget: The usb gadget state
4221 * @driver: The usb gadget driver
4223 * Stop udc hw block and stay tunned for future transmissions
4225 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4227 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4228 unsigned long flags = 0;
4234 /* all endpoints should be shutdown */
4235 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4236 if (hsotg->eps_in[ep])
4237 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4238 if (hsotg->eps_out[ep])
4239 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4242 spin_lock_irqsave(&hsotg->lock, flags);
4244 hsotg->driver = NULL;
4245 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4248 spin_unlock_irqrestore(&hsotg->lock, flags);
4250 if (!IS_ERR_OR_NULL(hsotg->uphy))
4251 otg_set_peripheral(hsotg->uphy->otg, NULL);
4253 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4254 dwc2_lowlevel_hw_disable(hsotg);
4260 * dwc2_hsotg_gadget_getframe - read the frame number
4261 * @gadget: The usb gadget state
4263 * Read the {micro} frame number
4265 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4267 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4271 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4272 * @gadget: The usb gadget state
4273 * @is_on: Current state of the USB PHY
4275 * Connect/Disconnect the USB PHY pullup
4277 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4279 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4280 unsigned long flags = 0;
4282 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4285 /* Don't modify pullup state while in host mode */
4286 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4287 hsotg->enabled = is_on;
4291 spin_lock_irqsave(&hsotg->lock, flags);
4294 dwc2_hsotg_core_init_disconnected(hsotg, false);
4295 dwc2_hsotg_core_connect(hsotg);
4297 dwc2_hsotg_core_disconnect(hsotg);
4298 dwc2_hsotg_disconnect(hsotg);
4302 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4303 spin_unlock_irqrestore(&hsotg->lock, flags);
4308 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4310 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4311 unsigned long flags;
4313 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4314 spin_lock_irqsave(&hsotg->lock, flags);
4317 * If controller is hibernated, it must exit from hibernation
4318 * before being initialized / de-initialized
4320 if (hsotg->lx_state == DWC2_L2)
4321 dwc2_exit_hibernation(hsotg, false);
4324 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4326 dwc2_hsotg_core_init_disconnected(hsotg, false);
4328 dwc2_hsotg_core_connect(hsotg);
4330 dwc2_hsotg_core_disconnect(hsotg);
4331 dwc2_hsotg_disconnect(hsotg);
4334 spin_unlock_irqrestore(&hsotg->lock, flags);
4339 * dwc2_hsotg_vbus_draw - report bMaxPower field
4340 * @gadget: The usb gadget state
4341 * @mA: Amount of current
4343 * Report how much power the device may consume to the phy.
4345 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4347 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4349 if (IS_ERR_OR_NULL(hsotg->uphy))
4351 return usb_phy_set_power(hsotg->uphy, mA);
4354 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4355 .get_frame = dwc2_hsotg_gadget_getframe,
4356 .udc_start = dwc2_hsotg_udc_start,
4357 .udc_stop = dwc2_hsotg_udc_stop,
4358 .pullup = dwc2_hsotg_pullup,
4359 .vbus_session = dwc2_hsotg_vbus_session,
4360 .vbus_draw = dwc2_hsotg_vbus_draw,
4364 * dwc2_hsotg_initep - initialise a single endpoint
4365 * @hsotg: The device state.
4366 * @hs_ep: The endpoint to be initialised.
4367 * @epnum: The endpoint number
4369 * Initialise the given endpoint (as part of the probe and device state
4370 * creation) to give to the gadget driver. Setup the endpoint name, any
4371 * direction information and other state that may be required.
4373 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4374 struct dwc2_hsotg_ep *hs_ep,
4387 hs_ep->dir_in = dir_in;
4388 hs_ep->index = epnum;
4390 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4392 INIT_LIST_HEAD(&hs_ep->queue);
4393 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4395 /* add to the list of endpoints known by the gadget driver */
4397 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4399 hs_ep->parent = hsotg;
4400 hs_ep->ep.name = hs_ep->name;
4402 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4403 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4405 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4406 epnum ? 1024 : EP0_MPS_LIMIT);
4407 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4410 hs_ep->ep.caps.type_control = true;
4412 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4413 hs_ep->ep.caps.type_iso = true;
4414 hs_ep->ep.caps.type_bulk = true;
4416 hs_ep->ep.caps.type_int = true;
4420 hs_ep->ep.caps.dir_in = true;
4422 hs_ep->ep.caps.dir_out = true;
4425 * if we're using dma, we need to set the next-endpoint pointer
4426 * to be something valid.
4429 if (using_dma(hsotg)) {
4430 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4433 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4435 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4440 * dwc2_hsotg_hw_cfg - read HW configuration registers
4441 * @param: The device state
4443 * Read the USB core HW configuration registers
4445 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4451 /* check hardware configuration */
4453 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4456 hsotg->num_of_eps++;
4458 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4459 sizeof(struct dwc2_hsotg_ep),
4461 if (!hsotg->eps_in[0])
4463 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4464 hsotg->eps_out[0] = hsotg->eps_in[0];
4466 cfg = hsotg->hw_params.dev_ep_dirs;
4467 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4469 /* Direction in or both */
4470 if (!(ep_type & 2)) {
4471 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4472 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4473 if (!hsotg->eps_in[i])
4476 /* Direction out or both */
4477 if (!(ep_type & 1)) {
4478 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4479 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4480 if (!hsotg->eps_out[i])
4485 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4486 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4488 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4490 hsotg->dedicated_fifos ? "dedicated" : "shared",
4496 * dwc2_hsotg_dump - dump state of the udc
4497 * @param: The device state
4499 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4502 struct device *dev = hsotg->dev;
4503 void __iomem *regs = hsotg->regs;
4507 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4508 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4509 dwc2_readl(regs + DIEPMSK));
4511 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4512 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4514 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4515 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4517 /* show periodic fifo settings */
4519 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4520 val = dwc2_readl(regs + DPTXFSIZN(idx));
4521 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4522 val >> FIFOSIZE_DEPTH_SHIFT,
4523 val & FIFOSIZE_STARTADDR_MASK);
4526 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4528 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4529 dwc2_readl(regs + DIEPCTL(idx)),
4530 dwc2_readl(regs + DIEPTSIZ(idx)),
4531 dwc2_readl(regs + DIEPDMA(idx)));
4533 val = dwc2_readl(regs + DOEPCTL(idx));
4535 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4536 idx, dwc2_readl(regs + DOEPCTL(idx)),
4537 dwc2_readl(regs + DOEPTSIZ(idx)),
4538 dwc2_readl(regs + DOEPDMA(idx)));
4541 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4542 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4547 * dwc2_gadget_init - init function for gadget
4548 * @dwc2: The data structure for the DWC2 driver.
4549 * @irq: The IRQ number for the controller.
4551 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
4553 struct device *dev = hsotg->dev;
4557 /* Dump fifo information */
4558 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4559 hsotg->params.g_np_tx_fifo_size);
4560 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4562 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4563 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4564 hsotg->gadget.name = dev_name(dev);
4565 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4566 hsotg->gadget.is_otg = 1;
4567 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4568 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4570 ret = dwc2_hsotg_hw_cfg(hsotg);
4572 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4576 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4577 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4578 if (!hsotg->ctrl_buff)
4581 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4582 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4583 if (!hsotg->ep0_buff)
4586 if (using_desc_dma(hsotg)) {
4587 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4592 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
4593 dev_name(hsotg->dev), hsotg);
4595 dev_err(dev, "cannot claim IRQ for gadget\n");
4599 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4601 if (hsotg->num_of_eps == 0) {
4602 dev_err(dev, "wrong number of EPs (zero)\n");
4606 /* setup endpoint information */
4608 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4609 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4611 /* allocate EP0 request */
4613 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4615 if (!hsotg->ctrl_req) {
4616 dev_err(dev, "failed to allocate ctrl req\n");
4620 /* initialise the endpoints now the core has been initialised */
4621 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4622 if (hsotg->eps_in[epnum])
4623 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4625 if (hsotg->eps_out[epnum])
4626 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4630 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4634 dwc2_hsotg_dump(hsotg);
4640 * dwc2_hsotg_remove - remove function for hsotg driver
4641 * @pdev: The platform information for the driver
4643 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4645 usb_del_gadget_udc(&hsotg->gadget);
4650 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4652 unsigned long flags;
4654 if (hsotg->lx_state != DWC2_L0)
4657 if (hsotg->driver) {
4660 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4661 hsotg->driver->driver.name);
4663 spin_lock_irqsave(&hsotg->lock, flags);
4665 dwc2_hsotg_core_disconnect(hsotg);
4666 dwc2_hsotg_disconnect(hsotg);
4667 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4668 spin_unlock_irqrestore(&hsotg->lock, flags);
4670 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4671 if (hsotg->eps_in[ep])
4672 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4673 if (hsotg->eps_out[ep])
4674 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4681 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4683 unsigned long flags;
4685 if (hsotg->lx_state == DWC2_L2)
4688 if (hsotg->driver) {
4689 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4690 hsotg->driver->driver.name);
4692 spin_lock_irqsave(&hsotg->lock, flags);
4693 dwc2_hsotg_core_init_disconnected(hsotg, false);
4695 dwc2_hsotg_core_connect(hsotg);
4696 spin_unlock_irqrestore(&hsotg->lock, flags);
4703 * dwc2_backup_device_registers() - Backup controller device registers.
4704 * When suspending usb bus, registers needs to be backuped
4705 * if controller power is disabled once suspended.
4707 * @hsotg: Programming view of the DWC_otg controller
4709 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4711 struct dwc2_dregs_backup *dr;
4714 dev_dbg(hsotg->dev, "%s\n", __func__);
4716 /* Backup dev regs */
4717 dr = &hsotg->dr_backup;
4719 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4720 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4721 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4722 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4723 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4725 for (i = 0; i < hsotg->num_of_eps; i++) {
4727 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4729 /* Ensure DATA PID is correctly configured */
4730 if (dr->diepctl[i] & DXEPCTL_DPID)
4731 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4733 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4735 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4736 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4738 /* Backup OUT EPs */
4739 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4741 /* Ensure DATA PID is correctly configured */
4742 if (dr->doepctl[i] & DXEPCTL_DPID)
4743 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4745 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4747 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4748 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4755 * dwc2_restore_device_registers() - Restore controller device registers.
4756 * When resuming usb bus, device registers needs to be restored
4757 * if controller power were disabled.
4759 * @hsotg: Programming view of the DWC_otg controller
4761 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
4763 struct dwc2_dregs_backup *dr;
4767 dev_dbg(hsotg->dev, "%s\n", __func__);
4769 /* Restore dev regs */
4770 dr = &hsotg->dr_backup;
4772 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4778 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
4779 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4780 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4781 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4782 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4784 for (i = 0; i < hsotg->num_of_eps; i++) {
4785 /* Restore IN EPs */
4786 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4787 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4788 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4790 /* Restore OUT EPs */
4791 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4792 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4793 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4796 /* Set the Power-On Programming done bit */
4797 dctl = dwc2_readl(hsotg->regs + DCTL);
4798 dctl |= DCTL_PWRONPRGDONE;
4799 dwc2_writel(dctl, hsotg->regs + DCTL);